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WO2019228045A1 - 供电时序控制电路及控制方法、显示驱动电路、显示装置 - Google Patents

供电时序控制电路及控制方法、显示驱动电路、显示装置 Download PDF

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Publication number
WO2019228045A1
WO2019228045A1 PCT/CN2019/080188 CN2019080188W WO2019228045A1 WO 2019228045 A1 WO2019228045 A1 WO 2019228045A1 CN 2019080188 W CN2019080188 W CN 2019080188W WO 2019228045 A1 WO2019228045 A1 WO 2019228045A1
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WO
WIPO (PCT)
Prior art keywords
terminal
circuit
output
voltage
electrically connected
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Application number
PCT/CN2019/080188
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English (en)
French (fr)
Inventor
朱立新
聂春扬
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19810649.4A priority Critical patent/EP3806080A1/en
Priority to US16/605,217 priority patent/US11482148B2/en
Publication of WO2019228045A1 publication Critical patent/WO2019228045A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a power supply timing control circuit and control method, a display driving circuit, and a display device.
  • the display device may be, for example, a liquid crystal display device (Liquid Crystal Display, TFT-LCD), or an organic light emitting diode (Organic Light Emitting Diode, OLED) display device.
  • the display device includes a display area for displaying an image, and a wiring area located around the display area.
  • a plurality of driving circuits are provided in the wiring area, and the plurality of driving circuits are used to drive the display area to display an image.
  • At least one embodiment of the present disclosure provides a power supply timing control circuit, including: a delay control sub-circuit, a delay detection sub-circuit, and an output sub-circuit; the delay control sub-circuit is electrically connected to a first input voltage terminal The delay control sub-circuit is configured to receive a first voltage output from the first input voltage terminal and delay the first voltage by a preset time to output; the delay detection sub-circuit and the The delay control sub-circuit is electrically connected to the output sub-circuit, and the delay detection sub-circuit is configured to send a trigger signal to the output sub-circuit when the first voltage is received; the output sub-circuit And is electrically connected to the first input voltage terminal and the signal output terminal, and the output sub-circuit is configured to be in an on state in response to the trigger signal to switch the first voltage provided by the first input voltage terminal Output to the signal output terminal, and allow the signal output terminal to output the first voltage.
  • the power supply timing control circuit further includes an auxiliary output sub-circuit; the auxiliary output sub-circuit is electrically connected to the output sub-circuit; the auxiliary output sub-circuit is Configured to allow the output sub-circuit to maintain the on state after receiving the trigger signal; the output sub-circuit is configured to continuously output the first voltage to the after receiving the trigger signal A signal output terminal, so that the signal output terminal continuously outputs the first voltage.
  • the auxiliary output sub-circuit is further connected to the first input voltage terminal, the first reference voltage terminal, the second input voltage terminal, the second reference voltage terminal, and the first The three reference voltage terminals are electrically connected;
  • the auxiliary output sub-circuit includes a power isolator, and the power isolator includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
  • a first input terminal is electrically connected to the first input voltage terminal;
  • a second input terminal of the power isolator is electrically connected to the first reference voltage terminal and the third reference voltage terminal;
  • An output terminal is electrically connected to the second input voltage terminal;
  • a second output terminal of the power isolator is electrically connected to the second reference voltage terminal;
  • the power isolator is configured to be based on the first input voltage The first voltage provided by the terminal, the first reference voltage provided by the first reference voltage terminal, and the third reference voltage provided by the third reference voltage terminal output to the second input voltage terminal and the
  • the power isolator is further configured to provide the second reference according to the first voltage, the first reference voltage, and the third reference voltage.
  • the voltage terminal outputs the second reference voltage isolated from the first reference voltage.
  • the auxiliary output sub-circuit further includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; both ends of the first capacitor are respectively connected to The first input voltage terminal is electrically connected to the first reference voltage terminal; both ends of the second capacitor are electrically connected to the first input terminal of the power isolator and the second input terminal of the power isolator, respectively. ; Both ends of the third capacitor are electrically connected to the first output terminal of the power isolator and the second output terminal of the power isolator; both ends of the fourth capacitor are respectively connected to the second input The voltage terminal is electrically connected to the second reference voltage terminal.
  • the auxiliary output sub-circuit further includes a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor;
  • the first input terminal of the power isolator is electrically connected to the third reference voltage terminal; both ends of the sixth capacitor are electrically connected to the second input terminal of the power isolator and the third reference voltage terminal, respectively.
  • Two ends of the seventh capacitor are electrically connected to the first output terminal and the third reference voltage terminal of the power isolator; two ends of the eighth capacitor are the second output of the power isolator And the third reference voltage terminal are electrically connected.
  • the auxiliary output sub-circuit further includes a first resistor and a second resistor; two ends of the first resistor are the second input voltage terminal and the second resistor, respectively.
  • a second reference voltage terminal is electrically connected; the second resistor is connected in parallel with the first resistor, and two ends of the second resistor are electrically connected to the second input voltage terminal and the second reference voltage terminal, respectively.
  • the output sub-circuit includes a switching transistor and a driving transistor; a gate of the switching transistor is electrically connected to the delay detection sub-circuit to receive the trigger A signal; a gate of the driving transistor is electrically connected to a second electrode of the switching transistor; a first electrode of the driving transistor is electrically connected to the first input voltage terminal to receive a signal provided by the first input voltage terminal A second voltage of the driving transistor; the second pole of the driving transistor is electrically connected to the signal output terminal; the driving transistor is configured to provide the trigger signal to a first voltage provided by a first input voltage terminal to the driving A second electrode of the transistor; the signal output terminal is configured to allow a first voltage located at the second electrode of the driving transistor to be output from the signal output terminal.
  • the power supply timing control circuit further includes an auxiliary output sub-circuit.
  • the auxiliary output sub-circuit is electrically connected to the output sub-circuit; the auxiliary output sub-circuit is also electrically connected to a second input voltage terminal and a second reference voltage terminal; a first pole of the switching transistor and the second The input voltage terminal is electrically connected to receive a second voltage isolated from the first voltage provided by the second input voltage terminal; the second pole of the switching transistor is electrically connected to the second reference voltage terminal to receive A second reference voltage provided by the second reference voltage terminal and isolated from the first reference voltage; a second pole of the driving transistor is also electrically connected to the second reference voltage terminal.
  • the output sub-circuit further includes: a third resistor, a fourth resistor, and a fifth resistor; both ends of the third resistor are respectively connected to the second input.
  • the voltage terminal is electrically connected to the output terminal of the delay detection sub-circuit; both ends of the fourth resistor are electrically connected to the output terminal of the delay detection sub-circuit and the gate of the switching transistor, respectively;
  • the two ends of the five resistors are electrically connected to the second electrode of the switching transistor and the second reference voltage terminal, respectively.
  • the delay control sub-circuit is electrically connected to a first reference voltage terminal;
  • the delay control sub-circuit includes an adjustable resistor and a ninth capacitor;
  • the first terminal of the adjustable resistor is electrically connected to the first input voltage terminal, the second terminal of the adjustable resistor is electrically connected to the first terminal of the ninth capacitor, and the second terminal of the ninth capacitor is connected to the first terminal of the ninth capacitor.
  • the first reference voltage terminal is electrically connected.
  • the adjustable range of the adjustable resistor is 1k-10M ⁇ .
  • the delay detection sub-circuit is further electrically connected to a first reference voltage terminal;
  • the delay detection sub-circuit includes a comparator, a sixth resistor, and a seventh resistor An eighth resistor and a tenth capacitor;
  • the positive input terminal of the comparator is electrically connected to the delay control sub-circuit, and the negative input terminal of the comparator is electrically connected to the first terminal of the eighth resistor
  • An output terminal of the comparator is electrically connected to the output sub-circuit;
  • a second terminal of the eighth resistor is electrically connected to a first terminal of the sixth resistor and a first terminal of the seventh resistor;
  • the second terminal of the sixth resistor is electrically connected to the first input voltage terminal;
  • the second terminal of the seventh resistor is electrically connected to the first reference voltage terminal;
  • the first reference voltage terminal and the comparator are electrically connected to the first input voltage terminal.
  • At least one embodiment of the present disclosure also provides a display driving circuit including a power supply timing control circuit provided by any embodiment of the present disclosure.
  • the display driving circuit further includes a power management chip; the power management chip has an input terminal and a plurality of voltage output terminals; and the power management chip is configured to The initial voltage received by the input terminal generates a plurality of output voltages; the plurality of output voltages are configured to be respectively output by the plurality of voltage output terminals; one of the plurality of voltage output terminals of the power management chip and A first input voltage terminal of the power supply timing control circuit is electrically connected.
  • the display driving circuit includes a plurality of the power supply timing control circuits; a plurality of the voltage output terminals of the power management chip and a plurality of the power supply timings, respectively
  • the first input voltage terminals of the control circuit are electrically connected to provide a plurality of output voltages to the first input voltage terminals of the plurality of power supply timing control circuits, respectively; the plurality of power supply timing control circuits are configured to control the Power supply timing for multiple output voltages.
  • the display driving circuit further includes a timing controller, a source driver, and a gate driver; a signal output terminal of the power supply timing control circuit and the timing controller, An electrical connection of the source driver or the gate driver; the timing controller, the source driver, or the gate driver is also electrically connected to a first reference voltage terminal.
  • the display driving circuit further includes a source driver and a grayscale voltage generator configured to generate a plurality of grayscale reference voltages;
  • the grayscale voltage generator includes A plurality of grayscale reference output terminals, each grayscale reference output terminal is configured to output one grayscale reference voltage; one of the plurality of grayscale reference output terminals of the grayscale voltage generator and the power supply timing
  • a first input voltage terminal of the control circuit is electrically connected;
  • a signal output terminal of the power supply timing control circuit is electrically connected to the source driver; and the source driver is also electrically connected to the first reference voltage terminal.
  • At least one embodiment of the present disclosure further provides a display device including a display driving circuit provided by any embodiment of the present disclosure.
  • the display device further includes a display panel including a common electrode layer; a first input voltage terminal of the power supply timing control circuit and a power management chip are configured A voltage output terminal for outputting a common voltage is electrically connected; and a signal output terminal of the power supply timing control circuit is electrically connected to the common electrode layer.
  • At least one embodiment of the present disclosure further provides a method for controlling a power supply timing control circuit provided by any embodiment of the present disclosure, which includes: the time delay control sub-circuit outputs the first The first voltage is output after delaying the preset time; the delay detection sub-circuit sends the trigger signal to the output sub-circuit when receiving the first voltage; the output sub-circuit responds to The trigger signal is in an on state and outputs a first voltage provided by the first input voltage terminal to the signal output terminal.
  • the output sub-circuit when the power supply timing control circuit further includes the auxiliary output sub-circuit, the output sub-circuit is configured to respond to the trigger signal in an on state to A first voltage provided by the first input voltage terminal is output to the signal output terminal. After the first voltage is output to the signal output terminal, the method further includes: the auxiliary output sub-circuit controlling the After receiving the trigger signal, the output sub-circuit maintains the on state.
  • FIG. 1 is an exemplary block diagram of a power supply timing control circuit provided by at least one embodiment of the present disclosure
  • FIG. 2A is a power supply timing diagram provided by at least one embodiment of the present disclosure
  • 2B is a timing diagram of a driving voltage output by a power management chip provided by at least one embodiment of the present disclosure
  • 3A is an exemplary block diagram of another power supply timing control circuit provided by at least one embodiment of the present disclosure.
  • 3B is another exemplary block diagram of a power supply timing control circuit provided by at least one embodiment of the present disclosure.
  • 3C is another exemplary block diagram of a power supply timing control circuit provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an auxiliary output sub-circuit in FIG. 3A;
  • FIG. 5 is a schematic structural diagram of an output sub-circuit provided by at least one embodiment of the present disclosure.
  • FIG. 6 is another schematic structural diagram of the output sub-circuit in FIG. 3A; FIG.
  • FIG. 7 is a schematic structural diagram of another power supply timing control circuit according to at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another power supply timing control circuit according to at least one embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a control method of a power supply timing control circuit according to at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another display device provided by at least one embodiment of the present disclosure.
  • FIG. 12 is an exemplary block diagram of a display driving circuit provided by at least one embodiment of the present disclosure.
  • the inventor of the present disclosure noticed in research that although software programming (Code) can be used to control the power supply timing of the driving circuit of the display device, the software programming itself may have defects, which may cause the actual power supply timing There is a deviation from the preset power supply timing and may cause display anomalies.
  • At least one embodiment of the present disclosure provides a power supply timing control circuit 01, which can be used as a component of a display device to control a power sequence or power supply sequence of a display panel.
  • the power supply timing control circuit 01 can control the power-on timing of the display panel by pure hardware. Therefore, the power supply timing control circuit 01 can control the display panel's power more accurately than by controlling the power-on timing of the display panel by software programming.
  • the power-on sequence can avoid potential display failure caused by abnormal power-on sequence of the display panel.
  • FIG. 1 is an exemplary block diagram of a power supply timing control circuit 01 provided by at least one embodiment of the present disclosure.
  • the power supply timing control circuit 01 may include a delay control sub-circuit 10, a delay detection sub-circuit 20, and an output sub-circuit 30.
  • the power supply timing control circuit 01 includes a first input voltage terminal VIN1 and a signal output terminal Vout.
  • the delay control sub-circuit 10 is electrically connected to the first input voltage terminal VIN1 to receive the first voltage V1 output from the first input voltage terminal VIN1.
  • the delay control sub-circuit 10 is configured to delay the first voltage V1 outputted from the first input voltage terminal VIN1 by a preset time T and output.
  • delaying the first voltage V1 by a preset time T to output means that the delay control sub-circuit 10 receives the first voltage V1 (for example, the delay control sub-circuit 10 receives the first voltage V1 at time T0).
  • a voltage V1) for a preset time T the voltage output by the delay control sub-circuit 10 is substantially equal to the first voltage V1 (for example, at time T0 + T, the voltage output by the delay control sub-circuit 10 is substantially equal to the first voltage V1).
  • the delay control sub-circuit 10 may also output a voltage, but the voltage value of the output voltage is smaller than the first voltage V1.
  • the specific circuit structure of the delay control sub-circuit 10 will be described in detail after the output sub-circuit 30 is explained, and will not be repeated here.
  • the above-mentioned first voltage V1 may be, for example, provided by a power management circuit and used to provide any driving voltage (for example, a digital operating voltage DVDD, an analog voltage AVDD, a gate-off voltage VGL, a gate-on). Any one of the voltages VGH).
  • the above-mentioned first voltage V1 may be an analog voltage AVDD or a digital voltage DVDD (also referred to as a digital operating voltage) for supplying to a source driver.
  • the first voltage V1 may also be a first operating voltage VGH and a second operating voltage VGL provided to the gate driver.
  • the voltage value of the first operating voltage VGH is greater than the voltage value of the second operating voltage VGL.
  • the first voltage V1 may also be a gray-scale reference voltage VGMA provided to a source driver, a digital voltage DVDD provided to a gate driver, or a common voltage Vcom provided to a common electrode layer of a display panel.
  • the power supply time (for example, the end time of the rising or falling edge) of the at least one driving voltage provided by the power management circuit deviates from the predetermined power supply time (that is, there is an abnormality in the power-on timing), and causes the display panel to fail.
  • the power supply sequence does not meet the actual application requirements; in this case, any one of the above driving voltages that needs to be controlled (or adjusted) can be provided as the first voltage V1 to the power supply sequence control circuit 01, and by using delay control
  • the sub-circuit 10 and the power supply timing control circuit 01 delay the first voltage V1 (that is, the voltage that needs to be controlled or adjusted) by outputting a preset time T, so that the timing of the driving voltage provided to the display panel meets the actual Application requirements can thereby more accurately control the power-on timing of the display panel and avoid potential display failure caused by abnormal power-on timing of the display panel.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display device includes a display driving circuit and a display panel.
  • the display driving circuit includes a plurality of power supply timing control circuits 01.
  • the display driving circuit further includes a power management chip 51 (or other applicable power management circuits).
  • the power management chip 51 has multiple voltage output terminals, and the power management chip is configured to generate multiple output voltages (for example, digital operating voltage DVDD) according to the initial voltage VDD (for example, 5 volts or 12 volts) received by the input terminals. , Analog voltage AVDD, gate-off voltage VGL, gate-on voltage VGH), and output from different voltage output terminals.
  • the display driving circuit may further include only one or two power supply timing control circuits 01.
  • the image processor (or interface connector) 52 may provide an initial voltage VDD to the power management chip 51.
  • each voltage output terminal of the power management chip 51 is electrically connected to a first input voltage terminal VIN1 of a power supply timing control circuit 01.
  • the multiple voltage output terminals of the power management chip 51 correspond to the multiple power supply sequence control circuits 01 one-to-one; the multiple voltage output terminals of the power management chip 51 are respectively corresponding to the first input voltage terminals VIN1 of the multiple power supply sequence control circuits 01. Electrically connected, thereby, a plurality of output voltages output by the power management chip are respectively provided to the corresponding power supply timing control circuit 01.
  • each power supply timing control circuit 01 connected to the power management chip 51 may sequentially generate multiple output voltages (or drive voltages, such as DVDD, AVDD, VGL, VGH) from the power management chip 51 in accordance with a preset power supply as required.
  • the timing is output to the corresponding load in sequence.
  • the load may be a timing controller, a source driver, or a gate driver, and these loads may be part of a display device.
  • the power supply timing (or power-up timing) may be the order in which a plurality of output voltages (or driving voltages) generated by the power management chip 51 are provided to the load.
  • FIG. 2A is a schematic diagram of a power supply sequence of a display panel (or a display device).
  • DVDD, AVDD, VGL, and VGH are provided to the corresponding loads at time t1, time t2, time t3, and time t4, respectively, and t1 ⁇ t2 ⁇ t3 ⁇ t4; in this case, the display panel (or The display device's preset power supply sequence is: DVDD, AVDD, VGL, VGH.
  • the power supply timing of the display panel (or display device) shown in FIG. 2A is the power supply timing (or a correct power supply timing) required by the display panel.
  • t1, t2, t3, and t4 can represent t1, t2, t3, and t4, respectively, and can also represent t1, t2, t3, and t4. Time difference at time t0.
  • a load (such as the source driver or gate driver) connected to the power supply timing control circuit 01 needs to receive DVDD before it can work. Therefore, DVDD supplies power to the load in preference to AVDD.
  • VGH and VGL are generated by AVDD, so AVDD needs to be powered before VGH and VGL (for example, AVDD needs to be provided before VGH and VGL are provided to the corresponding load).
  • the voltage of VGL is low, for example, it can be -8V, and the voltage of VGH is high, for example, it can be 30V.
  • the over-current protection or over-temperature protection of the driving circuit is caused, or a power management chip (Power) for generating the power supply voltage is generated.
  • the driving circuit can be provided with a lower amplitude voltage (such as the above-mentioned VGL) at the time of starting, and then provide a higher amplitude voltage (such as the above-mentioned VGH). So the power supply time of VGL can take precedence over VGH.
  • DVDD, AVDD, VGH, VGL are respectively input to the first input voltage terminal VIN1 connected to the delay control sub-circuit 10 in four different power supply timing control circuits 01, in order to obtain the power supply timing shown in FIG. 2A
  • the delay time (for example, t1) of the delay control sub-circuit 10 in the power supply timing control circuit 01 receiving DVDD is greater than the delay time (for example, t2) of the delay control sub-circuit 10 in the power supply timing control circuit 01 receiving AVDD.
  • the delay time of the delay control sub-circuit 10 in the power supply timing control circuit 01 receiving AVDD is greater than the delay time of the delay control sub-circuit 10 in the power supply timing control circuit 01 receiving VGL (for example, Equal to t3); the delay time of the delay control sub-circuit 10 in the power supply timing control circuit 01 receiving VGL (for example, equal to t3) is greater than the delay time of the delay control sub-circuit 10 in the power supply timing control circuit 01 receiving VGH ( E.g, To t4).
  • FIG. 2B shows a timing diagram of a driving voltage (eg, DVDD, AVDD, VGH, VGL) output by the power management chip 51.
  • a driving voltage eg, DVDD, AVDD, VGH, VGL
  • the power supply timing of the DVDD, VGH, and VGL meets the requirements, but compared to a predetermined power supply time, AVDD
  • the leading time of the power supply time is equal to t2-t5.
  • the power supply timing of receiving AVDD is The delay time of the delay control sub-circuit 10 in the control circuit 01 needs to be additionally increased by t2-t5.
  • the power supply timing control circuit 01 provided by at least one embodiment of the present disclosure is exemplarily described below with reference to FIGS. 3A to 3C.
  • FIG. 3A is another exemplary block diagram of the power supply timing control circuit 01 provided by at least one embodiment of the present disclosure.
  • the output time of the first voltage V1 output from the first input voltage terminal VIN1 may be delayed by the delay control sub-circuit 10 according to need.
  • the power supply timing control circuit 01 can control the output time of the first voltage V1 through pure hardware, the power supply timing control circuit 01 can control the output voltage more accurately than by controlling the output time of the first voltage V1 through software programming. Output time of the first voltage V1.
  • the power supply timing control circuit 01 (for example, multiple power supply timing control circuits 01) is used to control the power-on timing of the display panel
  • the power supply timing control circuit is compared to controlling the power-on timing of the display panel by software programming 01 can more accurately control the power-on timing of the display panel, thereby avoiding potential display failure caused by abnormal power-on timing of the display panel.
  • the delay detection sub-circuit 20 is electrically connected to the delay control sub-circuit 10 (for example, the output terminal of the delay control sub-circuit 10) and the output sub-circuit 30 (for example, the input terminal of the output sub-circuit 30). connection.
  • the delay detection sub-circuit 20 is configured to, when receiving a voltage having a voltage value substantially equal to the voltage value of the first voltage V1 (for example, after completing the preset time T delay, that is, at time T0 + T), The output sub-circuit 30 sends a trigger signal Em.
  • the output sub-circuit 30 is also electrically connected to the first input voltage terminal VIN1 and a signal output terminal Vout (for example, the signal output terminal Vout of the power supply timing control circuit 01).
  • the output sub-circuit 30 is configured to output the first voltage V1 of the first input voltage terminal VIN1 to the signal output terminal Vout according to the trigger signal Em output by the delay detection sub-circuit 20.
  • the power supply timing control circuit 01 may further include an auxiliary output sub-circuit 40.
  • FIG. 3B is still another exemplary block diagram of the power supply timing control circuit 01 provided by at least one embodiment of the present disclosure. Compared to the power supply timing control circuit 01 shown in FIG. 3A, the power supply timing control circuit 01 shown in FIG. 3B also shows the input and output ends of the output sub-circuit 30 and the auxiliary output sub-circuit 40.
  • the output sub-circuit 30 includes a first signal input terminal InP1, a second signal input terminal InP2, a third signal input terminal InP3, and a signal output terminal OUPT1; a first signal input terminal InP1 of the output sub-circuit 30 Is configured to be connected to the output of the delay detection sub-circuit 20 to receive the trigger signal Em; the second signal input terminal InP2 of the output sub-circuit 30 is configured to receive the first voltage V1 or the second voltage V2 (in FIG. 3B (Not shown, see FIG. 8); the third signal input terminal InP3 of the output sub-circuit 30 is configured to receive a first reference voltage (not shown in FIG. 3B, see FIG. 6) or configured to receive a second reference voltage.
  • the auxiliary output sub-circuit 40 includes a first input terminal InP4, a second input terminal InP5, a first output terminal OUPT2, and a second output terminal OUPT3.
  • the first input terminal InP4 of the auxiliary output sub-circuit 40 and the second input terminal InP5 of the auxiliary output sub-circuit 40 are electrically connected to the first input voltage terminal VIN1 and the first reference voltage terminal Vref, respectively.
  • the auxiliary output sub-circuit 40 is configured to generate a second voltage based on the first voltage V1 (for example, DVDD) output from the first input voltage terminal VIN1 and the first reference voltage (for example, GND1) provided by the first reference voltage terminal Vref. V2 and a second reference voltage (for example, GND2).
  • the second voltage V2 and the second reference voltage are output via the second output terminal OUPT3 of the auxiliary output sub-circuit 40 and the first output terminal OUPT2 of the auxiliary output sub-circuit 40, respectively.
  • FIG. 3C is still another exemplary block diagram of the power supply timing control circuit 01 provided by at least one embodiment of the present disclosure. Compared with the power supply timing control circuit 01 shown in FIG. 3B, the power supply timing control circuit 01 shown in FIG. 3C further shows the auxiliary output sub-circuit 40 and the output sub-circuit 30, the first input voltage terminal VIN1 and the first reference voltage. The connection relationship of the terminal Vref.
  • the power supply timing control circuit 01 shown in FIG. 3C may enable the output sub-circuit 30 to continuously output the first voltage provided by the first input voltage terminal VIN1 from the signal output terminal Vout of the power supply timing control circuit 01.
  • the power supply timing control circuit 01 provided by at least one embodiment of the present disclosure is exemplarily described below with reference to the circuit structures shown in FIGS. 4 to 8.
  • FIG. 6 shows an example diagram of a circuit structure of an output sub-circuit 30 provided by at least one embodiment of the present disclosure.
  • FIG. 6 also shows a delay detection sub-circuit 20.
  • the output sub-circuit 30 shown in FIG. 6 may make the signal output terminal Vout of the power supply timing control circuit 01 unable to continuously output the first voltage V1, which will be specifically described below with reference to FIG. 6.
  • the output sub-circuit 30 may include a transistor electrically connected to the first input voltage terminal VIN1 and the signal output terminal Vout.
  • the output sub-circuit 30 may include a driving transistor Qd.
  • a first electrode (such as a source s or a drain d) of the driving transistor Qd is electrically connected to the first input voltage terminal VIN1.
  • the second electrode (for example, the drain d or the source s) of the transistor Qd is electrically connected to the signal output terminal Vout.
  • the output sub-circuit 30 may further include a switching transistor Qc.
  • the gate of the switching transistor Qc is electrically connected to the delay detection sub-circuit 20 (the output terminal of the delay detection sub-circuit 20) to receive a trigger signal Em output from the delay detection sub-circuit 20;
  • the second pole is electrically connected to the gate of the driving transistor Qd;
  • the other pole for example, the first pole of the switching transistor Qc is electrically connected to the first input voltage terminal VIN1 to receive the first output from the first input voltage terminal VIN1; Voltage V1.
  • the switching transistor Qc when the switching transistor Qc is turned on (for example, after the gate of the switching transistor Qc receives a trigger signal Em or an active level), it passes through the turned-on switching transistor Qc and is input to the driving transistor Qd.
  • the voltage of the gate that is, the first voltage V1 derived from the first input voltage terminal VIN1
  • the driving transistor Qd can turn the first input voltage terminal VIN1
  • the provided first voltage V1 is transmitted to the signal output terminal Vout.
  • the first pole of the switching transistor Qc may be electrically connected to the first input voltage terminal VIN1, and the second pole of the switching transistor Qc is electrically connected to the gate of the driving transistor Qd.
  • the second pole of the switching transistor Qc and the second pole of the driving transistor Qd are also electrically connected to the first reference voltage terminal Vref1.
  • the output sub-circuit 30 can allow the signal output terminal Vout of the power supply timing control circuit 01 to continuously output the first voltage V1.
  • FIGS. 3A-3C, 4-5, and 7 This is explained in detail with FIG. 8.
  • the power supply timing control circuit 01 further includes an auxiliary output sub-circuit 40.
  • the auxiliary output sub-circuit 40 is electrically connected to the output sub-circuit 30.
  • the auxiliary output sub-circuit 40 may be configured to control the output sub-circuit 30 so that after the gate of the switching transistor Qc receives the trigger signal EM described above, the driving transistor Qd can be maintained in an on state.
  • the auxiliary output sub-circuit 40 is configured to output a second voltage V2 and a second reference voltage based on the first voltage V1 and the first reference voltage.
  • the first voltage V1 (the first reference voltage) and the second voltage V2 (the second reference voltage) are isolated from each other.
  • the first voltage V1 and the second voltage V2 are different from each other, the first reference voltage and the second reference voltage are different from each other, and the voltage difference between the first voltage V1 and the first reference voltage may be equal to the second voltage V2 and the second voltage, for example.
  • V2 is greater than V1.
  • auxiliary output sub-circuit 40 The specific structures of the auxiliary output sub-circuit 40 and the output sub-circuit 30 electrically connected to the auxiliary output sub-circuit 40 will be described in detail below.
  • the auxiliary output sub-circuit 40 is also electrically connected to the first input voltage terminal VIN1, the first reference voltage terminal Vref1, the second input voltage terminal VIN2, the second reference voltage terminal Vref2, and the third reference voltage terminal Vref3. .
  • the auxiliary output sub-circuit 40 further includes a power isolation module 401.
  • the power isolation module 401 may be implemented as a power isolator, and the power isolator may be implemented by a circuit.
  • the first input voltage terminal VIN1 and the first reference voltage terminal Vref1 are configured to be connected to the input terminal of the auxiliary output sub-circuit 40, and the second input voltage terminal VIN2 and the second reference voltage terminal Vref2 are configured to be connected to the auxiliary output sub-circuit.
  • the output of 40 is connected; the auxiliary output sub-circuit 40 is configured to output the second voltage V2 and the second reference voltage based on the first voltage V1 and the first reference voltage, and the second voltage V2 and the second reference voltage are configured to be respectively provided to The second input voltage terminal VIN2 and the second reference voltage terminal Vref2.
  • a first input terminal In1 of the power isolation module 401 is electrically connected to a first input voltage terminal VIN1.
  • the second input terminal In2 of the power isolation module 401 is electrically connected to the first reference voltage terminal Vref1 and the third reference voltage terminal Vref3.
  • the first output terminal Out1 of the power isolation module 401 is electrically connected to the second input voltage terminal VIN2.
  • the second output terminal Out2 of the power isolation module 401 is electrically connected to the second reference voltage terminal Vref2 and the third reference voltage terminal Vref3.
  • the power isolation module 401 is configured to be based on the first voltage V1 provided by the first input voltage terminal VIN1, the first reference voltage (for example, GND1) provided by the first reference voltage terminal Vref1, and the third reference voltage terminal Vref2.
  • the third reference voltage (for example, the case voltage) outputs a second voltage V2 isolated from the first voltage V1 to the second input voltage terminal VIN.
  • the second input voltage terminal VIN is electrically connected to the first pole of the switching transistor Qc of the output sub-circuit 30 and is configured to provide a second voltage V2 to the first pole of the switching transistor Qc of the output sub-circuit 30.
  • the isolation of the first voltage V1 input from the first input voltage terminal VIN1 and the output of the second input voltage terminal VIN2 from the second voltage V2 means that the reference point of the potential of the first input voltage terminal VIN1 (the above-mentioned first reference voltage GND1) ) And the reference point of the potential of the second input voltage terminal VIN2 (the above-mentioned second reference voltage GND2) are different.
  • the first voltage V1 input from the first input voltage terminal VIN1 and the output from the second input voltage terminal VIN2 and the second voltage V2 have no common ground, so they do not interfere with each other.
  • the driving transistor Qd can continuously maintain the on-state and continuously output the first voltage V1.
  • the output sub-circuit 40 may further include a first capacitor C1, a second capacitor C2, and a third capacitor.
  • the two ends of the first capacitor C1 are electrically connected to the first input voltage terminal VIN1 and the first reference voltage terminal Vref1, respectively.
  • the two ends of the second capacitor C2 are electrically connected to the first input terminal In1 of the power isolation module 401 and the second input terminal In2 of the power isolation module 401, respectively.
  • Both ends of the fourth capacitor C4 are electrically connected to the second input voltage terminal VIN2 and the second reference voltage terminal Vref2, respectively.
  • both ends of any one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are connected to the positive voltage terminal and the negative voltage terminal, respectively, so the above capacitors are all X capacitors. For eliminating differential mode interference and radiation.
  • auxiliary output sub-circuit 40 may further include a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8.
  • the two ends of the fifth capacitor C5 are electrically connected to the first input terminal In1 and the third reference voltage terminal Vref3 of the power isolation module 401, respectively.
  • Both ends of the sixth capacitor C6 are electrically connected to the second input terminal In2 and the third reference voltage terminal Vref3 of the power isolation module 401, respectively.
  • Both ends of the seventh capacitor C7 are electrically connected to the first output terminal Out1 and the third reference voltage terminal Vref3 of the power isolation module 401, respectively.
  • the two ends of the eighth capacitor C8 are electrically connected to the second output terminal Out2 and the third reference voltage terminal Vref3 of the power isolation module 401, respectively.
  • any one of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 are respectively connected to a positive (or negative) voltage terminal and a ground terminal (for example, GND1, GND2). Or housing), so the above capacitor is a Y capacitor, which is used to eliminate common mode interference.
  • auxiliary output sub-circuit 40 may further include a first resistor R1 and a second resistor R2.
  • the two ends of the first resistor R1 are electrically connected to the second input voltage terminal VIN2 and the second reference voltage terminal Vref2, respectively.
  • Both ends of the second resistor R2 are electrically connected to the second input voltage terminal VIN2 and the second reference voltage terminal Vref2, respectively.
  • the first resistor R1 and the second resistor R2 are connected in parallel, and are used to reduce the probability of fluctuations in the voltage output from the second input voltage terminal VIN2 and the second reference voltage terminal Vref2 to achieve the purpose of voltage stabilization.
  • the auxiliary output sub-circuit 40 when the auxiliary output sub-circuit 40 is electrically connected to the second input voltage terminal VIN2 and the second reference voltage terminal Vref2, in order to electrically connect the auxiliary output sub-circuit 40 to the output sub-circuit 30, in other embodiments, As shown in FIG. 5, the first pole of the switching transistor Qc in the output sub-circuit 30 is electrically connected to the second input voltage terminal VIN2, and the second pole of the switching transistor Qc is electrically connected to the second reference voltage terminal Vref2.
  • the gate of the driving transistor Qd in the output sub-circuit 30 is electrically connected to the second pole of the switching transistor Qc.
  • the first pole of the driving transistor Qd is electrically connected to the first input voltage terminal VIN1.
  • the second pole of the driving transistor Qd is connected to a signal.
  • the output terminal Vout is electrically connected to the second reference voltage terminal Vref2.
  • the first electrode of any one of the switching transistor Qc and the driving transistor Qd may be a source and a second electrode may be a drain; or the first electrode may be a drain and the second electrode may be a source.
  • Some embodiments of the present disclosure do not limit the type of the foregoing transistors.
  • Any one of the switching transistor Qc and the driving transistor Qd may be a transistor, a TFT (Thin Film Transistor, or a thin film transistor), or a MOS (Metal-Oxide-Semiconductor, Metal-oxide-semiconductor) transistor.
  • the driving transistor Qd Since the driving transistor Qd needs to be connected to a load (for example, a source driver or a gate driver of a display device), the driving transistor Qd is required to have a certain load capacity (that is, the driving current output by the driving transistor Qd needs to be greater than a predetermined current value). ), For example, when the power supply timing control circuit 01 is applied to a display device.
  • the load capacity (that is, the driving current output by the driving transistor Qd) is 60A or more. Since the MOS transistor is easier to obtain a larger loading capacity, in some embodiments of the present disclosure, the driving transistor Qd may be a MOS transistor.
  • the output sub-circuit 30 may further include a third resistor R3, a fourth resistor R4, and a fifth resistor R5.
  • both ends of the third resistor R3 are electrically connected to the second input voltage terminal VIN2 and the delay detection sub-circuit 20, respectively.
  • Both ends of the fourth resistor R4 are electrically connected to the delay detection sub-circuit 20 and the gate of the switching transistor Qc, respectively.
  • Both ends of the fifth resistor R5 are electrically connected to the second electrode of the switching transistor Qc and the second reference voltage terminal Vref2, respectively.
  • the auxiliary output sub-circuit 40 shown in FIG. 4 and the output sub-circuit 30 shown in FIG. 5 are both connected to the second input voltage terminal VIN2 and the second reference voltage terminal Vref2. Therefore, the electrical connection between the auxiliary output sub-circuit 40 and the output sub-circuit 30 can be achieved through the second input voltage terminal VIN2 and the second reference voltage terminal Vref2.
  • the output sub-circuit 30 is caused to receive the isolated first voltage V1 and the second reference voltage Vref2 output from the auxiliary output sub-circuit 40.
  • the output sub-circuit 40 and the output sub-circuit 30 are passed through the second input voltage terminal VIN2 and the second After the reference voltage terminal Vref2 is electrically connected, the auxiliary output sub-circuit 40 outputs a second voltage V2 isolated from the first voltage V1 from the second input voltage terminal VIN2, and can be provided to the first pole of the switching transistor Qc in FIG. 5.
  • the second voltage V2 output from the second input voltage terminal VIN2 can be transmitted to the gate of the driving transistor Qd through the switching transistor Qc.
  • the driving transistor Qd is turned on, and the first voltage V1 output from the first input voltage terminal VIN1 can be transmitted to the signal output terminal Vout through the driving transistor Qd.
  • the gate voltage Vg V2 of the driving transistor Qd. Because the first voltage V1 and the second voltage V2 are isolated from each other under the isolation of the power isolation module 401 in the auxiliary output sub-circuit 40, the gate source of the driving transistor Qd cannot be directly calculated based on the first voltage V1 and the second voltage V2.
  • the delay control sub-circuit 10 is electrically connected to the first reference voltage terminal Vref1.
  • the delay control sub-circuit 10 includes an adjustable resistor Rc and a ninth capacitor C9.
  • One end (ie, the first end) of the adjustable resistor Rc is electrically connected to the first input voltage terminal VIN1, and the other end (ie, the second end) of the adjustable resistor Rc is connected to one end of the ninth capacitor C9 (that is, , The first end) is electrically connected.
  • the first terminal of the ninth capacitor C9 is configured as an output terminal of the delay control sub-circuit 10.
  • the other terminal (ie, the second terminal) of the ninth capacitor C9 is electrically connected to the first reference voltage terminal Vref1.
  • the ninth capacitor C9 may be an ordinary capacitor or may be an electrolytic capacitor, which is not limited in the embodiment of the present disclosure.
  • the resistance value R of the adjustable resistor Rc may be adjusted so that the capacitance voltage Vc9 of the ninth capacitor C9 is increased (by charging to) the time Tc of the first voltage V1 (that is, the time of the ninth capacitor C9).
  • the charging time) is equal to the preset time T, so that the delay control sub-circuit 10 can output the first voltage V1 after the preset time T is delayed.
  • ⁇ is a constant related to the rising time of the capacitor voltage (Rising);
  • R is the resistance value of the adjustable resistor Rc;
  • C is the capacitance value of the ninth capacitor C9. It can be known from the above expression that when the resistance value R of the adjustable resistor Rc is larger, the charging time of the ninth capacitor C9 is longer, thereby making the preset time T larger; when the resistance value R of the adjustable resistor Rc is smaller, The shorter the charging time of the ninth capacitor C9 is, the smaller the preset time T is.
  • the resistance adjustment range of the adjustable resistor Rc may be set based on the first voltage V1 provided by the first input voltage terminal VIN1.
  • the resistance adjustment range of the adjustable resistor Rc may be 1k ⁇ to 10M ⁇ .
  • the resistance of the adjustable resistor Rc is less than 1k ⁇ , although the adjustment accuracy of the preset time T is high, the adjustment range of the preset time T is small, thereby increasing the power supply timing (power-on timing of the display panel). Adjust the difficulty.
  • the adjustable value of the adjustable resistor Rc is greater than 10M ⁇ , the preset time T and the charging time Tc of the ninth capacitor C9 will exceed the upper limit of the power-on time for startup, resulting in a delay in startup.
  • the delay detection sub-circuit 20 is also electrically connected to the first reference voltage terminal Vref1.
  • the first reference voltage terminal Vref1 is, for example, grounded.
  • the delay detection sub-circuit includes a comparator 201, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a tenth capacitor C10.
  • the first input terminal (positive input terminal) of the comparator 201 is electrically connected to the delay control sub-circuit 10, the second input terminal (negative input terminal) of the comparator 201 and one terminal (first terminal) of the eighth resistor R8 ) Electrical connection.
  • the positive input terminal of the comparator 201 is connected to the first terminal of the ninth capacitor C9 in the delay control sub-circuit 10 (that is, the output terminal of the delay control sub-circuit 10).
  • the comparator 201 may also be connected with a forward operating voltage (for example, the first voltage V1 provided by the first input voltage terminal VIN1) and a negative operating voltage (for example, A first reference voltage GND1) of the first reference voltage terminal Vref1.
  • a forward operating voltage for example, the first voltage V1 provided by the first input voltage terminal VIN1
  • a negative operating voltage for example, A first reference voltage GND1 of the first reference voltage terminal Vref1.
  • the embodiments of the present disclosure do not limit the size of the above-mentioned positive working voltage and negative working voltage, as long as the comparator 201 can be driven to work.
  • the positive working voltage is greater than zero volts, and the negative working voltage is less than or equal to zero volts.
  • the output terminal of the comparator 201 is electrically connected to the output sub-circuit 30.
  • the output terminal of the comparator 201 is electrically connected to the gate of the switching transistor Qc in the output sub-circuit 30.
  • the output terminal of the comparator 201 is electrically connected to the gate of the switching transistor Qc in the output sub-circuit 30 via a fourth resistor R4.
  • the other end (second end) of the eighth resistor R8 is electrically connected to one end (first end) of the sixth resistor R6 and one end (first end) of the seventh resistor R7.
  • the other end (second end) of the sixth resistor R6 is electrically connected to the first input voltage terminal VIN1.
  • the other end (second end) of the seventh resistor R7 is electrically connected to the first reference voltage terminal Vref1.
  • the magnitude of the voltage V- received by the negative voltage terminal of the comparator 201 can be adjusted, and thus, for example, the selection of the first voltage V1 can be controlled. Value and preset time T.
  • the output terminal of the comparator 201 outputs a first level (for example, a high level or an active level to the gate of the switching transistor Qc, The voltage value of the first level is greater than zero volts, for example, to turn on the switching transistor Qc.
  • the output terminal of the comparator 201 outputs The second level (for example, a low level or an inactive level, a voltage value of the second level is, for example, less than zero volts), and turns off the switching transistor Qc.
  • the active level refers to the level at which the transistor is turned on
  • the inactive level refers to the level at which the transistor medium is made.
  • the voltage V- received by the negative input terminal of the comparator 201 may be slightly smaller than the first voltage V1.
  • the ratio of the difference between the first voltage V1 and the voltage V- to the first voltage V1 is about 5%, that is, (V1-V-) / V1 is about 5%.
  • both ends of the tenth capacitor C10 are electrically connected to the first reference voltage terminal Vref1 and the forward input terminal of the comparator 201, respectively.
  • both ends of the tenth capacitor C10 may be respectively connected to the first reference voltage terminal Vref1 and the first input voltage terminal VIN1 (the terminal of the comparator 201 that receives the first voltage V1).
  • the tenth capacitor C10 plays a role of voltage stabilization and rectification.
  • the following takes the first input voltage terminal VIN1 to provide the first voltage V1 as a DVDD as an example, and uses the power supply timing control circuit 01 provided by the embodiment of the present disclosure to control the power supply timing (the end time of the rising edge of the DVDD) of the DVDD. .
  • the voltage V + outputted from the ninth capacitor C9 to the positive input terminal of the comparator 201 is smaller than the voltage V_ of the negative input terminal.
  • the output terminal of the comparator 201 outputs a low level, and the transistor is switched.
  • Qc is turned off, the driving transistor Qd is turned off, and no signal is output from the signal output terminal Vout (or Vout outputs a low level).
  • the capacitor voltage Vc9 of the ninth capacitor C9 DVDD.
  • the voltage V + output from the ninth capacitor C9 to the positive input terminal of the comparator 201 is greater than the voltage V_ from the negative input terminal, the output terminal of the comparator 201 outputs a high level, and the switching transistor Qc is turned on.
  • the power isolation module 401 in the auxiliary output sub-circuit 40 provides the isolated second voltage V2 and the second reference voltage GND2 to the first and second poles of the switching transistor Qc, respectively.
  • the second voltage V2 is transmitted to the gate of the driving transistor Qd after the switching transistor Qc is turned on.
  • the gate of the driving transistor Qd is kept on under the control of the second voltage V2 and will be isolated from the second voltage V2.
  • DVDD is transmitted to the signal output terminal Vout, thereby realizing the delayed output of the voltage DVDD.
  • the control process of the power supply timing of the remaining voltages AVDD, VGL, and VGH is the same as described above. The difference is that according to the power supply timing of AVDD, VGL, and VGH shown in FIG. 3A, it can be known that the power supply timing control circuit 01 receiving AVDD
  • the resistance of the adjustable resistor Rc is greater than the resistance of the adjustable resistor Rc in the power supply timing control circuit 01 receiving the DVDD, and smaller than the resistance of the adjustable resistor Rc in the power supply timing control circuit 01 receiving the VGL.
  • the resistance value of the adjustable resistor Rc in the power supply timing control circuit 01 receiving VGL is smaller than the resistance value of the adjustable resistor Rc in the power supply timing control circuit 01 receiving VGH.
  • the control processes for the remaining voltages AVDD, VGL, and VGH are the same as or similar to the control processes for the voltage DVDD, and are not repeated here.
  • An embodiment of the present disclosure provides a method for controlling any one of the power supply timing control circuits 01. As shown in FIG. 9, the method includes the following steps S101-S103.
  • step S101 the delay control sub-circuit 10 delays the first voltage V1 outputted from the first input voltage terminal VIN1 by a preset time T and outputs it.
  • Step S102 After the preset time T, when the delay detection sub-circuit 20 receives the first voltage V1, it sends a trigger signal Em to the output sub-circuit 30.
  • step S103 the output sub-circuit 30 is in an on state according to the trigger signal Em, and outputs the first voltage V1 of the first input voltage terminal VIN1 to the signal output terminal Vout.
  • the control method of the power supply timing control circuit 01 described above has the same or similar technical effects as the power supply timing circuit 01 provided in the foregoing embodiment, and details are not described herein again.
  • the method further includes:
  • step S104 the auxiliary output sub-circuit 40 controls the output sub-circuit 30 to keep the on state after receiving the trigger signal Em.
  • FIG. 12 is an exemplary block diagram of a display driving circuit provided by at least one embodiment of the present disclosure.
  • the display driving circuit provided by the embodiment of the present disclosure is exemplarily described below with reference to FIGS. 10 to 12.
  • the display driving circuit provided by the embodiment of the present disclosure includes at least one power supply timing control circuit 01 as described above.
  • the display driving circuit has the same or similar technical effects as the power supply timing control circuit 01 provided in the foregoing embodiment, and details are not described herein again.
  • the following describes the setting manner of the power supply timing control circuit 01 in the display driving circuit as an example.
  • the display driving circuit further includes a timing controller 53, a source driver 54, and a gate driver 55 shown in FIGS. 10 and 11.
  • the timing controller 53, the source driver 54, and the gate driver 55 can serve as loads for the power supply timing control circuit 01 described above.
  • the signal output terminal Vout of the power supply timing control circuit 01 for outputting the DVDD may be electrically connected to the timing controller 53.
  • the signal output terminals Vout of the power supply timing control circuits 01 respectively for outputting two DVDD and AVDD may be electrically connected to the source driver 54.
  • the signal output terminals Vout of the three power supply timing control circuits 01 respectively for outputting DVDD, VGL, and VGH may be electrically connected to the gate driver 55.
  • the timing controller 53, the source driver 54, or the gate driver 55 connected to the power supply timing control circuit 01 are also connected to the first reference voltage.
  • the terminal Vref1 is electrically connected to receive the first reference voltage GND1 output from the first reference voltage terminal Vref1.
  • the timing controller 53 is electrically connected to the image processor 52, the source driver 54, and the gate driver 55.
  • the timing controller 53 is in a working state after receiving a DVDD output by a power supply timing control circuit 01, and sends the data signal (Dat), clock signal (CLK), and control signal (ControlS) to the source according to the data signal (Dat), the clock signal (CLK), and the control signal (ControlS) output from the power supply timing control circuit 01.
  • the pole driver 54 provides a data signal Dat and a clock signal (CLK), and provides a gate start signal (StartVertical, STV, also known as a frame start signal) and a gate movement signal (ClockPulseVertical, CPV) to the gate driver 55. , Also known as the scan clock pulse signal).
  • the timing controller 53 may also provide an enable signal (Output Enable) to the gate driver 55.
  • the gate driver 55 may be in an operating state after receiving multiple DVDD, VGH, and VGL output from the power supply timing control circuit 01, and control the gate lines in the display panel to scan line by line.
  • the source driver 54 receives a plurality of DVDD and AVDD outputted from the power supply timing control circuit 01 and is in an operating state, and controls the data line to provide a data voltage Vdata to a selected row of sub-pixels in the display panel.
  • the display driving circuit further includes a grayscale voltage generator 56 electrically connected to the source driver 54.
  • the sum gray-scale voltage generator 56 is configured to generate a plurality of gray-scale reference voltages (for example, VGAM_1, VGMA_2,... VGMA_n; n ⁇ 2, n is a positive integer).
  • the source driver 54 may provide a data voltage Vdata corresponding to a preset grayscale value to each sub-pixel in the display panel according to the grayscale reference voltage.
  • a reference grayscale output terminal of the grayscale voltage generator 56 is electrically connected to a first input voltage terminal VIN1 of a power supply timing control circuit.
  • the signal output terminal Vout of the power supply timing control circuit 01 is electrically connected to the source driver 54.
  • the source driver 54 is also electrically connected to the first reference voltage terminal Vref1 to receive the first reference voltage GND1 output from the first reference voltage terminal Vref1.
  • the multiple gray-scale reference voltages generated by the gray-scale voltage generator 56 are respectively controlled by multiple power supply timing control circuits 01 (under a delay control), and can be sequentially provided to the source in accordance with a preset power supply sequence. ⁇ Driver 54.
  • An embodiment of the present disclosure provides a display device including any one of the display driving circuits described above.
  • the display device further includes a display panel.
  • the display panel includes a common electrode layer 02.
  • a power supply timing control circuit 01 may be additionally added to the display device.
  • the first input voltage terminal VIN of the power supply timing control circuit 01 is electrically connected to a voltage output terminal of the power management chip 51 for outputting a common voltage Vcom.
  • 02 is electrically connected, and the time when the common voltage Vcom is input to the common electrode layer 02 can be controlled by the power supply timing control circuit 01.
  • the embodiments of the present disclosure do not limit the power supply timing of the common voltage Vcom.
  • the common voltage Vcom can be powered on again. That is, the DVDD and AVDD can be provided.
  • VGL, VGL, VGH the common voltage Vcom is provided.
  • multiple driving voltages eg, power supply voltages
  • power supply voltages such as DVDD, AVDD, VGH, VGL, etc.
  • the delay time of the delay control sub-circuit 10 in the different power supply timing control circuit 01 can be set, so that multiple power supply timing control circuits 01 can sequentially output the plurality of power supplies according to a preset power supply timing.
  • Drive voltage for example, supply voltage
  • the delay detection sub-circuit 20 in the different power supply timing control circuit 01 can judge the delay time of the delay control sub-circuit 10, and when the delay time meets the requirements, for example, when receiving the DVDD power supply timing
  • the delay detection sub-circuit 20 in the control circuit 01 detects the actual delay time of the delay control sub-circuit 10.
  • the delay detection sub-circuit 20 controls The output sub-circuit 30 is turned on.
  • the first voltage V1 (such as the DVDD) of the first input voltage terminal VIN1 can be output to the load by the signal output terminal Vout of the power supply timing control circuit 01 through the output sub-circuit 30.
  • a source driver in a display device for example, a source driver in a display device.
  • the output modes of the other supply voltages are the same as described above.
  • the embodiment of the present disclosure controls the power supply timing of the power supply voltage required by each load by using the power supply timing control circuit 01 as a hardware device without software programming to control the power supply timing. Therefore, the power supply timing control circuit 01 has high stability and reliability, and can solve the problem that the power supply timing is controlled by software programming control.
  • the above display devices may be LCD and OLED display devices.
  • the display device may be any product or component having a display function, such as a display, a television, a digital photo frame, a mobile phone, or a tablet computer.
  • the display panels in FIG. 10 and FIG. 11 are described by using an LCD display panel as an example.
  • the setting method of the display device with the power supply timing control circuit 01 is the same as or similar to the setting method of the display device with the LCD display panel, and details are not described herein.
  • the foregoing program may be stored in a computer-readable storage medium.
  • the program is executed, the program is executed.
  • the method includes the steps of the foregoing method embodiment.
  • the foregoing storage medium includes: a ROM, a RAM, a magnetic disk, or an optical disk, and other media that can store program codes.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种供电时序控制电路(01)及控制方法、显示驱动电路、显示装置。供电时序控制电路(01)包括：延时控制子电路(10)、延时检测子电路(20)以及输出子电路(30)；延时控制子电路(10)与第一输入电压端(VIN1)电连接，延时控制子电路(10)被配置为接收第一输入电压端(VIN1)输出的第一电压(V1)，并将第一电压(V1)延时一预设时间后输出；延时检测子电路(20)与延时控制子电路(10)和输出子电路(30)电连接，延时检测子电路(20)被配置为在接收到第一电压(V1)时，向输出子电路(30)发送触发信号(EM)；输出子电路(30)还与第一输入电压端(VIN1)以及信号输出端(Vout)电连接，输出子电路(30)被配置为响应于触发信号(EM)处于开启状态，以将第一输入电压端(VIN1)提供的第一电压(V1)输出至信号输出端(Vout)，并允许信号输出端输出第一电压(V1)。供电时序控制电路(01)可以更为精确的控制第一电压(V1)的输出时间。

Description

供电时序控制电路及控制方法、显示驱动电路、显示装置
对相关申请的交叉参考
本申请要求于2018年5月28日递交的中国专利申请第201810523586.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种供电时序控制电路及控制方法、显示驱动电路、显示装置。
背景技术
显示装置例如可以为液晶显示装置(Liquid Crystal Display，TFT-LCD)，或者，有机发光二极管(Organic Light Emitting Diode，OLED)显示装置。显示装置包括用于显示图像的显示区域，以及位于该显示区域周边的布线区域。上述布线区域中设置有例如多个驱动电路，多个驱动电路用于驱动显示区域显示图像。
发明内容
本公开的至少一个实施例提供了一种供电时序控制电路，其包括：延时控制子电路、延时检测子电路以及输出子电路；所述延时控制子电路与第一输入电压端电连接，所述延时控制子电路被配置为接收所述第一输入电压端输出的第一电压，并将所述第一电压延时一预设时间后输出；所述延时检测子电路与所述延时控制子电路和所述输出子电路电连接，所述延时检测子电路被配置为在接收到所述第一电压时，向所述输出子电路发送触发信号；所述输出子电路还与所述第一输入电压端以及所述信号输出端电连接，所述输出子电路被配置为响应于所述触发信号处于开启状态，以将所述第一输入电压端提供的第一电压输出至所述信号输出端，并允许所述信号输出端输出所述第一电压。
例如，在所述供电时序控制电路的至少一个示例中，所述供电时序控制电路还包括辅助输出子电路；所述辅助输出子电路与所述输出子电路电连接；所述辅助输出子电路被配置为允许所述输出子电路在接收到所述触发信号后，保持所述开启状态；所述输出子电路被配置为在接收到所述触发信号后持续将所述第一电压输出至所述信号输出端，以使得所述信号输出端持续输出所述第一电压。
例如，在所述供电时序控制电路的至少一个示例中，所述辅助输出子电路还与所述第一输入电压端、第一参考电压端、第二输入电压端、第二参考电压端以及第三参考电压端电连接；所述辅助输出子电路包括电源隔离器，所述电源隔离器包括第一输入端、第二输入端、第一输出端和第二输出端；所述电源隔离器的第一输入端与所述第一输入电压端电连接；所述电源隔离器的第二输入端与所述第一参考电压端和所述第三参考电压端电连接；所述电源隔离器第一输出端与所述第二输入电压端电连接；所述电源隔离器的第二输出端与所述第二参考电压端电连接；所述电源隔离器被配置为根据所述第一输入电压端提供的第一电压、所述第一参考电压端提供的第一参考电压以及所述第三参考电压端提供的第三参考电压向所述第二输入电压端输出与所述第一电压隔离的第二电压，其中，所述第一参考电压与所述第二参考电压端输出的第二参考电压不同。
例如，在所述供电时序控制电路的至少一个示例中，所述电源隔离器还被配置为根据所述第一电压、所述第一参考电压以及所述第三参考电压向所述第二参考电压端输出与所述第一参考电压隔离的所述第二参考电压。
例如，在所述供电时序控制电路的至少一个示例中，所述辅助输出子电路还包括第一电容、第二电容、第三电容、第四电容；所述第一电容的两端分别与所述第一输入电压端和所述第一参考电压端电连接；所述第二电容的两端分别与所述电源隔离器的第一输入端和所述电源隔离器的第二输入端电连接；所述第三电容的两端分别与所述电源隔离器的第一输出端和所述电源隔离器的第二输出端电连接；所述第四电容的两端分别与所述第二输入电压端和所述第二参考电压端电连接。
例如，在所述供电时序控制电路的至少一个示例中，所述辅助输出子电路还包括第五电容、第六电容、第七电容、第八电容；所述第五电容的两端 分别与所述电源隔离器的第一输入端和所述第三参考电压端电连接；所述第六电容的两端分别与所述电源隔离器的第二输入端和所述第三参考电压端电连接；所述第七电容的两端分别与所述电源隔离器的第一输出端和所述第三参考电压端电连接；所述第八电容的两端分别所述电源隔离器的第二输出端和所述第三参考电压端电连接。
例如，在所述供电时序控制电路的至少一个示例中，所述辅助输出子电路还包括第一电阻以及第二电阻；所述第一电阻的两端分别所述第二输入电压端和所述第二参考电压端电连接；所述第二电阻与所述第一电阻并联，且所述第二电阻的两端分别与所述第二输入电压端和所述第二参考电压端电连接。
例如，在所述供电时序控制电路的至少一个示例中，所述输出子电路包括开关晶体管和驱动晶体管；所述开关晶体管的栅极与所述延时检测子电路电连接，以接收所述触发信号；所述驱动晶体管的栅极与所述开关晶体管的第二极电连接；所述驱动晶体管的第一极与所述第一输入电压端电连接，以接收所述第一输入电压端提供的第一电压；所述驱动晶体管的第二极与所述信号输出端电连接；所述驱动晶体管被配置为将所述触发信号将第一输入电压端提供的第一电压提供至所述驱动晶体管的第二极；所述信号输出端被配置为允许位于所述驱动晶体管的第二极的第一电压从所述信号输出端输出。
例如，在所述供电时序控制电路的至少一个示例中，供电时序控制电路还包括辅助输出子电路。所述辅助输出子电路与所述输出子电路电连接；所述辅助输出子电路还与第二输入电压端和第二参考电压端电连接；所述开关晶体管的第一极与所述第二输入电压端电连接，以接收所述第二输入电压端提供的与所述第一电压隔离的第二电压；所述开关晶体管的第二极与所述第二参考电压端电连接，以接收所述第二参考电压端提供的与所述第一参考电压隔离的第二参考电压；所述驱动晶体管的第二极还与所述第二参考电压端电连接。
例如，在所述供电时序控制电路的至少一个示例中，所述输出子电路还包括：第三电阻、第四电阻以及第五电阻；所述第三电阻的两端分别与所述第二输入电压端和所述延时检测子电路的输出端电连接；所述第四电阻的两端分别与所述延时检测子电路的输出端和所述开关晶体管的栅极电连接；所 述第五电阻的两端分别与所述开关晶体管的第二极和所述第二参考电压端电连接。
例如，在所述供电时序控制电路的至少一个示例中，所述延时控制子电路与第一参考电压端电连接；所述延时控制子电路包括可调电阻和第九电容；所述可调电阻的第一端与所述第一输入电压端电连接，所述可调电阻的第二端与所述第九电容的第一端电连接；所述第九电容的第二端与所述第一参考电压端电连接。
例如，在所述供电时序控制电路的至少一个示例中，所述可调电阻的调节范围为1k～10MΩ。
例如，在所述供电时序控制电路的至少一个示例中，所述延时检测子电路还与第一参考电压端电连接；所述延时检测子电路包括比较器、第六电阻、第七电阻、第八电阻以及第十电容；所述比较器的正向输入端与所述延时控制子电路电连接，所述比较器的负向输入端与所述第八电阻的第一端电连接，所述比较器的输出端与所述输出子电路电连接；所述第八电阻的第二端与所述第六电阻的第一端和所述第七电阻的第一端电连接；所述第六电阻的第二端与所述第一输入电压端电连接；所述第七电阻的第二端与所述第一参考电压端电连接；所述第十电容的两端分别与所述第一参考电压端和所述比较器的与所述第一输入电压端电连接。
本公开的至少一个实施例还提供了一种显示驱动电路，其包括本公开任一实施例提供的供电时序控制电路。
例如，在所述显示驱动电路的至少一个示例中，所述显示驱动电路还包括电源管理芯片；所述电源管理芯片具有输入端和多个电压输出端；所述电源管理芯片被配置为根据所述输入端接收到的初始电压，生成多个输出电压；所述多个输出电压被配置为分别由所述多个电压输出端输出；所述电源管理芯片的多个所述电压输出端的一个与所述供电时序控制电路的第一输入电压端电连接。
例如，在所述显示驱动电路的至少一个示例中，所述显示驱动电路包括多个所述供电时序控制电路；所述电源管理芯片的多个所述电压输出端分别与多个所述供电时序控制电路的第一输入电压端电连接，以分别向多个所述供电时序控制电路的第一输入电压端提供多个输出电压；所述多个所述供电 时序控制电路被配置为控制所述多个输出电压的供电时序。
例如，在所述显示驱动电路的至少一个示例中，所述显示驱动电路还包括时序控制器、源极驱动器以及栅极驱动器；所述供电时序控制电路的信号输出端与所述时序控制器、所述源极驱动器或者所述栅极驱动器的一个电连接；所述时序控制器、所述源极驱动器或者所述栅极驱动器还与第一参考电压端电连接。
例如，在所述显示驱动电路的至少一个示例中，所述显示驱动电路还包括源极驱动器以及被配置为生成多个灰阶基准电压的灰阶电压生成器；所述灰阶电压生成器包括多个灰阶基准输出端，每个灰阶基准输出端被配置为输出一个所述灰阶基准电压；所述灰阶电压生成器的多个所述灰阶基准输出端的一个与所述供电时序控制电路的第一输入电压端电连接；所述供电时序控制电路的信号输出端与所述源极驱动器电连接；所述源极驱动器还与所述第一参考电压端电连接。
本公开的至少一个实施例又提供了一种显示装置，其包括本公开任一实施例提供的显示驱动电路。
例如，在所述显示装置的至少一个示例中，所述显示装置还包括显示面板，所述显示面板包括公共电极层；所述供电时序控制电路的第一输入电压端与电源管理芯片中被配置为输出公共电压的电压输出端电连接；以及所述供电时序控制电路的信号输出端与所述公共电极层电连接。
本公开的至少一个实施例又再提供了一种控制本公开任一实施例提供的供电时序控制电路的方法，其包括：所述延时控制子电路将所述第一输入电压端输出的所述第一电压延时所述预设时间后输出；所述延时检测子电路在接收到所述第一电压时，向所述输出子电路发送所述触发信号；所述输出子电路响应于所述触发信号处于开启状态，并将所述第一输入电压端提供的第一电压输出至所述信号输出端。
例如，在所述方法的至少一个示例中，在所述供电时序控制电路还包括所述辅助输出子电路的情况下，所述输出子电路被配置为响应所述触发信号处于开启状态，以将所述第一输入电压端提供的第一电压输出至所述信号输出端，在所述第一电压输出至所述信号输出端之后，所述方法还包括：所述辅助输出子电路控制所述输出子电路在接收到所述触发信号后，保持所述开 启状态。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为本公开的至少一个实施例提供的一种供电时序控制电路的示例性框图；
图2A为本公开的至少一个实施例提供的一种供电时序图；
图2B为本公开的至少一个实施例提供的一种电源管理芯片输出的驱动电压的时序示意图；
图3A为本公开的至少一个实施例提供的另一种供电时序控制电路的示例性框图；
图3B是本公开的至少一个实施例提供的供电时序控制电路的再一种示例性框图；
图3C是本公开的至少一个实施例提供的供电时序控制电路的再一种示例性框图；
图4为图3A中辅助输出子电路的结构示意图；
图5为本公开的至少一个实施例提供的输出子电路的一种结构示意图；
图6为图3A中输出子电路的另一种结构示意图；
图7为本公开的至少一个实施例提供的另一种供电时序控制电路的结构示意图；
图8为本公开的至少一个实施例提供的再一种供电时序控制电路的结构示意图；
图9为本公开的至少一个实施例提供的一种供电时序控制电路的控制方法流程图；
图10为本公开的至少一个实施例提供的一种显示装置的结构示意图；
图11为本公开的至少一个实施例提供的另一种显示装置的结构示意图；以及
图12是本公开的至少一个实施例提供的显示驱动电路的示例性框图。
具体实施方式
为使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合本公开的实施例的附图，对本公开的实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人在研究中注意到，尽管可以采用软件编程(Code)对显示装置的驱动电路的供电时序进行控制，然而由于软件编程自身可能出现缺陷(Bug)，从而可能导致实际的供电时序与预设的供电时序之间存在偏差，并可能导致显示异常的出现。
本公开的至少一个实施例提供了一种供电时序控制电路01，该供电时序控制电路01可作为显示装置的部件，以用于控制显示面板的上电时序(power sequence)或供电时序。例如，供电时序控制电路01可以通过纯硬件来控制显示面板的上电时序，因此，相比于通过软件编程控制显示面板的上电时序，供电时序控制电路01可以更为精确的控制显示面板的上电时序，由此可以避免潜在的显示面板的上电时序异常导致的显示不良。
图1是本公开的至少一个实施例提供的供电时序控制电路01的一种示例性框图。如图1所示，该供电时序控制电路01可以包括延时控制子电路10、延时检测子电路20以及输出子电路30。如图1所示，该供电时序控制电路01包括第一输入电压端VIN1和信号输出端Vout。
如图1所示，延时控制子电路10与第一输入电压端VIN1电连接，以接收第一输入电压端VIN1输出的第一电压V1。该延时控制子电路10用于将第一输入电压端VIN1输出的第一电压V1延时一预设时间T后输出。
需要说明的是，将第一电压V1延时一预设时间T后输出是指在延时控制子电路10接收到第一电压V1之后(例如，延时控制子电路10在T0时刻接收到第一电压V1)的预设时间T，延时控制子电路10输出的电压实质上等于第一电压V1(例如，在T0+T时刻，延时控制子电路10输出的电压实质上等于第一电压V1)。例如，在T0时刻至T0+T时刻之间的时间段，延时控制子电路10也可以输出电压，但输出的电压的电压值小于第一电压V1。为清楚起见，延时控制子电路10的具体的电路结构将在阐述输出子电路30之后详述，在此不再赘述。
需要说明的是，上述第一电压V1可以是例如由电源管理电路提供的，并用于提供给显示面板的任意一个驱动电压(例如，数字工作电压DVDD、模拟电压AVDD、栅关闭电压VGL、栅开启电压VGH中的任意一个)。例如，在包括该供电时序控制电路01的显示装置中，上述第一电压V1可以是用于向源极驱动器提供的模拟电压AVDD或者数字电压DVDD(也被称为数字工作电压)。此外，上述第一电压V1还可以是用于向栅极驱动器提供的第一工作电压VGH和第二工作电压VGL，此处，第一工作电压VGH的电压值大于第二工作电压VGL的电压值。又例如，第一电压V1还可以是提供给源极驱动器的灰阶基准电压VGMA，提供给栅极驱动器提供的数字电压DVDD，或者提供给显示面板的公共电极层的公共电压Vcom。
在一个示例中，电源管理电路提供的至少一个驱动电压的供电时刻(例如，上升沿或下降沿的终止时刻)偏离预定的供电时刻(也即，上电时序存在异常)，并导致显示面板的供电时序不满足实际应用需求；此种情况下，可以将上述驱动电压中任意一个需要被控制(或被调节)的电压作为第一电压V1提供给供电时序控制电路01，并通过采用延时控制子电路10和供电时 序控制电路01对第一电压V1(也即，需要被控制或被调节的电压)延时一预设时间T后输出，以使得提供给显示面板的驱动电压的时序满足实际应用需求，由此可以更为精确的控制显示面板的上电时序，避免潜在的显示面板的上电时序异常导致的显示不良。
本公开的实施例还提供一种显示驱动电路，包括至少一个如上所述的供电时序控制电路01。本公开的一些实施例又提供了一种显示装置。图10为本公开的实施例提供的一种显示装置的结构示意图。该显示装置包括显示驱动电路和显示面板，如图10所示，显示驱动电路包括多个供电时序控制电路01。如图10所示，上述显示驱动电路还包括电源管理芯片51(或其他适用的电源管理电路)。该电源管理芯片51具有多个电压输出端，且该电源管理芯片用于根据输入端接收到的初始电压VDD(例如，5伏或12伏)，生成多个输出电压(例如，数字工作电压DVDD、模拟电压AVDD、栅关闭电压VGL、栅开启电压VGH)，并由不同的电压输出端输出。需要说明的是，显示驱动电路还可以仅包括一个或两个供电时序控制电路01。
例如，如图10所示，图像处理器(或者接口连接器)52可以向上述电源管理芯片51提供初始电压VDD。
例如，上述电源管理芯片51的每个电压输出端与一个供电时序控制电路01的第一输入电压端VIN1电连接。例如，电源管理芯片51的多个电压输出端与多个供电时序控制电路01一一对应；电源管理芯片51的多个电压输出端分别与多个供电时序控制电路01的第一输入电压端VIN1电连接，由此，电源管理芯片输出的多个输出电压分别提供给对应的供电时序控制电路01。
例如，与电源管理芯片51相连接的各个供电时序控制电路01可以根据需要依次将电源管理芯片51生成多个输出电压(或者驱动电压，例如，DVDD、AVDD、VGL、VGH)按照预设的供电时序，依次输出至对应的负载。例如，上述负载可以为时序控制器、源极驱动器或栅极驱动器，且这些负载可以是显示装置的组成部分。
例如，供电时序(或上电时序)可以是电源管理芯片51生成的多个输出电压(或者驱动电压)提供给负载的顺序。
图2A示出了一种显示面板(或显示装置)的供电时序示意图。如图2A所示，DVDD、AVDD、VGL、VGH分别在t1时刻、t2时刻、t3时刻和t4 时刻提供给对应的负载，且t1<t2<t3<t4；此种情况下，显示面板(或显示装置)的预设供电时序依次为：DVDD、AVDD、VGL、VGH。例如，图2A示出的显示面板(或显示装置)的供电时序是显示面板所需的供电时序(或者是一种正确的供电时序)。需要说明的是，为描述方便，t1、t2、t3和t4既可以分别表示t1时刻、t2时刻、t3时刻和t4时刻，也可以分别表示t1时刻、t2时刻、t3时刻和t4时刻相比于t0时刻的时间差。
例如，在显示装置中，供电时序控制电路01所连接的负载(例如上述源极驱动器或栅极驱动器)需要先接收到DVDD后，才能够进行工作。因此，DVDD优先于AVDD供电至上述负载。例如，VGH和VGL由AVDD生成，因此AVDD需要在VGH和VGL之前供电(例如，需要在向相应的负载提供VGH和VGL之前提供AVDD)。例如，由于VGL的电压较低，例如可以为-8V，而VGH的电压较高，例如可以为30V。因此，为了避免在开机时刻向显示装置中的驱动电路提供幅值较高的电压，而导致上述驱动电路发生过流保护或过温保护，或者导致用于生成上述供电电压的电源管理芯片(Power IC)发生过流保护或过温保护，可以在开机时刻向上述驱动电路提供幅值较低的电压(例如上述VGL)，然后再提供幅值较高的电压(例如上述VGH)。所以VGL的供电时间可以优先于VGH。
在一个示例中，假设电源管理芯片51输出的DVDD、AVDD、VGH、VGL的上升沿(或下降沿)的终止点均为t0时刻(假设t0＝0)，并且当上述电源管理芯片51输出的供电电压：DVDD、AVDD、VGH、VGL分别输入至四个不同的供电时序控制电路01中延时控制子电路10所连接的第一输入电压端VIN1时，为获得图2A所示的供电时序，接收DVDD的供电时序控制电路01中延时控制子电路10的延时时间(例如，等于t1)大于接收AVDD的供电时序控制电路01中延时控制子电路10的延时时间(例如，等于t2)；接收AVDD的供电时序控制电路01中延时控制子电路10的延时时间(例如，等于t2)大于接收VGL的供电时序控制电路01中延时控制子电路10的延时时间(例如，等于t3)；接收VGL的供电时序控制电路01中延时控制子电路10的延时时间(例如，等于t3)大于接收VGH的供电时序控制电路01中延时控制子电路10的延时时间(例如，等于t4)。
图2B示出了一种电源管理芯片51输出的驱动电压(例如，DVDD、 AVDD、VGH、VGL)的时序示意图。
在另一个示例中，假设电源管理芯片51输出的DVDD、AVDD、VGH、VGL如图2B所示，也即，DVDD、VGH和VGL的供电时序满足要求，但是相比于预定的供电时刻，AVDD的供电时刻超前的时间等于t2-t5，此种情况下，相比于接收DVDD(或VGH、VGL)的供电时序控制电路01中延时控制子电路10的延时时间，接收AVDD的供电时序控制电路01中延时控制子电路10的延时时间需额外增加t2-t5。
下面结合图3A-图3C对本公开的至少一个实施例提供的供电时序控制电路01进行示例性说明。
图3A是本公开的至少一个实施例提供的供电时序控制电路01的另一种示例性框图。
例如，在本公开的一些实施例提供的供电时序控制电路01中，可以通过延时控制子电路10，根据需要对第一输入电压端VIN1输出的第一电压V1的输出时间进行延时。例如，由于供电时序控制电路01可以通过纯硬件来控制第一电压V1的输出时间，因此，相比于通过软件编程控制第一电压V1的输出时间，供电时序控制电路01可以更为精确的控制第一电压V1的输出时间。因此，在将供电时序控制电路01(例如，多个供电时序控制电路01)用于控制显示面板的上电时序情况下，相比于通过软件编程控制显示面板的上电时序，供电时序控制电路01可以更为精确的控制显示面板的上电时序，由此可以避免潜在的显示面板的上电时序异常导致的显示不良。
如图3A所示，延时检测子电路20与上述延时控制子电路10(例如，延时控制子电路10的输出端)和输出子电路30(例如，输出子电路30的输入端)电连接。该延时检测子电路20用于在接收到电压值实质上等于第一电压V1的电压值的电压时(例如，在完成预设时间T延迟后，也即，在T0+T时刻)，向输出子电路30发送触发信号Em。
例如，如图3A所示，上述输出子电路30还与上述第一输入电压端VIN1以及信号输出端Vout(例如，供电时序控制电路01的信号输出端Vout)电连接。该输出子电路30被配置为根据延时检测子电路20输出的触发信号Em处于开启状态，并将第一输入电压端VIN1的第一电压V1输出至信号输出端Vout。
如图3A所示，在一些示例中，该供电时序控制电路01还可以包括辅助输出子电路40。
图3B是本公开的至少一个实施例提供的供电时序控制电路01的再一种示例性框图。相比于图3A所示的供电时序控制电路01，图3B所示的供电时序控制电路01还示出了输出子电路30和辅助输出子电路40的输入端和输出端。
例如，如图3B所示，输出子电路30包括第一信号输入端InP1、第二信号输入端InP2、第三信号输入端InP3和信号输出端OUPT1；输出子电路30的第一信号输入端InP1被配置为与延时检测子电路20的输出端相连，以接收触发信号Em；输出子电路30的第二信号输入端InP2被配置接收第一电压V1或被配置第二电压V2(图3B中未示出，参见图8)；输出子电路30的第三信号输入端InP3被配置为接收第一参考电压(图3B中未示出，参见图6)或被配置为接收第二参考电压。
如图3B所示，辅助输出子电路40包括第一输入端InP4、第二输入端InP5、第一输出端OUPT2和第二输出端OUPT3。例如，如图3B和图8所示，辅助输出子电路40的第一输入端InP4和辅助输出子电路40的第二输入端InP5分别与第一输入电压端VIN1和第一参考电压端Vref电连接相连，辅助输出子电路40被配置为基于第一输入电压端VIN1输出的第一电压V1(例如，DVDD)以及第一参考电压端Vref提供的第一参考电压(例如GND1)生成第二电压V2和第二参考电压(例如GND2)。例如，第二电压V2和第二参考电压(例如GND2)分别经由辅助输出子电路40的第二输出端OUPT3和辅助输出子电路40的第一输出端OUPT2输出。
图3C是本公开的至少一个实施例提供的供电时序控制电路01的再一种示例性框图。相比于图3B所示的供电时序控制电路01，图3C所示的供电时序控制电路01还示出了辅助输出子电路40与输出子电路30、第一输入电压端VIN1和第一参考电压端Vref的连接关系。
例如，如图3C所示，在输出子电路30的第三信号输入端InP3被配置为接收第二参考电压的情况下，辅助输出子电路40的第一输出端OUPT2与输出子电路30的第三信号输入端InP3相连。例如，如图3C所示，输出子电路30的第二信号输入端InP2被配置接收第二电压V2的情况下，辅助输 出子电路40的第二输出端OUPT3与输出子电路30的第二信号输入端InP2相连。例如，图3C所示的供电时序控制电路01可以使得输出子电路30可以将第一输入电压端VIN1提供的第一电压持续从供电时序控制电路01的信号输出端Vout输出。
下面结合图4-图8所示的电路结构对本公开的至少一个实施例提供的供电时序控制电路01进行示例性说明。
例如，图6示出了本公开的至少一个实施例提供的一种输出子电路30的电路结构的示例图，为方便描述，图6还示出了延时检测子电路20。例如，图6示出的输出子电路30可能使得供电时序控制电路01的信号输出端Vout无法持续输出第一电压V1，下面结合图6做具体说明。
例如，为了使得输出子电路30能够将第一输入电压端VIN1的第一电压V1传输至信号输出端Vout。上述输出子电路30可以包括一与第一输入电压端VIN1和信号输出端Vout电连接的晶体管。例如，如图6所示，该输出子电路30可以包括一驱动晶体管Qd，该驱动晶体管Qd的第一极(例如源极s或者漏极d)与上述第一输入电压端VIN1电连接；驱动晶体管Qd的第二极(例如漏极d或者源极s)与上述信号输出端Vout电连接。
例如，上述输出子电路30还可以包括一开关晶体管Qc。该开关晶体管Qc的栅极与延时检测子电路20(延时检测子电路20的输出端)电连接，以接收延时检测子电路20输出的触发信号Em；开关晶体管Qc的一极(例如第二极)与上述驱动晶体管Qd的栅极电连接；开关晶体管Qc的另一极(例如第一极)与第一输入电压端VIN1电连接，以接收第一输入电压端VIN1输出的第一电压V1。在此情况下，当上述开关晶体管Qc导通后(例如，在开关晶体管Qc的栅极接收到触发信号Em或有效电平后)，通过导通的开关晶体管Qc并输入至该驱动晶体管Qd的栅极的电压(也即，源于第一输入电压端VIN1的第一电压V1)，可以使得驱动晶体管Qd导通；在驱动晶体管Qd导通后，驱动晶体管Qd可以将第一输入电压端VIN1提供的第一电压V1传输至信号输出端Vout。
在一些实施例中，如图6所示，开关晶体管Qc的第一极可以与第一输入电压端VIN1电连接，开关晶体管Qc的第二极与驱动晶体管Qd的栅极电连接。此外，开关晶体管Qc的第二极以及驱动晶体管Qd的第二极还与第一 参考电压端Vref1电连接。在此情况下，当开关晶体管Qc导通后，输入至驱动晶体管Qd栅极的电压为第一输入电压端VIN1的第一电压V1，即驱动晶体管Qd的栅极电压Vg＝V1，此时，当驱动晶体管Qd导通后，该驱动晶体管Qd的漏极电压Vd、源极电压Vs以及栅极电压Vg均等于第一电压V1。此种情况下，驱动晶体管Qd的栅源电压小于驱动晶体管Qd的阈值电压(Vgs＝Vg-Vs＝0＜Vth)，因此，驱动晶体管Qd不再满足导通条件Vgs＞Vth，此时，该驱动晶体管Qd将截止，从而使得信号输出端Vout无信号输出(也即，信号输出端Vout不能持续输出第一电压V1)，进而导致整个供电时序控制电路01出现输出间断的问题。在此情况下，信号输出端Vout无法向与其连接的负载继续(或持续)提供供电电压。
例如，通过设置辅助输出子电路40，可以使得输出子电路30允许供电时序控制电路01的信号输出端Vout持续输出第一电压V1，下面结合图3A-图3C、图4-图5、图7和图8具体说明。
例如，如图3A-图3C所示，该供电时序控制电路01还包括辅助输出子电路40。该辅助输出子电路40与上述输出子电路30电连接。该辅助输出子电路40可以被配置为控制输出子电路30，以使得在开关晶体管Qc的栅极接收到上述触发信号EM后，驱动晶体管Qd可以保持在开启状态。
例如，辅助输出子电路40被配置为基于第一电压V1和第一参考电压输出第二电压V2和第二参考电压。例如，第一电压V1(第一参考电压)与第二电压V2(第二参考电压)彼此隔离。例如，第一电压V1与第二电压V2彼此不同，第一参考电压与第二参考电压彼此不同，第一电压V1与第一参考电压之间的电压差例如可以等于第二电压V2与第二参考电压之间的电压差。例如，V2大于V1。
以下对该辅助输出子电路40以及与该辅助输出子电路40电连接的上述输出子电路30的具体结构进行详细的说明。
如图4所示，上述辅助输出子电路40还与第一输入电压端VIN1、第一参考电压端Vref1、第二输入电压端VIN2、第二参考电压端Vref2以及第三参考电压端Vref3电连接。此外，上述辅助输出子电路40还包括电源隔离模块401。例如，电源隔离模块401可以实现为电源隔离器，电源隔离器可以由电路实现。
例如，第一输入电压端VIN1和第一参考电压端Vref1被配置为与辅助输出子电路40的输入端相连，第二输入电压端VIN2和第二参考电压端Vref2被配置为与辅助输出子电路40的输出端相连；辅助输出子电路40被配置为基于第一电压V1和第一参考电压输出第二电压V2和第二参考电压，第二电压V2和第二参考电压被配置为分别提供给第二输入电压端VIN2和第二参考电压端Vref2。
如图4所示，该电源隔离模块401的第一输入端In1与第一输入电压端VIN1电连接。电源隔离模块401的第二输入端In2与第一参考电压端Vref1和第三参考电压端Vref3电连接。电源隔离模块401第一输出端Out1与第二输入电压端VIN2电连接。电源隔离模块401的第二输出端Out2与第二参考电压端Vref2和第三参考电压端Vref3电连接。
例如，上述电源隔离模块401被配置为根据第一输入电压端VIN1提供的第一电压V1，第一参考电压端Vref1提供的第一参考电压(例如GND1)，以及第三参考电压端Vref2提供的第三参考电压(例如壳体电压)，向第二输入电压端VIN输出与第一电压V1隔离的第二电压V2。例如，该第二输入电压端VIN与输出子电路30的开关晶体管Qc的第一极电连接，且配置为向输出子电路30的开关晶体管Qc的第一极提供第二电压V2。
需要说明的是，上述电源隔离模块401中可以包括开关电源拓扑结构(例如，开关电源拓扑电路)。在此情况下，在该电源隔离模块401的作用下，可以使得输入至电源隔离模块401的第一参考电压端Vref1的第一参考电压GND1与该电源隔离模块401的第二参考电压端Vref2输出的第二参考电压GND2的电压值不同。
此时，第一输入电压端VIN1输入的第一电压V1与第二输入电压端VIN2输出与第二电压V2隔离是指，第一输入电压端VIN1的电位的参考点(上述第一参考电压GND1)和第二输入电压端VIN2的电位的参考点(上述第二参考电压GND2)不相同。在此情况下，第一输入电压端VIN1输入的第一电压V1与第二输入电压端VIN2输出与第二电压V2没有共地，因此互不干扰。
在此基础上，经过上述电源隔离模块401的隔离作用后，第一电压V1与第一参考电压GND1的电压差值，可以与第二电压V2第二参考电压GND2 的电压差值相同。示例性的，第一电压V1＝5V，第一参考电压GND1＝0V；第二电压V2＝10V，第二参考电压GND2＝5V。这样一来，当将电源隔离模块401与输出子电路30电连接后，电源隔离模块401可以用于向输出子电路30提供隔离后的电压，而不会对输出子电路30的信号输出端(或者供电时序控制电路01的信号输出端Vout)的输出产生影响(例如，不利影响)。例如，电源隔离模块401不仅不会导致信号输出端Vout的输出无法持续。例如，通过设置电源隔离模块401，可以使得信号输出端Vout持续输出第一电压V1。
例如，对于图8所述的供电时序控制电路01，在驱动晶体管Qd导通之前，驱动晶体管Qd的栅极电压Vg、漏极电压Vd和源极电压Vs分别等于第二电压V2、第一电压V1(例如，DVDD)和第二参考电压Vref2(例如，接地电压，也即，0伏)，此种情况下，驱动晶体管Qd的栅源电压Vgs大于驱动晶体管Qd的阈值电压(例如，Vgs＝Vg-Vs＝V2＞Vth)，因此，驱动晶体管Qd导通。
例如，对于图8所述的供电时序控制电路01，在驱动晶体管Qd导通之后，驱动晶体管Qd的栅极电压Vg、漏极电压Vd和源极电压Vs分别等于第二电压V2、第一电压V1(例如，DVDD)和第一电压V1(例如，DVDD)，此种情况下，驱动晶体管Qd的栅源电压Vgs大于驱动晶体管Qd的阈值电压(例如，Vgs＝Vg-Vs＝V2-V1＞Vth)，因此，驱动晶体管Qd依然处于导通状态。例如，由于电源隔离模块401的隔离作用，电源隔离模块401提供的第二电压V2和第二参考电压GND2均不会干扰驱动晶体管Qd的漏极电压Vd的电压(也即，信号输出端Vout输出的电压)，因此，驱动晶体管Qd可以持续保持导通状态，并持续输出第一电压V1。
例如，供电时序控制电路01的信号输出端Vout被配置为接收驱动晶体管Qd的源极电压Vs输出的第一电压V1，并将该第一电压V1作为供电时序控制电路01的输出。例如，在设置电源隔离模块401之后，由于电源隔离模块401的隔离作用，供电时序控制电路01的信号输出端Vout可以持续输出开启的驱动晶体管Qd提供的第一电压V1，而不受电源隔离模块401提供给输出子电路30的第二电压V2和第二参考电压GND2影响。
在此基础上，为了提高辅助输出子电路40输出信号的稳定性，在一些实施例中，如图4所示，上述输出子电路40还可以包括第一电容C1、第二电 容C2、第三电容C3、第四电容C4。
其中，第一电容C1的两端分别与第一输入电压端VIN1和第一参考电压端Vref1电连接。
第二电容C2的两端分别与电源隔离模块401的第一输入端In1和电源隔离模块401的第二输入端In2电连接。
第三电容C3的两端分别与电源隔离模块401的第一输出端Out1和电源隔离模块401的第二输出端Out2电连接。
第四电容C4的两端分别与第二输入电压端VIN2和第二参考电压端Vref2电连接。
由上述可知，上述第一电容C1、第二电容C2、第三电容C3、第四电容C4中的任意一个电容的两端分别与正电压端和负电压端连接，因此上述电容均为X电容，用于消除差模干扰和辐射。
此外，上述辅助输出子电路40还可以包括第五电容C5、第六电容C6、第七电容C7、第八电容C8。
其中，第五电容C5的两端分别与电源隔离模块401的第一输入端In1和第三参考电压端Vref3电连接。
第六电容C6的两端分别与电源隔离模块401的第二输入端In2和第三参考电压端Vref3电连接。
第七电容C7的两端分别与电源隔离模块401的第一输出端Out1和第三参考电压端Vref3电连接。
第八电容C8的两端分别电源隔离模块401的第二输出端Out2和第三参考电压端Vref3电连接。
由上述可知，上述第五电容C5、第六电容C6、第七电容C7、第八电容C8中的任意一种电容的两端分别连接正(或负)电压端与接地端(例如GND1、GND2或壳体)，因此上述电容为Y电容，用于消除共模干扰。
此外，上述辅助输出子电路40还可以包括第一电阻R1以及第二电阻R2。
其中，第一电阻R1的两端分别第二输入电压端VIN2和第二参考电压端Vref2电连接。
第二电阻R2的两端分别与第二输入电压端VIN2和第二参考电压端 Vref2电连接。
上述第一电阻R1与第二电阻R2并联，用于减小第二输入电压端VIN2和第二参考电压端Vref2输出的电压产生波动的几率，以达到稳压的目的。
例如，在辅助输出子电路40与第二输入电压端VIN2以及第二参考电压端Vref2电连接的情况下，为了使得上述辅助输出子电路40与输出子电路30电连接，在另一些实施例中，如图5所示，上述输出子电路30中的开关晶体管Qc的第一极与第二输入电压端VIN2电连接，开关晶体管Qc的第二极与第二参考电压端Vref2电连接。
上述输出子电路30中的驱动晶体管Qd的栅极与开关晶体管Qc的第二极电连接，驱动晶体管Qd的第一极与第一输入电压端VIN1电连接，驱动晶体管Qd的第二极与信号输出端Vout和第二参考电压端Vref2电连接。
需要说明的是，上述开关晶体管Qc和驱动晶体管Qd中任意一个晶体管的第一极可以源极，第二极可以为漏极；或者第一极为漏极，第二极源极。本公开的一些实施例对上述晶体管的类型不做限定，述开关晶体管Qc和驱动晶体管Qd中任意一个晶体管可以为三极管、TFT(Thin Film Transistor，简称薄膜晶体管)或者MOS(Metal-Oxide-Semiconductor，金属-氧化物-半导体)晶体管。
由于上述驱动晶体管Qd需要连接负载(例如，显示装置的源极驱动器或栅极驱动器)，因此要求驱动晶体管Qd具备一定的带载能力(也即，驱动晶体管Qd输出的驱动电流需要大于预定电流值)，例如在上述供电时序控制电路01应用于显示装置时。带载能力(也即，驱动晶体管Qd输出的驱动电流)在60A以上。由于MOS晶体管更容易获得较大的带载能力，因此在本公开的一些实施例中，上述驱动晶体管Qd可以为MOS晶体管。
本公开的一些实施例的附图是以开关晶体管Qc为三极管，驱动晶体管Qd为MOS晶体管为例对本公开的实施例进行说明，但本公开的实施例不限于此。
例如，为了提高输入至驱动晶体管Qd第二极输出电压的稳定性，上述输出子电路30还可以包括：第三电阻R3、第四电阻R4以及第五电阻R5。
如图4和图6所示，第三电阻R3的两端分别与第二输入电压端VIN2和延时检测子电路20电连接。第四电阻R4的两端分别与延时检测子电路20 和开关晶体管Qc的栅极电连接。第五电阻R5的两端分别与开关晶体管Qc的第二极和第二参考电压端Vref2电连接。
由上述描述可知，图4所示的辅助输出子电路40和图5所示的输出子电路30，均连接至第二输入电压端VIN2和第二参考电压端Vref2。因此，可以通过上述第二输入电压端VIN2和第二参考电压端Vref2实现辅助输出子电路40与输出子电路30的电连接。使得输出子电路30接收到辅助输出子电路40输出的隔离后的第一电压V1和第二参考电压Vref2。
在此情况下，为了解决上述驱动晶体管Qd导通后无法继续保持导通状态的问题，本公开的一些实施例中将输出子电路40与输出子电路30通过第二输入电压端VIN2和第二参考电压端Vref2电连接后，辅助输出子电路40由第二输入电压端VIN2输出与第一电压V1隔离的第二电压V2，能够提供至图5中开关晶体管Qc的第一极。
在此情况下，当延时检测子电路20输出的电压控制上述开关晶体管Qc导通后，第二输入电压端VIN2输出的第二电压V2可以通过开关晶体管Qc传输至驱动晶体管Qd的栅极，此时驱动晶体管Qd导通，第一输入电压端VIN1输出的第一电压V1可以通过驱动晶体管Qd传输至信号输出端Vout。
例如，当驱动晶体管Qd导通后，驱动晶体管Qd的漏极电压Vd、源极电压Vs相等，即Vd＝Vs＝V1。此时，驱动晶体管Qd的栅极电压Vg＝V2。由于在上述辅助输出子电路40中电源隔离模块401的隔离作用下，第一电压V1和第二电压V2相互隔离，根据第一电压V1和第二电压V2无法直接计算获得驱动晶体管Qd的栅源电压Vgs，所以当驱动晶体管Qd导通后，该驱动晶体管Qd的源极电压Vs的大小不会对驱动晶体管Qd导通状态产生影响(例如，不能使得驱动晶体管Qd从开启变为关闭)，从而使得该驱动晶体管Qd继续保持导通状态。
以下结合图7对图1中其余子电路(也即，延时控制子电路10和延时检测子电路20)的电路结构进行详细的说明。
如图7所示，上述延时控制子电路10与第一参考电压端Vref1电连接。延时控制子电路10包括可调电阻Rc和第九电容C9。
上述可调电阻Rc的一端(也即，第一端)与第一输入电压端VIN1电连接，可调电阻Rc的另一端(也即，第二端)与第九电容C9的一端(也即， 第一端)电连接。第九电容C9的第一端被配置为延时控制子电路10的输出端。
此外，该第九电容C9的另一端(也即，第二端)与第一参考电压端Vref1电连接。此处，该第九电容C9可以为普通电容，或者可以为电解电容，本公开的实施例对此不做限定。
在此情况下，可以调节可调电阻Rc的电阻值R，以使得第九电容C9的电容电压Vc9增加至(通过充电增加至)第一电压V1的时间Tc(也即，第九电容C9的充电时间)与预设时间T相等，由此使得延时控制子电路10可以将上述第一电压V1延时预设时间T之后输出。
第九电容C9的充电时间满足以下表达式：Tc＝T＝α×R×C。此处，α为与电容电压上升时间(Rising Time)相关的常数；R为可调电阻Rc的电阻值；C为第九电容C9的电容值。由上述表达式可知，当可调电阻Rc的电阻值R越大时，第九电容C9的充电时间越长，由此使得预设时间T越大；当可调电阻Rc的电阻值R越小时，第九电容C9的充电时间越短，由此使得预设时间T越小。
例如，当本公开的一些实施例提供的供电时序控制电路01应用于显示装置时，可以基于上述第一输入电压端VIN1提供的第一电压V1设定可调电阻Rc的电阻调节范围。例如，上述可调电阻Rc的电阻调节范围可以为1kΩ～10MΩ。当可调电阻Rc的电阻值小于1kΩ时，尽管预设时间T的调节精度较高，但是，预设时间T的调节范围较小，由此增加了供电时序(显示面板的上电时序)的调节难度。此外，当可调电阻Rc的调节数值大于10MΩ时，预设时间T和第九电容C9的充电时间Tc会超出开机供电时间的上限，导致开机延时。
例如，如图7所示，上述延时检测子电路20还与第一参考电压端Vref1电连接。第一参考电压端Vref1例如接地。
如图7所示，该延时检测子电路包括比较器201、第六电阻R6、第七电阻R7、第八电阻R8以及第十电容C10。
该比较器201的第一输入端(正向输入端)与延时控制子电路10电连接，比较器201的第二输入端(负向输入端)与第八电阻R8的一端(第一端)电连接。
如图7所示，上述比较器201的正向输入端与该延时控制子电路10中第九电容C9的第一端(也即，延时控制子电路10的输出端)相连接。此外，为了使得比较器201能够更好的工作，该比较器201还可以连接一正向工作电压(例如，第一输入电压端VIN1提供的第一电压V1)和一负工作向电压(例如，第一参考电压端Vref1的第一参考电压GND1)。本公开的实施例对上述正向工作电压和负向工作电压的大小不做限定，只要能够驱动比较器201进行工作即可。例如，正向工作电压大于零伏，负向工作电压小于等于零伏。
如图7所示，该比较器201的输出端与输出子电路30电连接。在该输出子电路30的结构如上所述时，上述比较器201的输出端与输出子电路30中开关晶体管Qc的栅极电连接。例如，比较器201的输出端与输出子电路30中开关晶体管Qc的栅极经由第四电阻R4电连接。
如图7所示，第八电阻R8的另一端(第二端)与第六电阻R6的一端(第一端)和第七电阻R7的一端(第一端)电连接。第六电阻R6的另一端(第二端)与第一输入电压端VIN1电连接。第七电阻R7的另一端(第二端)与第一参考电压端Vref1电连接。
在此情况下，通过对上述电阻R6和电阻R7的电阻值进行设置，可以对比较器201的负向电压端接收的电压V-的大小进行调节，由此可以控制例如第一电压V1的取值以及预设时间T。例如，当比较器201的正向电压端接收的电压V+＞V-时，该比较器201的输出端向开关晶体管Qc的栅极输出第一电平(例如，高电平或有效电平，第一电平的电压值例如大于零伏)，以导通该开关晶体管Qc。
当第九电容C9的电容电压Vc9未增加至第一输入电压端VIN提供的第一电压V1时，比较器201的正向电压端的电压值V+＜V-，此时比较器201的输出端输出第二电平(例如，低电平或无效电平，第二电平的电压值例如小于零伏)，并使得上述开关晶体管Qc截止。例如，有效电平是指使得晶体管导通的电平，无效电平是指使得晶体管介质的电平。
需要说明的是，在设置比较器201负向输入端接收的电压V-的大小时，不仅可以参考第一输入电压端VIN1向比较器201提供的第一电压V1的大小，还可以将该比较器201的类型、灵敏度、第九电容C9的实际充电时间 等纳入考虑(以对电压V-进行微调)。在一些实施例中，上述比较器201的负向输入端接收的电压V-可以略小于第一电压V1。例如，第一电压V1与电压V-的差值与第一电压V1比值约为5％，也即，(V1-V-)/V1约为5％。
例如，上述第五电阻R5起到限流保护的作用。例如，第十电容C10的两端分别与第一参考电压端Vref1和比较器201的正向输入端电连接。例如，如图7所示，第十电容C10的两端还可以分别与第一参考电压端Vref1以及第一输入电压端VIN1(比较器201的接收第一电压V1的端子电连接)。例如，第十电容C10起到稳压、整流的作用。
以下以第一输入电压端VIN1提供第一电压V1为DVDD为例，采用本公开的实施例提供的供电时序控制电路01，对DVDD的供电时刻(DVDD的上升沿的终止时刻)的控制进行说明。
如图8所示，首先，对可调电阻Rc的阻值进行调节，使得第九电容C9的电容电压Vc9增加至(通过充电增加至)第一电压V1的时间Tc＝t1(如图2A所示)，电压DVDD经过可调电阻Rc后对第九电容C9进行充电。在对第九电容C9进行充电的初期，该第九电容C9输出至比较器201正向输入端的电压V+小于负向输入端的电压V_，此时比较器201的输出端输出低电平，开关晶体管Qc截止，驱动晶体管Qd截止，信号输出端Vout无信号输出(或者Vout输出低电平)。
接下来，当第九电容C9的充电时间达到t1(大于或等于t1)后，第九电容C9的电容电压Vc9＝DVDD。此时，第九电容C9输出至比较器201正向输入端的电压V+大于负向输入端的电压V_，比较器201的输出端输出高电平，开关晶体管Qc导通。
接下来，辅助输出子电路40中的电源隔离模块401向开关晶体管Qc的第一极和第二极分别提供隔离后的第二电压V2和第二参考电压GND2。第二电压V2在开关晶体管Qc导通后，传输至驱动晶体管Qd的栅极，该驱动晶体管Qd的栅极在第二电压V2的控制下保持导通状态，并将与第二电压V2隔离的DVDD传输至信号输出端Vout，从而实现电压DVDD的延时输出。
例如，其余电压AVDD、VGL以及VGH的供电时刻的控制过程同上所述，不同之处在于，根据如图3A所示的AVDD、VGL以及VGH的供电时 序可知，接收AVDD的供电时序控制电路01中可调电阻Rc的阻值大于接收DVDD的供电时序控制电路01中可调电阻Rc的阻值，且小于接收VGL的供电时序控制电路01中可调电阻Rc的阻值。此外，接收VGL的供电时序控制电路01中可调电阻Rc的阻值小于接收VGH的供电时序控制电路01中可调电阻Rc的阻值。例如，对于其余电压AVDD、VGL以及VGH的控制过程与对电压DVDD的控制过程相同或相似，此处不再赘述。
本公开的实施例提供一种用于控制上述任意一种供电时序控制电路01的方法，如图9所示，上述方法包括以下的步骤S101-步骤S103。
步骤S101、延时控制子电路10将第一输入电压端VIN1输出的第一电压V1延时一预设时间T后输出。
步骤S102、在预设时间T后，延时检测子电路20接收到第一电压V1时，向输出子电路30发送触发信号Em。
步骤S103、输出子电路30根据上述触发信号Em处于开启状态，并将第一输入电压端VIN1的第一电压V1输出至信号输出端Vout。
上述供电时序控制电路01的控制方法与前述实施例提供的供电时序电路01具有相同或相似的技术效果，此处不再赘述。
此外，在供电时序控制电路还包括辅助输出子电路的情况下，上述步骤S103之后，该方法还包括：
步骤S104、辅助输出子电路40控制输出子电路30在接收到触发信号Em后，保持开启状态。
图12是本公开的至少一个实施例提供的显示驱动电路的示例性框图。以下结合图10-图12对本公开的实施例提供的显示驱动电路进行示例性说明。本公开的实施例提供的显示驱动电路包括至少一个如上所述的供电时序控制电路01。该显示驱动电路具有与前述实施例提供的供电时序控制电路01相同或相似的技术效果，此处不再赘述。
以下对供电时序控制电路01在显示驱动电路中的设置方式进行举例说明。
例如，上述显示驱动电路还包括图10和图11所示的时序控制器53、源极驱动器54以及栅极驱动器55。
时序控制器53、源极驱动器54以及栅极驱动器55可以作为上述供电时 序控制电路01的负载。
示例性的，用于输出DVDD的供电时序控制电路01的信号输出端Vout可以与时序控制器53电连接。
例如，分别用于输出DVDD和AVDD的两个的供电时序控制电路01的信号输出端Vout可以均于源极驱动器54电连接。
例如，分别用于输出DVDD、VGL、VGH的三个的供电时序控制电路01的信号输出端Vout可以均与栅极驱动器55电连接。
例如，如图10和图11所示，为了使得上述负载能够更好的工作，连接有供电时序控制电路01的上述时序控制器53、源极驱动器54或者栅极驱动器55还与第一参考电压端Vref1电连接，以接收该第一参考电压端Vref1输出的第一参考电压GND1。
此外，时序控制器53与图像处理器52、源极驱动器54以及栅极驱动器55电连接。
例如，该时序控制器53接收一供电时序控制电路01输出的DVDD后，处于工作状态，并根据图像处理器52输出的数据信号(Dat)、时钟信号(CLK)以及控制信号(ControlS)向源极驱动器54提供数据信号Dat和时钟信号(CLK)，并向栅极驱动器55提供栅起始信号(Start Vertical，STV，也被称为帧起始信号)以及栅移动信号(Clock Pulse Vertical，CPV，也被称为扫描时钟脉冲信号)。例如，时序控制器53还可以向栅极驱动器55提供使能信号(Output Enable,OE)。
例如，栅极驱动器55可以在接收多个供电时序控制电路01输出的DVDD、VGH以及VGL后处于工作状态，并控制显示面板中的栅线逐行进行扫描。
例如，源极驱动器54接收多个供电时序控制电路01输出的DVDD、AVDD后处于工作状态，并控制数据线向显示面板中被选通一行亚像素提供数据电压Vdata。
例如，为了实现灰阶显示，如图11所示，该显示驱动电路还包括与源极驱动器54电连接的灰阶电压生成器56。该和灰阶电压生成器56用于生成多个灰阶基准电压(例如，VGAM_1、VGMA_2……VGMA_n；n≥2，n为正整数)。源极驱动器54可以根据上述灰阶基准电压向显示面板中各个亚像素 提供与预设的灰阶值相配的数据电压Vdata。
例如，灰阶电压生成器56的一个基准灰阶输出端与一个供电时序控制电路的第一输入电压端VIN1电连接。
例如，供电时序控制电路01的信号输出端Vout与源极驱动器54电连接。同上所述，该源极驱动器54还与第一参考电压端Vref1电连接，以接收该第一参考电压端Vref1输出的第一参考电压GND1。
这样一来，灰阶电压生成器56生成的多个灰阶基准电压分别在多个供电时序控制电路01的控制下(一一延时控制下)，可以按照预设的供电顺序依次提供至源极驱动器54。
本公开的实施例提供一种显示装置，包括如上所述的任意一种显示驱动电路。
例如，上述显示装置还包括显示面板，如图11所示，该显示面板包括公共电极层02。
为了对输入至公共电极层02的公共电压Vcom的供电时序进行控制，该显示装置中还可以额外增加一供电时序控制电路01。该供电时序控制电路01的第一输入电压端VIN与一个上述电源管理芯片51中用于输出公共电压Vcom的一个电压输出端电连接，供电时序控制电路01的信号输出端Vout与上述公共电极层02电连接，通过可以通过供电时序控制电路01对公共电压Vcom输入至公共电极层02的时间进行控制。
其中，本公开的一些实施例对公共电压Vcom的供电时序不做限定，例如可以在DVDD、AVDD、VGL、VGH上电之后，公共电压Vcom再开始上电，也即，可以在提供DVDD、AVDD、VGL、VGH之后，再提供公共电压Vcom。
例如，多个驱动电压(例如，供电电压)，例如DVDD、AVDD、VGH、VGL等可以分别输入至不同的供电时序控制电路01中延时控制子电路10所连接的第一输入电压端VIN1中。此时，可以对上述不同的供电时序控制电路01中延时控制子电路10的延时时间进行设定，从而使得多个供电时序控制电路01能够按照预设的供电时序，依次输出上述多个驱动电压(例如，供电电压)。
在此基础上，不同的供电时序控制电路01中延时检测子电路20可以对 延时控制子电路10的延时时间进行判断，当延时时间满足要求时，例如，当接收DVDD的供电时序控制电路01中延时检测子电路20对延时控制子电路10的实际延时时间进行检测，当该实际延时时间等于(或者大于等于)上述时间t1时，该延时检测子电路20控制输出子电路30开启，此种情况下，可以通过输出子电路30将第一输入电压端VIN1的第一电压V1(例如上述DVDD)由该供电时序控制电路01的信号输出端Vout输出至负载，例如，显示装置中的源极驱动器。其余供电电压的输出方式同上所述。
由上述可知，本公开的实施例通过作为硬件设备的供电时序控制电路01，对各个负载所需的供电电压的供电时序进行控制，而无需软件编程对供电时序进行控制。因此该供电时序控制电路01具有较高的稳定性和可靠性，能够解决软件编程控制供电时序，导致供电时序存在偏差的问题。
需要说明的是，在本公开的实施例中，上述显示装置可以为LCD和OLED显示装置。且该显示装置可以为显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。其中，图10和图11中的显示面板是以LCD显示面板为例进行的说明。当显示面板为OLED显示面板时，上述具有供电时序控制电路01的显示装置的设置方式与具有LCD显示面板的显示装置的设置方式相同或相似，在此不赘述。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开的实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (22)

  1. 一种供电时序控制电路，包括：延时控制子电路、延时检测子电路以及输出子电路；
    所述延时控制子电路与第一输入电压端电连接，所述延时控制子电路被配置为接收所述第一输入电压端输出的第一电压，并将所述第一电压延时一预设时间后输出；
    所述延时检测子电路与所述延时控制子电路和所述输出子电路电连接，所述延时检测子电路被配置为在接收到所述第一电压时，向所述输出子电路发送触发信号；以及
    所述输出子电路还与所述第一输入电压端以及所述信号输出端电连接，所述输出子电路被配置为响应于所述触发信号处于开启状态，以将所述第一输入电压端提供的第一电压输出至所述信号输出端，并允许所述信号输出端输出所述第一电压。
  2. 根据权利要求1所述的供电时序控制电路，其中，所述供电时序控制电路还包括辅助输出子电路；
    所述辅助输出子电路与所述输出子电路电连接；
    所述辅助输出子电路被配置为允许所述输出子电路在接收到所述触发信号后，保持所述开启状态；以及
    所述输出子电路被配置为在接收到所述触发信号后持续将所述第一电压输出至所述信号输出端，以使得所述信号输出端持续输出所述第一电压。
  3. 根据权利要求2所述的供电时序控制电路，其中，所述辅助输出子电路还与所述第一输入电压端、第一参考电压端、第二输入电压端、第二参考电压端以及第三参考电压端电连接；
    所述辅助输出子电路包括电源隔离器，所述电源隔离器包括第一输入端、第二输入端、第一输出端和第二输出端；
    所述电源隔离器的第一输入端与所述第一输入电压端电连接；所述电源隔离器的第二输入端与所述第一参考电压端和所述第三参考电压端电连接；所述电源隔离器第一输出端与所述第二输入电压端电连接；所述电源隔离器的第二输出端与所述第二参考电压端电连接；
    所述电源隔离器被配置为根据所述第一输入电压端提供的第一电压、所述第一参考电压端提供的第一参考电压以及所述第三参考电压端提供的第三参考电压向所述第二输入电压端输出与所述第一电压隔离的第二电压，其中，所述第一参考电压与所述第二参考电压端输出的第二参考电压不同。
  4. 根据权利要求3所述的供电时序控制电路，其中，所述电源隔离器还被配置为根据所述第一电压、所述第一参考电压以及所述第三参考电压向所述第二参考电压端输出与所述第一参考电压隔离的所述第二参考电压。
  5. 根据权利要求3所述的供电时序控制电路，其中，所述辅助输出子电路还包括第一电容、第二电容、第三电容、第四电容；
    所述第一电容的两端分别与所述第一输入电压端和所述第一参考电压端电连接；
    所述第二电容的两端分别与所述电源隔离器的第一输入端和所述电源隔离器的第二输入端电连接；
    所述第三电容的两端分别与所述电源隔离器的第一输出端和所述电源隔离器的第二输出端电连接；以及
    所述第四电容的两端分别与所述第二输入电压端和所述第二参考电压端电连接。
  6. 根据权利要求3所述的供电时序控制电路，其中，所述辅助输出子电路还包括第五电容、第六电容、第七电容、第八电容；
    所述第五电容的两端分别与所述电源隔离器的第一输入端和所述第三参考电压端电连接；
    所述第六电容的两端分别与所述电源隔离器的第二输入端和所述第三参考电压端电连接；
    所述第七电容的两端分别与所述电源隔离器的第一输出端和所述第三参考电压端电连接；以及
    所述第八电容的两端分别所述电源隔离器的第二输出端和所述第三参考电压端电连接。
  7. 根据权利要求3所述的供电时序控制电路，其中，所述辅助输出子电路还包括第一电阻以及第二电阻；
    所述第一电阻的两端分别所述第二输入电压端和所述第二参考电压端电 连接；以及
    所述第二电阻与所述第一电阻并联，且所述第二电阻的两端分别与所述第二输入电压端和所述第二参考电压端电连接。
  8. 根据权利要求1-7任一项所述的供电时序控制电路，其中，所述输出子电路包括开关晶体管和驱动晶体管；
    所述开关晶体管的栅极与所述延时检测子电路电连接，以接收所述触发信号；
    所述驱动晶体管的栅极与所述开关晶体管的第二极电连接；
    所述驱动晶体管的第一极与所述第一输入电压端电连接，以接收所述第一输入电压端提供的第一电压；
    所述驱动晶体管的第二极与所述信号输出端电连接；
    所述驱动晶体管被配置为将所述触发信号将第一输入电压端提供的第一电压提供至所述驱动晶体管的第二极；以及
    所述信号输出端被配置为允许位于所述驱动晶体管的第二极的第一电压从所述信号输出端输出。
  9. 根据权利要求8所述的供电时序控制电路，还包括辅助输出子电路，
    其中，所述辅助输出子电路与所述输出子电路电连接；
    所述辅助输出子电路还与第二输入电压端和第二参考电压端电连接；
    所述开关晶体管的第一极与所述第二输入电压端电连接，以接收所述第二输入电压端提供的与所述第一电压隔离的第二电压；
    所述开关晶体管的第二极与所述第二参考电压端电连接，以接收所述第二参考电压端提供的与所述第一参考电压隔离的第二参考电压；以及
    所述驱动晶体管的第二极还与所述第二参考电压端电连接。
  10. 根据权利要求9所述的供电时序控制电路，其中，所述输出子电路还包括：第三电阻、第四电阻以及第五电阻；
    所述第三电阻的两端分别与所述第二输入电压端和所述延时检测子电路的输出端电连接；
    所述第四电阻的两端分别与所述延时检测子电路的输出端和所述开关晶体管的栅极电连接；以及
    所述第五电阻的两端分别与所述开关晶体管的第二极和所述第二参考电 压端电连接。
  11. 根据权利要求1-7任一所述的供电时序控制电路，其中，所述延时控制子电路与第一参考电压端电连接；
    所述延时控制子电路包括可调电阻和第九电容；
    所述可调电阻的第一端与所述第一输入电压端电连接，所述可调电阻的第二端与所述第九电容的第一端电连接；以及
    所述第九电容的第二端与所述第一参考电压端电连接。
  12. 根据权利要求11所述的供电时序控制电路，其中，所述可调电阻的调节范围为1k～10MΩ。
  13. 根据权利要求1-7任一所述的供电时序控制电路，其中，所述延时检测子电路还与第一参考电压端电连接；
    所述延时检测子电路包括比较器、第六电阻、第七电阻、第八电阻以及第十电容；
    所述比较器的正向输入端与所述延时控制子电路电连接，所述比较器的负向输入端与所述第八电阻的第一端电连接，所述比较器的输出端与所述输出子电路电连接；
    所述第八电阻的第二端与所述第六电阻的第一端和所述第七电阻的第一端电连接；
    所述第六电阻的第二端与所述第一输入电压端电连接；
    所述第七电阻的第二端与所述第一参考电压端电连接；
    所述第十电容的两端分别与所述第一参考电压端和所述比较器的与所述第一输入电压端电连接。
  14. 一种显示驱动电路，包括至少一个如权利要求1-13任一项所述的供电时序控制电路。
  15. 根据权利要求14所述的显示驱动电路，其中，所述显示驱动电路还包括电源管理芯片；
    所述电源管理芯片具有输入端和多个电压输出端；
    所述电源管理芯片被配置为根据所述输入端接收到的初始电压，生成多个输出电压；
    所述多个输出电压被配置为分别由所述多个电压输出端输出；以及
    所述电源管理芯片的多个所述电压输出端的一个与所述供电时序控制电路的第一输入电压端电连接。
  16. 根据权利要求15所述的显示驱动电路，其中，所述显示驱动电路包括多个所述供电时序控制电路；
    所述电源管理芯片的多个所述电压输出端分别与多个所述供电时序控制电路的第一输入电压端电连接，以分别向多个所述供电时序控制电路的第一输入电压端提供多个输出电压；以及
    所述多个所述供电时序控制电路被配置为控制所述多个输出电压的供电时序。
  17. 根据权利要求15所述的显示驱动电路，其中，所述显示驱动电路还包括时序控制器、源极驱动器以及栅极驱动器；
    所述供电时序控制电路的信号输出端与所述时序控制器、所述源极驱动器或者所述栅极驱动器的一个电连接；以及
    所述时序控制器、所述源极驱动器或者所述栅极驱动器还与第一参考电压端电连接。
  18. 根据权利要求14所述的显示驱动电路，其中，所述显示驱动电路还包括源极驱动器以及被配置为生成多个灰阶基准电压的灰阶电压生成器；
    所述灰阶电压生成器包括多个灰阶基准输出端，每个灰阶基准输出端被配置为输出一个所述灰阶基准电压；
    所述灰阶电压生成器的多个所述灰阶基准输出端的一个与所述供电时序控制电路的第一输入电压端电连接；
    所述供电时序控制电路的信号输出端与所述源极驱动器电连接；以及
    所述源极驱动器还与所述第一参考电压端电连接。
  19. 一种显示装置，包括如权利要求14-18任一项所述的显示驱动电路。
  20. 根据权利要求19所述的显示装置，其中，所述显示装置还包括显示面板，所述显示面板包括公共电极层；
    所述供电时序控制电路的第一输入电压端与电源管理芯片中被配置为输出公共电压的电压输出端电连接；以及
    所述供电时序控制电路的信号输出端与所述公共电极层电连接。
  21. 一种用于控制如权利要求1-13任一项所述的供电时序控制电路的方 法，包括：
    所述延时控制子电路将所述第一输入电压端输出的所述第一电压延时所述预设时间后输出；
    所述延时检测子电路在接收到所述第一电压时，向所述输出子电路发送所述触发信号；
    所述输出子电路响应于所述触发信号处于开启状态，并将所述第一输入电压端提供的第一电压输出至所述信号输出端。
  22. 根据权利要求21所述的方法，其中，在所述供电时序控制电路还包括所述辅助输出子电路的情况下，所述输出子电路被配置为响应所述触发信号处于开启状态，以将所述第一输入电压端提供的第一电压输出至所述信号输出端，在所述第一电压输出至所述信号输出端之后，所述方法还包括：
    所述辅助输出子电路控制所述输出子电路在接收到所述触发信号后，保持所述开启状态。
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