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WO2019139337A1 - Motherboard, method for fabrication of compound semiconductor solar cell by using same motherboard, and compound semiconductor solar cell - Google Patents

Motherboard, method for fabrication of compound semiconductor solar cell by using same motherboard, and compound semiconductor solar cell Download PDF

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Publication number
WO2019139337A1
WO2019139337A1 PCT/KR2019/000302 KR2019000302W WO2019139337A1 WO 2019139337 A1 WO2019139337 A1 WO 2019139337A1 KR 2019000302 W KR2019000302 W KR 2019000302W WO 2019139337 A1 WO2019139337 A1 WO 2019139337A1
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WIPO (PCT)
Prior art keywords
layer
lattice constant
single crystal
crystal wafer
compound semiconductor
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PCT/KR2019/000302
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French (fr)
Korean (ko)
Inventor
김수현
권구한
김건호
이홍철
최원석
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엘지전자 주식회사
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Publication of WO2019139337A1 publication Critical patent/WO2019139337A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264Inorganic materials
    • H01L31/0304Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/544Solar cells from Group III-V materials
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a mosquito board, a method of manufacturing a compound semiconductor solar cell using the mother board, and a compound semiconductor solar cell, and more particularly, to a mosquito board capable of producing a high efficiency compound semiconductor solar cell, A method of manufacturing a compound semiconductor solar cell, and a compound semiconductor solar cell.
  • the compound semiconductor is not a single element such as silicon or germanium, but two or more elements are combined to operate as a semiconductor.
  • various kinds of compound semiconductors have been developed and used in various fields. Typical examples of such compound semiconductors include light emitting devices such as light emitting diodes and laser diodes using solar cells, solar cells, and thermoelectric conversion devices using Peltier effect .
  • the compound semiconductor solar cell is composed of gallium arsenide (hereinafter referred to as GaAs), gallium indium phosphor (hereinafter referred to as GaInP), gallium aluminum arsenide (hereinafter referred to as GaAlAs), gallium indium arsenide II-VI compound semiconductors such as cadmium sulphide (CdS), cadmium tellurium (CdTe), zinc sulfide (ZnS), and the like; I-III-VI compound semiconductors typified by copper indium-selenium (CuInSe2) or the like are used to form various layers.
  • GaAs gallium arsenide
  • GaInP gallium indium phosphor
  • GaAlAs gallium aluminum arsenide
  • GaInS gallium indium arsenide II-VI compound semiconductors
  • CdS cadmium sulphide
  • CdTe cadmium tellurium
  • ZnS zinc sulfide
  • a compound semiconductor layer may be formed by a metal organic chemical vapor deposition (MOCVD) method, an MBE (Molecular Beam Epitaxy) method, or any other suitable method for forming an epitaxial layer.
  • MOCVD metal organic chemical vapor deposition
  • MBE Molecular Beam Epitaxy
  • the compound semiconductor layer formed on the mother substrate and formed on the mother substrate is formed as a single junction structure or a multiple junction structure.
  • the single-junction compound semiconductor layer is for forming a compound semiconductor solar cell having a single junction structure
  • the compound semiconductor solar cell having a single junction structure has one cell including a base layer and an emitter layer do.
  • the compound semiconductor layer of the multiple junction structure is for forming a compound semiconductor solar cell having a multi junction structure, and the compound semiconductor solar cell of the multiple junction structure comprises two or more cells including the base layer and the emitter layer.
  • a compound semiconductor solar cell having a double junction structure has a bottom cell and a top cell
  • a compound semiconductor solar cell having a junction structure of triple junction structure or more has a bottom cell and a top cell, And has at least one middle cell positioned therein.
  • the mother substrate for forming the compound semiconductor layer is formed of a GaAs single crystal wafer or a Ge single crystal wafer, and a GaAs single crystal wafer or a Ge single crystal wafer has a lattice constant of 5.65 angstroms.
  • the compound semiconductor layer formed on the mother substrate has the same lattice constant as the mother substrate.
  • the compound semiconductor layer forming the bottom cell located on the rear electrode side has a lower band gap energy than the compound semiconductor layer forming the top cell located on the front electrode side
  • the compound semiconductor layer forming the top cell is formed of a material having a higher band gap energy than the bottom cell, for example, GaInP.
  • the bottom cell when a compound semiconductor layer having a double junction structure is grown on a GaAs single crystal wafer or a Ge single crystal wafer having 5.65 angstroms, the bottom cell has a base layer formed on the basis of GaAs or Ge , The band gap energy of the bottom cell has a band gap energy of 1.42 eV which is equal to the band gap energy of the base layer of the bottom cell.
  • the band gap energy of the top cell must have a band gap energy of 1.88 eV which is equal to the band gap energy of the base layer of the top cell.
  • a mother substrate comprises a GaAs single crystal wafer or a Ge single crystal wafer; And a metamorphic layer in direct physical contact with one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction.
  • the lattice constant of the first surface contacting the GaAs single crystal wafer or the Ge single crystal wafer is formed to be smaller than the lattice constant of the second surface located on the opposite side of the first surface from both surfaces of the modified layer,
  • the lattice constant of the first surface may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
  • the lattice constant on the first surface of the modified layer may be equal to the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer.
  • the GaAs single crystal wafer or the Ge single crystal wafer may have a lattice constant of 5.65 A and the modified layer may have a lattice constant of 5.70 A to 5.77 A larger than the lattice constant of the GaAs single crystal wafer or Ge single crystal wafer.
  • the modified layer having the above-mentioned lattice constant may be formed of In x Ga 1-x P or In x Ga 1 -x As, wherein x on the first surface is zero, X in the plane is 0.19.
  • x means atomic% (atomic%).
  • the mother substrate may further include a sacrificial layer in direct physical contact with the second surface of the modified layer.
  • the sacrificial layer may have the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer or may have the same lattice constant as the lattice constant on the second surface of the modified layer.
  • the sacrifice layer is preferably formed to a thickness of 1 nm to 10 nm, and may be formed based on AlAs or AlGaAs.
  • the sacrificial layer may be formed based on AlInAs or AlAsSb.
  • a compound semiconductor solar cell having such a configuration includes a step of forming a sacrificial layer on one side of a mother substrate; And forming a compound semiconductor layer for forming at least one cell on the sacrificial layer.
  • the mother substrate may be a GaAs single crystal wafer or a Ge single crystal wafer; And a metamorphic layer in direct physical contact with one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction.
  • the lattice constant of the first surface contacting the GaAs single crystal wafer or the Ge single crystal wafer from both surfaces of the modified layer is smaller than the lattice constant of the second surface located on the opposite side of the first surface .
  • the lattice constant of the modified layer can be increased stepwise, exponentially or logarithmically from the first surface to the second surface.
  • the lattice constant on the first surface of the modified layer may be equal to the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer.
  • the modified layer is In x Ga 1 -x P or In x Ga 1 having a lattice constant of 5.70 ⁇ to 5.77 ⁇ - can be formed as x As.
  • x means atomic%
  • x on the first side is zero
  • x on the second side is 0.19.
  • the sacrificial layer may be formed to be in direct physical contact with the second surface of the modified layer, and may be formed based on AlAs or AlGaAs having the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer, Can be formed based on AlInAs or AlAsSb having the same lattice constant as the lattice constant on the second surface.
  • Layer is preferably formed to a thickness of 1 nm to 10 nm.
  • the base layer of the bottom cell may be formed of In y Ga 1 - y As having a band gap energy of 0.95 eV to 1.20 eV and a lattice constant of 5.70 ⁇ to 5.77 ⁇ ,
  • y and z mean atomic%, y is 0.13 to 0.30, and z is 0.24 to 0.40.
  • a back electrode having a sheet electrode shape may be formed on a back surface of the bottom cell and a grid electrode may be formed on a front surface of the top cell.
  • a compound semiconductor solar cell having a multi junction structure of this structure particularly a compound semiconductor solar cell having a double junction structure, has a band gap energy of 0.95 eV to 1.20 eV and a lattice constant of In y Ga 1 - y As having a lattice constant of 5.70 ⁇ to 5.77 ⁇
  • a base layer of a bottom cell formed;
  • a base layer of a top cell formed of Ga z In 1 - z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A;
  • a rear electrode disposed on a back surface of the bottom cell and formed in the form of a sheet electrode;
  • a front electrode formed on a front surface of the top cell and formed in a grid shape.
  • y is from 0.13 to 0.30
  • z is from 0.24 to 0.40.
  • a mother substrate comprises a GaAs single crystal wafer or a Ge single crystal wafer; A metamorphic layer formed of Ga v In 1 -v P and located on one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction; And a protective layer formed of In w Ga 1 - w As and located on one side of the modified layer.
  • v and w mean atomic%, respectively.
  • the lattice constant of the GaAs monocrystalline wafer or the Ge monocrystalline wafer on both sides of the modified layer is the same as the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer
  • the lattice constant on the second surface is greater than the lattice constant on the first surface and is equal to the lattice constant of the protective layer.
  • the lattice constant of the modified layer may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
  • the GaAs single crystal wafer or the Ge single crystal wafer has a lattice constant of 5.65 A and the denaturing layer and the protective layer have a lattice constant of 5.70 A to 5.77 A larger than the lattice constant of the GaAs single crystal wafer or Ge single crystal wafer.
  • the modified layer on the first side is formed of Ga 0.52 In 0.48 P having a band gap energy of 1.60 to 1.80 eV, and v on the second side is 0.24 to 0.40.
  • w 0.13 to 0.30.
  • the mother substrate may further include a sacrificial layer located on the protective layer.
  • the sacrificial layer may have the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer or may have the same lattice constant as the lattice constant on the second surface of the modified layer.
  • the sacrifice layer is preferably formed to a thickness of 1 nm to 10 nm, and may be formed based on AlAs or AlGaAs.
  • the sacrificial layer may be formed based on AlInAs or AlAsSb.
  • a compound semiconductor solar cell having such a configuration includes a step of forming a sacrificial layer on one side of a mother substrate; And forming a compound semiconductor layer for forming at least one cell on the sacrificial layer.
  • the mother substrate may be a GaAs single crystal wafer or a Ge single crystal wafer; A metamorphic layer formed of Ga v In 1 -v P and located on one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction; And In w Ga 1 - w As, and may include a protective layer located on one side of the modified layer, and the first side contacting the GaAs single crystal wafer or the Ge single crystal wafer from both sides of the modified layer Wherein the lattice constant at the second surface located on the opposite side of the first surface is larger than the lattice constant at the first surface and the lattice constant at the second surface located at the opposite side of the first surface is larger than the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer, Lt; / RTI >
  • v and w mean atomic%, respectively.
  • the lattice constant of the modified layer can be increased stepwise, exponentially or logarithmically from the first surface to the second surface.
  • the modified layer on the first side is formed of Ga 0.52 In 0.48 P having a band gap energy of 1.60 to 1.80 eV, and v on the second side is 0.24 to 0.40.
  • the sacrificial layer may be formed on the protective layer.
  • the sacrificial layer may be formed on the GaAs single crystal wafer or the Ge single crystal wafer based on AlAs or AlGaAs having the same lattice constant, or may be formed on the second surface of the modified layer, Can be formed based on AlInAs or AlAsSb having the same lattice constant.
  • Layer is preferably formed to a thickness of 1 nm to 10 nm.
  • the mother substrate has a modified layer (and a protective layer for protecting the denatured layer) having an increased lattice constant as compared with a GaAs single crystal wafer or a Ge single crystal wafer, and the compound semiconductor layer is a denatured layer Lt; / RTI >
  • the band gap energy of the bottom cell and the top cell can be lowered as compared with the prior art.
  • the band gap energy of the bottom cell is 1.42 eV and the band gap energy of the top cell is 1.88 eV, the theoretical efficiency is limited to about 34.9%.
  • the band gap energy of the bottom cell can be reduced to 1.1 eV
  • the band gap energy of the top cell can be reduced to 1.7 eV.
  • the bottom cell and the top cell of the compound semiconductor solar cell can be formed so as to have a band gap energy close to the maximum theoretical efficiency obtained in a compound semiconductor solar cell having a double junction structure.
  • a sacrificial layer is used to directly form a compound semiconductor layer on a GaAs single crystal wafer or a Ge single crystal wafer without separating the GaAs single crystal wafer or the Ge single crystal wafer from the compound semiconductor layer, thereby forming a modified layer between the compound semiconductor layers
  • the band gap energy may be adjusted by changing the lattice constant between the band gap energy and the band gap energy.
  • the modified layer is formed directly on the GaAs single crystal wafer or the Ge single crystal wafer, and optionally the protective layer is formed directly on the modified layer, after the sacrificial layer is removed through the ELO (epitaxial lift off) Or the mother board comprising the denaturation layer and the protective layer can be reused.
  • manufacturing cost can be reduced and formation time of the compound semiconductor layer can be reduced compared with the case where the lattice constant and the band gap energy are adjusted using the modified layer between the cell and the cell.
  • the mother substrate of the present invention can also be used for the production of a compound semiconductor solar cell having a multi-junction structure of triple junction structure or more including at least one middle cell.
  • FIG. 1 is a graph showing the correlation between the band gap energy and the lattice constant of various materials forming the compound semiconductor layer.
  • FIG. 2 is a graph showing a correlation between band gap energies of a top cell and a bottom cell according to a lattice constant change.
  • 3 is a graph showing the correlation between the lattice constant and the theoretical efficiency in three measurement environments.
  • FIG. 5 is a table showing changes in the band gap energy of the first light absorbing layer of the top cell and the band gap energy of the second light absorbing layer of the bottom cell according to the size of the lattice constant and the theoretical efficiency.
  • FIG. 6 is a sectional view of a mother board according to the first embodiment of the present invention.
  • FIG. 7 is a sectional view of a mother board according to a second embodiment of the present invention.
  • FIG. 8 is a process diagram showing a method of manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
  • FIG. 9 is a sectional view of a mother board according to a third embodiment of the present invention.
  • FIG. 10 is a sectional view of a mother board according to a fourth embodiment of the present invention.
  • FIG. 11 is a process diagram showing a method for manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
  • FIG. 12 is a cross-sectional view of a compound semiconductor solar cell manufactured by the manufacturing method shown in Fig. 8 or Fig.
  • first, second, etc. may be used to describe various components, but the components may not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another.
  • the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.
  • the term "and / or” may include any combination of a plurality of related listed items or any of a plurality of related listed items.
  • the thickness is enlarged to clearly represent the layers and regions.
  • a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over” another part, it means that there is no other part in the middle.
  • FIG. 1 is a graph showing the correlation between the band gap energy and the lattice constant of various materials forming the compound semiconductor layer.
  • FIG. 2 is a graph showing a correlation between band gap energies of a top cell and a bottom cell according to a lattice constant change.
  • 3 is a graph showing the correlation between the lattice constant and the theoretical efficiency in three measurement environments.
  • FIG. 5 is a table showing changes in the band gap energy of the first light absorbing layer of the top cell and the band gap energy of the second light absorbing layer of the bottom cell according to the size of the lattice constant and the theoretical efficiency.
  • FIG. 6 is a sectional view of a mother board according to the first embodiment of the present invention.
  • FIG. 7 is a sectional view of a mother board according to a second embodiment of the present invention.
  • FIG. 8 is a process diagram showing a method of manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
  • FIG. 9 is a sectional view of a mother board according to a third embodiment of the present invention.
  • FIG. 10 is a sectional view of a mother board according to a fourth embodiment of the present invention.
  • FIG. 11 is a process diagram showing a method for manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
  • FIG. 12 is a cross-sectional view of a compound semiconductor solar cell manufactured by the manufacturing method shown in Fig. 8 or Fig.
  • the compound semiconductor solar cell having the double junction structure compound semiconductor layer includes a top cell C1, a grid-shaped front electrode 100 located on the front surface of the top cell C1, The first tunnel layer TRJ1 located between the top cell C1 and the bottom cell C2 and the first tunnel layer TRJ1 located between the top cell C1 and the bottom cell C2, and a rear electrode 200 having a sheet electrode shape.
  • the plurality of layers forming the top cell C1, the bottom cell C2 and the first tunnel layer TRJ1 are all formed of a compound semiconductor, and the front electrode 100 and the rear electrode 200 are formed of a conductive metal .
  • the top cell C1 includes a first light absorbing layer PV1, a first surface of the first light absorbing layer PV1, for example, a first window layer WD1 located on a front surface, And a first rear front layer BSF1 located on the second side of the first light absorbing layer PV1, for example, the rear side.
  • the first light absorbing layer PV1 includes a first base layer PV1-1 including an n-type impurity and in contact with the first window layer WD1, a first base layer PV1-1 including a p-type impurity, And a first emitter layer PV1-2 located on the rear surface of the first base layer PV1-1 and forming a pn junction with the first base layer PV1-1 and the first emitter layer PV1-1, 2) is formed of an indium phosphide (hereinafter referred to as InP) -based compound semiconductor.
  • InP indium phosphide
  • the first base layer PV1-1 is formed of n-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A
  • (PV1-2) is formed of p-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 ⁇ to 5.77 ⁇ .
  • z is in the range of 0.24 to 0.40.
  • the reason for limiting the range of z is to effectively reduce the bandgap of the top cell by effectively reducing the lattice constant of the top cell.
  • the p-type impurity doped in the first emitter layer PV1-2 may be selected from carbon (C), magnesium (Mg), zinc (Zn), or a combination thereof.
  • the doped n-type impurity may be selected from silicon (Si), selenium (Se), tellurium (Te), or a combination thereof.
  • a pn junction in which the first emitter layer PV1-2 and the first base layer PV1-1 are joined is formed in the first light-absorbing layer PV1, so that the first light-
  • the electron-hole pairs generated by the light are separated into electrons and holes by the internal potential difference formed by the pn junction of the first light-absorbing layer PV1, the electrons move toward the n-type, and the holes move toward the p-type.
  • the holes generated in the first light absorbing layer PV1 move to the rear electrode 200 through the bottom cell C2, and the electrons generated in the first light absorbing layer PV1 pass through the first window layer WD1, And moves to the front electrode 100 through the front contact layer FC.
  • holes generated in the first light absorbing layer PV1 may be transmitted through the front contact layer FC
  • the electrons generated in the first light absorbing layer PV1 move to the rear electrode 200 through the rear contact layer BC.
  • the first backside front layer BSF1 has the same conductivity type as the first emitter layer PV1-2 physically in direct contact and is made of an InP-based material similar to the first window layer WD1, For example, p-type AlInP.
  • the first backside front layer (BSF1) may be formed of p-type Al 0.67 In 0.33 P having a band gap energy of 2.2 eV and a lattice constant of 5.70 A to 5.77 A.
  • the first rear whole front layer BSF1 is formed of a first rear front layer BSF1 and a second rear front layer BSF2 which are physically in direct contact with each other in order to effectively block charges (holes or electrons) Is formed entirely on the back surface of the emitter layer PV1-2.
  • the first emitter layer PV1-2 and the first base layer PV1-1 can be made of the same material (homogeneous junction) having the same band gap energies and can be made of different materials having different band gap energies It can be made of other materials (heterojunction).
  • the first base layer PV1-1 may be formed of n-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A
  • the first emitter layer PV1-2 may be formed of p-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 ⁇ to 5.77 ⁇ .
  • the first window layer WD1 may be formed between the first light absorbing layer PV1 and the front electrode 100 and may be formed by doping an n-type impurity into the III-VI group semiconductor compound.
  • first emitter layer PV1-2 when the first emitter layer PV1-2 is located on the first base layer PV1-1 and the first window layer WD1 is located on the first emitter layer PV1-2, WD1) may include a p-type impurity.
  • the first window layer WD1 functions to passivate the front surface of the first light absorbing layer PV1. Therefore, when carriers (electrons and holes) move to the surface of the first light absorbing layer PV1, the first window layer WD1 can prevent the carriers from recombining on the surface of the first light absorbing layer PV1.
  • the first window layer WD1 is disposed on the front surface of the first light absorbing layer PV1, that is, on the light incident surface, the first light absorbing layer PV1 is formed on the first light absorbing layer PV1, It is necessary to have a band gap energy energy higher than the band gap energy energy of the first photovoltaic element PV1.
  • the first window layer WD1 it is necessary to form the first window layer WD1 with a substance which is hardly dissolved in the ELO process using hydrofluoric acid.
  • the first window layer WD1 may be formed of n-type Al 0.33 In 0.67 P having a band gap energy of 2.2 eV and a lattice constant of 5.70 A to 5.77 A.
  • the first rear whole layer BSF1 may be thicker than the first window layer WD1.
  • the first rear whole layer BSF1 may be formed to a thickness of 50 to 100 nm.
  • the antireflection film (not shown) may be located in a region other than the region where the front electrode 100 and / or the front contact layer FC are located in the front surface of the first window layer WD1.
  • the antireflection film may be disposed on the front contact layer FC and the front electrode 100 as well as the first window layer WD1.
  • the antireflection film having such a configuration may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or a combination thereof.
  • the compound semiconductor solar cell may further include a bus bar electrode physically connecting the plurality of front electrodes 100.
  • the bus bar electrode may be exposed to the outside without being covered by the antireflection film.
  • the front electrode 100 may be formed to extend in the first direction and spaced apart at a predetermined interval along a second direction Y-Y 'orthogonal to the first direction.
  • the front electrode 100 having such a structure may be formed to include an electrically conductive material and may include at least one of gold (Au), germanium (Ge), and nickel (Ni), for example.
  • the front contact layer FC positioned between the first window layer WD1 and the front electrode 100 dopes the Group III-VI semiconductor compound with an n-type impurity at a doping concentration higher than that of the first base layer PV1-1 .
  • the front contact layer (FC) may be formed of n + type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A.
  • the front contact layer FC forms an ohmic contact between the first window layer WD1 and the front electrode 100. That is, when the front electrode 100 directly contacts the first window layer WD1, the impurity doping concentration of the first window layer WD1 is low, so that the gap between the front electrode 100 and the first light absorbing layer PV1 Ohmic contacts are not well formed.
  • the carrier moved to the first window layer WD1 can not easily move to the front electrode 100 and can be destroyed.
  • the front contact layer FC is formed between the front electrode 100 and the first window layer WD1
  • the movement of the carriers is prevented by the front contact layer FC forming the ohmic contact with the front electrode 100 So that the short circuit current density (Jsc) of the compound semiconductor solar cell increases.
  • the efficiency of the solar cell can be further improved.
  • the front contact layer FC can be formed in the same plane shape as the front electrode 100.
  • the bottom cell C2 includes a second light absorbing layer PV2, a first surface of the second light absorbing layer PV2, for example, a second window layer WD2 located on the front surface, a second light absorbing layer PV2, A second backside front layer BSF2 located on a second side of the first back side layer BS2 and a rear side contact layer BC located on the back side of the second rear front side layer BSF2, .
  • the bottom cell C2 includes a light absorbing layer formed of a compound semiconductor including a second base layer and a second emitter layer based on GaAs.
  • the second base layer and the second emitter layer may be formed of In y Ga 1-y As having a band gap energy of 0.95 eV to 1.20 eV and a lattice constant of 5.70 ⁇ to 5.77 ⁇ .
  • y is in the range of 0.13 to 0.30. The reason why y is limited to the above range is to effectively reduce the band gap of the bottom cell by effectively reducing the lattice constant of In y Ga 1-y As.
  • the bottom cell C2 includes a second base layer PV2-1 formed of n-type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A, (PV2-2) formed of p-type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A, forming a pn junction with the first emitter layer (PV2-1) A second light absorbing layer PV2, an n-type Ga 0.33 layer having a band gap energy of 1.7 eV and a lattice constant of 5.70 A to 5.77 A, located between the first tunnel layer TRJ1 and the second base layer PV2-1, A second window layer WD2 formed of In 0.67 P and a p-type Ga 0.33 In layer having a band gap energy of 1.7 eV and a lattice constant of 5.70 A to 5.77 A, which are located on the back surface of the second emitter layer PV
  • the bottom cell C2 is located at the rear of the top cell C1 to absorb light of long wavelength transmitted through the top cell C1 without being absorbed in the top cell C1.
  • the second base layer PV2-1 and the second emitter layer PV2-2 form the first base layer PV1-1 and the first emitter layer PV1-2 of the top cell C1 A material having a band gap energy lower than the band gap energy of GaInP (approximately 1.9Ev), for example, InGaAs having a band gap energy of approximately 1.1 eV.
  • the second base layer PV2-1 and the second emitter layer PV2-2 may be formed of In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A, respectively have.
  • the second window layer WD2 and the second rear whole front side BSF2 are formed of a material having a higher band gap energy than the second base layer PV2-1 and the second emitter layer PV2-2, GaInP or AlGaInP.
  • the second window layer WD2 and the second rear whole layer BSF2 may be formed of Ga 0.33 In 0.67 P having a band gap energy of 1.7 eV and a lattice constant of 5.70 A to 5.77 A, respectively.
  • the first tunnel layer TRJ1 includes a first layer TRJ1 formed of p ++ type AlInGaAs doped with a higher concentration of p-type impurity than the first rear front layer BSF1 and physically in direct contact with the first rear front layer BSF1 And a second layer TRJ1-2 formed of n ++ -type GaInP doped with n-type impurity at a higher concentration than the second window layer WD2 and physically in direct contact with the second window layer WD2 can do.
  • the rear contact layer BC located on the rear surface of the first rear front layer BSF1 is entirely located on the rear surface of the first rear front layer BSF1 and is formed by doping a Group III- .
  • the back contact layer BC may be formed of p + type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A.
  • This rear contact layer BC can form an ohmic contact with the rear electrode 200, and the short circuit current density Jsc of the compound semiconductor solar cell can be further improved. As a result, the efficiency of the solar cell can be further improved.
  • the thickness of the front contact layer FC and the rear contact layer BC may each be formed to a thickness of 100 nm to 300 nm.
  • the front contact layer FC may be formed to a thickness of 100 nm and the rear contact layer BC may be formed to a thickness of 300 nm.
  • the rear electrode 200 positioned on the rear surface of the rear contact layer BC may be formed as a sheet-like conductive material positioned entirely on the rear surface of the rear contact layer BC, unlike the front electrode 100 . That is, the rear electrode 200 may be referred to as a sheet electrode located on the entire rear surface of the rear contact layer BC.
  • the rear electrode 200 may be formed in the same plane as the first light absorbing layer PV1, and may be formed of various conductive materials.
  • the rear electrode 200 includes a first electrode layer 200A that directly contacts a bottom layer of the bottom cell C2, for example, a rear surface of the rear contact layer BC to transmit a carrier, And a second electrode layer 200B positioned on the rear surface of the first electrode layer 200A to support the first electrode layer 200A.
  • the first electrode layer 200A for transmitting a carrier is formed of a material having a contact resistance similar to that of a conventional rear electrode forming material, that is, gold (Au), and is formed of a material having a high reflectivity can do.
  • the first electrode layer 200A directly contacting the rear contact layer BC is formed of silver (Ag) having an excellent electrical bonding property with the rear contact layer BC and having an average reflectivity of 95% or more at a wavelength range of 600 nm to 950 nm ) May be formed by physical vapor deposition to a thickness of 50 to 500 nm.
  • the second electrode layer 200B that supports the first electrode layer 200A has a higher contact resistance than silver (Ag) that forms the first electrode layer 200B and has low reflectivity at a wavelength range of 600 nm to 950 nm.
  • Copper (Cu) can be formed by electroplating to a thickness of 1 to 10 ⁇ .
  • the silver (Ag) having a low contact resistance with the rear contact layer BC and having a high average reflectivity in the wavelength range of 600 nm to 950 nm is used as the material for forming the first electrode layer 200A, And the photon recycling can be increased due to the reduction of the optical loss, so that the efficiency of the solar cell can be improved.
  • the compound semiconductor solar cell having such a structure can be manufactured by using any one of the mother board shown in Figs. 6, 7, 9 and 10.
  • Fig. 6 shows the mother board of the first embodiment with the modified layer
  • Fig. 7 shows the mother board of the second embodiment with the modified layer and the sacrificial layer.
  • Fig. 9 shows a mother board of a third embodiment with a denatured layer and a protective layer
  • Fig. 10 shows a mother board of the fourth embodiment with a denatured layer, a protective layer and a sacrificial layer.
  • the mother substrate 300-1, 300-2, 300-3, and 300-4 of the first to fourth embodiments may include a GaAs single crystal wafer or a Ge single crystal wafer, respectively.
  • the mother substrate 300-1, 300-2, 300-3, and 300-4 includes the GaAs wafer 300A will be described as an example.
  • the mother substrate 300-1 of the first embodiment includes a GaAs wafer 300A and a metamorphic layer 300B that is in direct physical contact with one side of the GaAs wafer 300A.
  • the GaAs wafer 300A serves as a base layer for providing a plurality of compound semiconductor layers forming the bottom cell C2 and a plurality of compound semiconductor layers forming the top cell C1 to form a suitable lattice structure.
  • the modified layer 300A has a lattice constant of a plurality of compound semiconductor layers forming the bottom cell C2 and a lattice constant of a plurality of compound semiconductor layers forming the top cell C1 in comparison with the lattice constant of the GaAs wafer 300A Thereby adjusting the band gap energy of the bottom cell C2 and the band gap energy of the top cell C1 so as to obtain an efficiency close to the maximum theoretical efficiency obtained in a compound semiconductor solar cell having a double junction structure.
  • the lattice constant of the modified layer 300B varies along the thickness direction. That is, the denatured layer 300B means a layer whose lattice constant varies along the thickness direction.
  • the lattice constant on the first surface contacting the GaAs wafer 300A on both sides of the modified layer 300B is equal to the lattice constant of the GaAs wafer 300A.
  • lattice constant of the modified layer 300B on the second surface located on the opposite side of the first surface may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
  • the GaAs wafer 300A has a lattice constant of 5.65 ANGSTROM. Therefore, when the lattice constant of the compound semiconductor layer formed on the modified layer 300B is increased by the lattice constant of the GaAs wafer 300A using the modified layer 300B, the top cell and the bottom cell are formed directly on the GaAs wafer The band gap energy of the first light absorbing layer PV1 of the top cell C1 and the band gap energy of the second light absorbing layer PV2 of the bottom cell C2 can be lowered.
  • a top cell (C1) and a first band gap energy is 1.88 of the light absorption layer (PV1)
  • a bottom cell (C2) a second band gap of the light absorbing layer (PV2) to the formation of the GaAs to form a
  • the energy is 1.42.
  • the efficiency (AMO efficiency) when used in a space environment is 31.3%
  • the efficiency (AM1.5G efficiency) when used in a ground environment is 34.9% Is 32.5%.
  • the modified layer 300B having the lattice constant increased to 5.7A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52
  • a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.8, with the GaAs to form the P The band gap energy is reduced to 1.2.
  • the efficiency (AMO efficiency) for use in a space environment is 33.8%
  • the efficiency for use in a ground environment is 36.9% Is 33.6%.
  • the modified layer 300B having the lattice constant increased to 5.73A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52 In 0 .48 a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.72, with the GaAs to form the P The band gap energy is lowered to 1.09.
  • the efficiency (AMO efficiency) when used in a space environment is 34.2%
  • the efficiency (AM1.5G efficiency) when used in a ground environment is 37.1% Is 34.2%.
  • the modified layer 300B having the lattice constant increased to 5.75A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52 In 0 .48 a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.66, with the GaAs to form the P The band gap energy is lowered to 1.03.
  • the efficiency (AMO efficiency) in the space environment is 33.9%
  • the efficiency (AM1.5G efficiency) in the use in the ground environment is 36.6%
  • the efficiency (AM1.5D efficiency) Is 34.8%.
  • the modified layer 300B having the lattice constant increased to 5.76A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52
  • a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.63, with the GaAs to form the P The band gap energy is lowered to 1.09.
  • the efficiency (AMO efficiency) when used in a space environment is 33.5%
  • the efficiency (AM1.5G efficiency) when used in a ground environment is 36.3% Is 35.1%.
  • the AMO efficiency and AM1.5G efficiency are the highest when using a dense layer having a lattice constant of 5.73 ⁇ on the second side, and the AM1.5D efficiency is a lattice constant of 5.76 ⁇ on the second side The highest value is obtained in the case of using the modified layer having a high refractive index.
  • a double-junction solar cell can be manufactured by appropriately selecting a modified layer having a lattice constant of 5.7 A to 5.77 A on the second surface in accordance with the use environment of the solar cell.
  • x on the first surface of the modified layer 300B is 0 (zero), and x on the second surface is 0.19.
  • the modified layer 300B may be formed to a thickness of 200 to 300 nm and may be formed of a plurality of films within the thickness range to increase the lattice constant from the first surface to the second surface.
  • a sacrificial layer 400 physically in direct contact with the modified layer 300B of the mother substrate 300-1 is formed on one surface of the modified layer 300B and the bottom cell C2 is formed on the sacrificial layer 400.
  • a compound semiconductor layer CS3 for forming the first tunnel layer TRJ1 and a compound semiconductor layer CS1 for forming the top cell C1 are sequentially formed.
  • the sacrificial layer 400 may be formed of AlAs or AlAsSb having the same lattice constant as the lattice constant of the second surface of the modified layer 300B or may be formed of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A, can do.
  • the sacrificial layer 400 has a lattice constant equal to the lattice constant of the second surface of the modified layer 300B, the compound semiconductor layer of the bottom cell C2 formed on the sacrificial layer 400 and the compound semiconductor layer of the top cell C1 ) Has the same lattice constant as that of the modified layer 300B, so there is no particular limitation in forming the sacrifice layer.
  • the sacrifice layer 400 may be formed to a thickness of 20 to 50 nm.
  • the compound semiconductor layer formed on the sacrifice layer 400 is formed in the same lattice as the denatured layer 300B In order to have a constant, the thickness of the sacrificial layer 400 must be very thin.
  • the sacrifice layer 400 when the sacrifice layer 400 is formed to a thickness of 1 nm to 10 nm, the sacrifice layer 400 is formed on the basis of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A
  • the compound semiconductor layer of the bottom cell C2 and the compound semiconductor layer of the top cell C1 have the same lattice constant as the lattice constant of the second surface of the modified layer 300B.
  • the sacrifice layer 400 is preferably formed to a thickness of 1 to 10 nm.
  • the compound semiconductor layer formed on the sacrificial layer 400 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or any other suitable method for forming an epitaxial layer, And may be formed by a regular growth method or an inverse growth method.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the sacrificial layer is removed by the ELF (epitaxial lift off) method using hydrofluoric acid (HF), so that the mother substrate 300-1 can be separated from the compound semiconductor layer.
  • ELF epiaxial lift off
  • HF hydrofluoric acid
  • the mother substrate 300-1 is formed of the GaAs wafer 300A and the modified layer 300B has been described.
  • mother board of the present invention can be modified into various forms.
  • the mother substrate 300-2 may be formed of a GaAs wafer 300A-2, a denatured layer 300B, and a sacrificial layer 400. As shown in FIG.
  • the modified layer 300 and the sacrificial layer 400 provided on the mother substrate of the second embodiment of the present embodiment are the same as those described in the first embodiment.
  • the mother substrate 300-3 of the third embodiment includes a GaAs wafer 300A, a modified layer 300B-3 located on one side of the GaAs wafer 300A, And a protective layer 300C-3 located on one side of the modified layer 300B-3.
  • the modified layer 300B-3 is formed by lattice constants of a plurality of compound semiconductor layers forming the bottom cell C2 and lattice constants of a plurality of compound semiconductor layers forming the top cell C1 to a lattice constant of the GaAs wafer 300A
  • the bandgap energy of the bottom cell C2 and the bandgap energy of the top cell C1 are adjusted so as to obtain an efficiency close to the maximum theoretical efficiency obtained in the compound semiconductor solar cell having the double junction structure.
  • the lattice constant of the modified layer 300B-3 varies along the thickness direction.
  • the lattice constant of the first surface in contact with the GaAs wafer 300A on both sides of the modified layer 300B-3 is equal to the lattice constant of the GaAs wafer 300A, and the lattice constant of the first surface contacting the protective layer 300C-
  • the lattice constant on the second surface is the same as the lattice constant of the protective layer 300C-3.
  • the atomic% of Ga may decrease stepwise, exponentially or logarithmically from the first surface to the second surface. Therefore, the lattice constant of the modified layer 300B-3 may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
  • the modified layer 300B-3 of this embodiment is formed of Ga v In 1 -v P, and the size of v for forming the lattice constant of the second surface of the modified layer 300B-3 from 5.70A to 5.77A Is in the range of 0.24 to 0.40, and the modified layer (300B-3) has a band gap energy of 1.60 to 1.80 eV.
  • the modified layer 300B-3 may be formed to a thickness of 200 to 300 nm, and may be formed of a plurality of films within the thickness range to increase the lattice constant from the first surface to the second surface.
  • the protective layer (300C-3) is formed on the modified layer (300B-3) to protect the modified layer (300B-3) in the ELO process, In w Ga 1 - it is formed of a single layer formed of a w As.
  • the protective layer 300C-3 has a band gap energy of 0.95 to 1.20 eV, and the protective layer 300C-3 has a band gap energy of 0.95 to 1.20 eV, with w having a lattice constant of 5.70 A to 5.77 A of 0.13 to 0.30.
  • a method of manufacturing a compound semiconductor solar cell using a mother substrate 300-3 including a modified layer 300B-3 formed on a GaAs wafer 300A and a protective layer 300C-3 will be described below.
  • the compound semiconductor layer CS3 for forming the first tunnel layer TRJ1 and the compound semiconductor layer CS1 for forming the top cell C1 are sequentially formed.
  • the sacrificial layer 400 may be made of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A or AlInAs or AlAsSb having the same lattice constant as the lattice constant of the protective layer 300C-3 .
  • the sacrifice layer 400 has a lattice constant equal to the lattice constant of the protective layer 300C-3, the compound semiconductor layer of the bottom cell C2 formed on the sacrifice layer 400 and the compound of the top cell C1 Since the semiconductor layer also has the same lattice constant as the protective layer 300C-3, there is no particular limitation in forming the sacrificial layer.
  • the sacrifice layer 400 may be formed to a thickness of 20 to 50 nm.
  • the compound semiconductor layer formed on the sacrifice layer 400 is formed on the protective layer 300C-
  • the thickness of the sacrificial layer 400 should be very thin.
  • the sacrifice layer 400 when the sacrifice layer 400 is formed to a thickness of 1 nm to 10 nm, the sacrifice layer 400 is formed on the basis of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A
  • the compound semiconductor layer of the bottom cell C2 and the compound semiconductor layer of the top cell C1 have the same lattice constant as the lattice constant of the protective layer 300C-3.
  • the sacrifice layer 400 is preferably formed to a thickness of 1 to 10 nm.
  • the sacrificial layer is removed by the ELF (epitaxial lift off) method using hydrofluoric acid (HF), so that the mother substrate 300-3 can be separated from the compound semiconductor layer
  • the protective layer 300C-3 for protecting the denatured layer 300B-3 in the ELO process is removed by using NH 4 OH / H 2 O 2 / DI water, H 3 PO 4 / H 2 O 2 / DI water, H 2 SO 4 / H 2 O 2 / DI water, or a mixture thereof.
  • the protective layer 300C-3 may not be removed.
  • the mother substrate 300-3 is formed of the GaAs wafer 300A, the modified layer 300B-3, and the protective layer 300C-3 has been described.
  • the mother substrate 300-4 may be formed of the GaAs wafer 300A, the denatured layer 300B-4, the protective layer 300C-4, and the sacrificial layer 400.
  • the manufacturing method of the present invention can also be used in manufacturing a compound semiconductor solar cell having a compound semiconductor layer having a triple junction or more structure.

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Abstract

The present invention relates to a motherboard, a method for fabrication of a compound semiconductor solar cell by using the motherboard, and a compound semiconductor solar cell. A motherboard according to an aspect of the present invention comprises a GaAs single crystal wafer or a Ge single crystal wafer; and a metamorphic layer being physically in direct contact with one surface of the GaAs single crystal wafer or the Ge single crystal wafer and changing in lattice constant with thickness directions. Of the opposite surfaces of the metamorphic layer, a first surface in contact with the GaAs single crystal wafer or the Ge single crystal wafer is formed to have a smaller lattice constant than that of a second surface opposite to the first surface and the lattice constant of the metamorphic layer may increase in a stepwise, exponential, or logarithmic manner from the first surface to the second surface.

Description

모기판, 상기 모기판을 이용한 화합물 반도체 태양전지의 제조 방법, 및 화합물 반도체 태양전지A mother substrate, a method for manufacturing a compound semiconductor solar cell using the mother substrate, and a compound semiconductor solar cell
본 발명은 모기판, 상기 모기판을 이용한 화합물 반도체 태양전지의 제조 방법, 및 화합물 반도체 태양전지에 관한 것으로, 보다 상세하게는 고효율의 화합물 반도체 태양전지를 제조할 수 있는 모기판, 상기 모기판을 이용한 화합물 반도체 태양전지의 제조 방법, 및 화합물 반도체 태양전지에 관한 것이다.The present invention relates to a mosquito board, a method of manufacturing a compound semiconductor solar cell using the mother board, and a compound semiconductor solar cell, and more particularly, to a mosquito board capable of producing a high efficiency compound semiconductor solar cell, A method of manufacturing a compound semiconductor solar cell, and a compound semiconductor solar cell.
화합물 반도체는 실리콘이나 게르마늄과 같은 단일 원소가 아닌 2종 이상의 원소가 결합되어 반도체로서 동작한다. 이러한 화합물 반도체는 현재 다양한 종류가 개발되어 다양한 분야에서 사용되고 있으며, 대표적으로, 광전 변환 효과를 이용한 발광 다이오드나 레이저 다이오드 등의 발광 소자, 태양 전지, 그리고 펠티어 효과(Peltier Effect)를 이용한 열전 변환 소자 등에 이용된다.The compound semiconductor is not a single element such as silicon or germanium, but two or more elements are combined to operate as a semiconductor. Currently, various kinds of compound semiconductors have been developed and used in various fields. Typical examples of such compound semiconductors include light emitting devices such as light emitting diodes and laser diodes using solar cells, solar cells, and thermoelectric conversion devices using Peltier effect .
이 중에서 화합물 반도체 태양전지는 갈륨 아세나이드(이하, GaAs라 함), 갈륨 인듐 인(이하, GaInP라 함), 갈륨 알루미늄 아세나이드(이하, GaAlAs라 함), 갈륨 인듐 아세나이드(이하, GaInAs라 함), 알루미늄 인듐 아세나이드(이하, AlInP라 함) 등의 Ⅲ-V족 화합물 반도체, 카드뮴 황(CdS), 카드뮴 텔루륨(CdTe), 아연 황(ZnS) 등의 Ⅱ-Ⅵ족 화합물 반도체, 구리 인듐 셀레늄(CuInSe2)으로 대표되는 I-Ⅲ-Ⅵ족 화합물 반도체 등을 사용하여 다양한 층들을 형성하고 있다.Among them, the compound semiconductor solar cell is composed of gallium arsenide (hereinafter referred to as GaAs), gallium indium phosphor (hereinafter referred to as GaInP), gallium aluminum arsenide (hereinafter referred to as GaAlAs), gallium indium arsenide II-VI compound semiconductors such as cadmium sulphide (CdS), cadmium tellurium (CdTe), zinc sulfide (ZnS), and the like; I-III-VI compound semiconductors typified by copper indium-selenium (CuInSe2) or the like are used to form various layers.
화합물 반도체로 형성되는 다양한 층(이하, 화합물 반도체층이라 함)들은 MOCVD(Metal Organic Chemical Vapor Deposition) 방법, MBE(Molecular Beam Epitaxy) 방법 또는 에피택셜층을 형성하기 위한 임의의 다른 적절한 방법에 의해 모기판(mother substrate)에 형성되고, 모기판에 형성되는 화합물 반도체층은 단일 접합 구조 또는 다중 접합 구조로 형성된다.(Hereinafter referred to as a compound semiconductor layer) may be formed by a metal organic chemical vapor deposition (MOCVD) method, an MBE (Molecular Beam Epitaxy) method, or any other suitable method for forming an epitaxial layer. The compound semiconductor layer formed on the mother substrate and formed on the mother substrate is formed as a single junction structure or a multiple junction structure.
여기에서, 단일 접합 구조의 화합물 반도체층은 단일 접합 구조의 화합물 반도체 태양전지를 형성하기 위한 것으로, 단일 접합 구조의 화합물 반도체 태양전지는 베이스층과 에미터층을 포함하는 1개의 셀(cell)을 구비한다.Here, the single-junction compound semiconductor layer is for forming a compound semiconductor solar cell having a single junction structure, and the compound semiconductor solar cell having a single junction structure has one cell including a base layer and an emitter layer do.
그리고 다중 접합 구조의 화합물 반도체층은 다중 접합 구조의 화합물 반도체 태양전지를 형성하기 위한 것으로, 다중 접합 구조의 화합물 반도체 태양전지는 베이스층과 에미터층을 포함하는 셀을 2개 이상 구비한다.The compound semiconductor layer of the multiple junction structure is for forming a compound semiconductor solar cell having a multi junction structure, and the compound semiconductor solar cell of the multiple junction structure comprises two or more cells including the base layer and the emitter layer.
따라서, 이중 접합 구조의 화합물 반도체 태양전지는 바텀 셀(bottom cell)과 탑 셀(top cell)을 구비하며, 삼중 접합 구조 이상의 접합 구조를 구비한 화합물 반도체 태양전지는 바텀 셀과 탑셀 및 이들 사이에 위치하는 1개 이상의 미들 셀(middle cell)을 구비한다.Therefore, a compound semiconductor solar cell having a double junction structure has a bottom cell and a top cell, and a compound semiconductor solar cell having a junction structure of triple junction structure or more has a bottom cell and a top cell, And has at least one middle cell positioned therein.
통상적으로, 화합물 반도체층을 형성하기 위한 모기판은 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼로 형성되고, GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼는 5.65Å의 격자상수(lattice constant)를 갖는다.Typically, the mother substrate for forming the compound semiconductor layer is formed of a GaAs single crystal wafer or a Ge single crystal wafer, and a GaAs single crystal wafer or a Ge single crystal wafer has a lattice constant of 5.65 angstroms.
따라서, 모기판 위에 형성되는 화합물 반도체층은 모기판과 동일한 격자상수를 갖게 된다.Therefore, the compound semiconductor layer formed on the mother substrate has the same lattice constant as the mother substrate.
이에, 이중 접합 구조의 화합물 반도체 태양전지에 있어서, 후면 전극 쪽에 위치한 바텀 셀(bottom cell)을 형성하는 화합물 반도체층은 전면 전극 쪽에 위치한 탑 셀을 형성하는 화합물 반도체층에 비해 밴드갭 에너지가 낮은 물질, 예를 들어 GaAs로 형성되고, 탑 셀을 형성하는 화합물 반도체층은 바텀 셀에 비해 밴드갭 에너지가 높은 물질, 예를 들어 GaInP로 형성된다.Therefore, in the compound semiconductor solar cell having a double junction structure, the compound semiconductor layer forming the bottom cell located on the rear electrode side has a lower band gap energy than the compound semiconductor layer forming the top cell located on the front electrode side For example, GaAs, and the compound semiconductor layer forming the top cell is formed of a material having a higher band gap energy than the bottom cell, for example, GaInP.
그런데, 도 1 및 도 2를 참조하면, 5.65Å을 갖는 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼에 이중 접합 구조의 화합물 반도체층을 성장시킨 경우, 바텀 셀은 GaAs 또는 Ge를 기반으로 형성된 베이스층을 구비하므로, 바텀 셀이 갖는 밴드갭 에너지는 바텀 셀의 베이스층이 갖는 밴드갭 에너지와 동일한 1.42eV의 밴드갭 에너지를 가질 수 밖에 없다.1 and 2, when a compound semiconductor layer having a double junction structure is grown on a GaAs single crystal wafer or a Ge single crystal wafer having 5.65 angstroms, the bottom cell has a base layer formed on the basis of GaAs or Ge , The band gap energy of the bottom cell has a band gap energy of 1.42 eV which is equal to the band gap energy of the base layer of the bottom cell.
그리고, 통상적으로 탑 셀은 GaInP를 기반으로 형성된 베이스층을 구비하므로, 탑 셀의 밴드갭 에너지는 탑 셀의 베이스층이 갖는 밴드갭 에너지와 동일한 1.88eV의 밴드갭 에너지를 가질 수 밖에 없다.And, since the top cell typically has a base layer formed on the basis of GaInP, the band gap energy of the top cell must have a band gap energy of 1.88 eV which is equal to the band gap energy of the base layer of the top cell.
이 경우, 도 3 및 도 4를 참조하면, GaAs를 기반으로 형성된 베이스층을 구비한 바텀 셀과 GaInP를 기반으로 형성된 베이스층을 구비한 탑 셀을 포함하는 이중 접합 구조의 화합물 반도체 태양전지의 이론 효율은 34.9%로 제한된다.In this case, referring to FIGS. 3 and 4, the theory of a double junction structure compound semiconductor solar cell including a bottom cell having a base layer formed on the basis of GaAs and a top cell having a base layer formed on the basis of GaInP The efficiency is limited to 34.9%.
그런데, 도 3 및 도 4를 참조하면, 이중 접합 구조의 화합물 반도체 태양전지에서 얻을 수 있는 최대 이론 효율은 37.5%이므로, 상기한 이중 접합 구조의 화합물 반도체 태양전지의 이론 효율은 상기 최대 이론 효율과 차이가 있다.3 and 4, since the maximum theoretical efficiency obtained in a compound semiconductor solar cell having a double junction structure is 37.5%, the theoretical efficiency of the compound semiconductor solar cell having the double junction structure is the same as the maximum theoretical efficiency There is a difference.
따라서, 이중 접합 구조의 화합물 반도체 태양전지의 이론 효율을 상기 최대 이론 효율까지 높일 수 있는 방안이 요구된다.Therefore, there is a need for a method of increasing the theoretical efficiency of the double junction structure compound semiconductor solar cell to the maximum theoretical efficiency.
본 발명은 최대 이론 효율에 근접한 고효율의 화합물 반도체 태양전지를 제조할 수 있는 모기판, 상기 모기판을 이용한 화합물 반도체 태양전지의 제조 방법, 및 고효율의 화합물 반도체 태양전지를 제공하는데 그 목적이 있다.It is an object of the present invention to provide a mother board capable of manufacturing a high efficiency compound semiconductor solar cell close to maximum theoretical efficiency, a method of manufacturing a compound semiconductor solar cell using the mother board, and a high efficiency compound semiconductor solar cell.
본 발명의 한 측면에 따른 모기판은 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼; 및 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 한쪽 면과 물리적으로 직접 접촉하며, 두께 방향을 따라 격자상수가 변하는 변성층(metamorphic layer)을 포함할 수 있다.A mother substrate according to one aspect of the present invention comprises a GaAs single crystal wafer or a Ge single crystal wafer; And a metamorphic layer in direct physical contact with one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction.
상기 변성층의 양쪽 면 중에서 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 접촉하는 제1 면에서의 격자상수는 상기 제1 면의 반대쪽에 위치하는 제2 면에서의 격자상수보다 작게 형성되며, 상기 변성층의 격자상수는 상기 제1 면으로부터 상기 제2 면으로 갈수록 계단식, 지수 함수적 또는 로그 함수적으로 증가할 수 있다.The lattice constant of the first surface contacting the GaAs single crystal wafer or the Ge single crystal wafer is formed to be smaller than the lattice constant of the second surface located on the opposite side of the first surface from both surfaces of the modified layer, The lattice constant of the first surface may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
상기 변성층의 제1 면에서의 격자상수는 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수와 동일할 수 있다.The lattice constant on the first surface of the modified layer may be equal to the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer.
상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼는 5.65Å의 격자상수를 가질 수 있으며, 상기 변성층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수보다 큰 5.70Å 내지 5.77Å의 격자상수를 가질 수 있다.The GaAs single crystal wafer or the Ge single crystal wafer may have a lattice constant of 5.65 A and the modified layer may have a lattice constant of 5.70 A to 5.77 A larger than the lattice constant of the GaAs single crystal wafer or Ge single crystal wafer.
상기한 격자상수를 갖는 변성층은 In xGa 1-xP 또는 In xGa 1-xAs로 형성될 수 있으며, 이때, 상기 제1 면에서의 상기 x는 0(zero)이고, 상기 제2 면에서의 상기 x는 0.19이다.The modified layer having the above-mentioned lattice constant may be formed of In x Ga 1-x P or In x Ga 1 -x As, wherein x on the first surface is zero, X in the plane is 0.19.
여기에서, x는 원자 %(atomic %)를 의미한다.Here, x means atomic% (atomic%).
상기 모기판은 상기 변성층의 제2 면과 물리적으로 직접 접촉하는 희생층을 더 포함할 수 있다.The mother substrate may further include a sacrificial layer in direct physical contact with the second surface of the modified layer.
상기 희생층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖거나, 상기 변성층의 제2 면에서의 격자상수와 서로 동일한 격자상수를 가질 수 있다.The sacrificial layer may have the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer or may have the same lattice constant as the lattice constant on the second surface of the modified layer.
상기 희생층이 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖는 경우, 상기 희생층은 1nm 내지 10nm의 두께로 형성되는 것이 바람직하며, AlAs 또는 AlGaAs를 기반으로 형성될 수 있다.When the sacrificial layer has the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer, the sacrifice layer is preferably formed to a thickness of 1 nm to 10 nm, and may be formed based on AlAs or AlGaAs.
이와 달리, 희생층이 상기 변성층의 제2 면에서의 격자상수와 서로 동일한 격자상수를 갖는 경우, 상기 희생층은 AlInAs 또는 AlAsSb를 기반으로 형성될 수 있다.Alternatively, if the sacrificial layer has a lattice constant equal to the lattice constant of the second surface of the modified layer, the sacrificial layer may be formed based on AlInAs or AlAsSb.
이러한 구성의 화합물 반도체 태양전지는, 모기판의 한쪽 면 위에 희생층을 형성하는 단계; 및 1개 이상의 셀을 형성하기 위한 화합물 반도체층을 상기 희생층 위에 형성하는 단계를 포함하는 화합물 반도체 태양전지의 제조 방법에 의해 제조할 수 있다.A compound semiconductor solar cell having such a configuration includes a step of forming a sacrificial layer on one side of a mother substrate; And forming a compound semiconductor layer for forming at least one cell on the sacrificial layer.
이때, 상기 모기판은 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼; 및 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 한쪽 면과 물리적으로 직접 접촉하며, 두께 방향을 따라 격자상수가 변하는 변성층(metamorphic layer)을 포함할 수 있다.At this time, the mother substrate may be a GaAs single crystal wafer or a Ge single crystal wafer; And a metamorphic layer in direct physical contact with one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction.
상기 변성층에 있어서, 상기 변성층의 양쪽 면 중에서 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 접촉하는 제1 면에서의 격자상수를 상기 제1 면의 반대쪽에 위치하는 제2 면에서의 격자상수보다 작게 형성할 수 있다. 이때, 상기 변성층의 격자상수는 상기 제1 면으로부터 상기 제2 면으로 갈수록 계단식, 지수 함수적 또는 로그 함수적으로 증가시킬 수 있다.In the modified layer, the lattice constant of the first surface contacting the GaAs single crystal wafer or the Ge single crystal wafer from both surfaces of the modified layer is smaller than the lattice constant of the second surface located on the opposite side of the first surface . At this time, the lattice constant of the modified layer can be increased stepwise, exponentially or logarithmically from the first surface to the second surface.
상기 변성층의 제1 면에서의 격자상수는 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수와 동일할 수 있다.The lattice constant on the first surface of the modified layer may be equal to the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer.
한 예로, 상기 변성층은 5.70Å 내지 5.77Å의 격자상수를 갖는 In xGa 1 -xP 또는 In xGa 1 - xAs로 형성할 수 있다. 이때, x는 원자 %(atomic %)를 의미하며, 상기 제1 면에서의 상기 x는 0(zero)이고, 상기 제2 면에서의 상기 x는 0.19이다.For example, the modified layer is In x Ga 1 -x P or In x Ga 1 having a lattice constant of 5.70Å to 5.77Å - can be formed as x As. Where x means atomic%, x on the first side is zero, and x on the second side is 0.19.
상기 희생층은 상기 변성층의 제2 면과 물리적으로 직접 접촉하도록 형성할 수 있으며, 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 형성하거나, 상기 변성층의 제2 면에서의 격자상수와 서로 동일한 격자상수를 갖는 AlInAs 또는 AlAsSb를 기반으로 형성할 수 있다.The sacrificial layer may be formed to be in direct physical contact with the second surface of the modified layer, and may be formed based on AlAs or AlGaAs having the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer, Can be formed based on AlInAs or AlAsSb having the same lattice constant as the lattice constant on the second surface.
상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 상기 희생층을 형성하는 경우, 상기 희생층 위에 형성되는 화합물 반도체층이 변성층과 동일한 격자상수를 갖도록 하기 위해서는 희생층을 1nm 내지 10nm의 두께로 형성하는 것이 바람직하다.When the sacrifice layer is formed on the GaAs single crystal wafer or the Ge single crystal wafer based on AlAs or AlGaAs having the same lattice constant as that of the GaAs monocrystalline wafer or the Ge single crystal wafer, in order to have the same lattice constant as that of the modified layer formed on the sacrifice layer, Layer is preferably formed to a thickness of 1 nm to 10 nm.
상기 화합물 반도체층을 형성할 때, 바텀 셀의 베이스층은 0.95eV 내지 1.20eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 In yGa 1 - yAs로 형성할 수 있고, 탑 셀의 베이스층은 1.60eV 내지 1.80eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 Ga zIn 1-zP로 형성할 수 있다. When forming the compound semiconductor layer, the base layer of the bottom cell may be formed of In y Ga 1 - y As having a band gap energy of 0.95 eV to 1.20 eV and a lattice constant of 5.70 Å to 5.77 Å, Can be formed of Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A.
이때, y 및 z는 각각 원자 %(atomic %)를 의미하며, 상기 y는 0.13 내지 0.30이고, 상기 z는 0.24 내지 0.40이다.Here, y and z mean atomic%, y is 0.13 to 0.30, and z is 0.24 to 0.40.
여기에서, y 및 z를 상기 범위로 한정하는 이유는 각 셀의 밴드갭을 효과적으로 낮추기 위한 화합물 반도체층의 격자상수를 만족시키기 위함이다.The reason why y and z are limited to the above range is to satisfy the lattice constant of the compound semiconductor layer for effectively lowering the bandgap of each cell.
그리고 상기 바텀 셀의 후면(back surface)에는 면전극(sheet electrode) 형상의 후면 전극을 형성할 수 있고, 상기 탑 셀의 전면(front surface)에는 그리드(grid) 형상의 전면 전극을 형성할 수 있다.A back electrode having a sheet electrode shape may be formed on a back surface of the bottom cell and a grid electrode may be formed on a front surface of the top cell. .
이러한 구성의 다중 접합 구조의 화합물 반도체 태양전지, 특히 이중 접합 구조의 화합물 반도체 태양전지는 0.95eV 내지 1.20eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 In yGa 1 - yAs로 형성되는 바텀 셀의 베이스층; 1.60eV 내지 1.80eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 Ga zIn 1 - zP로 형성하는 탑 셀의 베이스층; 상기 바텀 셀의 후면(back surface)에 위치하며, 면전극(sheet electrode) 형상으로 형성되는 후면 전극; 및 상기 탑 셀의 전면(front surface)에 위치하며, 그리드(grid) 형상으로 형성되는 전면 전극을 포함할 수 있다.A compound semiconductor solar cell having a multi junction structure of this structure, particularly a compound semiconductor solar cell having a double junction structure, has a band gap energy of 0.95 eV to 1.20 eV and a lattice constant of In y Ga 1 - y As having a lattice constant of 5.70 Å to 5.77 Å A base layer of a bottom cell formed; A base layer of a top cell formed of Ga z In 1 - z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A; A rear electrode disposed on a back surface of the bottom cell and formed in the form of a sheet electrode; And a front electrode formed on a front surface of the top cell and formed in a grid shape.
이때, 상기 y는 0.13 내지 0.30이고, 상기 z는 0.24 내지 0.40이다.Here, y is from 0.13 to 0.30, and z is from 0.24 to 0.40.
본 발명의 다른 측면에 따른 모기판은 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼; Ga vIn 1 -vP로 형성되고, 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 한쪽 면에 위치하며, 두께 방향을 따라 격자상수가 변하는 변성층(metamorphic layer); 및 In wGa 1 - wAs로 형성되고, 상기 변성층의 한쪽 면에 위치하는 보호층을 포함할 수 있다.A mother substrate according to another aspect of the present invention comprises a GaAs single crystal wafer or a Ge single crystal wafer; A metamorphic layer formed of Ga v In 1 -v P and located on one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction; And a protective layer formed of In w Ga 1 - w As and located on one side of the modified layer.
여기에서, v 및 w는 각각 원자 %(atomic %)를 의미한다.Here, v and w mean atomic%, respectively.
상기 변성층의 양쪽 면 중에서 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 접촉하는 제1 면에서의 격자상수는 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수와 동일하고, 상기 제1 면의 반대쪽에 위치하는 제2 면에서의 격자상수는 상기 제1 면에서의 격자상수보다 크고 상기 보호층의 격자상수와 동일하다.Wherein the lattice constant of the GaAs monocrystalline wafer or the Ge monocrystalline wafer on both sides of the modified layer is the same as the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer, The lattice constant on the second surface is greater than the lattice constant on the first surface and is equal to the lattice constant of the protective layer.
상기 변성층의 격자상수는 상기 제1 면으로부터 상기 제2 면으로 갈수록 계단식, 지수 함수적 또는 로그 함수적으로 증가할 수 있다.The lattice constant of the modified layer may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼는 5.65Å의 격자상수를 가지며, 상기 변성층 및 상기 보호층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수보다 큰 5.70Å 내지 5.77Å의 격자상수를 갖는다.The GaAs single crystal wafer or the Ge single crystal wafer has a lattice constant of 5.65 A and the denaturing layer and the protective layer have a lattice constant of 5.70 A to 5.77 A larger than the lattice constant of the GaAs single crystal wafer or Ge single crystal wafer.
상기 제1 면에서의 상기 변성층은 1.60 내지 1.80eV의 밴드갭 에너지를 갖는 Ga 0.52In 0.48P로 형성되고, 상기 제2 면에서의 상기 v는 0.24 내지 0.40이다.The modified layer on the first side is formed of Ga 0.52 In 0.48 P having a band gap energy of 1.60 to 1.80 eV, and v on the second side is 0.24 to 0.40.
상기 보호층에 있어서, 상기 w는 0.13 내지 0.30이다.In the protective layer, w is 0.13 to 0.30.
상기 모기판은 상기 보호층 위에 위치하는 희생층을 더 포함할 수 있다.The mother substrate may further include a sacrificial layer located on the protective layer.
상기 희생층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖거나, 상기 변성층의 제2 면에서의 격자상수와 서로 동일한 격자상수를 가질 수 있다.The sacrificial layer may have the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer or may have the same lattice constant as the lattice constant on the second surface of the modified layer.
상기 희생층이 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖는 경우, 상기 희생층은 1nm 내지 10nm의 두께로 형성되는 것이 바람직하며, AlAs 또는 AlGaAs를 기반으로 형성될 수 있다.When the sacrificial layer has the same lattice constant as the GaAs single crystal wafer or the Ge single crystal wafer, the sacrifice layer is preferably formed to a thickness of 1 nm to 10 nm, and may be formed based on AlAs or AlGaAs.
이와 달리, 희생층이 상기 변성층의 제2 면에서의 격자상수와 서로 동일한 격자상수를 갖는 경우, 상기 희생층은 AlInAs 또는 AlAsSb를 기반으로 형성될 수 있다.Alternatively, if the sacrificial layer has a lattice constant equal to the lattice constant of the second surface of the modified layer, the sacrificial layer may be formed based on AlInAs or AlAsSb.
이러한 구성의 화합물 반도체 태양전지는, 모기판의 한쪽 면 위에 희생층을 형성하는 단계; 및 1개 이상의 셀을 형성하기 위한 화합물 반도체층을 상기 희생층 위에 형성하는 단계를 포함하는 화합물 반도체 태양전지의 제조 방법에 의해 제조할 수 있다.A compound semiconductor solar cell having such a configuration includes a step of forming a sacrificial layer on one side of a mother substrate; And forming a compound semiconductor layer for forming at least one cell on the sacrificial layer.
이때, 상기 모기판은 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼; Ga vIn 1 -vP로 형성되고, 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 한쪽 면에 위치하며, 두께 방향을 따라 격자상수가 변하는 변성층(metamorphic layer); 및 In wGa 1 - wAs로 형성되고, 상기 변성층의 한쪽 면에 위치하는 보호층을 포함할 수 있고, 상기 변성층의 양쪽 면 중에서 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 접촉하는 제1 면에서의 격자상수는 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수와 동일하고, 상기 제1 면의 반대쪽에 위치하는 제2 면에서의 격자상수는 상기 제1 면에서의 격자상수보다 크고 상기 보호층의 격자상수와 동일하다.At this time, the mother substrate may be a GaAs single crystal wafer or a Ge single crystal wafer; A metamorphic layer formed of Ga v In 1 -v P and located on one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction; And In w Ga 1 - w As, and may include a protective layer located on one side of the modified layer, and the first side contacting the GaAs single crystal wafer or the Ge single crystal wafer from both sides of the modified layer Wherein the lattice constant at the second surface located on the opposite side of the first surface is larger than the lattice constant at the first surface and the lattice constant at the second surface located at the opposite side of the first surface is larger than the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer, Lt; / RTI >
이때, v 및 w는 각각 원자 %(atomic %)를 의미한다.Here, v and w mean atomic%, respectively.
상기 변성층의 격자상수는 상기 제1 면으로부터 상기 제2 면으로 갈수록 계단식, 지수 함수적 또는 로그 함수적으로 증가시킬 수 있다.The lattice constant of the modified layer can be increased stepwise, exponentially or logarithmically from the first surface to the second surface.
상기 제1 면에서의 상기 변성층은 1.60 내지 1.80eV의 밴드갭 에너지를 갖는 Ga 0.52In 0.48P로 형성하고, 상기 제2 면에서의 상기 v는 0.24 내지 0.40이다. The modified layer on the first side is formed of Ga 0.52 In 0.48 P having a band gap energy of 1.60 to 1.80 eV, and v on the second side is 0.24 to 0.40.
상기 희생층은 상기 보호층 위에 형성할 수 있으며, 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 형성하거나, 상기 변성층의 제2 면에서의 격자상수와 서로 동일한 격자상수를 갖는 AlInAs 또는 AlAsSb를 기반으로 형성할 수 있다.The sacrificial layer may be formed on the protective layer. The sacrificial layer may be formed on the GaAs single crystal wafer or the Ge single crystal wafer based on AlAs or AlGaAs having the same lattice constant, or may be formed on the second surface of the modified layer, Can be formed based on AlInAs or AlAsSb having the same lattice constant.
상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 상기 희생층을 형성하는 경우, 상기 희생층 위에 형성되는 화합물 반도체층이 변성층과 동일한 격자상수를 갖도록 하기 위해서는 희생층을 1nm 내지 10nm의 두께로 형성하는 것이 바람직하다.When the sacrifice layer is formed on the GaAs single crystal wafer or the Ge single crystal wafer based on AlAs or AlGaAs having the same lattice constant as that of the GaAs monocrystalline wafer or the Ge single crystal wafer, in order to have the same lattice constant as that of the modified layer formed on the sacrifice layer, Layer is preferably formed to a thickness of 1 nm to 10 nm.
본 발명에 따르면, 모기판은 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼에 비해 증가된 격자상수를 갖는 변성층(및 변성층을 보호하는 보호층)을 구비하고, 화합물 반도체층이 변성층(또는 보호층) 위에 위치한다.According to the present invention, the mother substrate has a modified layer (and a protective layer for protecting the denatured layer) having an increased lattice constant as compared with a GaAs single crystal wafer or a Ge single crystal wafer, and the compound semiconductor layer is a denatured layer Lt; / RTI >
그런데, 격자상수가 증가하면 바텀 셀 및 탑 셀의 밴드갭 에너지를 종래에 비해 낮출 수 있다.However, if the lattice constant increases, the band gap energy of the bottom cell and the top cell can be lowered as compared with the prior art.
즉, 바텀 셀과 탑 셀이 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 동일한 격자상수를 갖는 종래의 이중 접합 구조의 화합물 반도체 태양전지에서는 바텀 셀의 밴드갭 에너지가 1.42eV이고 탑 셀의 밴드갭 에너지가 1.88eV이므로 이론 효율이 34.9% 정도로 제한된다.That is, in the conventional double junction compound semiconductor solar cell having the same lattice constant as the GaAs single crystal wafer or the Ge cell single crystal wafer in the bottom cell and the top cell, the band gap energy of the bottom cell is 1.42 eV and the band gap energy of the top cell is 1.88 eV, the theoretical efficiency is limited to about 34.9%.
하지만, 본 발명에 있어서, 바텀 셀의 밴드갭 에너지는 1.1eV 수준으로 낮출 수 있고, 탑 셀의 밴드갭 에너지는 1.7eV 수준으로 낮출 수 있다.However, in the present invention, the band gap energy of the bottom cell can be reduced to 1.1 eV, and the band gap energy of the top cell can be reduced to 1.7 eV.
따라서, 이중 접합 구조의 화합물 반도체 태양전지에서 얻을 수 있는 최대 이론 효율에 근접하는 밴드갭 에너지를 갖도록 화합물 반도체 태양전지의 바텀 셀과 탑 셀을 형성할 수 있다.Accordingly, the bottom cell and the top cell of the compound semiconductor solar cell can be formed so as to have a band gap energy close to the maximum theoretical efficiency obtained in a compound semiconductor solar cell having a double junction structure.
종래에는 희생층을 사용하여 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼를 화합물 반도체층과 분리시키지 않고, GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼 위에 화합물 반도체층을 직접 형성하며, 화합물 반도체층 사이에 변성층을 형성하여 셀 사이의 격자상수를 변화시켜 밴드갭 에너지를 조정하는 경우가 있다.Conventionally, a sacrificial layer is used to directly form a compound semiconductor layer on a GaAs single crystal wafer or a Ge single crystal wafer without separating the GaAs single crystal wafer or the Ge single crystal wafer from the compound semiconductor layer, thereby forming a modified layer between the compound semiconductor layers, The band gap energy may be adjusted by changing the lattice constant between the band gap energy and the band gap energy.
하지만, 이 경우에는 고가인 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼를 재사용할 수 없음과 아울러, 증착 시간이 셀을 형성하기 위한 화합물 반도체층에 비해 오래 걸리는 변성층을 화합물 반도체 태양전지를 제조할 때마다 형성해야 하는 문제점이 있다.However, in this case, expensive GaAs single crystal wafers or Ge single crystal wafers can not be reused, and a modified layer in which a deposition time is longer than that of a compound semiconductor layer for forming a cell is formed every time a compound semiconductor solar cell is manufactured There is a problem to be done.
그러나 본 발명에서는 변성층이 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼 바로 위에 형성되고, 선택적으로 보호층이 변성층 바로 위에 형성되므로, ELO(epitaxial lift off) 공정을 통해 희생층을 제거한 후에는 변성층 및/또는 변성층과 보호층을 포함하는 모기판을 재사용할 수 있다.However, in the present invention, since the modified layer is formed directly on the GaAs single crystal wafer or the Ge single crystal wafer, and optionally the protective layer is formed directly on the modified layer, after the sacrificial layer is removed through the ELO (epitaxial lift off) Or the mother board comprising the denaturation layer and the protective layer can be reused.
따라서, 셀과 셀 사이에 변성층을 사용하여 격자상수 및 밴드갭 에너지를 조정하는 경우에 비해 제조 원가를 절감할 수 있고, 화합물 반도체층의 형성 시간을 줄일 수 있다.Therefore, manufacturing cost can be reduced and formation time of the compound semiconductor layer can be reduced compared with the case where the lattice constant and the band gap energy are adjusted using the modified layer between the cell and the cell.
본 발명의 모기판은 하나 이상의 미들 셀을 포함하는 삼중 접합 구조 이상의 다중 접합 구조를 갖는 화합물 반도체 태양전지의 제조에도 사용할 수 있다.The mother substrate of the present invention can also be used for the production of a compound semiconductor solar cell having a multi-junction structure of triple junction structure or more including at least one middle cell.
도 1은 화합물 반도체층을 형성하는 다양한 물질의 밴드갭 에너지와 격자상수의 상관 관계를 나타내는 그래프이다.FIG. 1 is a graph showing the correlation between the band gap energy and the lattice constant of various materials forming the compound semiconductor layer.
도 2는 격자상수 변화에 따른 탑 셀 및 바텀 셀의 밴드갭 에너지의 상관 관계를 나타내는 그래프이다.2 is a graph showing a correlation between band gap energies of a top cell and a bottom cell according to a lattice constant change.
도 3은 3가지 측정 환경에서 격자상수와 이론 효율의 상관 관계를 나타내는 그래프이다.3 is a graph showing the correlation between the lattice constant and the theoretical efficiency in three measurement environments.
도 4는 지상 환경에서 사용하는 화합물 반도체 태양전지의 탑 셀과 바텀 셀의 밴드갭 에너지의 크기와 이론 효율의 상관 관계를 나타내는 도면이다.4 is a graph showing the correlation between the magnitude of the band gap energy of the top cell and the bottom cell of the compound semiconductor solar cell used in the terrestrial environment and the theoretical efficiency.
도 5는 격자 상수의 크기에 따른 탑 셀의 제1 광 흡수층의 밴드갭 에너지와 바텀 셀의 제2 광 흡수층의 밴드갭 에너지의 변화 및 이론 효율을 측정한 테이블이다.FIG. 5 is a table showing changes in the band gap energy of the first light absorbing layer of the top cell and the band gap energy of the second light absorbing layer of the bottom cell according to the size of the lattice constant and the theoretical efficiency.
도 6은 본 발명의 제1 실시예에 따른 모기판의 단면도이다.6 is a sectional view of a mother board according to the first embodiment of the present invention.
도 7은 본 발명의 제2 실시예에 따른 모기판의 단면도이다.7 is a sectional view of a mother board according to a second embodiment of the present invention.
도 8은 도 6에 도시한 모기판을 사용하여 화합물 반도체 태양전지를 제조하는 방법을 나타내는 공정도이다.8 is a process diagram showing a method of manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
도 9는 본 발명의 제3 실시예에 따른 모기판의 단면도이다.9 is a sectional view of a mother board according to a third embodiment of the present invention.
도 10은 본 발명의 제4 실시예에 따른 모기판의 단면도이다.10 is a sectional view of a mother board according to a fourth embodiment of the present invention.
도 11은 도 9에 도시한 모기판을 사용하여 화합물 반도체 태양전지를 제조하는 방법을 나타내는 공정도이다.11 is a process diagram showing a method for manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
도 12는 도 8 또는 도 11에 도시한 제조 방법에 의해 제조한 화합물 반도체 태양전지의 단면도이다.12 is a cross-sectional view of a compound semiconductor solar cell manufactured by the manufacturing method shown in Fig. 8 or Fig.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해될 수 있다.While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood that the present invention is not intended to be limited to the specific embodiments but includes all changes, equivalents, and alternatives falling within the spirit and scope of the present invention.
본 발명을 설명함에 있어서 제1, 제2 등의 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되지 않을 수 있다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용될 수 있다. In describing the present invention, the terms first, second, etc. may be used to describe various components, but the components may not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another.
예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성요소는 제2 구성요소로 명명될 수 있고, 유사하게 제2 구성요소도 제1 구성요소로 명명될 수 있다.For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.
"및/또는" 이라는 용어는 복수의 관련된 기재된 항목들의 조합 또는 복수의 관련된 기재된 항목들 중의 어느 항목을 포함할 수 있다.The term "and / or" may include any combination of a plurality of related listed items or any of a plurality of related listed items.
어떤 구성요소가 다른 구성요소에 "연결되어" 있다거나 "결합되어" 있다고 언급되는 경우는, 그 다른 구성요소에 직접적으로 연결되어 있거나 또는 결합되어 있을 수도 있지만, 중간에 다른 구성요소가 존재할 수도 있다고 이해될 수 있다.Where an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, but other elements may be present in between Can be understood.
반면에, 어떤 구성요소가 다른 구성요소에 "직접 연결되어" 있다거나 "직접 결합되어" 있다고 언급된 때에는, 중간에 다른 구성요소가 존재하지 않는 것으로 이해될 수 있다.On the other hand, when it is mentioned that an element is "directly connected" or "directly coupled" to another element, it can be understood that no other element exists in between.
본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함할 수 있다.The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions may include plural expressions unless the context clearly dictates otherwise.
본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것으로서, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해될 수 있다.In the present application, the terms "comprises", "having", and the like are used interchangeably to designate one or more of the features, numbers, steps, operations, elements, components, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.
도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 층, 막, 영역, 판 등의 부분이 다른 부분 "위에" 있다고 할 때, 이는 다른 부분 "바로 위에" 있는 경우뿐 아니라 그 중간에 다른 부분이 있는 경우도 포함한다. 반대로 어떤 부분이 다른 부분 "바로 위에" 있다고 할 때에는 중간에 다른 부분이 없는 것을 뜻한다.In the drawings, the thickness is enlarged to clearly represent the layers and regions. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가질 수 있다. Unless otherwise defined, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미를 가지는 것으로 해석될 수 있으며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않을 수 있다.Terms such as those defined in commonly used dictionaries can be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are, unless expressly defined in the present application, interpreted in an ideal or overly formal sense .
아울러, 이하의 실시예는 당 업계에서 평균적인 지식을 가진 자에게 보다 완전하게 설명하기 위해서 제공되는 것으로서, 도면에서의 요소들의 형상 및 크기 등은 보다 명확한 설명을 위해 과장될 수 있다.In addition, the following embodiments are provided to explain more fully to the average person skilled in the art. The shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.
이하, 첨부도면을 참조하여 본 발명을 설명한다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
도 1은 화합물 반도체층을 형성하는 다양한 물질의 밴드갭 에너지와 격자상수의 상관 관계를 나타내는 그래프이다.FIG. 1 is a graph showing the correlation between the band gap energy and the lattice constant of various materials forming the compound semiconductor layer.
도 2는 격자상수 변화에 따른 탑 셀 및 바텀 셀의 밴드갭 에너지의 상관 관계를 나타내는 그래프이다.2 is a graph showing a correlation between band gap energies of a top cell and a bottom cell according to a lattice constant change.
도 3은 3가지 측정 환경에서 격자상수와 이론 효율의 상관 관계를 나타내는 그래프이다.3 is a graph showing the correlation between the lattice constant and the theoretical efficiency in three measurement environments.
도 4는 지상 환경에서 사용하는 화합물 반도체 태양전지의 탑 셀과 바텀 셀의 밴드갭 에너지의 크기와 이론 효율의 상관 관계를 나타내는 도면이다.4 is a graph showing the correlation between the magnitude of the band gap energy of the top cell and the bottom cell of the compound semiconductor solar cell used in the terrestrial environment and the theoretical efficiency.
도 5는 격자 상수의 크기에 따른 탑 셀의 제1 광 흡수층의 밴드갭 에너지와 바텀 셀의 제2 광 흡수층의 밴드갭 에너지의 변화 및 이론 효율을 측정한 테이블이다.FIG. 5 is a table showing changes in the band gap energy of the first light absorbing layer of the top cell and the band gap energy of the second light absorbing layer of the bottom cell according to the size of the lattice constant and the theoretical efficiency.
도 6은 본 발명의 제1 실시예에 따른 모기판의 단면도이다.6 is a sectional view of a mother board according to the first embodiment of the present invention.
도 7은 본 발명의 제2 실시예에 따른 모기판의 단면도이다.7 is a sectional view of a mother board according to a second embodiment of the present invention.
도 8은 도 6에 도시한 모기판을 사용하여 화합물 반도체 태양전지를 제조하는 방법을 나타내는 공정도이다.8 is a process diagram showing a method of manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
도 9는 본 발명의 제3 실시예에 따른 모기판의 단면도이다.9 is a sectional view of a mother board according to a third embodiment of the present invention.
도 10은 본 발명의 제4 실시예에 따른 모기판의 단면도이다.10 is a sectional view of a mother board according to a fourth embodiment of the present invention.
도 11은 도 9에 도시한 모기판을 사용하여 화합물 반도체 태양전지를 제조하는 방법을 나타내는 공정도이다.11 is a process diagram showing a method for manufacturing a compound semiconductor solar cell using the mother substrate shown in Fig.
도 12는 도 8 또는 도 11에 도시한 제조 방법에 의해 제조한 화합물 반도체 태양전지의 단면도이다.12 is a cross-sectional view of a compound semiconductor solar cell manufactured by the manufacturing method shown in Fig. 8 or Fig.
먼저, 본 발명의 모기판을 사용한 화합물 반도체 태양전지의 제조 방법에 의해 제조한 이중 접합 구조의 화합물 반도체층을 구비한 화합물 반도체 태양전지에 대해 도 12를 참조하여 설명한다.First, a compound semiconductor solar cell having a double junction structure compound semiconductor layer manufactured by the method for manufacturing a compound semiconductor solar cell using the mother substrate of the present invention will be described with reference to FIG.
이중 접합 구조의 화합물 반도체층을 구비한 화합물 반도체 태양전지는 탑 셀(C1), 탑 셀(C1)의 전면(front surface)에 위치하는 그리드(grid) 형상의 전면 전극(100), 탑 셀(C1)의 후면에 위치하는 바텀 셀(C2), 탑 셀(C1)과 바텀 셀(C2)의 사이에 위치하는 제1 터널층(TRJ1), 및 바텀 셀(C2)의 후면에 위치하는 면전극(sheet electrode) 형상의 후면 전극(200)을 포함한다.The compound semiconductor solar cell having the double junction structure compound semiconductor layer includes a top cell C1, a grid-shaped front electrode 100 located on the front surface of the top cell C1, The first tunnel layer TRJ1 located between the top cell C1 and the bottom cell C2 and the first tunnel layer TRJ1 located between the top cell C1 and the bottom cell C2, and a rear electrode 200 having a sheet electrode shape.
이때, 탑 셀(C1)과 바텀 셀(C2) 및 제1 터널층(TRJ1)을 각각 형성하는 복수의 층들은 모두 화합물 반도체로 형성되고, 전면 전극(100)과 후면 전극(200)은 도전성 금속으로 형성된다.At this time, the plurality of layers forming the top cell C1, the bottom cell C2 and the first tunnel layer TRJ1 are all formed of a compound semiconductor, and the front electrode 100 and the rear electrode 200 are formed of a conductive metal .
탑 셀(C1)은 제1 광 흡수층(PV1), 제1 광 흡수층(PV1)의 제1 면, 예를 들어 전면(front surface)에 위치하는 제1 윈도우층(WD1), 제1 윈도우층(WD1)의 전면에 위치하는 전면 콘택층(FC), 및 제1 광 흡수층(PV1)의 제2 면, 예를 들어 후면에 위치하는 제1 후면 전계층(BSF1)을 포함한다.The top cell C1 includes a first light absorbing layer PV1, a first surface of the first light absorbing layer PV1, for example, a first window layer WD1 located on a front surface, And a first rear front layer BSF1 located on the second side of the first light absorbing layer PV1, for example, the rear side.
제1 광 흡수층(PV1)은 n형 불순물을 포함하며 제1 윈도우층(WD1)과 접촉하는 제1 베이스층(PV1-1)과, p형 불순물을 포함하여 제1 베이스층(PV1-1)과 pn 접합을 형성하며 제1 베이스층(PV1-1)의 후면에 위치하는 제1 에미터층(PV1-2)을 포함하며, 제1 베이스층(PV1-1)과 제1 에미터층(PV1-2)은 인듐 인(이하, InP라 함) 기반의 화합물 반도체로 형성된다.The first light absorbing layer PV1 includes a first base layer PV1-1 including an n-type impurity and in contact with the first window layer WD1, a first base layer PV1-1 including a p-type impurity, And a first emitter layer PV1-2 located on the rear surface of the first base layer PV1-1 and forming a pn junction with the first base layer PV1-1 and the first emitter layer PV1-1, 2) is formed of an indium phosphide (hereinafter referred to as InP) -based compound semiconductor.
한 예로, 제1 베이스층(PV1-1)은 1.60eV 내지 1.80eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 n형 Ga zIn 1-zP로 형성되고, 제1 에미터층(PV1-2)은 1.60eV 내지 1.80eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p형 Ga zIn 1-zP로 형성된다.As an example, the first base layer PV1-1 is formed of n-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A, (PV1-2) is formed of p-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 Å to 5.77 Å.
이때, 상기 z는 0.24 내지 0.40 인데, 상기 z의 범위를 한정하는 이유는 탑 셀의 격자상수를 효과적으로 저감시킴으로써 탑 셀의 밴드갭을 효과적으로 낮출 수 있도록 하기 위함이다.In this case, z is in the range of 0.24 to 0.40. The reason for limiting the range of z is to effectively reduce the bandgap of the top cell by effectively reducing the lattice constant of the top cell.
한 예로, 제1 베이스층(PV1-1)은 1.7eV의 밴드갭 에너지를 갖는 n형 Ga 0.33In 0.67P로 형성될 수 있고, 제1 에미터층(PV1-2)은 1.7eV의 밴드갭 에너지를 갖는 p형 Ga 0.33In 0.67P로 형성될 수 있다.For example, the first base layer PV1-1 may be formed of n-type Ga 0.33 In 0.67 P having a band gap energy of 1.7 eV, and the first emitter layer PV1-2 may have a band gap energy of 1.7 eV Lt; RTI ID = 0.0 > Ga 0.33 In 0.67 P. < / RTI >
제1 에미터층(PV1-2)에 도핑되는 p형 불순물은 탄소(C), 마그네슘(Mg), 아연(Zn) 또는 이들의 조합으로부터 선택될 수 있고, 제1 베이스층(PV1-1)에 도핑되는 n형 불순물은 실리콘(Si), 셀레늄(Se), 텔루륨(Te) 또는 이들의 조합으로부터 선택될 수 있다.The p-type impurity doped in the first emitter layer PV1-2 may be selected from carbon (C), magnesium (Mg), zinc (Zn), or a combination thereof. The doped n-type impurity may be selected from silicon (Si), selenium (Se), tellurium (Te), or a combination thereof.
이에 따라, 제1 광 흡수층(PV1)의 내부에는 제1 에미터층(PV1-2)과 제1 베이스층(PV1-1)이 접합된 pn 접합이 형성되므로, 제1 광 흡수층(PV1)으로 입사된 빛에 의해 생성된 전자-정공 쌍은 제1 광 흡수층(PV1)의 pn 접합에 의해 형성된 내부 전위차에 의해 전자와 정공으로 분리되어 전자는 n형 쪽으로 이동하고, 정공은 p형 쪽으로 이동한다.Accordingly, a pn junction in which the first emitter layer PV1-2 and the first base layer PV1-1 are joined is formed in the first light-absorbing layer PV1, so that the first light- The electron-hole pairs generated by the light are separated into electrons and holes by the internal potential difference formed by the pn junction of the first light-absorbing layer PV1, the electrons move toward the n-type, and the holes move toward the p-type.
따라서, 제1 광 흡수층(PV1)에서 생성된 정공은 바텀 셀(C2)을 통하여 후면 전극(200)으로 이동하고, 제1 광 흡수층(PV1)에서 생성된 전자는 제1 윈도우층(WD1)과 전면 콘택층(FC)을 통해 전면 전극(100)으로 이동한다.Therefore, the holes generated in the first light absorbing layer PV1 move to the rear electrode 200 through the bottom cell C2, and the electrons generated in the first light absorbing layer PV1 pass through the first window layer WD1, And moves to the front electrode 100 through the front contact layer FC.
이와 달리, 제1 에미터층(PV1-2)과 제1 베이스층(PV1-1)의 위치가 서로 바뀐 경우, 제1 광 흡수층(PV1)에서 생성된 정공은 전면 콘택층(FC)을 통하여 전면 전극(100)으로 이동하고, 제1 광 흡수층(PV1)에서 생성된 전자는 후면 콘택층(BC)을 통하여 후면 전극(200)으로 이동한다.Alternatively, when the positions of the first emitter layer PV1-2 and the first base layer PV1-1 are changed from each other, holes generated in the first light absorbing layer PV1 may be transmitted through the front contact layer FC The electrons generated in the first light absorbing layer PV1 move to the rear electrode 200 through the rear contact layer BC.
제1 후면 전계층(BSF1)은 물리적으로 직접 접촉하고 있는 제1 에미터층(PV1-2)과 동일한 도전성 타입을 가지며, 제1 윈도우층(WD1)과 동일하게 InP를 기반으로 하는 물질, 예를 들어 p형 AlInP로 형성될 수 있다. The first backside front layer BSF1 has the same conductivity type as the first emitter layer PV1-2 physically in direct contact and is made of an InP-based material similar to the first window layer WD1, For example, p-type AlInP.
한 예로, 제1 후면 전계층(BSF1)은 2.2eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p형 Al 0.67In 0.33P로 형성될 수 있다.As an example, the first backside front layer (BSF1) may be formed of p-type Al 0.67 In 0.33 P having a band gap energy of 2.2 eV and a lattice constant of 5.70 A to 5.77 A.
제1 후면 전계층(BSF1)은 전면 전극(100) 쪽으로 이동해야 할 전하(정공 또는 전자)가 후면 전극(200) 쪽으로 이동하는 것을 효과적으로 차단(blocking)하기 위해, 물리적으로 직접 접촉하고 있는 제1 에미터층(PV1-2)의 후면에 전체적으로(entirely) 형성된다.The first rear whole front layer BSF1 is formed of a first rear front layer BSF1 and a second rear front layer BSF2 which are physically in direct contact with each other in order to effectively block charges (holes or electrons) Is formed entirely on the back surface of the emitter layer PV1-2.
제1 에미터층(PV1-2)과 제1 베이스층(PV1-1)은 서로 동일한 밴드갭 에너지를 갖는 서로 동일한 물질로 이루어질 수 있고(동종 접합), 이와 달리, 서로 다른 밴드갭 에너지를 갖는 서로 다른 물질로 이루어질 수 있다(이종 접합).The first emitter layer PV1-2 and the first base layer PV1-1 can be made of the same material (homogeneous junction) having the same band gap energies and can be made of different materials having different band gap energies It can be made of other materials (heterojunction).
동종 접합의 경우, 제1 베이스층(PV1-1)은 1.60eV 내지 1.80eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 n형 Ga zIn 1-zP로 형성될 수 있고, 제1 에미터층(PV1-2)은 1.60eV 내지 1.80eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p형 Ga zIn 1-zP로 형성될 수 있다.In the case of homojunction, the first base layer PV1-1 may be formed of n-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A, The first emitter layer PV1-2 may be formed of p-type Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 Å to 5.77 Å.
제1 윈도우층(WD1)은 제1 광 흡수층(PV1)과 전면 전극(100) 사이에 형성될 수 있으며, III-VI족 반도체 화합물에 n형의 불순물을 도핑하여 형성할 수 있다.The first window layer WD1 may be formed between the first light absorbing layer PV1 and the front electrode 100 and may be formed by doping an n-type impurity into the III-VI group semiconductor compound.
그러나, 제1 에미터층(PV1-2)이 제1 베이스층(PV1-1) 위에 위치하고 제1 윈도우층(WD1)이 제1 에미터층(PV1-2) 위에 위치하는 경우, 제1 윈도우층(WD1)은 p형의 불순물을 포함할 수 있다.However, when the first emitter layer PV1-2 is located on the first base layer PV1-1 and the first window layer WD1 is located on the first emitter layer PV1-2, WD1) may include a p-type impurity.
제1 윈도우층(WD1)은 제1 광 흡수층(PV1)의 전면(front surface)을 패시베이션(passivation)하는 기능을 한다. 따라서, 제1 광 흡수층(PV1)의 표면으로 캐리어(전자나 정공)가 이동할 경우, 제1 윈도우층(WD1)은 캐리어가 제1 광 흡수층(PV1)의 표면에서 재결합하는 것을 방지할 수 있다.The first window layer WD1 functions to passivate the front surface of the first light absorbing layer PV1. Therefore, when carriers (electrons and holes) move to the surface of the first light absorbing layer PV1, the first window layer WD1 can prevent the carriers from recombining on the surface of the first light absorbing layer PV1.
아울러, 제1 윈도우층(WD1)은 제1 광 흡수층(PV1)의 전면, 즉 광 입사면에 배치되므로, 제1 광 흡수층(PV1)으로 입사되는 빛을 거의 흡수하지 않도록 하기 위하여 제1 광 흡수층(PV1)의 밴드갭 에너지 에너지보다 높은 밴드갭 에너지 에너지를 가질 필요가 있다.In addition, since the first window layer WD1 is disposed on the front surface of the first light absorbing layer PV1, that is, on the light incident surface, the first light absorbing layer PV1 is formed on the first light absorbing layer PV1, It is necessary to have a band gap energy energy higher than the band gap energy energy of the first photovoltaic element PV1.
또한, 불산을 이용한 ELO 공정에서 용해되기 어려운 물질로 제1 윈도우층(WD1)을 형성할 필요가 있다.In addition, it is necessary to form the first window layer WD1 with a substance which is hardly dissolved in the ELO process using hydrofluoric acid.
따라서, 한 예로, 제1 윈도우층(WD1)은 2.2eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 n형 Al 0.33In 0.67P로 형성될 수 있다.Thus, for example, the first window layer WD1 may be formed of n-type Al 0.33 In 0.67 P having a band gap energy of 2.2 eV and a lattice constant of 5.70 A to 5.77 A.
제1 후면 전계층(BSF1)은 제1 윈도우층(WD1)의 두께보다 두껍게 형성될 수 있다. 한 예로, 제1 후면 전계층(BSF1)은 50 내지 100nm의 두께로 형성될 수 있다.The first rear whole layer BSF1 may be thicker than the first window layer WD1. As an example, the first rear whole layer BSF1 may be formed to a thickness of 50 to 100 nm.
반사 방지막(도시하지 않음)은 제1 윈도우층(WD1)의 전면 위 중에서 전면 전극(100) 및/또는 전면 콘택층(FC)이 위치하는 영역을 제외한 나머지 영역에 위치할 수 있다.The antireflection film (not shown) may be located in a region other than the region where the front electrode 100 and / or the front contact layer FC are located in the front surface of the first window layer WD1.
이와 달리, 반사 방지막은 제1 윈도우층(WD1) 뿐만 아니라, 전면 콘택층(FC) 및 전면 전극(100) 위에도 배치될 수 있다.Alternatively, the antireflection film may be disposed on the front contact layer FC and the front electrode 100 as well as the first window layer WD1.
이러한 구성의 반사 방지막은 불화마그네슘, 황화아연, 티타늄 옥사이드, 실리콘 옥사이드, 이들의 유도체 또는 이들의 조합을 포함할 수 있다.The antireflection film having such a configuration may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or a combination thereof.
화합물 반도체 태양전지는 복수의 전면 전극(100)을 물리적으로 연결하는 버스바 전극을 더 구비할 수 있으며, 버스바 전극은 반사 방지막에 의해 덮여지지 않고 외부로 노출될 수 있다.The compound semiconductor solar cell may further include a bus bar electrode physically connecting the plurality of front electrodes 100. The bus bar electrode may be exposed to the outside without being covered by the antireflection film.
전면 전극(100)은 제1 방향으로 길게 연장되어 형성될 수 있으며, 제1 방향과 직교하는 제2 방향(Y-Y')을 따라 복수개가 일정한 간격으로 이격될 수 있다.The front electrode 100 may be formed to extend in the first direction and spaced apart at a predetermined interval along a second direction Y-Y 'orthogonal to the first direction.
이러한 구성의 전면 전극(100)은 전기 전도성 물질을 포함하여 형성될 수 있으며, 일례로 금속인 금(Au), 게르마늄(Ge), 니켈(Ni) 중 적어도 하나를 포함하여 형성될 수 있다.The front electrode 100 having such a structure may be formed to include an electrically conductive material and may include at least one of gold (Au), germanium (Ge), and nickel (Ni), for example.
제1 윈도우층(WD1)과 전면 전극(100) 사이에 위치하는 전면 콘택층(FC)은 III-VI족 반도체 화합물에 n형 불순물을 제1 베이스층(PV1-1)보다 높은 도핑농도로 도핑하여 형성할 수 있다. 한 예로, 전면 콘택층(FC)은 1.1eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 n+형 In 0.19Ga 0.81As로 형성할 수 있다.The front contact layer FC positioned between the first window layer WD1 and the front electrode 100 dopes the Group III-VI semiconductor compound with an n-type impurity at a doping concentration higher than that of the first base layer PV1-1 . As an example, the front contact layer (FC) may be formed of n + type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A.
전면 콘택층(FC)은 제1 윈도우층(WD1)과 전면 전극(100) 간에 오믹 콘택(ohmic contact)을 형성한다. 즉, 전면 전극(100)이 제1 윈도우층(WD1)에 바로 접촉하는 경우, 제1 윈도우층(WD1)의 불순물 도핑농도가 낮음으로 인해 전면 전극(100)과 제1 광 흡수층(PV1) 간의 오믹 콘택이 잘 형성되지 않는다. The front contact layer FC forms an ohmic contact between the first window layer WD1 and the front electrode 100. That is, when the front electrode 100 directly contacts the first window layer WD1, the impurity doping concentration of the first window layer WD1 is low, so that the gap between the front electrode 100 and the first light absorbing layer PV1 Ohmic contacts are not well formed.
따라서, 제1 윈도우층(WD1)으로 이동한 캐리어가 전면 전극(100)으로 쉽게 이동하지 못하고 소멸될 수 있다.Therefore, the carrier moved to the first window layer WD1 can not easily move to the front electrode 100 and can be destroyed.
그러나, 전면 전극(100)과 제1 윈도우층(WD1) 사이에 전면 콘택층(FC)이 형성된 경우, 전면 전극(100)과 오믹 콘택을 형성하는 전면 콘택층(FC)에 의해 캐리어의 이동이 원활하게 이루어져 화합물 반도체 태양전지의 단락전류밀도(Jsc)가 증가한다. 이에 따라 태양전지의 효율을 보다 향상시킬 수 있다.However, when the front contact layer FC is formed between the front electrode 100 and the first window layer WD1, the movement of the carriers is prevented by the front contact layer FC forming the ohmic contact with the front electrode 100 So that the short circuit current density (Jsc) of the compound semiconductor solar cell increases. As a result, the efficiency of the solar cell can be further improved.
전면 콘택층(FC)은 전면 전극(100)과 동일한 평면 형상으로 형성할 수 있다.The front contact layer FC can be formed in the same plane shape as the front electrode 100.
이어서, 바텀 셀(C2)과 제1 터널층(TRJ1)에 대해 설명한다.Next, the bottom cell C2 and the first tunnel layer TRJ1 will be described.
바텀 셀(C2)은 제2 광 흡수층(PV2), 제2 광 흡수층(PV2)의 제1 면, 예를 들어 전면(front surface)에 위치하는 제2 윈도우층(WD2), 제2 광 흡수층(PV2)의 제2 면, 예를 들어 후면(back surface)에 위치하는 제2 후면 전계층(BSF2), 및 제2 후면 전계층(BSF2)의 후면에 위치하는 후면 콘택층(BC)을 포함한다.The bottom cell C2 includes a second light absorbing layer PV2, a first surface of the second light absorbing layer PV2, for example, a second window layer WD2 located on the front surface, a second light absorbing layer PV2, A second backside front layer BSF2 located on a second side of the first back side layer BS2 and a rear side contact layer BC located on the back side of the second rear front side layer BSF2, .
바텀 셀(C2)은 GaAs 기반의 제2 베이스층과 제2 에미터층을 포함하는 화합물 반도체로 형성된 광 흡수층을 포함한다.The bottom cell C2 includes a light absorbing layer formed of a compound semiconductor including a second base layer and a second emitter layer based on GaAs.
한 예로, 제2 베이스층과 제2 에미터층은 0.95eV 내지 1.20eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 In yGa 1-yAs로 형성될 수 있다. 여기에서, y는 0.13 내지 0.30인데, y를 상기 범위로 한정하는 이유는 In yGa 1-yAs의 격자상수를 효과적으로 저감시킴으로써 바텀 셀의 밴드갭을 효과적으로 낮추기 위함이다.As an example, the second base layer and the second emitter layer may be formed of In y Ga 1-y As having a band gap energy of 0.95 eV to 1.20 eV and a lattice constant of 5.70 Å to 5.77 Å. Here, y is in the range of 0.13 to 0.30. The reason why y is limited to the above range is to effectively reduce the band gap of the bottom cell by effectively reducing the lattice constant of In y Ga 1-y As.
구체적으로, 바텀 셀(C2)은 1.1eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 n형 In 0.19Ga 0.81As로 형성되는 제2 베이스층(PV2-1) 및 제2 베이스층(PV2-1)과 pn 접합을 형성하며 1.1eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p형 In 0.19Ga 0.81As로 형성되는 제2 에미터층(PV2-2)을 포함하는 제2 광 흡수층(PV2), 제1 터널층(TRJ1)과 제2 베이스층(PV2-1) 사이에 위치하며 1.7eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 n형 Ga 0.33In 0.67P로 형성되는 제2 윈도우층(WD2), 제2 에미터층(PV2-2)의 후면에 위치하며 1.7eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p형 Ga 0.33In 0.67P로 형성되는 제2 후면 전계층(BSF2), 및 제2 후면 전계층(BSF2)과 후면 전극(200) 사이에 위치하며 1.1eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p형 In 0.19Ga 0.81As로 형성되는 후면 콘택층(BC)을 포함한다.Specifically, the bottom cell C2 includes a second base layer PV2-1 formed of n-type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A, (PV2-2) formed of p-type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A, forming a pn junction with the first emitter layer (PV2-1) A second light absorbing layer PV2, an n-type Ga 0.33 layer having a band gap energy of 1.7 eV and a lattice constant of 5.70 A to 5.77 A, located between the first tunnel layer TRJ1 and the second base layer PV2-1, A second window layer WD2 formed of In 0.67 P and a p-type Ga 0.33 In layer having a band gap energy of 1.7 eV and a lattice constant of 5.70 A to 5.77 A, which are located on the back surface of the second emitter layer PV 2-2, 0.67 P in place between two layers around the rear (BSF2), and a second layer around the back (BSF2) and a back electrode 200 formed in and having a lattice constant of the 1.1eV band gap energy and 5.70Å to 5.77Å and a rear contact layer BC formed of p-type In 0.1 9 Ga 0.81 As.
바텀 셀(C2)은 탑 셀(C1)에서 흡수되지 못하고 탑 셀(C1)을 투과한 장파장의 빛을 흡수하기 위해 탑 셀(C1)의 후면에 위치한다.The bottom cell C2 is located at the rear of the top cell C1 to absorb light of long wavelength transmitted through the top cell C1 without being absorbed in the top cell C1.
따라서, 제2 베이스층(PV2-1)과 제2 에미터층(PV2-2)은 탑 셀(C1)의 제1 베이스층(PV1-1)과 제1 에미터층(PV1-2)을 형성하는 GaInP의 밴드갭 에너지(대략 1.9Ev)보다 낮은 밴드갭 에너지를 갖는 물질, 예를 들어 대략 1.1eV의 밴드갭 에너지를 갖는 InGaAs로 형성된다. 한 예로, 제2 베이스층(PV2-1)과 제2 에미터층(PV2-2)은 1.1eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 In 0.19Ga 0.81As로 각각 형성될 수 있다.Therefore, the second base layer PV2-1 and the second emitter layer PV2-2 form the first base layer PV1-1 and the first emitter layer PV1-2 of the top cell C1 A material having a band gap energy lower than the band gap energy of GaInP (approximately 1.9Ev), for example, InGaAs having a band gap energy of approximately 1.1 eV. For example, the second base layer PV2-1 and the second emitter layer PV2-2 may be formed of In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A, respectively have.
그리고, 제2 윈도우층(WD2)과 제2 후면 전계층(BSF2)은 제2 베이스층(PV2-1)과 제2 에미터층(PV2-2)보다 높은 밴드갭 에너지를 갖는 물질, 예를 들어 GaInP 또는 AlGaInP로 형성될 수 있다. 한 예로, 제2 윈도우층(WD2)과 제2 후면 전계층(BSF2)은 1.7eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 Ga 0.33In 0.67P로 각각 형성될 수 있다.The second window layer WD2 and the second rear whole front side BSF2 are formed of a material having a higher band gap energy than the second base layer PV2-1 and the second emitter layer PV2-2, GaInP or AlGaInP. For example, the second window layer WD2 and the second rear whole layer BSF2 may be formed of Ga 0.33 In 0.67 P having a band gap energy of 1.7 eV and a lattice constant of 5.70 A to 5.77 A, respectively.
제1 터널층(TRJ1)은 p형 불순물이 제1 후면 전계층(BSF1)보다 고농도로 도핑된 p++형 AlInGaAs로 형성되며 제1 후면 전계층(BSF1)과 물리적으로 직접 접촉하는 제1 층(TRJ1-1)과, n형 불순물이 제2 윈도우층(WD2)보다 고농도로 도핑된 n++형 GaInP로 형성되며 제2 윈도우층(WD2)과 물리적으로 직접 접촉하는 제2 층(TRJ1-2)을 포함할 수 있다.The first tunnel layer TRJ1 includes a first layer TRJ1 formed of p ++ type AlInGaAs doped with a higher concentration of p-type impurity than the first rear front layer BSF1 and physically in direct contact with the first rear front layer BSF1 And a second layer TRJ1-2 formed of n ++ -type GaInP doped with n-type impurity at a higher concentration than the second window layer WD2 and physically in direct contact with the second window layer WD2 can do.
한 예로, 제1 층(TRJ1-1)은 1.6eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p++형 AlInGaAs(Al=0.3)로 형성될 수 있고, 제2 층(TRJ1-2)은 1.7eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 n++형 GaInP(Ga=0.33)로 형성될 수 있다.For example, the first layer TRJ1-1 may be formed of p ++ type AlInGaAs (Al = 0.3) having a band gap energy of 1.6 eV and a lattice constant of 5.70 A to 5.77 A, and the second layer TRJ1-2 ) Can be formed of n ++ type GaInP (Ga = 0.33) having a band gap energy of 1.7 eV and a lattice constant of 5.70 A to 5.77 A.
제1 후면 전계층(BSF1)의 후면 위에 위치하는 후면 콘택층(BC)은 제1 후면 전계층(BSF1)의 후면에 전체적으로 위치하며, III-VI족 반도체 화합물에 p형 불순물을 도핑하여 형성할 수 있다. 한 예로, 후면 콘택층(BC)은 1.1eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 p+형 In 0.19Ga 0.81As로 형성할 수 있다.The rear contact layer BC located on the rear surface of the first rear front layer BSF1 is entirely located on the rear surface of the first rear front layer BSF1 and is formed by doping a Group III- . As an example, the back contact layer BC may be formed of p + type In 0.19 Ga 0.81 As having a band gap energy of 1.1 eV and a lattice constant of 5.70 A to 5.77 A.
이러한 후면 콘택층(BC)은 후면 전극(200)과 오믹 콘택을 형성할 수 있어, 화합물 반도체 태양전지의 단락전류밀도(Jsc)를 보다 향상시킬 수 있다. 이에 따라 태양전지의 효율을 보다 향상시킬 수 있다.This rear contact layer BC can form an ohmic contact with the rear electrode 200, and the short circuit current density Jsc of the compound semiconductor solar cell can be further improved. As a result, the efficiency of the solar cell can be further improved.
전면 콘택층(FC)의 두께와 후면 콘택층(BC)은 각각 100nm 내지 300nm의 두께로 형성될 수 있다. 한 예로, 전면 콘택층(FC)은 100nm의 두께로 형성되고 후면 콘택층(BC)은 300nm의 두께로 형성될 수 있다.The thickness of the front contact layer FC and the rear contact layer BC may each be formed to a thickness of 100 nm to 300 nm. In one example, the front contact layer FC may be formed to a thickness of 100 nm and the rear contact layer BC may be formed to a thickness of 300 nm.
그리고 후면 콘택층(BC)의 후면 위에 위치하는 후면 전극(200)은 전면 전극(100)과는 다르게 후면 콘택층(BC)의 후면에 전체적으로 위치하는 시트(Sheet) 형상의 도전체로 형성될 수 있다. 즉, 후면 전극(200)은 후면 콘택층(BC)의 후면 전체에 위치하는 면 전극(sheet electrode)이라고 말할 수 있다.The rear electrode 200 positioned on the rear surface of the rear contact layer BC may be formed as a sheet-like conductive material positioned entirely on the rear surface of the rear contact layer BC, unlike the front electrode 100 . That is, the rear electrode 200 may be referred to as a sheet electrode located on the entire rear surface of the rear contact layer BC.
이때, 후면 전극(200)은 제1 광 흡수층(PV1)과 동일한 평면적으로 형성될 수 있으며, 다양한 도전성 물질로 형성될 수 있다.At this time, the rear electrode 200 may be formed in the same plane as the first light absorbing layer PV1, and may be formed of various conductive materials.
한 예로, 후면 전극(200)은 바텀 셀(C2)의 최하부층, 예컨대 후면 콘택층(BC)의 후면과 직접 접촉하여 전하(carrier)를 전송하는 제1 전극층(200A)과, 제1 전극층(200A)을 지지하기 위하여 제1 전극층(200A)의 후면에 위치하는 제2 전극층(200B)을 포함할 수 있다.For example, the rear electrode 200 includes a first electrode layer 200A that directly contacts a bottom layer of the bottom cell C2, for example, a rear surface of the rear contact layer BC to transmit a carrier, And a second electrode layer 200B positioned on the rear surface of the first electrode layer 200A to support the first electrode layer 200A.
이때, 전하(carrier)를 전송하는 제1 전극층(200A)은 종래의 후면 전극 형성 물질, 즉 금(Au)과 유사한 수준의 접촉 저항을 갖는 물질로 형성함과 아울러, 높은 반사도를 갖는 물질로 형성할 수 있다.At this time, the first electrode layer 200A for transmitting a carrier is formed of a material having a contact resistance similar to that of a conventional rear electrode forming material, that is, gold (Au), and is formed of a material having a high reflectivity can do.
따라서, 후면 콘택층(BC)과 직접 접촉하는 제1 전극층(200A)으로는 후면 콘택층(BC)과의 전기적 접합 특성이 우수하며 600nm 내지 950nm의 파장대에서 95% 이상의 평균 반사도를 갖는 은(Ag)을 물리적 기상 증착법(physical vapour deposition)에 의해 50 내지 500nm의 두께로 증착하는 것에 의해 형성할 수 있다.Therefore, the first electrode layer 200A directly contacting the rear contact layer BC is formed of silver (Ag) having an excellent electrical bonding property with the rear contact layer BC and having an average reflectivity of 95% or more at a wavelength range of 600 nm to 950 nm ) May be formed by physical vapor deposition to a thickness of 50 to 500 nm.
그리고 제1 전극층(200A)을 지지하는 제2 전극층(200B)으로는 제1 전극층(200B)을 형성하는 은(Ag)에 비해 접촉 저항이 높고 600nm 내지 950nm의 파장대에서 반사도가 낮지만 재료비가 저렴한 구리(Cu)를 전기도금법(electroplating)에 의해 1 내지 10㎛의 두께로 도금하는 것에 의해 형성할 수 있다.The second electrode layer 200B that supports the first electrode layer 200A has a higher contact resistance than silver (Ag) that forms the first electrode layer 200B and has low reflectivity at a wavelength range of 600 nm to 950 nm. However, Copper (Cu) can be formed by electroplating to a thickness of 1 to 10 탆.
이와 같이, 제1 전극층(200A)을 형성하는 물질로 후면 콘택층(BC)과의 접촉 저항이 낮고 600nm 내지 950nm의 파장대에서 평균 반사도가 높은 은(Ag)을 사용하면, 후면 콘택층(BC)과의 접촉 저항을 양호하게 유지함과 아울러, 광 손실 감소로 인해 광자 재활용(photon recycling)을 증가시킬 수 있어 태양전지의 효율을 개선할 수 있다.When the silver (Ag) having a low contact resistance with the rear contact layer BC and having a high average reflectivity in the wavelength range of 600 nm to 950 nm is used as the material for forming the first electrode layer 200A, And the photon recycling can be increased due to the reduction of the optical loss, so that the efficiency of the solar cell can be improved.
이러한 구성의 화합물 반도체 태양전지는 도 6, 도 7, 도 9 및 도 10에 도시한 모기판 중 어느 하나의 모기판을 사용하여 제조할 수 있다.The compound semiconductor solar cell having such a structure can be manufactured by using any one of the mother board shown in Figs. 6, 7, 9 and 10.
이하, 도 5 내지 도 8을 참조하여 도 9에 도시한 화합물 반도체 태양전지의 제조 방법에 대해 설명한다.Hereinafter, a method of manufacturing the compound semiconductor solar cell shown in Fig. 9 will be described with reference to Figs. 5 to 8. Fig.
화합물 반도체 태양전지의 제조 방법에 대해 설명하기 전에 본 발명의 실시예에 따른 모기판에 대해 먼저 설명한다.Before describing a method of manufacturing a compound semiconductor solar cell, a mother board according to an embodiment of the present invention will be described first.
도 6은 변성층을 구비한 제1 실시예의 모기판에 대해 도시하고 있고, 도 7은 변성층과 희생층을 구비한 제2 실시예의 모기판에 대해 도시하고 있다.Fig. 6 shows the mother board of the first embodiment with the modified layer, and Fig. 7 shows the mother board of the second embodiment with the modified layer and the sacrificial layer.
그리고 도 9는 변성층 및 보호층을 구비한 제3 실시예의 모기판에 대해 도시하고 있고, 도 10은 변성층과 보호층 및 희생층을 구비한 제4 실시예의 모기판에 대해 도시하고 있다.And Fig. 9 shows a mother board of a third embodiment with a denatured layer and a protective layer, and Fig. 10 shows a mother board of the fourth embodiment with a denatured layer, a protective layer and a sacrificial layer.
제1 내지 제4 실시예의 모기판(300-1, 300-2, 300-3, 300-4)은 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼를 각각 포함할 수 있다. 이하에서는 모기판(300-1, 300-2, 300-3, 300-4)이 각각 GaAs 웨이퍼(300A)를 포함하는 경우를 예로 들어 설명한다.The mother substrate 300-1, 300-2, 300-3, and 300-4 of the first to fourth embodiments may include a GaAs single crystal wafer or a Ge single crystal wafer, respectively. Hereinafter, the case where the mother substrate 300-1, 300-2, 300-3, and 300-4 includes the GaAs wafer 300A will be described as an example.
제1 실시예의 모기판(300-1)은 GaAs 웨이퍼(300A)와, GaAs 웨이퍼(300A)의 한쪽 면과 물리적으로 직접 접촉하는 변성층(metamorphic layer)(300B)을 포함한다.The mother substrate 300-1 of the first embodiment includes a GaAs wafer 300A and a metamorphic layer 300B that is in direct physical contact with one side of the GaAs wafer 300A.
GaAs 웨이퍼(300A)는 바텀 셀(C2)을 형성하는 복수의 화합물 반도체층과 탑 셀(C1)을 형성하는 복수의 화합물 반도체층이 형성되는 적절한 격자 구조를 제공하기 위한 베이스층으로 작용한다.The GaAs wafer 300A serves as a base layer for providing a plurality of compound semiconductor layers forming the bottom cell C2 and a plurality of compound semiconductor layers forming the top cell C1 to form a suitable lattice structure.
변성층(300A)은 바텀 셀(C2)을 형성하는 복수의 화합물 반도체층의 격자상수와 탑 셀(C1)을 형성하는 복수의 화합물 반도체층의 격자상수를 GaAs 웨이퍼(300A)의 격자상수에 비해 증가시킴으로써, 이중 접합 구조의 화합물 반도체 태양전지에서 얻을 수 있는 최대 이론 효율에 근접한 효율을 얻을 수 있도록 바텀 셀(C2)의 밴드갭 에너지와 탑 셀(C1)의 밴드갭 에너지를 조정한다.The modified layer 300A has a lattice constant of a plurality of compound semiconductor layers forming the bottom cell C2 and a lattice constant of a plurality of compound semiconductor layers forming the top cell C1 in comparison with the lattice constant of the GaAs wafer 300A Thereby adjusting the band gap energy of the bottom cell C2 and the band gap energy of the top cell C1 so as to obtain an efficiency close to the maximum theoretical efficiency obtained in a compound semiconductor solar cell having a double junction structure.
상기한 효과를 얻기 위해, 변성층(300B)은 두께 방향을 따라 격자상수가 변한다. 즉, 변성층(300B)은 두께 방향을 따라 격자상수가 변하는 층을 의미한다.To obtain the above effect, the lattice constant of the modified layer 300B varies along the thickness direction. That is, the denatured layer 300B means a layer whose lattice constant varies along the thickness direction.
이때, 변성층(300B)의 양쪽 면 중에서 GaAs 웨이퍼(300A)와 접촉하는 제1 면에서의 격자상수는 GaAs 웨이퍼(300A)의 격자상수와 동일하다.At this time, the lattice constant on the first surface contacting the GaAs wafer 300A on both sides of the modified layer 300B is equal to the lattice constant of the GaAs wafer 300A.
그리고 제1 면의 반대쪽에 위치하는 제2 면에서의 변성층(300B)의 격자상수는 제1 면으로부터 제2 면으로 갈수록 계단식, 지수 함수적 또는 로그 함수적으로 증가할 수 있다.And the lattice constant of the modified layer 300B on the second surface located on the opposite side of the first surface may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
GaAs 웨이퍼(300A)는 5.65Å의 격자상수를 갖는다. 따라서, 변성층(300B)을 이용하여 상기 변성층(300B) 위에 형성되는 화합물 반도체층의 격자상수를 GaAs 웨이퍼(300A)의 격자상수보다 증가시키면, GaAs 웨이퍼 바로 위에 탑 셀과 바텀 셀을 형성하는 경우에 비해 탑 셀(C1)의 제1 광 흡수층(PV1)의 밴드갭 에너지와 바텀 셀(C2)의 제2 광 흡수층(PV2)의 밴드갭 에너지를 낮출 수 있다.The GaAs wafer 300A has a lattice constant of 5.65 ANGSTROM. Therefore, when the lattice constant of the compound semiconductor layer formed on the modified layer 300B is increased by the lattice constant of the GaAs wafer 300A using the modified layer 300B, the top cell and the bottom cell are formed directly on the GaAs wafer The band gap energy of the first light absorbing layer PV1 of the top cell C1 and the band gap energy of the second light absorbing layer PV2 of the bottom cell C2 can be lowered.
도 5를 참조하면, 5.65Å의 격자상수를 갖는 GaAs 웨이퍼 위에 바텀 셀과 탑 셀을 형성한 경우, Ga 0 . 52In 0 .48P로 형성한 탑 셀(C1)의 제1 광 흡수층(PV1)의 밴드갭 에너지가 1.88이고, GaAs로 형성한 바텀 셀(C2)의 제2 광 흡수층(PV2)의 밴드갭 에너지가 1.42이다.Referring to FIG. 5, when a bottom cell and a top cell are formed on a GaAs wafer having a lattice constant of 5.65 Å, Ga 0 . 52 In 0 .48 P a top cell (C1) and a first band gap energy is 1.88 of the light absorption layer (PV1), a bottom cell (C2) a second band gap of the light absorbing layer (PV2) to the formation of the GaAs to form a The energy is 1.42.
따라서, 우주 환경에서 사용할 경우의 효율(AMO 효율)이 31.3%이고, 지상 환경에서 사용할 경우의 효율(AM1.5G 효율)이 34.9%이며, 집광 태양전지로 사용할 경우의 효율(AM1.5D 효율)이 32.5%인 것을 알 수 있다.Therefore, the efficiency (AMO efficiency) when used in a space environment is 31.3%, the efficiency (AM1.5G efficiency) when used in a ground environment is 34.9% Is 32.5%.
그런데, 제2 면에서의 격자상수를 5.7Å으로 증가시킨 변성층(300B)을 5.65Å의 격자상수를 갖는 GaAs 웨이퍼 위에 형성한 후 변성층(300B) 위에 바텀 셀과 탑 셀을 형성한 경우에는 Ga 0 . 52In 0 .48P로 형성한 탑 셀(C1)의 제1 광 흡수층(PV1)의 밴드갭 에너지가 1.8로 낮아지고, GaAs로 형성한 바텀 셀(C2)의 제2 광 흡수층(PV2)의 밴드갭 에너지가 1.2로 낮아진다.However, when the modified layer 300B having the lattice constant increased to 5.7A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52 In 0 .48 a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.8, with the GaAs to form the P The band gap energy is reduced to 1.2.
따라서, 우주 환경에서 사용할 경우의 효율(AMO 효율)이 33.8%이고, 지상 환경에서 사용할 경우의 효율(AM1.5G 효율)이 36.9%이며, 집광 태양전지로 사용할 경우의 효율(AM1.5D 효율)이 33.6%인 것을 알 수 있다.Therefore, the efficiency (AMO efficiency) for use in a space environment is 33.8%, the efficiency for use in a ground environment (AM 1.5G efficiency) is 36.9% Is 33.6%.
그리고, 제2 면에서의 격자상수를 5.73Å으로 증가시킨 변성층(300B)을 5.65Å의 격자상수를 갖는 GaAs 웨이퍼 위에 형성한 후 변성층(300B) 위에 바텀 셀과 탑 셀을 형성한 경우에는 Ga 0 . 52In 0 .48P로 형성한 탑 셀(C1)의 제1 광 흡수층(PV1)의 밴드갭 에너지가 1.72로 낮아지고, GaAs로 형성한 바텀 셀(C2)의 제2 광 흡수층(PV2)의 밴드갭 에너지가 1.09로 낮아진다.When the modified layer 300B having the lattice constant increased to 5.73A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52 In 0 .48 a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.72, with the GaAs to form the P The band gap energy is lowered to 1.09.
따라서, 우주 환경에서 사용할 경우의 효율(AMO 효율)이 34.2%이고, 지상 환경에서 사용할 경우의 효율(AM1.5G 효율)이 37.1%이며, 집광 태양전지로 사용할 경우의 효율(AM1.5D 효율)이 34.2%인 것을 알 수 있다.Therefore, the efficiency (AMO efficiency) when used in a space environment is 34.2%, the efficiency (AM1.5G efficiency) when used in a ground environment is 37.1% Is 34.2%.
그리고, 제2 면에서의 격자상수를 5.75Å으로 증가시킨 변성층(300B)을 5.65Å의 격자상수를 갖는 GaAs 웨이퍼 위에 형성한 후 변성층(300B) 위에 바텀 셀과 탑 셀을 형성한 경우에는 Ga 0 . 52In 0 .48P로 형성한 탑 셀(C1)의 제1 광 흡수층(PV1)의 밴드갭 에너지가 1.66으로 낮아지고, GaAs로 형성한 바텀 셀(C2)의 제2 광 흡수층(PV2)의 밴드갭 에너지가 1.03으로 낮아진다.When the modified layer 300B having the lattice constant increased to 5.75A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52 In 0 .48 a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.66, with the GaAs to form the P The band gap energy is lowered to 1.03.
따라서, 우주 환경에서 사용할 경우의 효율(AMO 효율)이 33.9%이고, 지상 환경에서 사용할 경우의 효율(AM1.5G 효율)이 36.6%이며, 집광 태양전지로 사용할 경우의 효율(AM1.5D 효율)이 34.8%인 것을 알 수 있다.Accordingly, the efficiency (AMO efficiency) in the space environment is 33.9%, the efficiency (AM1.5G efficiency) in the use in the ground environment is 36.6%, the efficiency (AM1.5D efficiency) Is 34.8%.
그리고, 제2 면에서의 격자상수를 5.76Å으로 증가시킨 변성층(300B)을 5.65Å의 격자상수를 갖는 GaAs 웨이퍼 위에 형성한 후 변성층(300B) 위에 바텀 셀과 탑 셀을 형성한 경우에는 Ga 0 . 52In 0 .48P로 형성한 탑 셀(C1)의 제1 광 흡수층(PV1)의 밴드갭 에너지가 1.63으로 낮아지고, GaAs로 형성한 바텀 셀(C2)의 제2 광 흡수층(PV2)의 밴드갭 에너지가 1.09로 낮아진다.Then, when the modified layer 300B having the lattice constant increased to 5.76A on the second surface is formed on the GaAs wafer having the lattice constant of 5.65A and the bottom cell and the top cell are formed on the modified layer 300B Ga 0 . 52 In 0 .48 a top cell (C1) the first light absorbing layer a second light absorbing layer (PV2) of (PV1) a bottom cell (C2) formed in the band gap energy is lowered to 1.63, with the GaAs to form the P The band gap energy is lowered to 1.09.
따라서, 우주 환경에서 사용할 경우의 효율(AMO 효율)이 33.5%이고, 지상 환경에서 사용할 경우의 효율(AM1.5G 효율)이 36.3%이며, 집광 태양전지로 사용할 경우의 효율(AM1.5D 효율)이 35.1%인 것을 알 수 있다.Therefore, the efficiency (AMO efficiency) when used in a space environment is 33.5%, the efficiency (AM1.5G efficiency) when used in a ground environment is 36.3% Is 35.1%.
이상에서 살펴 본 바에 따르면, AMO 효율 및 AM1.5G 효율은 제2 면에서 5.73Å의 격자상수를 갖는 변성층을 사용하는 경우에 가장 높고, AM1.5D 효율은 제2 면에서 5.76Å의 격자상수를 갖는 변성층을 사용하는 경우에 가장 높은 것을 알 수 있다.According to the above, the AMO efficiency and AM1.5G efficiency are the highest when using a dense layer having a lattice constant of 5.73Å on the second side, and the AM1.5D efficiency is a lattice constant of 5.76Å on the second side The highest value is obtained in the case of using the modified layer having a high refractive index.
따라서, 제2 면에서 5.7Å 내지 5.77Å의 격자상수를 갖는 변성층을 태양전지의 사용 환경에 따라 적절히 선택하여 이중 접합 태양전지를 제조할 수 있다.Therefore, a double-junction solar cell can be manufactured by appropriately selecting a modified layer having a lattice constant of 5.7 A to 5.77 A on the second surface in accordance with the use environment of the solar cell.
본 발명인의 실험에 의하면, In xGa 1 -xP 또는 In xGa 1 - xAs로 형성한 변성층(300B)에 있어서, 변성층(300B)의 제2 면에서의 격자상수를 5.70Å 내지 5.77Å로 형성하기 위한 x의 크기는 0.19인 것을 알 수 있었다.According to experiments of the present inventors, In x Ga 1 -x P or In x Ga 1 - in the modified layer (300B) formed by x As, to the lattice constant of the second surface of the modified layer (300B) 5.70Å And the size of x for forming 5.77A was 0.19.
따라서, 변성층(300B)의 제1 면에서의 x는 0(zero)이고, 제2 면에서의 x는 0.19이다.Therefore, x on the first surface of the modified layer 300B is 0 (zero), and x on the second surface is 0.19.
변성층(300B)은 200 내지 300nm의 두께로 형성할 수 있으며, 제1 면으로부터 제2 면 쪽으로 격자상수를 증가시키기 위해 상기 두께 범위 내에서 복수의 막으로 형성할 수 있다.The modified layer 300B may be formed to a thickness of 200 to 300 nm and may be formed of a plurality of films within the thickness range to increase the lattice constant from the first surface to the second surface.
이하에서는 제1 실시예의 모기판(300-1)을 이용하여 화합물 반도체 태양전지를 제조하는 방법에 대해 설명한다.Hereinafter, a method of manufacturing a compound semiconductor solar cell using the mother substrate 300-1 of the first embodiment will be described.
먼저, 모기판(300-1)의 변성층(300B)과 물리적으로 직접 접촉하는 희생층(400)을 변성층(300B)의 한쪽 면에 형성하고, 희생층(400) 위에 바텀 셀(C2)을 형성하는 화합물 반도체층(CS2)과, 제1 터널층(TRJ1)을 형성하기 위한 화합물 반도체층(CS3), 및 탑 셀(C1)을 형성하는 화합물 반도체층(CS1)을 순차적으로 형성한다.A sacrificial layer 400 physically in direct contact with the modified layer 300B of the mother substrate 300-1 is formed on one surface of the modified layer 300B and the bottom cell C2 is formed on the sacrificial layer 400. [ A compound semiconductor layer CS3 for forming the first tunnel layer TRJ1 and a compound semiconductor layer CS1 for forming the top cell C1 are sequentially formed.
희생층(400)은 GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs로 형성하거나, 변성층(300B)의 제2 면에서의 격자상수와 서로 동일한 격자상수를 갖는 AlInAs 또는 AlAsSb로 형성할 수 있다.The sacrificial layer 400 may be formed of AlAs or AlAsSb having the same lattice constant as the lattice constant of the second surface of the modified layer 300B or may be formed of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A, can do.
희생층(400)이 변성층(300B)의 제2 면에서의 격자상수와 서로 동일한 격자상수를 갖는 경우에는 희생층(400) 위에 형성되는 바텀 셀(C2)의 화합물 반도체층과 탑 셀(C1)의 화합물 반도체층도 변성층(300B)과 동일한 격자상수를 갖게 되므로, 희생층을 형성하는 데 특별한 제약이 없다. 이 경우, 희생층(400)은 20 내지 50nm의 두께로 형성할 수 있다.When the sacrificial layer 400 has a lattice constant equal to the lattice constant of the second surface of the modified layer 300B, the compound semiconductor layer of the bottom cell C2 formed on the sacrificial layer 400 and the compound semiconductor layer of the top cell C1 ) Has the same lattice constant as that of the modified layer 300B, so there is no particular limitation in forming the sacrifice layer. In this case, the sacrifice layer 400 may be formed to a thickness of 20 to 50 nm.
하지만, GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 희생층(400)을 형성하는 경우, 희생층(400) 위에 형성되는 화합물 반도체층이 변성층(300B)과 동일한 격자상수를 갖도록 하기 위해서는 희생층(400)의 두께를 매우 얇게 형성해야 한다.However, when the sacrifice layer 400 is formed on the basis of the AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A, the compound semiconductor layer formed on the sacrifice layer 400 is formed in the same lattice as the denatured layer 300B In order to have a constant, the thickness of the sacrificial layer 400 must be very thin.
이에, 본 발명인이 실험한 바에 따르면, 희생층(400)을 1nm 내지 10nm의 두께로 형성한 경우에는 GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 희생층(400)을 형성하더라도 바텀 셀(C2)의 화합물 반도체층과 탑 셀(C1)의 화합물 반도체층이 변성층(300B)의 제2 면에서의 격자상수와 동일한 격자상수를 갖는 것을 알 수 있었다.According to the experiment of the present invention, when the sacrifice layer 400 is formed to a thickness of 1 nm to 10 nm, the sacrifice layer 400 is formed on the basis of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A The compound semiconductor layer of the bottom cell C2 and the compound semiconductor layer of the top cell C1 have the same lattice constant as the lattice constant of the second surface of the modified layer 300B.
따라서, GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 희생층(400)을 형성하는 경우, 희생층(400)은 1 내지 10nm의 두께로 형성하는 것이 바람직하다.Therefore, when forming the sacrificial layer 400 based on AlAs or AlGaAs having the same lattice constant as that of the GaAs wafer 300A, the sacrifice layer 400 is preferably formed to a thickness of 1 to 10 nm.
희생층(400) 위에 형성하는 화합물 반도체층은 MOCVD(Metal Organic Chemical Vapor Deposition) 방법, MBE(Molecular Beam Epitaxy) 방법 또는 에피택셜층을 형성하기 위한 임의의 다른 적절한 방법에 의해 형성할 수 있으며, 레귤러 성장(regular growth)법 또는 인버스 성장(inverse growth)법으로 형성할 수 있다.The compound semiconductor layer formed on the sacrificial layer 400 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or any other suitable method for forming an epitaxial layer, And may be formed by a regular growth method or an inverse growth method.
화합물 반도체층을 형성한 후에는 불산(HF)을 이용한 ELO(epitaxial lift off)법에 의해 희생층을 제거함으로써 모기판(300-1)을 화합물 반도체층과 분리할 수 있다.After the compound semiconductor layer is formed, the sacrificial layer is removed by the ELF (epitaxial lift off) method using hydrofluoric acid (HF), so that the mother substrate 300-1 can be separated from the compound semiconductor layer.
도 6의 제1 실시예에서는 모기판(300-1)이 GaAs 웨이퍼(300A)와 변성층(300B)으로 형성된 경우에 대해 설명하였다.In the first embodiment shown in Fig. 6, the case where the mother substrate 300-1 is formed of the GaAs wafer 300A and the modified layer 300B has been described.
하지만, 본 발명의 모기판은 다양한 형태로 변형이 가능하다.However, the mother board of the present invention can be modified into various forms.
이에 대해 설명하면, 도 7에 도시한 바와 같이, 모기판(300-2)은 GaAs 웨이퍼(300A-2)와 변성층(300B) 및 희생층(400)으로 형성될 수도 있다.7, the mother substrate 300-2 may be formed of a GaAs wafer 300A-2, a denatured layer 300B, and a sacrificial layer 400. As shown in FIG.
본 실시예의 제2 실시예의 모기판에 구비된 변성층(300)과 희생층(400)은 전술한 제1 실시예에서 설명한 것들과 서로 동일하다.The modified layer 300 and the sacrificial layer 400 provided on the mother substrate of the second embodiment of the present embodiment are the same as those described in the first embodiment.
이와 달리, 도 9에 도시한 바와 같이, 제3 실시예의 모기판(300-3)은 GaAs 웨이퍼(300A)와, GaAs 웨이퍼(300A)의 한쪽 면에 위치하는 변성층(300B-3) 및, 변성층(300B-3)의 한쪽 면 위에 위치하는 보호층(300C-3)을 포함한다.9, the mother substrate 300-3 of the third embodiment includes a GaAs wafer 300A, a modified layer 300B-3 located on one side of the GaAs wafer 300A, And a protective layer 300C-3 located on one side of the modified layer 300B-3.
변성층(300B-3)은 바텀 셀(C2)을 형성하는 복수의 화합물 반도체층의 격자상수와 탑 셀(C1)을 형성하는 복수의 화합물 반도체층의 격자상수를 GaAs 웨이퍼(300A)의 격자상수에 비해 증가시킴으로써, 이중 접합 구조의 화합물 반도체 태양전지에서 얻을 수 있는 최대 이론 효율에 근접한 효율을 얻을 수 있도록 바텀 셀(C2)의 밴드갭 에너지와 탑 셀(C1)의 밴드갭 에너지를 조정한다.The modified layer 300B-3 is formed by lattice constants of a plurality of compound semiconductor layers forming the bottom cell C2 and lattice constants of a plurality of compound semiconductor layers forming the top cell C1 to a lattice constant of the GaAs wafer 300A The bandgap energy of the bottom cell C2 and the bandgap energy of the top cell C1 are adjusted so as to obtain an efficiency close to the maximum theoretical efficiency obtained in the compound semiconductor solar cell having the double junction structure.
상기한 효과를 얻기 위해, 변성층(300B-3)은 두께 방향을 따라 격자상수가 변한다.In order to obtain the above effect, the lattice constant of the modified layer 300B-3 varies along the thickness direction.
즉, 변성층(300B-3)의 양쪽 면 중에서 GaAs 웨이퍼(300A)와 접촉하는 제1 면에서의 격자상수는 GaAs 웨이퍼(300A)의 격자상수와 동일하고, 보호층(300C-3)과 접촉하는 제2 면에서의 격자상수는 보호층(300C-3)의 격자상수와 동일하다.That is, the lattice constant of the first surface in contact with the GaAs wafer 300A on both sides of the modified layer 300B-3 is equal to the lattice constant of the GaAs wafer 300A, and the lattice constant of the first surface contacting the protective layer 300C- The lattice constant on the second surface is the same as the lattice constant of the protective layer 300C-3.
그리고 변성층(300B-3)은 제1 면으로부터 제2 면으로 갈수록 Ga의 원자%가 계단식, 지수 함수적 또는 로그 함수적으로 감소할 수 있다. 따라서, 변성층(300B-3)의 격자상수는 제1 면으로부터 제2 면으로 갈수록 계단식, 지수 함수적 또는 로그 함수적으로 증가할 수 있다.In the modified layer 300B-3, the atomic% of Ga may decrease stepwise, exponentially or logarithmically from the first surface to the second surface. Therefore, the lattice constant of the modified layer 300B-3 may increase stepwise, exponentially or logarithmically from the first surface to the second surface.
본 실시예의 변성층(300B-3)은 Ga vIn 1 -vP로 형성되며, 변성층(300B-3)의 제2 면에서의 격자상수를 5.70Å 내지 5.77Å로 형성하기 위한 v의 크기는 0.24 내지 0.40이고, 변성층(300B-3)은 1.60 내지 1.80eV의 밴드갭 에너지를 갖는다.The modified layer 300B-3 of this embodiment is formed of Ga v In 1 -v P, and the size of v for forming the lattice constant of the second surface of the modified layer 300B-3 from 5.70A to 5.77A Is in the range of 0.24 to 0.40, and the modified layer (300B-3) has a band gap energy of 1.60 to 1.80 eV.
따라서, 제1 면에서의 변성층(300B-3)은 Ga 0 . 52In 0 .48P로 형성되고, 제2 면에서의 변성층(300B)은 Ga vIn 1-vP(v=0.24 내지 0.40)로 형성된다.Therefore, the modified layer 300B-3 on the first surface is made of Ga 0 . 52 In 0 .48 P, and the modified layer 300 B on the second surface is formed of Ga v In 1 -v P (v = 0.24 to 0.40).
변성층(300B-3)은 200 내지 300nm의 두께로 형성할 수 있으며, 제1 면으로부터 제2 면 쪽으로 격자상수를 증가시키기 위해 상기 두께 범위 내에서 복수의 막으로 형성할 수 있다.The modified layer 300B-3 may be formed to a thickness of 200 to 300 nm, and may be formed of a plurality of films within the thickness range to increase the lattice constant from the first surface to the second surface.
보호층(300C-3)은 ELO 공정에서 변성층(300B-3)을 보호하기 위해 변성층(300B-3) 위에 형성되며, In wGa 1 - wAs로 형성된 단일 층으로 형성된다. 이때, 보호층(300C-3)이 5.70Å 내지 5.77Å의 격자상수를 갖는 w의 범위는 0.13 내지 0.30이며, 보호층(300C-3)은 0.95 내지 1.20eV의 밴드갭 에너지를 갖는다.The protective layer (300C-3) is formed on the modified layer (300B-3) to protect the modified layer (300B-3) in the ELO process, In w Ga 1 - it is formed of a single layer formed of a w As. The protective layer 300C-3 has a band gap energy of 0.95 to 1.20 eV, and the protective layer 300C-3 has a band gap energy of 0.95 to 1.20 eV, with w having a lattice constant of 5.70 A to 5.77 A of 0.13 to 0.30.
이하에서는 GaAs 웨이퍼(300A) 위에 형성된 변성층(300B-3) 및 보호층(300C-3)을 포함하는 모기판(300-3)을 이용하여 화합물 반도체 태양전지를 제조하는 방법에 대해 설명한다.A method of manufacturing a compound semiconductor solar cell using a mother substrate 300-3 including a modified layer 300B-3 formed on a GaAs wafer 300A and a protective layer 300C-3 will be described below.
먼저, 모기판(300-3)의 보호층(300C-3) 위에 희생층(400)을 형성하고, 희생층(400) 위에 바텀 셀(C2)을 형성하는 화합물 반도체층(CS2)과, 제1 터널층(TRJ1)을 형성하기 위한 화합물 반도체층(CS3), 및 탑 셀(C1)을 형성하는 화합물 반도체층(CS1)을 순차적으로 형성한다.A compound semiconductor layer CS2 forming a sacrificial layer 400 on the protective layer 300C-3 of the mother substrate 300-3 and forming a bottom cell C2 on the sacrificial layer 400, The compound semiconductor layer CS3 for forming the first tunnel layer TRJ1 and the compound semiconductor layer CS1 for forming the top cell C1 are sequentially formed.
희생층(400)은 GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs로 형성하거나, 보호층(300C-3)의 격자상수와 서로 동일한 격자상수를 갖는 AlInAs 또는 AlAsSb로 형성할 수 있다.The sacrificial layer 400 may be made of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A or AlInAs or AlAsSb having the same lattice constant as the lattice constant of the protective layer 300C-3 .
희생층(400)이 보호층(300C-3)의 격자상수와 서로 동일한 격자상수를 갖는 경우에는 희생층(400) 위에 형성되는 바텀 셀(C2)의 화합물 반도체층과 탑 셀(C1)의 화합물 반도체층도 보호층(300C-3)과 동일한 격자상수를 갖게 되므로, 희생층을 형성하는 데 특별한 제약이 없다. 이 경우, 희생층(400)은 20 내지 50nm의 두께로 형성할 수 있다.When the sacrifice layer 400 has a lattice constant equal to the lattice constant of the protective layer 300C-3, the compound semiconductor layer of the bottom cell C2 formed on the sacrifice layer 400 and the compound of the top cell C1 Since the semiconductor layer also has the same lattice constant as the protective layer 300C-3, there is no particular limitation in forming the sacrificial layer. In this case, the sacrifice layer 400 may be formed to a thickness of 20 to 50 nm.
하지만, GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 희생층(400)을 형성하는 경우, 희생층(400) 위에 형성되는 화합물 반도체층이 보호층(300C-3)과 동일한 격자상수를 갖도록 하기 위해서는 희생층(400)의 두께를 매우 얇게 형성해야 한다.However, when the sacrifice layer 400 is formed on the basis of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A, the compound semiconductor layer formed on the sacrifice layer 400 is formed on the protective layer 300C- In order to have the same lattice constant, the thickness of the sacrificial layer 400 should be very thin.
이에, 본 발명인이 실험한 바에 따르면, 희생층(400)을 1nm 내지 10nm의 두께로 형성한 경우에는 GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 희생층(400)을 형성하더라도 바텀 셀(C2)의 화합물 반도체층과 탑 셀(C1)의 화합물 반도체층이 보호층(300C-3)의 격자상수와 동일한 격자상수를 갖는 것을 알 수 있었다.According to the experiment of the present invention, when the sacrifice layer 400 is formed to a thickness of 1 nm to 10 nm, the sacrifice layer 400 is formed on the basis of AlAs or AlGaAs having the same lattice constant as the GaAs wafer 300A The compound semiconductor layer of the bottom cell C2 and the compound semiconductor layer of the top cell C1 have the same lattice constant as the lattice constant of the protective layer 300C-3.
따라서, GaAs 웨이퍼(300A)와 서로 동일한 격자상수를 갖는 AlAs 또는 AlGaAs를 기반으로 희생층(400)을 형성하는 경우, 희생층(400)은 1 내지 10nm의 두께로 형성하는 것이 바람직하다.Therefore, when forming the sacrificial layer 400 based on AlAs or AlGaAs having the same lattice constant as that of the GaAs wafer 300A, the sacrifice layer 400 is preferably formed to a thickness of 1 to 10 nm.
희생층(400) 위에 화합물 반도체층을 형성한 후에는 불산(HF)을 이용한 ELO(epitaxial lift off)법에 의해 희생층을 제거함으로써 모기판(300-3)을 화합물 반도체층과 분리할 수 있고, 희생층을 제거한 후에는 ELO 공정에서 변성층(300B-3)을 보호하는 보호층(300C-3)을 NH 4OH/H 2O 2/DI water, H 3PO 4/H 2O 2/DI water, H 2SO 4/H 2O 2/DI water 중 하나, 또는 이들의 혼합액을 사용하여 제거할 수 있다. 이와 달리, 보호층(300C-3)은 제거하지 않을 수도 있다.After the compound semiconductor layer is formed on the sacrificial layer 400, the sacrificial layer is removed by the ELF (epitaxial lift off) method using hydrofluoric acid (HF), so that the mother substrate 300-3 can be separated from the compound semiconductor layer After the sacrificial layer is removed, the protective layer 300C-3 for protecting the denatured layer 300B-3 in the ELO process is removed by using NH 4 OH / H 2 O 2 / DI water, H 3 PO 4 / H 2 O 2 / DI water, H 2 SO 4 / H 2 O 2 / DI water, or a mixture thereof. Alternatively, the protective layer 300C-3 may not be removed.
도 9의 실시예에서는 모기판(300-3)이 GaAs 웨이퍼(300A)와 변성층(300B-3) 및 보호층(300C-3)으로 형성된 경우에 대해 설명하였지만, 도 10에 도시한 바와 같이, 모기판(300-4)은 GaAs 웨이퍼(300A), 변성층(300B-4), 보호층(300C-4) 및 희생층(400)으로 형성될 수도 있다.9, the case where the mother substrate 300-3 is formed of the GaAs wafer 300A, the modified layer 300B-3, and the protective layer 300C-3 has been described. However, as shown in FIG. 10 And the mother substrate 300-4 may be formed of the GaAs wafer 300A, the denatured layer 300B-4, the protective layer 300C-4, and the sacrificial layer 400. [
이상에서는 이중 접합 구조의 화합물 반도체 태양전지를 예로 들어 설명하지만, 본 발명의 제조 방법은 삼중 접합 이상의 구조를 갖는 화합물 반도체층을 구비한 화합물 반도체 태양전지를 제조할 때에도 사용할 수 있음이 자명하다.Although the compound semiconductor solar cell having a double junction structure is described above as an example, it is obvious that the manufacturing method of the present invention can also be used in manufacturing a compound semiconductor solar cell having a compound semiconductor layer having a triple junction or more structure.
이상에서 본 발명의 바람직한 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (18)

  1. GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼; 및GaAs single crystal wafer or Ge single crystal wafer; And
    상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 한쪽 면과 물리적으로 직접 접촉하며, 두께 방향을 따라 격자상수가 변하는 변성층(metamorphic layer)A metamorphic layer directly contacting the one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction,
    을 포함하는 모기판.A mosquito board comprising.
  2. 제1항에서,The method of claim 1,
    상기 변성층의 양쪽 면 중에서 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 접촉하는 제1 면에서의 격자상수는 상기 제1 면의 반대쪽에 위치하는 제2 면에서의 격자상수보다 작게 형성되는 모기판.Wherein the lattice constant of the first surface contacting the GaAs single crystal wafer or the Ge single crystal wafer on both sides of the modified layer is smaller than the lattice constant of the second surface located on the opposite side of the first surface.
  3. 제2항에서,3. The method of claim 2,
    상기 변성층의 격자상수는 상기 제1 면으로부터 상기 제2 면으로 갈수록 계단식, 지수 함수적 또는 로그 함수적으로 증가하는 모기판.Wherein the lattice constant of the modified layer increases stepwise, exponentially or logarithmically from the first surface to the second surface.
  4. 제1항 내지 제3항 중 어느 한 항에서,4. The method according to any one of claims 1 to 3,
    상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼는 5.65Å의 격자상수를 가지며, 상기 변성층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수보다 큰 5.70Å 내지 5.77Å의 격자상수를 갖는 모기판.Wherein the GaAs monocrystalline wafer or Ge monocrystalline wafer has a lattice constant of 5.65A and the denaturation layer has a lattice constant of 5.70A to 5.77A larger than the lattice constant of the GaAs single crystal wafer or the Ge single crystal wafer.
  5. 제4항에서,5. The method of claim 4,
    상기 변성층은 In xGa 1-xP 또는 In xGa 1-xAs로 형성되며, 상기 제1 면에서의 상기 x는 0(zero)이고, 상기 제2 면에서의 상기 x는 0.19인 모기판.Wherein the modified layer is formed of In x Ga 1-x P or In x Ga 1 -x As, wherein x on the first surface is zero and the x on the second surface is 0.19 plate.
  6. 제5항에서,The method of claim 5,
    상기 변성층의 제2 면과 물리적으로 직접 접촉하는 희생층을 더 포함하는 모기판.And a sacrificial layer in direct physical contact with the second surface of the modified layer.
  7. 제6항에서,The method of claim 6,
    상기 희생층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 가지며, AlAs 또는 AlGaAs를 기반으로 형성되고, 1nm 내지 10nm의 두께로 형성되는 모기판.Wherein the sacrificial layer has a lattice constant equal to that of the GaAs single crystal wafer or the Ge single crystal wafer and is formed on the basis of AlAs or AlGaAs and formed to a thickness of 1 nm to 10 nm.
  8. 제6항에서,The method of claim 6,
    상기 희생층은 상기 변성층의 제2 면에서의 격자상수와 서로 동일한 격자상수를 가지며, AlInAs 또는 AlAsSb를 기반으로 형성되는 모기판.Wherein the sacrificial layer has a lattice constant equal to the lattice constant on the second surface of the modified layer and is formed based on AlInAs or AlAsSb.
  9. 제4항에서,5. The method of claim 4,
    상기 변성층은 Ga vIn 1-vP로 형성되고, 상기 제1 면에서의 상기 변성층은 1.60 내지 1.80eV의 밴드갭 에너지를 갖는 Ga 0 . 52In 0 .48P로 형성되고, 상기 제2 면에서의 상기 v는 0.24 내지 0.40인 모기판.The modified layer is a Ga 1-v In v is formed from a P, the modified layer in the first surface having a Ga 0 of 1.60 to 1.80eV bandgap energy. 52 In 0 .48 P, and v in said second side is 0.24 to 0.40.
  10. 제9항에서,The method of claim 9,
    상기 변성층의 한쪽 면에 위치하며 In wGa 1-wAs로 형성되는 보호층을 더 포함하며,Further comprising a protective layer located on one side of the modified layer and formed of In w Ga 1-w As,
    상기 변성층의 양쪽 면 중에서 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 접촉하는 제1 면에서의 격자상수는 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수와 동일하고, 상기 제2 면에서의 격자상수는 상기 제1 면에서의 격자상수보다 크고 상기 보호층의 격자상수와 동일한 모기판.Wherein the lattice constant of the GaAs monocrystalline wafer or the Ge monocrystalline wafer on both sides of the modified layer is the same as the lattice constant of the GaAs single crystal wafer or Ge single crystal wafer, And a lattice constant greater than the lattice constant at the first surface and equal to the lattice constant of the protective layer.
  11. 제10항에서,11. The method of claim 10,
    상기 보호층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 격자상수보다 큰 5.70Å 내지 5.77Å의 격자상수를 갖는 모기판.Wherein the protective layer has a lattice constant of 5.70 A to 5.77 A greater than the lattice constant of the GaAs single crystal wafer or Ge single crystal wafer.
  12. 제10항에서,11. The method of claim 10,
    상기 보호층에 있어서, 상기 w는 0.13 내지 0.30인 모기판.Wherein, in the protective layer, w is 0.13 to 0.30.
  13. 제12항에서,The method of claim 12,
    상기 보호층 위에 위치하는 희생층을 더 포함하는 모기판.And a sacrificial layer disposed over the protective layer.
  14. 제13항에서,The method of claim 13,
    상기 희생층은 상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼와 서로 동일한 격자상수를 가지며, AlAs 또는 AlGaAs를 기반으로 형성되고, 1nm 내지 10nm의 두께로 형성되는 모기판.Wherein the sacrificial layer has a lattice constant equal to that of the GaAs single crystal wafer or the Ge single crystal wafer and is formed on the basis of AlAs or AlGaAs and formed to a thickness of 1 nm to 10 nm.
  15. 제13항에서,The method of claim 13,
    상기 희생층은 상기 보호층의 격자상수와 서로 동일한 격자상수를 가지며, AlInAs 또는 AlAsSb를 기반으로 형성되는 모기판.Wherein the sacrificial layer has a lattice constant equal to the lattice constant of the protective layer and is formed based on AlInAs or AlAsSb.
  16. 모기판의 한쪽 면 위에 희생층을 형성하는 단계; 및Forming a sacrificial layer on one side of the mother substrate; And
    1개 이상의 셀을 형성하기 위한 화합물 반도체층을 상기 희생층 위에 형성하는 단계Forming a compound semiconductor layer for forming one or more cells on the sacrificial layer
    를 포함하며,/ RTI >
    상기 모기판은,The mosquito-
    GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼; 및GaAs single crystal wafer or Ge single crystal wafer; And
    상기 GaAs 단결정 웨이퍼 또는 Ge 단결정 웨이퍼의 한쪽 면과 물리적으로 직접 접촉하며, 두께 방향을 따라 격자상수가 변하는 변성층(metamorphic layer)A metamorphic layer directly contacting the one side of the GaAs single crystal wafer or the Ge single crystal wafer and having a lattice constant varying along the thickness direction,
    을 포함하는 화합물 반도체 태양전지의 제조 방법.Wherein the method comprises the steps of:
  17. 제16항에서,17. The method of claim 16,
    상기 모기판은 상기 변성층의 한쪽 면에 위치하며 상기 희생층의 한쪽 면과 물리적으로 직접 접촉하는 보호층을 더 포함하는 화합물 반도체 태양전지의 제조 방법.Wherein the mother substrate further comprises a protective layer located on one side of the modified layer and physically in direct contact with one side of the sacrificial layer.
  18. 다중 접합 구조의 화합물 반도체 태양전지로서,A compound semiconductor solar cell having a multi-junction structure,
    0.95eV 내지 1.20eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 In yGa 1-yAs로 형성되는 바텀 셀의 베이스층;A base layer of a bottom cell formed of In y Ga 1-y As having a band gap energy of 0.95 eV to 1.20 eV and a lattice constant of 5.70 A to 5.77 A;
    1.60eV 내지 1.80eV의 밴드갭 에너지와 5.70Å 내지 5.77Å의 격자상수를 갖는 Ga zIn 1-zP로 형성하는 탑 셀의 베이스층;A base layer of a top cell formed of Ga z In 1-z P having a band gap energy of 1.60 eV to 1.80 eV and a lattice constant of 5.70 A to 5.77 A;
    상기 바텀 셀의 후면(back surface)에 위치하며, 면전극(sheet electrode) 형상으로 형성되는 후면 전극; 및A rear electrode disposed on a back surface of the bottom cell and formed in the form of a sheet electrode; And
    상기 탑 셀의 전면(front surface)에 위치하며, 그리드(grid) 형상으로 형성되는 전면 전극A front electrode disposed on a front surface of the top cell and formed in a grid shape,
    을 포함하며,/ RTI >
    상기 y는 0.13 내지 0.30이고, 상기 z는 0.24 내지 0.40인 화합물 반도체 태양전지.Y is from 0.13 to 0.30, and z is from 0.24 to 0.40.
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