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WO2019100822A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2019100822A1
WO2019100822A1 PCT/CN2018/105694 CN2018105694W WO2019100822A1 WO 2019100822 A1 WO2019100822 A1 WO 2019100822A1 CN 2018105694 W CN2018105694 W CN 2018105694W WO 2019100822 A1 WO2019100822 A1 WO 2019100822A1
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WO
WIPO (PCT)
Prior art keywords
pull
node
output
potential
shift register
Prior art date
Application number
PCT/CN2018/105694
Other languages
English (en)
French (fr)
Inventor
山岳
王继国
樊君
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18855161.8A priority Critical patent/EP3719783A4/en
Priority to US16/339,752 priority patent/US10950319B2/en
Publication of WO2019100822A1 publication Critical patent/WO2019100822A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to display technology, and in particular to a shift register and corresponding driving method, gate driving circuit, and display device.
  • the performance of the gate driving circuit directly affects the quality of the liquid crystal display.
  • the reliability requirements for GOA are more demanding.
  • LCD liquid crystal display
  • the demand for reducing power consumption and increasing system stability has also increased, and low power consumption and stability have become the focus of attention in the field of GOA technology.
  • the drive control capability of the single-stage shift register is enhanced, and the reliability of the display driven by the GOA is improved, which is very important for realizing a narrow-frame vehicle display product.
  • the present disclosure provides a shift register and corresponding driving method, gate driving circuit, and display device.
  • An aspect of the present disclosure relates to a shift register, which may include: an input and reset circuit connected to an input terminal, a pull-up node, and a reset terminal, configured to be in a case where a potential of the input terminal is an operating potential, Setting the potential of the pull-up node to the working potential, and setting the potential of the pull-up node to the reset potential when the potential of the reset terminal is the working potential; the first output circuit, the pull-up node, the first control signal terminal, The first output end is connected to be configured to output a first gate driving signal at the first output end when the potential of the pull-up node and the potential of the first control signal end are the working potential; the second output circuit, and the pull-up The node, the second control signal end, and the second output end are connected, and configured to output a second gate driving signal at the second output end when the potential of the pull-up node and the potential of the second control signal end are working potentials; a first pull-down circuit connected to the first pull-down node, the
  • the pull-down node selection circuit may include: a first pull-down selection switch element, the control end of which is connected to the first pull-down node selection signal end, and one of the first end and the second end and the first The pull-down node is connected; the second pull-down select switch element has a control end connected to the first pull-down node selection signal end, and one of the first end and the second end is connected to the second pull-down node, the first end and the second end thereof The other of the terminals is connected to the reference signal end; the third pull-down selection switch element has a control end connected to the second pull-down node selection signal end, and one of the first end and the second end is connected to the second pull-down node, The other of the first end and the second end is connected to the other of the first end and the second end of the first pull-down selection switching element; and the fourth pull-down selection switching element is selected by the control end and the second pull-down node The signal ends are connected, and one of the first end and the second end is
  • the pull-down node selection circuit may further include: a first capacitor connected between the first pull-down node and the reference signal end; and a second capacitor connected between the second pull-down node and the reference signal end.
  • the pull-down node selection circuit may further include: a selection control switching element, wherein the control end and one of the first end and the second end are connected to the pull-down selection control signal end, the first end and the second end thereof The other of the first and second ends of the first pull-down selection switch element is connected to the other of the first end and the second end of the third pull-down selection switch element.
  • the input and reset circuit may include: a first input switching element having a control end coupled to the input end, one of the first end and the second end being coupled to the first scan control signal end, the first The other of the end and the second end is connected to the pull-up node; and the second input switching element has a control end connected to the reset end, and one of the first end and the second end is connected to the second scan control signal end The other one of the first end and the second end is connected to the pull-up node, wherein, in the forward scanning, the potential of the first scanning control signal is the working potential, and the potential of the second scanning control signal is the reset potential, and the opposite At the time of scanning, the potential of the first scan control signal is the reset potential, and the potential of the second scan control signal is the operating potential.
  • the input and reset circuit may further include: a first pull-down node reset switching element, the control end of which is connected to the pull-up node, and one of the first end and the second end is connected to the first pull-down node One of the first end and the second end is connected to the reference signal end; and the second pull-down node resets the switching element, the control end of which is connected to the pull-up node, and one of the first end and the second end The second pull-down node is connected, and the other of the first end and the second end is connected to the reference signal end.
  • the first output circuit may include: a first output switching element whose control end is connected to the working potential end, one of the first end and the second end is connected to the pull-up node; and the second output switching element a control end thereof is connected to the other of the first end and the second end of the first output switching element, and one of the first end and the second end is connected to the first control signal end, the first end and the second end thereof
  • the other of the terminals is coupled to the first output; and a first output capacitor coupled between the control terminal of the second output switching element and the first output.
  • the second output circuit may include: a third output switching element whose control end is connected to the working potential end, one of the first end and the second end is connected to the pull-up node; and the fourth output switching element a control end thereof connected to the other of the first end and the second end of the third output switching element, wherein one of the first end and the second end is connected to the second control signal end, the first end and the second end
  • the other of the terminals is coupled to the second output; and a second output capacitor coupled between the control terminal and the second output of the fourth output switching component.
  • the first pull-down circuit may include: a first pull-down switching element, the control end of which is connected to the first pull-down node, and one of the first end and the second end is connected to the pull-up node, The other of the first end and the second end is connected to the reference signal end;
  • the second pull-down switching element has a control end connected to the first pull-down node, and one of the first end and the second end and the first output end Connected, the other of the first end and the second end is connected to the reference signal end;
  • the third pull-down switch element has a control end connected to the first pull-down node, and one of the first end and the second end The second output is connected, and the other of the first end and the second end is connected to the reference signal end.
  • the second pull-down circuit may include: a fourth pull-down switching element, the control end thereof is connected to the second pull-down node, and one of the first end and the second end is connected to the pull-up node, and the first end thereof And the other of the second end is connected to the reference signal end;
  • the fifth pull-down switching element has a control end connected to the second pull-down node, and one of the first end and the second end is connected to the first output end, the first One of the one end and the second end is connected to the reference signal end;
  • the sixth pull-down switching element has a control end connected to the second pull-down node, and one of the first end and the second end is connected to the second output end The other of the first end and the second end is connected to the reference signal end.
  • Another aspect of the present disclosure is directed to a gate driving circuit including a plurality of cascaded shift registers as described above, wherein, in addition to the first stage, inputs of other stages of shift registers are cascaded with The second output of the shift register of the previous stage is connected, and except for the last stage, the reset ends of the shift registers of the other stages are connected to the first output of the shift register of the subsequent stage.
  • Yet another aspect of the present disclosure is directed to a display device including the gate drive circuit as described above.
  • Yet another aspect of the present disclosure is directed to a display device that can include a first gate driving circuit and a second gate driving circuit, the first gate driving circuit including N cascades as previously described a shift register, the second gate driving circuit includes N cascaded shift registers as described above; wherein a reset end of the first stage shift register of the first gate driving circuit is connected to the second gate a first output terminal of the first stage shift register of the driving circuit; an input end of the i-th stage shift register of the first gate driving circuit is connected to the second of the i-th stage shift register of the second gate driving circuit The output end, the reset end of the i-th stage shift register of the first gate driving circuit is connected to the first output end of the i-th stage shift register of the second gate driving circuit, wherein 1 ⁇ i ⁇ N; the second gate The input end of the jth stage shift register of the driving circuit is connected to the second output end of the jth stage shift register of the first gate driving circuit, and the reset end of the jth stage shift register of the second gate driving
  • Yet another aspect of the present disclosure is directed to a method for driving a shift register as described above, comprising: alternately setting one of a first pulldown node and a second pulldown node to be active in two adjacent frames Pull-down node, in the case where one of the pull-down nodes is set as the active node, the potential of the other pull-down node is set to the reset potential; in each frame, for each stage of the shift register, in the first stage, in response to the reception Up to the input signal, pulling up the potential of the pull-up node to the working potential; in the second stage, in response to receiving the first clock signal, outputting the first gate driving signal at the first output end, and responsive to the first clock a second clock signal received after the signal, outputting a second gate drive signal at the second output; in the third stage, setting the potential of the active pull-down node to be responsive to the reference signal received after the second clock signal a working potential; and setting a potential of the pull-up node, the first output terminal, and the second output terminal to
  • the first pulldown node and the second pulldown node may be alternately used as active pulldown nodes in accordance with a predetermined number of frames.
  • FIG. 1 illustrates a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 2 shows another circuit configuration diagram of the shift register shown in FIG. 1.
  • FIG. 3 illustrates a shift register in accordance with another embodiment of the present disclosure.
  • FIG. 4 illustrates an exemplary circuit diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 5 illustrates an exemplary operational timing of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 6 illustrates an exemplary driving method of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 7 illustrates an exemplary connection manner of a gate driving circuit including a shift register according to an embodiment of the present disclosure.
  • Fig. 8 is a view schematically showing an operation timing chart of the gate driving circuit shown in Fig. 7 during two adjacent frames.
  • FIG. 9 illustrates another exemplary connection manner of a gate driving circuit including a shift register according to an embodiment of the present disclosure.
  • FIG. 10 illustrates a display device in accordance with an embodiment of the present disclosure.
  • the term "operating potential” refers to a potential that is capable of turning a respective switching element on or capable of operating a corresponding circuit. For example, if the switching element needs to be turned on when the potential of its control terminal is high, the operating potential can correspond to a high level, and if the switching element needs to be turned on when the potential of its control terminal is low, then The working potential can correspond to a low potential.
  • the term “reset potential” means a potential opposite to the "operating potential", that is, a potential capable of turning off the corresponding switching element or enabling the corresponding circuit to be inoperative.
  • the reset potential may correspond to a low level; or if the operating potential corresponds to a low level, the reset potential may correspond to a high level.
  • the working potential and the reset potential can be determined according to the actual conditions of the circuit. In the following description, for the sake of brevity, a high level is selected as the operating potential, and a low level is selected as the reset potential. However, the technical solution of the present disclosure is not limited to such an example.
  • the potential of the terminal is at a high level, or the terminal is at a high level level.
  • the potential of the terminal is at a low level, or the terminal is at a low level.
  • the low voltage value or voltage range can be selected according to the actual condition of the circuit and the design specification, so that when the voltage is the selected value or within the selected range, the corresponding switching element is cut off or the corresponding circuit is not jobs.
  • the high level voltage is usually higher than the low level.
  • the voltage value or voltage range of the high level can be selected according to the actual condition of the circuit and the design specification, so that when the voltage is the selected value or within the selected range, the corresponding switching element can be turned on or correspondingly The circuit can work.
  • both high and low levels may correspond to different voltage values within a certain range.
  • terms like “first high level” and “second high level” may be used to describe a high level having different voltage values in a high level range.
  • the switching element can be any element or circuit with a control terminal that can function as a switch.
  • a switching element can be turned on, for example, when the potential of its control terminal is at a high level, that is, a path is formed between the first end and the second end such that the potentials of the first end and the second end are the same or substantially the same.
  • the switching element when the switching element is turned on, the potentials of the first end and the second end are not necessarily identical due to the on-resistance of the switching element, but there may be some difference.
  • such a switching element can employ various types of switching devices having a control terminal such as a thin film transistor or a field effect block as needed, and can adopt an N-channel type or a P-channel type as needed.
  • a description will be made by taking a switching element using an N-channel type thin film transistor as an example.
  • the control terminal of the switching element may correspond to one of the gate, the first end, and the second end of the transistor, which may correspond to one of a source and a drain of the transistor, the first end and the second end
  • the other of the transistors may correspond to the other of the source and the drain of the transistor.
  • the first end and the second end of the switch are interchangeable.
  • the technical solution of the present disclosure is not limited to such an example.
  • FIG. 1 shows an exemplary shift register 100 in accordance with an embodiment of the present disclosure.
  • the shift register 100 includes an input and reset circuit 101, a first output circuit 102, a second output circuit 103, a first pull-down circuit 104, a second pull-down circuit 105, and a pull-down node selection circuit 106.
  • the shift register 100 further includes a first pulldown node PD1 and a second pulldown node PD2.
  • the input and reset circuit 101 is connected to the input terminal, the pull-up node, and the reset terminal, and is configured to set the potential of the pull-up node to the operating potential and the reset terminal at the potential of the input terminal. When the potential is the operating potential, the potential of the pull-up node is set to the reset potential.
  • the input and reset circuit 101 shown in FIG. 1 may include an input circuit 101_1 and a reset circuit 101_2 as shown in FIG. 2. It should be understood that the shift register shown in FIGS. 1 and 2 differs in that the input and reset circuits in FIG. 1 are split into an output circuit 101_1 and a reset circuit 101_2 as shown in FIG. 2.
  • the input circuit 101_1 is connected to the input terminal IN of the shift register 100, the first scanning direction control terminal CN, and the pull-up node PU.
  • the input circuit 101_1 can make the pull-up node PU communicate with the input terminal IN and/or the first scan direction control terminal CN by turning on the internal switching element thereof, thereby causing the pull-up node
  • the potential of the PU becomes an operating potential, such as a high level.
  • the input circuit 101_1 can be implemented in different ways, and can be connected to different terminals of the shift register 100 according to needs and implementations, so that when an input signal is received via the input terminal IN, the potential of the pull-up node PU is set to Working potential.
  • the input circuit 101_1 may also be connected to the operating potential terminal VGH, wherein the input circuit 101_1 may turn on the pull-up node PU and work by turning on its internal switching element when receiving a signal via the input terminal IN.
  • the potential terminal VGH is connected to cause the potential of the pull-up node PU to become the operating potential.
  • the input circuit 101_1 can also be connected to a clock signal terminal which provides a high-level clock signal when receiving a signal via the input terminal IN, wherein when a signal is received via the input terminal IN
  • the input circuit 101_1 can cause the pull-up node PU to communicate with the clock signal terminal by turning on the internal switching element, thereby causing the potential of the pull-up node PU to become the operating potential.
  • the input circuit 101_1 may include at least one switching element, and for example, the control end of the switching element may be connected to the input terminal IN, and one of the first end and the second end thereof may be connected to the pull-up node PU, And the other of the first end and the second end thereof is connected to the first scanning direction control terminal CN or the working potential terminal VGH or the aforementioned clock signal terminal as the case may be.
  • the input circuit 101_1 is also connected to the first pull-down node PD1 and the reference signal terminal RS. While the pull-up node PU is set to a high level, the input circuit 101_1 can connect the reference signal terminal RS and the first pull-down node PD1 by, for example, turning on the internal switching element, thereby setting the first pull-down node PD1. Is low.
  • the input circuit 101_1 may not be connected to the first pull-down node PD1 and the reference signal terminal RS, or the shift register 100 may implement a similar function in another manner.
  • the shift register 100 may implement a similar function in another manner.
  • separate components, circuits, and sub-circuits may be provided in the shift register 100 to ensure that the first pull-down node PD1 is set to a low level while the pull-up node PU is set to a high level.
  • a separate switching element may be disposed outside the input circuit 101_1, and the control end and the first end of the switching element are respectively connected to the pull-up node PU and the first pull-down node PD1, and the switching element is The potential of the second terminal is low when the shift register 100 receives a signal via the input terminal IN.
  • the input circuit 101_1 operates and the pull-up node PU becomes a high level, and the switch is turned on when the pull-up node PU is at a high level, so that the first pull-down is performed.
  • the potential of the node PD1 is at a low level.
  • the reset circuit 101_2 is connected to the reset terminal RESET of the shift register 100, the second scan direction control terminal CNB, and the pull-up node PU.
  • the reset circuit 101_2 can cause the pull-up node PU to communicate with the reset terminal RESET and/or the second scan direction control terminal CNB by turning on the internal switching element thereof, thereby causing the pull-up node
  • the potential of the PU becomes a reset potential, for example, a low level.
  • the reset circuit 101_2 can be implemented in different ways, and can be connected to different terminals of the shift register 100 according to needs and implementations, so that when the signal is received via the reset terminal RESET, the potential of the pull-up node PU is set to reset. Potential.
  • the reset circuit 101_2 may be connected to the reference signal terminal RS, and the signal of the reference signal terminal RS may be a direct current signal or an alternating current signal, and in the reset phase, the signal of the reference signal terminal RS is low.
  • the reference signal terminal RS may be a reset potential terminal VGL, and the reset potential terminal VGL outputs a DC low level signal.
  • the reset circuit 101_2 can make the pull-up node PU and the reset potential terminal VGL communicate by turning on the internal switching element, thereby causing the potential of the pull-up node PU to become the reset potential.
  • the reference signal terminal RS may also be a clock signal terminal that provides a low-level clock signal when the reset terminal RESET receives a signal.
  • the reset circuit 102 can cause the pull-up node PU to communicate with the clock signal terminal by turning on the internal switching element, thereby causing the potential of the pull-up node PU to become the reset potential.
  • the reset circuit 101_2 may include at least one switching element, and for example, the control terminal of the switching element may be connected to the reset terminal RESET, one of the first end and the second end of the switching element and the pull-up node
  • the PUs are connected, and the other one of the first end and the second end of the switching element is connected to the second scanning direction control terminal CNB or the reference signal terminal RS (for example, RS is the reset potential terminal VGL or the aforementioned clock signal terminal). Connected.
  • the reset circuit 101_2 is also connected to the second pull-down node PD2 and the reference signal terminal RS. While the pull-up node PU is set to a high level, the reset circuit 102 can connect the reference signal terminal RS and the second pull-down node PD2 by, for example, turning on its internal switching element, thereby setting the second pull-down node PD2 to Low level.
  • the reset circuit 101_2 may not be connected to the second pull-down node PD2 and the reference signal terminal RS, or the shift register 100 may adopt another manner to implement a similar function.
  • separate components, circuits, and sub-circuits may be provided in shift register 100 to ensure that second pull-down node PD2 is set low while setting pull-up node PU high.
  • a separate switching element may be disposed outside the reset circuit 101_2, and the control terminal and the first end of the switching element are respectively connected to the pull-up node PU and the second pull-down node PD2, and the potential of the second end of the switching element is The shift register 100 is at a low level when it receives a signal via the input terminal IN.
  • the input circuit 101_1 operates and the circuit of the pull-up node PU becomes a high level, and the switch is turned on when the pull-up node PU is at a high level, so that the second The potential of the pull-down node PD2 is low.
  • the shift register 100 shown in FIG. 1 can support bidirectional scanning.
  • the shift register 100 can operate in a forward scanning mode.
  • the forward scan mode when the shift register 100 receives a signal via the input terminal IN, the input circuit 101_1 sets the pull-up node PU to a high level, and when the shift register 100 receives a signal via the reset terminal RESET, resets Circuit 101_2 sets pull-up node PU to a low level.
  • the shift register 100 can operate in a reverse scanning mode.
  • the input circuit 101_1 may correspond to the reset circuit 101_2 in the forward scan mode
  • the reset circuit 101_2 may correspond to the input circuit 101_1 in the forward scan mode
  • the required clock signal (if any) can be adjusted accordingly.
  • the input circuit 101_1 may also be referred to as a first input circuit
  • the reset circuit 101_2 may also be referred to as a second input circuit.
  • the input circuit and the reset circuit in the shift register may adopt a different setting from the input circuit and the reset circuit in the shift register 100 shown in FIG. 1 without supporting the bidirectional scan function. the way.
  • the shift register 100 may not set the first scan direction control terminal CN and the second scan direction control terminal CNB. Accordingly, the input circuit 101_1 and the reset circuit 101_2 may not be the same.
  • a scan direction control terminal CN is connected to the second scan direction control terminal CNB, but other implementations such as those described above may be employed.
  • the reset circuit 101_2 may also be connected to the output of the shift register (for example, the first output terminal OUT1 and/or the second in FIG. 1 or FIG. 2).
  • the output terminal OUT2) is connected, and the output of the shift register is also set to a low level when a signal is received via the reset terminal RESET.
  • the reset circuit 101_2 may include another switching element, and the control terminal, the first end, and the second end of the switching element are respectively coupled to the reset terminal RESET, the output terminal, and the reference signal terminal RS of the shift register. Connected.
  • the first output circuit 102 is connected to the pull-up node PU, the first clock signal terminal CK1, and the first output terminal OUT1.
  • the shift register 100 receives a signal via the input terminal IN, the potential of the pull-up node PU becomes a high level under the control of the input circuit 101_1, and the first output circuit 102 starts operating to maintain the potential of the pull-up node PU (or Registered) is in a high state, but does not output a gate drive signal at the first output terminal OUT1.
  • the shift register 100 receives the first clock signal via the first clock signal terminal CK1, the first output circuit 102 outputs a gate driving signal at the first output terminal OUT1, thereby completing the shift output.
  • the first output circuit 102 can include a capacitor and at least one switching element, wherein, for example, a capacitor can be disposed between the pull-up node PU and the first output terminal OUT1, the control terminal of the switching element, first The terminal and the second terminal are respectively connected to the pull-up node PU, the first clock signal terminal CK1 and the first output terminal OUT1, and cause the first clock signal terminal CK1 to be low when the shift register 100 receives the input signal.
  • the shift register 100 When the shift register 100 receives the input signal via the input terminal IN, the potential of the pull-up node PU becomes a high level under the control of the input circuit 101_1, and the capacitor in the first output circuit 102 starts charging. However, since the first clock signal terminal CK1 is at a low level at this time, the potentials of the first terminal and the second terminal of the switching element after being turned on are all in a low state, so that there is no gate at the first output terminal OUT1. Pole drive signal output. Subsequently, the potential of the pull-up node PU is maintained in a high state by the bootstrap action of the capacitor in the first output circuit 102, and may even be further pulled high, and the switching elements in the first output circuit 102 are kept at On state.
  • the shift register 100 receives the first clock signal (or the first clock signal terminal CK1 is at a high level), the potentials of the first end and the second end of the switching element in the first output circuit 102 become high. Flat, thereby outputting a gate drive signal at the first output terminal OUT1.
  • the first output circuit 102 may also not include a capacitor.
  • the second output circuit 103 is connected to the pull-up node PU, the second clock signal terminal CK2, and the second output terminal OUT2.
  • the circuit structure inside the second output circuit 103 may be the same as or different from the first output circuit 102.
  • the operation of the second output circuit 103 and its connection to other nodes, circuits or components in the shift register 100 are similar to the first output circuit 102, except that the second output circuit 103 is based on the second clock signal via The second clock signal received by CK2 outputs a gate drive signal at the second output terminal OUT2.
  • the second clock signal can be set to be later than the first clock signal (eg, the rising edge of the high level of the second clock signal can be aligned with the falling edge of the high level of the first clock signal),
  • the shift register 100 is capable of sequentially outputting a plurality of gate drive signals through the first output terminal OUT1 and the second output terminal OUT2.
  • FIG. 1 or FIG. 2 shows only two output circuits 102 and 103, in the case where it is required to support multiple outputs, the shift register according to an embodiment of the present disclosure may include three or more output circuits, and these More output circuits may adopt a similar circuit structure and connection manner as the first output circuit 102 and the second output circuit 103, and may refer to the first clock signal terminal CK1 and the second clock signal terminal CK2 and the first clock signal and the first The relationship between the two clock signals sets more clock terminals for more output circuits and determines the relationship between the clock signals received via these more clock terminals, respectively.
  • two pull-down nodes PD1 and PD2 are provided, and include a first pull-down circuit 104 and a second pull-down circuit 105, wherein the first pull-down circuit 104 and the first pull-down node PD1, the pull-up node The PU, the first output terminal OUT1, the second output terminal OUT2 and the reference signal terminal RS are connected, and the second pull-down circuit 105 and the second pull-down node PD2, the pull-up node PU, the first output terminal OUT1, the second output terminal OUT2, and The reference signal terminal RS is connected.
  • the first pull-down circuit 104 operates when the potential of the first pull-down node PD1 is at a high level, and the internal switching elements thereof are turned on, respectively, the pull-up node PU, the first output terminal OUT1, the second output terminal OUT2, and the reference signal
  • the terminals RS are connected such that the potentials of the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2 are both low.
  • the second pull-down circuit 105 operates when the potential of the second pull-down node PD2 is at a high level, and the internal switching elements thereof are turned on, respectively, the pull-up node PU, the first output terminal OUT1, the second output terminal OUT2, and the reference signal terminal RS
  • the connection is such that the potentials of the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2 are both low.
  • the first pull-down circuit 104 may include at least three switching elements, wherein the control terminals of each of the three switching elements are connected to the first pull-down node PD1, among the three switching elements The first end of each of the first switching terminals is connected to the reset signal terminal RS, and the second ends of the three switching elements are respectively connected to the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2.
  • the second pull-down circuit 105 can adopt a similar circuit structure except that the control terminal of the switching element in the second pull-down circuit 105 is connected to the second pull-down node PD2.
  • multiple dropdown nodes can be used simultaneously.
  • the two pull-down nodes PD1 and PD2 in FIG. 1 or FIG. 2 may be simultaneously in a high level or a low level state, thereby causing the two pull-down circuits 104 and 105 to operate simultaneously or not.
  • the pull-down capability of the potential of the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2 can be improved.
  • multiple pulldown nodes can be used alternately.
  • a plurality of pull-down nodes can be alternately used in units of one frame.
  • the potential of the second pull-down node PD2 may be always low during the first frame period, such that during the period of the frame, only the first pull-down circuit 104 can operate, and the second pull-down The circuit 105 is always inactive; during the subsequent second frame period, the potential of the first pull-down node PD1 is always at a low level, so that during the period of the frame, only the second pull-down circuit 105 can operate, and A pull down circuit 104 never works.
  • the potential of the second pull-down node PD2 may be always at a low level during the first frame and the second frame, so that only the first pull-down circuit 104 can operate during the first frame and the second frame period.
  • the second pull-down circuit 105 is always inactive; during the subsequent third frame and the fourth frame period, the potential of the first pull-down node PD1 is always low, so that during the third frame and the fourth frame Internally, only the second pull-down circuit 105 is operational, while the first pull-down circuit 104 is always inoperative.
  • Alternate use of multiple pull-down nodes and corresponding pull-down circuits is beneficial to improve circuit reliability.
  • FIG. 1 shows only two pull-down nodes and two pull-down circuits
  • the shift register according to an embodiment of the present disclosure may include three or more pull-down nodes and corresponding pull-down circuits.
  • a pull-down node selection circuit 106 may be provided in the shift register 100, and the pull-down node selection circuit 106 is used to select a pull-down node to be used, and control the Select the potential of the pull-down node. It should be appreciated that since the shift register according to an embodiment of the present invention may have a plurality of pull-down nodes and may select to use one or more of the plurality of pull-down nodes, the potential of the pull-down node selected for use may be controlled Change, therefore, in this article, "drop-down node” can also be referred to as "active drop-down node.”
  • the pull-down node selection circuit 106 and the first pull-down node selection signal terminal PDS1, the second pull-down node selection signal terminal PDS2, the first pull-down node PD1, the second pull-down node PD2, and the pull-down selection control signal terminal CK3 is connected to the reference signal terminal RS.
  • the pull-down node selection circuit 106 may be configured to turn on a switching element that internally connects the second pull-down node PD2 and the reference signal terminal RS when receiving the signal via the first pull-down node selection signal terminal PDS1, so that the first During the period in which the potential of the pull node selection signal terminal PDS1 is high, the potential of the second pull-down node PD2 is always at a low level, and when the signal is received via the second pull-down node selection signal terminal PDS2, the internal connection is first.
  • the switching elements of the pull-down node PD1 and the reference signal terminal RS are turned on, so that the potential of the first pull-down node PD1 is always at a low level during a period in which the potential of the second pull-down node selection signal terminal PDS2 is high.
  • the shift register 100 includes three or more pull-down nodes
  • more pull-down node selection signal terminals may be set for the shift register 100, and the pull-down node selection circuit 106 and these pull-down node selection signal terminals may be provided. Connect to all drop-down nodes.
  • the plurality of pull-down nodes may select signal terminals (including the first pull-down node selection signal terminal PDS1 and the second pull-down node selection signal terminal) within a time period determined in units of one or more frames.
  • the potential of a pull-down node selection signal terminal in PDS2) is set to a high level, and the pull-down node corresponding to the pull-down node selection signal end is selected as an active pull-down node by the pull-down node selection circuit 106 while maintaining other inactive pull-down nodes. The potential is low.
  • the third clock signal received via the pull-down selection control signal terminal CK3 may be set later than the second clock signal received via the second clock signal terminal CK2 (eg, the high level of the third clock signal may be made)
  • the rising edge is aligned with the falling edge of the high level of the second clock signal, and the first clock signal and the second clock signal are both in a low state when the third clock signal is high level) to ensure the first
  • the pull circuit 104 and the second pull-down circuit 105 start to operate after both the first output circuit 102 and the second output circuit 103 complete the output operation.
  • the third clock signal can be set to be later than the clock signal for the output circuit of the final output of all of the output circuits.
  • the rising edge of the high level of the third clock signal can be aligned with the falling edge of the high level of the clock signal for the output circuit of the last completed output of all the output circuits, and the clock signals used for all the output circuits are
  • the third clock signal is high, it is in a low state to ensure that all pull-down circuits start to work after all output circuits have completed the output operation.
  • FIG. 4 shows an exemplary circuit configuration of the shift register 100.
  • the input circuit 101_1 may include a first input switching element SW1 and a first pull-down node reset switching element SW2, wherein the control end of the first input switching element SW1, the first end And the second end is respectively connected to the input terminal IN of the shift register, the first scanning direction control terminal CN and the pull-up node PU0, and the first pull-down node resets the control end, the first end and the second end of the switching element SW2 respectively
  • the pull-up node PU0, the first pull-down node PD1 and the reference signal terminal RS are connected.
  • the reset circuit 101_2 may include a second input switching element SW8 and a second pull-down node reset switching element SW3, wherein the control terminal, the first end and the second end of the second input switching element SW8 are respectively associated with a reset terminal RESET of the shift register,
  • the second scanning direction control end CNB is connected to the pull-up node PU0, and the second pull-down node resets the control end, the first end and the second end of the switching element SW3 with the pull-up node PU0, the second pull-down node PD2 and the reference signal end RS, respectively. Connected.
  • the first output circuit 102 may include a second output switching element SW4, a first output switching element SW5, and a first output capacitor C1, wherein the control end, the first end, and the second end of the second output switching element SW4 are respectively associated with the node PU1
  • the first clock signal terminal CK1 is connected to the first output terminal OUT1
  • the two ends of the first output capacitor C1 are respectively connected to the node PU1 and the first output terminal OUT1
  • the control end, the first end and the first output switching element SW5 are respectively The two ends are respectively connected to the working potential terminal VGH, the pull-up node PU0 and the node PU1.
  • the second output circuit 103 may include a fourth output switching element SW6, a third output switching element SW7, and a second output capacitor C2, wherein the control end, the first end, and the second end of the fourth output switching element SW6 are respectively associated with the node PU2
  • the second clock signal terminal CK2 is connected to the second output terminal OUT2, and the two ends of the second output capacitor C2 are respectively connected to the node PU2 and the second output terminal OUT2, and the control terminal, the first terminal and the third terminal of the third output switching element SW7.
  • the two ends are respectively connected to the working potential terminal VGH, the pull-up node PU0 and the node PU2.
  • the control terminals of the first output switching element SW5 and the third output switching element SW7 are connected to the operating potential terminal VGH, and the first output switching element SW5 and the third output switching element SW7 It is always in an on state such that the potential of the node PU1 in the first output circuit 103 and the node PU2 in the second output circuit 104 is always the same as the potential of the pull-up node PU0.
  • the first output switching element SW5 and the third output switching element SW7 are optional, and in the case where the first output switching element SW5 and the third output switching element SW7 are not provided, the node PU1 and the node PU0 (or FIG.
  • the pull-up node PU is the same point. Since the potentials of the nodes PU0, PU1, and PU2 are always the same, the nodes PU0, PU1, and PU2 can be considered as reflections of the pull-up node PU of the shift register 100 at different positions in the shift register circuit. In fact, in the circuit shown in FIG. 4, a node having the same potential as the node PU0 and/or PU1 and/or PU2 at any time can be regarded as a pull-up node PU, and simply use "pull up" hereinafter. Node PU" stands for these nodes.
  • the first pull-down circuit 103 may include a first pull-down switching element SW14, a second pull-down switching element SW15, and a third pull-down switching element SW16, wherein the first pull-down switching element SW14, the second pull-down switching element SW15, and the third pull-down
  • the control terminals of the switching element SW16 are both connected to the first pull-down node PD1, and the first ends of the first pull-down switching element SW14, the second pull-down switching element SW15 and the third pull-down switching element SW16 are connected to the reference signal terminal RS,
  • the second ends of a pull-down switching element SW14, a second pull-down switching element SW15, and a third pull-down switching element SW16 are respectively connected to the node PU0 (or the pull-up node PU), the first output terminal OUT1, and the second output terminal OUT2.
  • the second pull-down circuit 104 may include a fourth pull-down switching element SW17, a sixth pull-down switching element SW18, and a fifth pull-down switching element SW19, wherein the fourth pull-down switching element SW17, the sixth pull-down switching element SW18, and the fifth pull-down switching element SW19
  • the control terminals are all connected to the second pull-down node PD2, and the first ends of the fourth pull-down switching element SW17, the sixth pull-down switching element SW18 and the fifth pull-down switching element SW19 are connected to the reference signal terminal RS, and the fourth pull-down switching element SW17
  • the second ends of the sixth pull-down switching element SW18 and the fifth pull-down switching element SW19 are respectively connected to the node PU0 (or the pull-up node PU), the second output terminal OUT2, and the first output terminal OUT1.
  • the pull-down node selection circuit 106 may include a selection control switching element SW9, a first pull-down selection switching element SW10, a second pull-down selection switching element SW11, a third pull-down selection switching element SW12, a fourth pull-down selection switching element SW13, and a first capacitor C3.
  • a second capacitor C4 wherein the control terminal and the first end of the selection control switching element SW9 are both connected to the pull-down selection control signal terminal CK3 of the shift register, and the second end of the control switching element SW9 is selected and the first pull-down selection switch
  • the first end of the element SW10 is connected to the first end of the third pull-down selection switch element SW12, and the control end and the second end of the first pull-down selection switch element SW10 are respectively connected to the first pull-down node selection signal terminal PDS1 and the first
  • the pull node PD1 is connected, and the control end and the second end of the third pull-down selection switch element SW12 are respectively connected to the second pull-down node selection signal terminal PDS2 and the second pull-down node PD2, and the control terminal of the second pull-down selection switch element SW11 is first.
  • the terminal and the second end are respectively connected to the first pull-down node selection signal terminal PDS1, the second pull-down node PD2, and the reference signal terminal RS, and the fourth pull-down selection switching component
  • the control terminal, the first end and the second end of the SW13 are respectively connected to the second pull-down node selection signal terminal PDS2, the first pull-down node PD1 and the reference signal terminal RS, and the first capacitor C3 is disposed at the first pull-down node PD1 and the reference Between the signal terminals RS, the second capacitor C4 is disposed between the second pull-down node PD2 and the reference signal terminal RS.
  • the switching element SW8 may be connected to the reference signal terminal RS instead of the second scanning signal terminal CNB, and may further include another switching element, for example, The control terminal, the first terminal and the second terminal of the further switching element are respectively connected to the reset terminal RESET, the first output terminal OUT1 (and/or the second output terminal OUT2) and the reference signal terminal RS.
  • more pulldown nodes can be set and more pull down circuits are set accordingly.
  • more outputs can be set and more output circuits are set accordingly.
  • the present disclosure is not limited to the exemplary circuit configuration shown in FIG.
  • FIG. 5 shows the shift register 100 shown in FIG. 1, FIG. 2 or FIG. 4 in the forward scan mode (the first scan direction control terminal CN is at a high level, and the second scan direction control terminal CNB is at a low level).
  • the timing of the operation during the next two frames i-th frame and i+1-th frame).
  • the first pull-down node select signal terminal PDS1 is at a high level
  • the second pull-down node selects a signal terminal PDS2 at a low level.
  • the first pull-down selection switching element SW10 and the second pull-down selection switching element SW11 are turned on, and the third pull-down selection switching element SW12 and the fourth pull-down selection switching element SW13 are turned off, thereby selecting the first lower
  • the pull node PD1 acts as a live pulldown node and causes the second pulldown node PD2 to be always low.
  • the cutoff causes the second pull-down circuit 105 to not operate during the ith frame.
  • the shift register 100 When the shift register 100 receives the input signal via the input terminal IN, the first input switching element SW1 and the first pull-down node reset switching element SW2 in the input circuit 101_1 are turned on, so that the potential of the pull-up node PU becomes a high level. The potential of the first pull-down node PD1 becomes a low level. The first output capacitor C1 and the second output capacitor C2 of the first output circuit 102 and the second output circuit 103 start to be charged, and the second output switching element SW4 and the fourth output switching element SW6 are turned on. At this time, the potentials of the first clock signal terminal CK1 and the second clock signal terminal CK2 are both low levels, so that no gate drive signal is output at both the first output terminal OUT1 and the second output terminal OUT2.
  • the potential of the input terminal IN becomes a low level.
  • the potential of the pull-up node PU continues to be maintained in a high state by the first output capacitor C1 and the second output capacitor C2, such that the second output switching element SW4 and the fourth of the second output circuit 103 in the first output circuit 102
  • the output switching element SW6 is still in an on state.
  • the potential of the first clock signal terminal CK1 becomes a high level, so that the potential of the first output terminal OUT1 becomes a high level, thereby outputting a gate driving signal at the first output terminal OUT1, and the second clock signal terminal CK2 remains It is low level, so there is still no gate drive signal output at the second output terminal OUT2.
  • the potential of the first clock signal terminal CK1 becomes a low level
  • the potential of the second clock signal terminal CK2 becomes a high level
  • the potential of the first output terminal OUT1 becomes a low level
  • the potential of the second output terminal OUT2 It becomes a high level to output a gate drive signal at the second output terminal OUT2.
  • the potential of the reset terminal RESET of the shift register 100 becomes a high level, so that The second input switching element SW8 in the reset circuit 101_2 is turned on, thereby causing the potential of the pull-up node PU to be at a low level.
  • the potential of the pull-down selection control signal terminal CK3 becomes a high level, and the selection control switching element SW9 in the pull-down node selection circuit 106 is turned on, so that the first pull-down node PD1 becomes a high level, and the pull-down node selection circuit 106
  • the first capacitor C3 in the middle begins to charge.
  • the first pull-down switching element SW14, the second pull-down switching element SW15, and the third pull-down switching element SW16 in the first pull-down circuit 104 are turned on, so that the pull-up node PU, The potentials of the first output terminal OUT1 and the second output terminal OUT2 become a low level.
  • the potential of the pull-down selection control signal terminal CK3 becomes a low level
  • the potential of the first pull-down node PD1 continues to remain in a high state state by the first capacitor C3 in the pull-down node selection circuit 106, and when the selection control signal is pulled down
  • the potential of the terminal CK3 becomes the high level again
  • the potential of the first pull-up node PD1 is at the high level
  • the first capacitor C3 in the pull-down node selection circuit 106 starts charging again. This is repeated such that the potential of the first pull-down node PD1 is always in a high state.
  • the first pull-down node selection signal terminal PDS1 is at a low level
  • the second pull-down node selection signal terminal PDS2 is at a high level.
  • the first pull-down selection switching element SW10 and the second pull-down selection switching element SW11 are turned off, and the third pull-down selection switching element SW12 and the fourth pull-down selection switching element SW13 are turned on, thereby selecting the second pull-down.
  • the node PD2 acts as an active pulldown node and causes the first pulldown node PD1 to be always low.
  • the first pull-down switching element SW14, the second pull-down switching element SW15 and the third pull-down switching element in the first pull-down circuit 104 connected to the first pull-down node PD1 by the control terminal SW16 is all turned off, so that the first pull-down circuit 104 does not operate during the (i+1)th frame.
  • the operation timing of the shift register is similar to the operation timing during the ith frame, and the same points are not repeated. The difference is that when the potential of the pull-down selection control signal terminal CK3 becomes a high level, the selection control switching element SW9 in the pull-down node selection circuit 106 is turned on, the second pull-down node PD2 becomes a high level, and the pull-down node selection circuit 106 The second capacitor C4 in the middle begins to charge.
  • the fourth pull-down switching element SW17, the sixth pull-down switching element SW18, and the fifth pull-down switching element SW19 in the second pull-down circuit 105 are turned on, so that the pull-up node PU and the second output are The potential of the terminal OUT2 and the first output terminal OUT1 becomes a low level.
  • the first scan direction control terminal CN of the shift register is at a low level, and the second scan direction control terminal CNB is at a high level.
  • the reset circuit 101_2 corresponds to the input circuit 101_1 in the case of forward scanning
  • the input circuit 101_1 corresponds to the reset circuit 101_2 in the case of forward scanning.
  • the operation timing of the shift register in the reverse scan mode is similar to the operation timing in the forward scan mode, and the related description is omitted herein.
  • Fig. 5 only shows the case where two pull-down nodes are alternately used in units of one frame.
  • two pull-down nodes may be alternately used in units of a plurality of frames as needed (for example, two pull-down nodes may be alternately used between adjacent two frames and two frames, or may be adjacent).
  • the two drop-down nodes are alternately used between one frame and three frames, etc., or more pull-down nodes are set, and these pull-down nodes are sequentially used in units of one or more frames set in advance.
  • the operation timing of these modified shift registers is similar to that shown in FIG. 5, unlike the period of switching of the pull-down node and/or the number of pull-down nodes, the related description is omitted herein.
  • the duty ratio of each clock signal may be 1/3.
  • each clock signal is occupied.
  • the air ratio can be set to be smaller as needed, for example 1/4.
  • the duty ratio of each clock signal can be set to 1/4.
  • the duty ratio of each clock signal can be set to 1/5, and so on.
  • FIG. 6 illustrates a method for driving a shift register in accordance with an embodiment of the present disclosure.
  • the exemplary method begins in step 601.
  • the shift register selects one of the first pulldown node and the second pulldown node as the active pulldown node and sets the potential of the other to the reset potential.
  • the first pull-down node selection signal terminal PDS1 and the second pull-down node selection signal terminal PDS2 of the shift register 100 may be provided correspondingly. signal.
  • the pull-down node selection circuit 106 sets one of the first pull-down node PD1 and the second pull-down node PD2 as an active pull-down node according to the potentials of the first pull-down node selection signal terminal PDS1 and the second pull-down node selection signal terminal PDS2, and Set the other potential to remain low at all times.
  • the first pulldown node PD1 and the second pulldown node PD2 may be alternately used as the active pulldown node in accordance with a preset number of frames.
  • the shift register receives the input signal and sets the potential of the pull-up node to the operating potential.
  • the shift register 100 can pull up the node PU (including nodes PU0, PU1, and PU2) upon receiving an input signal via the input IN.
  • the potential of the ) is set to a high level.
  • the first output terminal OUT1 and the second output terminal OUT2 have no gate drive signal output.
  • step 610 the shift register outputs a first gate drive signal at the first output in response to receiving the first clock signal.
  • the shift register 100 may output at the first output terminal OUT1 when receiving the first clock signal via the first clock signal terminal CK1 terminal.
  • Gate drive signal At this time, the potential of the pull-up node PU (including the nodes PU0, PU1, and PU2) can be maintained in a high state by the capacitance in the first output circuit 102 and the second output circuit 103, and is not present at the second output terminal OUT2.
  • Gate drive signal output output.
  • step 615 the shift register outputs a second gate drive signal at the second output in response to the second clock signal received after the first clock signal.
  • the shift register 100 may output at the second output terminal OUT2 when receiving the second clock signal via the second clock signal terminal CK2 terminal.
  • Gate drive signal At this time, the potential of the pull-up node PU (including the nodes PU0, PU1, and PU2) is still maintained in a high state by the capacitors in the first output circuit 102 and the second output circuit 103, and is not present at the first output terminal OUT1. Gate drive signal output.
  • step 620 the shift register sets the potential of the active pull-down node to the operating potential in response to the reference signal received after the second clock signal.
  • the shift register 100 can cause the pull-up node PU (including the nodes PU0, PU1, and PU2) when receiving the reference signal via the reset terminal RESET. ) becomes low.
  • the pull-down node selection circuit 106 in the shift register 100 can receive the third clock signal via the pull-down selection control signal terminal CK3 in response to the shift register 100, and select the first pull-down node PD1 or the first selected as the active pull-down node.
  • the potential of the two pull-down node PD2 is set to a high level.
  • the shift register sets the potentials of the pull-up node, the first output, and the second output to a reset potential.
  • the potential of the active pull-down node the first pull-down node PD1 or the second pull-down node PD2
  • active The pull-down circuit the first pull-down circuit 104 or the second pull-down circuit 105 corresponding to the pull-down node starts to work, and pulls up the node PU (including the nodes PU0, PU1, and PU2), the first output terminal OUT1, and the second output terminal.
  • the potential of OUT2 is set to low.
  • the capacitor in the pull-down node selection circuit 106 is charged while the potential of the active pull-down node is set to the high level, when the shift register 100 When the potential of the pull-down selection control signal terminal CK3 is low, the potential of the active pull-down node continues to remain in a high state state by the capacitor in the pull-down node selection circuit 106, so that the active pull-down node corresponds to the pull-down circuit (first down)
  • the pull circuit 104 or the second pull-down circuit 105) is still in operation, so that the potentials of the pull-up node PU (including the nodes PU0, PU1, and PU2), the first output terminal OUT1, and the second output terminal OUT2 remain at a low level. status.
  • FIG. 7 illustrates an exemplary connection manner of a gate driving circuit including a shift register according to an embodiment of the present disclosure.
  • Terminals of the reference signal terminal RS of the shift register, the working potential terminal VGH, the first scanning direction control terminal CN, the second scanning direction control terminal CNB, the first pull-down node selection signal terminal PDS1, and the second pull-down node selection signal terminal PDS2 Mainly used to receive external control signals, so these terminals of the shift register are not shown in Figure 7 for cascading the shift register.
  • each shift register is the exemplary shift register 100 shown in FIG. 1, FIG. 2, or FIG.
  • the shift register according to an embodiment of the present disclosure may have other modifications, for example, may have more outputs and clock signal terminals, and may be based on the relationship between the respective clock signals described above. Set these clock signals.
  • the input terminal IN of the first stage shift register SR1 receives the frame start signal STV.
  • the input terminals IN of the shift registers (for example, SR2, SR3, SR4, SR5 in FIG. 7) other than the first stage are respectively associated with the corresponding upper-stage shift registers (for example, SR1, SR2 in FIG. 7).
  • the second output terminals OUT2 of the SR3, SR4) are connected, that is, the shift registers of the stages other than the first stage receive the gate drive signals from the second output terminal OUT2 of the corresponding upper stage shift register as their inputs. signal.
  • the reset terminals RESET of the shift registers (for example, SR1, SR2, SR3, and SR4 in FIG. 7) other than the last stage are respectively associated with the corresponding next-stage shift registers (for example, SR2, SR3 in FIG. 7).
  • the first output terminal OUT1 of SR4 and SR5) is connected, that is, the shift registers of the stages other than the last stage receive the gate drive signal from the first output terminal OUT1 of the corresponding next stage shift register as a reference thereof. signal.
  • the reset terminal RESET of the last set of shift registers (not shown in FIG. 7), for example, can receive the frame start signal STV (not shown in FIG. 7) in the reverse scan.
  • a clock signal can be supplied to the shift registers of the gate drive circuits through the timing control circuit.
  • the gate driving circuit is formed by the exemplary shift register 100 as shown in FIG. 1, FIG. 2 or FIG. 4, four clock signal lines (CLOCK1, CLOCK2, CLOCK3, and the like) connected to the timing control circuit 701 can be used.
  • CLOCK4 provides a clock signal to the first clock signal terminal CK1, the second clock signal terminal CK2, and the pull-down node selection signal terminal CK3 of each stage shift register.
  • the duty ratio of each clock signal can be set to 1/4, and the falling edge of the high level of the clock signal supplied via CLOCK1 is aligned with the rising edge of the high level of the clock signal supplied via CLOCK2.
  • the falling edge of the high level of the clock signal supplied via CLOCK2 is aligned with the rising edge of the high level of the clock signal supplied via CLOCK3, so that the falling edge of the high level of the clock signal supplied via CLOCK3 is passed
  • the rising edge of the high level of the clock signal supplied by CLOCK4 is aligned, and the falling edge of the high level of the clock signal supplied via CLOCK4 is aligned with the rising edge of the high level of the clock signal supplied via CLOCK1.
  • the first clock signal terminal CK1, the second clock signal terminal CK2, and the pull-down node selection signal terminal CK3 cascaded in the odd-numbered shift register may be connected to the clock signal lines CLOCK1, CLOCK2, and CLOCK3, respectively, and cascaded in even-numbered stages.
  • the first clock signal terminal CK1, the second clock signal terminal CK2, and the pull-down node selection signal terminal CK3 of the shift register are connected to the clock signal lines CLOCK3, CLOCK4, and CLOCK1, respectively.
  • the progressive scan output of the single-sided gate drive circuit can be realized by providing a clock signal to the shift registers of the gate drive circuits in the configuration shown in FIG.
  • Fig. 8 is a view schematically showing an operation timing chart of the gate driving circuit shown in Fig. 7 during two adjacent frames (i-th frame and i-th frame).
  • CLOCK1 to CLOCK4 are clock signals having a duty ratio of 1/4, and as described above, the falling edge of the high level of the clock signal supplied by CLOCK1 and the high level of the clock signal supplied by CLOCK2.
  • the rising edge is aligned.
  • the falling edge of the high-level clock signal provided by CLOCK2 is aligned with the rising edge of the high-level clock signal provided by CLOCK3.
  • the falling edge of the high-level clock signal provided by CLOCK3 is connected with CLOCK4.
  • the rising edge of the high level of the supplied clock signal is aligned, and the falling edge of the high level of the clock signal provided by CLOCK4 is aligned with the rising edge of the high level of the clock signal provided by CLOCK1.
  • PSD1 is at a high level, so that the first pull-down node PD1 is selected as the active pull-down node, and the potential of the second pull-down node PD2 is set to the reset potential, and the potential of the PD1 node can be selected at the pull-down node.
  • the signal terminal CK3 is at a high level, it is set to an operating potential.
  • PSD2 is at a high level, so that the second pull-down node PD2 is selected as the active pull-down node, and the potential of the first pull-down node PD1 is set to the reset potential, and the potential of the PD2 node can be When the pull-down node selects the signal terminal CK3 to be high, it is set to the operating potential.
  • the gate driving circuit can realize the 8-way progressive scan output of SR1OUT1-SR4OUT2 as shown in FIG.
  • FIG. 9 illustrates another exemplary connection manner of a gate driving circuit including a shift register according to an embodiment of the present disclosure.
  • FIG. 9 shows a configuration of a clock signal for the progressive scan output of the bilateral gate drive circuit with each of the shift registers having two output terminals OUT1 and OUT2 as an example.
  • the bilateral gate driving circuit includes a first gate driving circuit and a second gate driving circuit, each gate driving circuit including a plurality of shift registers.
  • Fig. 9 only schematically shows that each gate driving circuit includes four shift registers (SR1-1, SR1-2, SR1-3, SR1-4, and SR2-1, SR2-2, SR2-3). , SR2-4), and more shift registers can be included in the actual application.
  • the input end of the first stage shift register of the first gate driving circuit is connected to the frame start signal, and the reset end of the first stage shift register of the first gate driving circuit is connected to the first stage shift of the second gate driving circuit a first output terminal OUT1 of the bit register;
  • the input end of the i-th stage shift register of the first gate driving circuit is connected to the second output end OUT2 of the i-th stage shift register of the second gate driving circuit, and the i-th stage shift of the first gate driving circuit
  • the reset end of the bit register is connected to the first output terminal OUT1 of the i-th stage shift register of the second gate driving circuit, where 1 ⁇ i ⁇ N;
  • the input end of the jth stage shift register of the second gate driving circuit is connected to the second output terminal OUT2 of the jth stage shift register of the first gate driving circuit, and the jth stage shift register of the second gate driving circuit
  • the reset terminal is connected to the first output terminal OUT1 of the j+1th stage shift register of the first gate driving circuit, where 1 ⁇ j ⁇ N.
  • the input terminal IN of SR1-1 is connected to the frame start signal STV
  • the second output terminal OUT2 of SR1-1 is connected to the input terminal IN of SR2-1
  • the reset terminal RESET of SR1-1 Connected to the first output terminal OUT1 of SR2-1
  • the input terminal of SR1-2 is connected to the second output terminal OUT of SR2-1
  • the reset terminal RESET of SR2-1 is connected to the first output terminal OUT1 of SR1-2, This type of push.
  • the lines CLOCK1, CLOCK2 and CLOCK3 are connected, and the first clock signal terminal CK1, the second clock signal terminal CK2 and the pull-down selection signal terminal CK3 of the shift registers of the second gate driving circuit are respectively supplied from the timing control circuit 902.
  • the clock signal lines CLOCK7, CLOCK8 and CLOCK5 are connected.
  • the two timing control circuits 901 and 902 shown in FIG. 9 may output four clock signals (CLOCK1-CLOCK8) to control the respective gate driving circuits, or may use the same timing control circuit to output four clocks.
  • a signal is used to control the gate drive circuit.
  • the clock signal line CLOCK7 shown in FIG. 9 corresponds to CLOCK3
  • the clock signal line CLOCK8 corresponds to CLOCK4
  • the clock signal line CLOCK5 corresponds to CLOCK1.
  • the gate drive circuit can realize the bilateral scan output by the connection manner of the shift registers of the gate drive circuits as shown in FIG. 9 and the arrangement of the clock signals supplied to the shift registers of the stages.
  • each stage shift register in the gate drive circuit shown in FIG. 7 or FIG. 9 is similar to the operation of the exemplary shift register 100 shown in FIG. 5, except that each of FIG. 5
  • the duty ratio of one clock signal is 1/3
  • the duty ratio of the clock signal received by each stage shift register in FIG. 7 or FIG. 9 is 1/4.
  • each stage shift register in the gate driving circuit supports n (n is a positive integer) output and correspondingly includes n+1 clock signal terminals
  • the gate driving circuit can be provided to the gate driving circuit through the timing control circuit. 2*n clock signals, wherein the duty ratio of each clock signal can be set equal to or less than 1/(2n), and these clock signals are respectively supplied to each stage shift in a manner similar to FIG. 7 or FIG. n+1 clock signals of the bit register.
  • FIG. 10 illustrates a display device including two gate driving circuits including a first gate driving circuit 1001 and a second gate driving circuit 1002, according to an embodiment of the present disclosure.
  • the cascade structure inside the gate drive circuit is not shown in FIG. 10, but only a few of the shift registers SR1-SR3 are exemplarily shown.
  • the manner in which the shift registers of the two gate drive circuits in the display device shown in FIG. 10 are connected may be the one shown in FIG.
  • a pixel P is provided, and the timing controller 1004 supplies a clock to the data signal providing circuit 1003 and the two gate driving circuits 1001, 1002. signal.
  • the cascade is in the The first output terminal OUT1 and the second output terminal OUT2 of the shift register of the i-stage (i is a positive integer) are respectively connected to the 4i-3th and 4i-2th scanning signal lines, and the second gate driving circuit 1002
  • the first output terminal OUT1 and the second output terminal OUT2 of the shift register of the jth stage (j is a positive integer) are connected to the 4j-1th and 4jth scanning signal lines, respectively.
  • the first output terminal OUT1 and the second output terminal OUT2 of the first-stage shift register SR1 in the first gate driving circuit 1001 are connected to the scanning signal line 1 and the scanning signal line, respectively.
  • the first output terminal OUT1 and the second output terminal OUT2 of the first-stage shift register SR1 in the second gate driving circuit 1002 are connected to the scanning signal line 3 and the scanning signal line 4, respectively, and so on.
  • the first gate electrode can be made in a manner similar to that shown in FIG.
  • the three output terminals of the first stage shift register in the driving circuit 1001 are respectively connected to the first to third scanning signal lines, so that the three output terminals of the first stage shift register in the second gate driving circuit 1002 Connected to the 4th to 6th scanning signal lines respectively, so that the three output ends of the second stage shift register in the first gate driving circuit 1001 are respectively connected to the 7th to 9th scanning signal lines, so that the second The three output terminals of the second stage shift register in the gate driving circuit 1002 are connected to the 10th to 12th scanning signal lines, and so on.
  • a counter (not shown in Fig. 10) may be provided. Whenever a frame start signal is sent to the first gate driving circuit 901, the value of the counter is incremented by one. When the value of the counter reaches a value set in advance (for example, set in a control chip or a controller of the display device in advance), the control circuit or the processor (not shown in FIG.
  • the display device may be changed to be supplied to the first a first pull-down node of each stage shift register of the gate drive circuit 1001 and the second gate drive circuit 1002 selects a signal of the signal terminal PDS1 and the second pull-down node selection signal terminal PDS2, thereby causing the first gate drive All shift registers in circuit 1001 and second gate drive circuit 1002 change the corresponding active pull-down node.
  • a shift register according to an embodiment of the present disclosure may support multiple outputs; and may perform circuit by alternately setting two or more pull-down nodes in a shift register and alternately using a predetermined number of frame units More reliable.
  • the shift register according to an embodiment of the present disclosure can enhance the drive control capability of the single-stage shift register by relatively few switching elements.
  • the gate drive circuit and the display device employing the shift register according to an embodiment of the present disclosure are more reliable, and are more advantageous for implementing a narrow bezel vehicle display product.

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Abstract

一种移位寄存器及其驱动方法以及对应的栅极驱动电路和显示装置。移位寄存器(100)包括输入和复位电路(101)、第一输出电路(102)、第二输出电路(103)、第一下拉电路(104)和第二下拉电路(105)，其中，第一输出电路(102)和第二输出电路(103)分别根据第一时钟信号端(CK1)和第二时钟信号端(CK2)的电位，输出栅极驱动信号，第一下拉电路(104)和第二下拉电路(105)分别根据第一下拉节点(PD1)和第二下拉节点(PD2)的电位，对上拉节点(PU)、第一输出端(OUT1)和第二输出端(OUT2)的电位进行复位。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置
本申请要求于2017年11月27日递交的第201711204895.0号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术，具体地涉及一种移位寄存器以及对应的驱动方法、栅极驱动电路和显示装置。
背景技术
作为显示器中的主要驱动电路，栅极驱动电路(GOA)的各项性能直接影响到液晶显示的质量。在车载显示器件的情况下，针对GOA的可靠性要求更为苛刻。近年来，液晶显示器(LCD)面板的尺寸越来越大，集成化程度越来越高，电路结构越来越复杂。在降低功耗、增加系统稳定性等方面的需求也随之增加，低功耗和稳定性成为GOA技术领域关注的热点。用相对较少的开关元件，增强单级移位寄存器的驱动控制能力，提高GOA所驱动的显示器的可靠性，对于实现窄边框车载显示产品非常重要。
发明内容
本公开提供一种移位寄存器以及对应的驱动方法、栅极驱动电路和显示装置。
本公开的一方面涉及一种移位寄存器，该移位寄存器可以包括：输入和复位电路，与输入端、上拉节点、复位端相连，被配置为在输入端的电位为工作电位的情况下，将上拉节点的电位设置为工作电位，并且在复位端的电位为工作电位的情况下，将上拉节点的电位设置为复位电位；第一输出电路，与上拉节点、第一控制信号端、第一输出端相连，被配置为在上拉节点的电位和第一控制信号端的电位为工作电位的情况下，在第一输出端输出第一栅极驱动信号；第二输出电路，与上拉节点、第二控制信号端、第二输出端相连，被配置为在上拉节点的电位和第二控制信号端的电位为工作电位的情况 下，在第二输出端输出第二栅极驱动信号；第一下拉电路，与第一下拉节点、上拉节点、第一输出端、第二输出端相连，被配置为在第一下拉节点的电位为工作电位的情况下，将上拉节点、第一输出端和第二输出端的电位设置为复位电位；第二下拉电路，与第二下拉节点、上拉节点、第一输出端、第二输出端相连，被配置为在第二下拉节点的电位为工作电位的情况下，将上拉节点、第一输出端和第二输出端的电位设置为复位电位；以及下拉节点选择电路，与第一下拉节点选择信号端、第二下拉节点选择信号端、第一下拉节点、第二下拉节点相连，被配置为根据第一下拉节点选择信号端的电位和第二下拉节点选择信号端的电位，将第一下拉节点和第二下拉节点中的一个选择为活跃下拉节点。
在一个实施例中，下拉节点选择电路可以包括：第一下拉选择开关元件，其控制端与第一下拉节点选择信号端相连，其第一端和第二端中的一个与第一下拉节点相连；第二下拉选择开关元件，其控制端与第一下拉节点选择信号端相连，其第一端和第二端中的一个与第二下拉节点相连，其第一端和第二端中的另一个与参考信号端相连；第三下拉选择开关元件，其控制端与第二下拉节点选择信号端相连，其第一端和第二端中的一个与第二下拉节点相连，其第一端和第二端中的另一个与第一下拉选择开关元件的第一端和第二端中的另一个相连；以及第四下拉选择开关元件，其控制端与第二下拉节点选择信号端相连，其第一端和第二端中的一个与第一下拉节点相连，其第一端和第二端中的另一个与参考信号端相连。
在一个实施例中，下拉节点选择电路还可以包括：第一电容器，连接在第一下拉节点与参考信号端之间；以及第二电容器，连接在第二下拉节点与参考信号端之间。
在一个实施例中，下拉节点选择电路还可以包括：选择控制开关元件，其控制端以及第一端和第二端中的一个都与下拉选择控制信号端相连，其第一端和第二端中的另一个与第一下拉选择开关元件的第一端和第二端中的另一个相连，并且与第三下拉选择开关元件的第一端和第二端中的另一个相连。
在一个实施例中，输入和复位电路可以包括：第一输入开关元件，其控制端与输入端相连，其第一端和第二端中的一个与第一扫描控制信号端相连，其第一端和第二端中的另一个与上拉节点相连；以及，第二输入开关元件，其控制端与复位端相连，其第一端和第二端中的一个与第二扫描控制信号端 相连，其第一端和第二端中的另一个与上拉节点相连，其中，正向扫描时，第一扫描控制信号的电位为工作电位，第二扫描控制信号的电位为复位电位，而反向扫描时，第一扫描控制信号的电位为复位电位，第二扫描控制信号的电位为工作电位。
在一个实施例中，输入和复位电路还可以包括：第一下拉节点复位开关元件，其控制端与上拉节点相连，其第一端和第二端中的一个与第一下拉节点相连，其第一端和第二端中的另一个与参考信号端相连；以及，第二下拉节点复位开关元件，其控制端与上拉节点相连，其第一端和第二端中的一个与第二下拉节点相连，其第一端和第二端中的另一个与参考信号端相连。
在一个实施例中，第一输出电路可以包括：第一输出开关元件，其控制端与工作电位端相连，其第一端和第二端中的一个与上拉节点相连；第二输出开关元件，其控制端与第一输出开关元件的第一端和第二端中的另一个相连，其第一端和第二端中的一个与第一控制信号端相连，其第一端和第二端中的另一个与第一输出端相连；以及第一输出电容器，其连接在第二输出开关元件的控制端与第一输出端之间。
在一个实施例中，第二输出电路可以包括：第三输出开关元件，其控制端与工作电位端相连，其第一端和第二端中的一个与上拉节点相连；第四输出开关元件，其控制端与第三输出开关元件的第一端和第二端中的另一个相连，其第一端和第二端中的一个与第二控制信号端相连，其第一端和第二端中的另一个与第二输出端相连；以及第二输出电容器，其连接在第四输出开关元件的控制端与第二输出端之间。
在一个实施例中，第一下拉电路可以包括：第一下拉开关元件，其控制端与第一下拉节点相连，其第一端和第二端中的一个与上拉节点相连，其第一端和第二端中的另一个与参考信号端相连；第二下拉开关元件，其控制端与第一下拉节点相连，其第一端和第二端中的一个与第一输出端相连，其第一端和第二端中的另一个与参考信号端相连；以及第三下拉开关元件，其控制端与第一下拉节点相连，其第一端和第二端中的一个与第二输出端相连，其第一端和第二端中的另一个与参考信号端相连。
在一个实施例中，第二下拉电路可以包括：第四下拉开关元件，其控制端与第二下拉节点相连，其第一端和第二端中的一个与上拉节点相连，其第一端和第二端中的另一个与参考信号端相连；第五下拉开关元件，其控制端 与第二下拉节点相连，其第一端和第二端中的一个与第一输出端相连，其第一端和第二端中的另一个与参考信号端相连；以及第六下拉开关元件，其控制端与第二下拉节点相连，其第一端和第二端中的一个与第二输出端相连，其第一端和第二端中的另一个与参考信号端相连。
本公开的另一方面涉及一种栅极驱动电路，其包括多个级联的如上所述的移位寄存器，其中，除第一级以外，其它各级移位寄存器的输入端与级联在其前一级的移位寄存器的第二输出端相连，并且除最后一级以外，其它各级移位寄存器的复位端与级联在其后一级的移位寄存器的第一输出端相连。
本公开的又一方面涉及一种显示装置，其包括如上所述的栅极驱动电路。
本公开的又一方面涉及一种显示装置，该显示装置可以包括第一栅极驱动电路和第二栅极驱动电路，所述第一栅极驱动电路包括N个级联的如前所述的移位寄存器，所述第二栅极驱动电路包括N个级联的如前所述的移位寄存器；其中，第一栅极驱动电路的第1级移位寄存器的复位端连接第二栅极驱动电路的第1级移位寄存器的第一输出端；第一栅极驱动电路的第i级移位寄存器的输入端连接第二栅极驱动电路的第i-1级移位寄存器的第二输出端，第一栅极驱动电路的第i级移位寄存器的复位端连接第二栅极驱动电路的第i级移位寄存器的第一输出端，其中1<i≤N；第二栅极驱动电路的第j级移位寄存器的输入端连接第一栅极驱动电路的第j级移位寄存器的第二输出端，第二栅极驱动电路的第j级移位寄存器的复位端连接第一栅极驱动电路的第j+1级移位寄存器的第一输出端，其中，1≤j<N。
本公开的又一方面涉及一种用于驱动如上所述的移位寄存器的方法，其包括：在相邻两帧中，将第一下拉节点和第二下拉节点中的一个交替设置为活跃下拉节点，在将其中一个下拉节点设置为活跃节点的情况下，将另一个下拉节点的电位设置为复位电位；在每一帧中，对于每级移位寄存器，第一阶段中，响应于接收到输入信号，将上拉节点的电位上拉为工作电位；第二阶段中，响应于接收到第一时钟信号，在第一输出端输出第一栅极驱动信号，并且响应于在第一时钟信号之后所接收的第二时钟信号，在第二输出端输出第二栅极驱动信号；第三阶段中，响应于在第二时钟信号之后所接收的参考信号，将活跃下拉节点的电位设置为工作电位；以及将上拉节点、第一输出端和第二输出端的电位设置为复位电位。
在一个实施例中，可以按照预先设定的数量的帧，交替使用第一下拉节 点和第二下拉节点作为活跃下拉节点。
附图说明
图1示出根据本公开的实施例的移位寄存器。
图2示出了如图1所示的移位寄存器的另一电路结构示意图。
图3示出根据本公开的另一实施例的移位寄存器。
图4示出根据本公开的实施例的移位寄存器的示例性的电路图。
图5示出根据本公开的实施例的移位寄存器的示例性的工作时序。
图6示出根据本公开的实施例的移位寄存器的示例性的驱动方法。
图7示出包括根据本公开的实施例的移位寄存器的栅极驱动电路的一种示例性的连接方式。
图8示意性地示出了如图7所示的栅极驱动电路在相邻两帧期间的工作时序图。
图9示出包括根据本公开的实施例的移位寄存器的栅极驱动电路的另一种示例性的连接方式。
图10示出根据本公开的实施例的显示装置。
具体实施方式
下面结合附图来描述本公开的实施例。所描述的实施例仅是示例性的，而不用于限制本公开的范围。
在本文中，序数词“第一”、“第二”等仅用于区分不同的端子、元件或电路，而不用于限定这些端子、元件或电路的次序和/或重要度。
在本文中，术语“工作电位”指能够使相应的开关元件导通或者能够使相应的电路工作的电位。例如，如果开关元件需要在其控制端的电位为高电平时才能够导通，则工作电位可以对应于高电平，而如果开关元件需要在其控制端的电位为低电平时才能够导通，则工作电位可以对应于低电位。术语“复位电位”表示与“工作电位”相对的电位，即能够使相应的开关元件切断或者能够使相应的电路不工作的电位。例如，如果工作电位对应于高电平，则复位电位可以对应于低电平；或者如果工作电位对应于低电平，则复位电位可以对应于高电平。工作电位和复位电位可以根据电路的实际情况下决定。在下文的描述中，为了简洁，选择高电平作为工作电位，并且选择低电平作为复 位电位。然而，本公开的技术方案不局限于这样的示例。
在本文中，在经由该端子接收到高电平的信号的情况下，或者在该端子与能够提供高电平的电源相连的情况下，端子的电位为高电平，或者该端子处于高电平。在经由该端子未接收到高电平的信号的情况下，或者在该端子与能够提供低电平的电源相连的情况下，端子的电位为低电平，或者该端子处于低电平。
在本文中，高电平和低电平是相对而言的。可以根据电路的实际情况和设计规范来选择低电平的电压值或电压范围，使得当电压为所选择的值，或者在所选择的范围内时，相应的开关元件被切断或者相应的电路不工作。高电平的电压值通常高于低电平。同样，可以根据电路的实际情况和设计规范来选择高电平的电压值或电压范围，使得当电压为所选择的值，或者在所选择的范围内时，相应的开关元件能够导通或者相应的电路能够工作。
另外，高电平和低电平均可以对应于在某个范围内的不同的电压值。例如，在需要进行区分的情况下，可能使用类似于“第一高电平”、“第二高电平”这样的术语来描述在高电平范围内具有不同的电压值的高电平。在本文中，为了描述上的方便，可能采用“1”来代替高电平，并且采用“0”来代替低电平。
另外，开关元件可以是带有控制端的、能够起到开关作用的任何元件或电路。这样的开关元件例如可以在其控制端的电位为高电平时导通，即其第一端和第二端之间形成通路，使得其第一端和第二端的电位相同或大致相同。在实际的情况下，当开关元件导通时，由于开关元件的导通电阻的作用，其第一端和第二端的电位未必完全相同，而是可能存在一些差异。在本文中，为了描述上的简洁，除非特别指出或者需要考虑导通电阻的影响，否则简单地假设开关元件的第一端和第二端的电位在该开关元件导通时是相同的。
在实际的电路中，这样的开关元件可以根据需要采用薄膜晶体管或场效应块等各种类型的、具有控制端的开关器件，并且可以根据需要采用N沟道型或P沟道型。在本文中，将以采用N沟道型薄膜晶体管的开关元件为例进行描述。在本文的示例中，开关元件的控制端可以对应于晶体管的栅极、第一端和第二端中的一个可以对应于晶体管的源极和漏极中的一个，第一端和第二端中的另一个可以对应于晶体管的源极和漏极中的另一个。在本文中，开关的第一端和第二端是可以互换的。然而，本公开的技术方案不局限于这样的示例。
图1示出根据本公开的实施例的示例性移位寄存器100。移位寄存器100包括输入和复位电路101、第一输出电路102、第二输出电路103、第一下拉电路104、第二下拉电路105和下拉节点选择电路106。如图1所示，移位寄存器100还包括第一下拉节点PD1和第二下拉节点PD2。
该输入和复位电路101与输入端、上拉节点、复位端相连，在整体上被配置为在输入端的电位为工作电位的情况下，将上拉节点的电位设置为工作电位，并且在复位端的电位为工作电位的情况下，将上拉节点的电位设置为复位电位。
具体地，图1所示的输入和复位电路101可以包括输入电路101_1和复位电路101_2，如图2所示。应当了解，图1和图2所示的移位寄存器的区别在于：图1中的输入和复位电路被拆分成如图2所示的输出电路101_1和复位电路101_2。
如图2所示，输入电路101_1与移位寄存器100的输入端IN、第一扫描方向控制端CN和上拉节点PU相连。在经由输入端IN接收到信号时，输入电路101_1可以通过将其内部的开关元件导通，使上拉节点PU与输入端IN和/或第一扫描方向控制端CN连通，从而使上拉节点PU的电位成为工作电位，例如高电平。
输入电路101_1可以通过不同的方式来实现，并且可以根据需要和实现方式，与移位寄存器100的不同端子相连，从而在经由输入端IN接收到输入信号时，将上拉节点PU的电位设置为工作电位。
在一个示例中，输入电路101_1也可以与工作电位端VGH相连，其中，在经由输入端IN接收到信号时，输入电路101_1可以通过将其内部的开关元件导通，使上拉节点PU与工作电位端VGH连通，从而使上拉节点PU的电位成为工作电位。
在另外的示例中，输入电路101_1也可以与一个时钟信号端相连，该时钟信号端在经由输入端IN接收到信号时提供高电平的时钟信号，其中，在经由输入端IN接收到信号时，输入电路101_1可以通过将其内部的开关元件导通，使上拉节点PU与该时钟信号端连通，从而使上拉节点PU的电位成为工作电位。
在一个示例中，输入电路101_1可以包括至少一个开关元件，并且例如可以将该开关元件的控制端与输入端IN相连，将其第一端和第二端中的一 个与上拉节点PU相连，并且根据情况将其第一端和第二端中的另一个与第一扫描方向控制端CN或工作电位端VGH或前述的时钟信号端相连。
在图1所示的示例中，输入电路101_1还与第一下拉节点PD1和参考信号端RS相连。在将上拉节点PU设置为高电平的同时，输入电路101_1可以例如通过导通内部的开关元件，使参考信号端RS和第一下拉节点PD1连通，从而将第一下拉节点PD1设置为低电平。
在另外的示例中，输入电路101_1可以不与第一下拉节点PD1和参考信号端RS相连，或者移位寄存器100可以采用另外的方式来实现类似的功能。例如，可以在移位寄存器100中设置单独的元件、电路和子电路，用以在将上拉节点PU设置为高电平的同时，确保将第一下拉节点PD1设置为低电平。在一个示例中，可以在输入电路101_1的外部设置单独的开关元件，将该开关元件的控制端、第一端分别与上拉节点PU和第一下拉节点PD1相连，并使该开关元件的第二端的电位在移位寄存器100经由输入端IN接收到信号时为低电平。这样，在移位寄存器100经由输入端IN接收到信号时，输入电路101_1工作并使上拉节点PU成为高电平，该开关在上拉节点PU为高电平时导通，使得第一下拉节点PD1的电位为低电平。
在图2所示的示例中，复位电路101_2与移位寄存器100的复位端RESET、第二扫描方向控制端CNB和上拉节点PU相连。在经由复位端RESET接收到信号时，复位电路101_2可以通过将其内部的开关元件导通，使上拉节点PU与复位端RESET和/或第二扫描方向控制端CNB连通，从而使上拉节点PU的电位成为复位电位，例如低电平。
复位电路101_2可以通过不同的方式来实现，并且可以根据需要和实现方式，与移位寄存器100的不同端子相连，从而在经由复位端RESET接收到信号时，将上拉节点PU的电位设置为复位电位。
例如，复位电路101_2可以与参考信号端RS相连，该参考信号端RS的信号可以是直流信号或交流信号，并且在复位阶段，该参考信号端RS的信号为低电位。
具体地，参考信号端RS可以是复位电位端VGL，该复位电位端VGL输出直流低电平信号。在经由复位端RESET接收到信号时，复位电路101_2可以通过将其内部的开关元件导通，使上拉节点PU与复位电位端VGL连通，从而使上拉节点PU的电位成为复位电位。
在另外的示例中，参考信号端RS也可以是一个时钟信号端，该时钟信号端在复位端RESET接收到信号时提供低电平的时钟信号。在经由复位端RESET接收到信号时，复位电路102可以通过将其内部的开关元件导通，使上拉节点PU与该时钟信号端连通，从而使上拉节点PU的电位成为复位电位。
在一个示例中，复位电路101_2可以包括至少一个开关元件，并且例如可以将该开关元件的控制端与复位端RESET相连，将该开关元件的第一端和第二端中的一个与上拉节点PU相连，并且根据情况将该开关元件的第一端和第二端中的另一个与第二扫描方向控制端CNB或参考信号端RS(例如RS为复位电位端VGL或前述的时钟信号端)相连。
在图2所示的示例中，复位电路101_2还与第二下拉节点PD2和参考信号端RS相连。在将上拉节点PU设置为高电平的同时，复位电路102可以例如通过导通其内部的开关元件，使参考信号端RS和第二下拉节点PD2连通，从而将第二下拉节点PD2设置为低电平。
在另外的示例中，复位电路101_2可以不与第二下拉节点PD2和参考信号端RS相连，或者移位寄存器100可以采用另外的方式来实现类似的功能。在一个示例中，可以在移位寄存器100中设置单独的元件、电路和子电路，用以在将上拉节点PU设置为高电平的同时，确保将第二下拉节点PD2设置为低电平。例如，可以在复位电路101_2的外部设置单独的开关元件，将该开关元件的控制端、第一端分别与上拉节点PU和第二下拉节点PD2相连，并使该开关元件的第二端的电位在移位寄存器100经由输入端IN接收到信号时为低电平。这样，在移位寄存器100经由输入端IN接收到信号时，输入电路101_1工作并使上拉节点PU的电路成为高电平，该开关在上拉节点PU为高电平时导通，使得第二下拉节点PD2的电位为低电平。
如图1所示的移位寄存器100可以支持双向扫描。
当第一扫描方向控制端CN为高电平而第二扫描方向控制端CNB为低电平时，移位寄存器100可以工作于正向扫描模式。在正向扫描模式下，当移位寄存器100经由输入端IN接收到信号时，输入电路101_1将上拉节点PU设置为高电平，当移位寄存器100经由复位端RESET接收到信号时，复位电路101_2将上拉节点PU设置为低电平。
当第一扫描方向控制端CN为低电平而第二扫描方向控制端CNB为高电 平时，移位寄存器100可以工作于反向扫描模式。在反向扫描模式下，就工作过程和功能而言，输入电路101_1可以对应于正向扫描模式下的复位电路101_2，复位电路101_2可以对应于正向扫描模式下的输入电路101_1，并且针对所需的时钟信号(如果有)可以做出相应的调整。
在支持双向扫描的情况下，输入电路101_1也可以被称为第一输入电路，而复位电路101_2也可以被称为第二输入电路。
在不需要支持双向扫描功能的情况下，根据本公开的实施例的移位寄存器中的输入电路和复位电路可以采用与图1所示的移位寄存器100中的输入电路和复位电路不同的设置方式。
例如，在不需要支持双向扫描功能的情况下，移位寄存器100可以不设置第一扫描方向控制端CN和第二扫描方向控制端CNB，相应地，输入电路101_1和复位电路101_2可以不与第一扫描方向控制端CN和第二扫描方向控制端CNB相连，而是可以采用例如前文所述的其他实现方式。
另外，在不需要支持双向扫描功能的情况下，如图3所示，复位电路101_2还可以与移位寄存器的输出端(例如图1或图2中的第一输出端OUT1和/或第二输出端OUT2)相连，并且在经由复位端RESET接收到信号时还将移位寄存器的输出端设置为低电平。例如，在一个示例中，复位电路101_2可以包括另外的开关元件，并将该开关元件的控制端、第一端和第二端分别与移位寄存器的复位端RESET、输出端和参考信号端RS相连。
在移位寄存器100中，第一输出电路102与上拉节点PU、第一时钟信号端CK1和第一输出端OUT1相连。当移位寄存器100经由输入端IN接收到信号时，上拉节点PU的电位在输入电路101_1的控制下成为高电平，第一输出电路102开始工作，将上拉节点PU的电位保持(或寄存)在高电平状态，但是不在第一输出端OUT1处输出栅极驱动信号。随后，当移位寄存器100经由第一时钟信号端CK1接收到第一时钟信号时，第一输出电路102在第一输出端OUT1处输出栅极驱动信号，从而完成移位输出。
在一个示例中，第一输出电路102可以包括电容器和至少一个开关元件，其中，例如，可以将电容器设置在上拉节点PU和第一输出端OUT1之间，将开关元件的控制端、第一端和第二端分别与上拉节点PU、第一时钟信号端CK1和第一输出端OUT1相连，并且使第一时钟信号端CK1在移位寄存器100接收到输入信号时为低电平。
当移位寄存器100经由输入端IN接收到输入信号时，上拉节点PU的电位在输入电路101_1的控制下成为高电平，第一输出电路102中的电容器开始充电。然而，由于第一时钟信号端CK1此时为低电平，所以开关元件的第一端和第二端在导通后的电位均为低电平状态，从而在第一输出端OUT1处无栅极驱动信号输出。随后，上拉节点PU的电位通过第一输出电路102中的电容器的自举作用而保持为高电平状态，甚至可能会被进一步地拉高，并保持第一输出电路102中的开关元件处于导通状态。然后，当移位寄存器100接收到第一时钟信号(或者第一时钟信号端CK1为高电平)时，第一输出电路102中的开关元件的第一端和第二端的电位均成为高电平，从而在第一输出端OUT1处输出栅极驱动信号。
在另外的示例中，第一输出电路102也可以不包括电容器。
在移位寄存器100中，第二输出电路103与上拉节点PU、第二时钟信号端CK2和第二输出端OUT2相连。第二输出电路103内部的电路结构可以与第一输出电路102相同，也可以不同。
第二输出电路103的工作原理以及其与移位寄存器100中的其他节点、电路或元件的连接方式与第一输出电路102类似，不同之处在于第二输出电路103根据经由第二时钟信号端CK2所接收到的第二时钟信号在第二输出端OUT2输出栅极驱动信号。
在一个示例中，可以将第二时钟信号设置为晚于第一时钟信号(例如，可以使第二时钟信号的高电平的上升沿与第一时钟信号的高电平的下降沿对齐)，使得移位寄存器100能够先后通过第一输出端OUT1和第二输出端OUT2相继地输出多个栅极驱动信号。
虽然图1或图2仅示出两个输出电路102和103，但是在需要支持多输出的情况下，根据本公开的实施例的移位寄存器可以包括三个或更多的输出电路，并且这些更多的输出电路可以采用与第一输出电路102和第二输出电路103类似的电路结构和连接方式，并且可以参考第一时钟信号端CK1和第二时钟信号端CK2以及第一时钟信号和第二时钟信号之间的关系，针对更多的输出电路设置更多的时钟端，并确定分别经由这些更多的时钟端所接收的时钟信号之间的关系。
在移位寄存器100中，设置两个下拉节点PD1和PD2，并且包括第一下拉电路104和第二下拉电路105，其中，第一下拉电路104与第一下拉节点 PD1、上拉节点PU、第一输出端OUT1、第二输出端OUT2和参考信号端RS相连，并且第二下拉电路105与第二下拉节点PD2、上拉节点PU、第一输出端OUT1、第二输出端OUT2和参考信号端RS相连。
第一下拉电路104在第一下拉节点PD1的电位为高电平时工作，其内部的开关元件导通，分别将上拉节点PU、第一输出端OUT1、第二输出端OUT2与参考信号端RS连通，使得上拉节点PU、第一输出端OUT1和第二输出端OUT2的电位均成为低电平。第二下拉电路105在第二下拉节点PD2的电位为高电平时工作，其内部的开关元件导通，分别将上拉节点PU、第一输出端OUT1、第二输出端OUT2与参考信号端RS连通，使得上拉节点PU、第一输出端OUT1和第二输出端OUT2的电位均成为低电平。
在一个示例中，第一下拉电路104可以包括至少三个开关元件，其中，将这三个开关元件中的每一个的控制端与第一下拉节点PD1相连，将这三个开关元件中的每一个的第一端与复位信号端RS相连，并将这三个开关元件的第二端分别与上拉节点PU、第一输出端OUT1、第二输出端OUT2相连。第二下拉电路105可以采用类似的电路结构，不同之处在于第二下拉电路105中的开关元件的控制端与第二下拉节点PD2相连。
在一个示例中，可以同时使用多个下拉节点。例如，可以使图1或图2中的两个下拉节点PD1和PD2同时处于高电平或低电平状态，从而使得两个下拉电路104和105同时工作或不工作。由此，可以提高对上拉节点PU、第一输出端OUT1和第二输出端OUT2的电位的下拉能力。
在另外的示例中，可以交替地使用多个下拉节点。例如，可以使用一帧为单位交替地使用多个下拉节点。在一个示例中，可以在第一帧期间内，使第二下拉节点PD2的电位始终为低电平，从而使得在该帧的期间内，仅第一下拉电路104能够工作，而第二下拉电路105始终不工作；在随后的第二帧期间内，使第一下拉节点PD1的电位始终为低电平，从而使得在该帧的期间内，仅第二下拉电路105能够工作，而第一下拉电路104始终不工作。也可以使用多个帧为单位来交替地使用多个下拉节点以及对应的多个下拉电路。例如，可以在第一帧和第二帧期间内，使第二下拉节点PD2的电位始终为低电平，从而使得在第一帧和第二帧期间内，仅第一下拉电路104能够工作，而第二下拉电路105始终不工作；在随后的第三帧和第四帧期间内，使第一下拉节点PD1的电位始终为低电平，从而使得在第三帧和第四帧期间内，仅 第二下拉电路105能够工作，而第一下拉电路104始终不工作。交替地使用多个下拉节点以及对应的下拉电路，有利于提高电路的可靠性。
虽然图1仅示出两个下拉节点和两个下拉电路，但是根据本公开的实施例的移位寄存器可以包括三个或更多的下拉节点和相应的下拉电路。
在设置有多个下拉节点的情况下，如图1所示，可以在移位寄存器100中设置下拉节点选择电路106，并通过该下拉节点选择电路106来选择要使用的下拉节点，并控制所选择的下拉节点的电位。应当了解，由于根据本发明的实施例的移位寄存器可以具有多个下拉节点，并且可以选择使用该多个下拉节点中的一个或几个，由于被选择使用的下拉节点的电位可以被控制而改变，因此，在本文中，“下拉节点”也可以被称为“活跃下拉节点”。
在移位寄存器100中，下拉节点选择电路106与第一下拉节点选择信号端PDS1、第二下拉节点选择信号端PDS2、第一下拉节点PD1、第二下拉节点PD2、下拉选择控制信号端CK3和参考信号端RS相连。
下拉节点选择电路106可以被配置为在经由第一下拉节点选择信号端PDS1接收到信号时，使其内部连接第二下拉节点PD2和参考信号端RS的开关元件导通，使得在第一下拉节点选择信号端PDS1的电位为高电平期间内，第二下拉节点PD2的电位始终为低电平，并且在经由第二下拉节点选择信号端PDS2接收到信号时，使其内部连接第一下拉节点PD1和参考信号端RS的开关元件导通，使得在第二下拉节点选择信号端PDS2的电位为高电平期间内，第一下拉节点PD1的电位始终为低电平。
另外，在移位寄存器100包括三个或更多的下拉节点的情况下，可以针对移位寄存器100设置更多的下拉节点选择信号端，并将下拉节点选择电路106与这些下拉节点选择信号端和所有的下拉节点相连。
在一个示例中，可以在以一个或多个帧为单位所确定的一个时间段内，将多个下拉节点选择信号端(包括第一下拉节点选择信号端PDS1和第二下拉节点选择信号端PDS2)中的一个下拉节点选择信号端的电位设置为高电平，并且通过下拉节点选择电路106将与该下拉节点选择信号端相对应的下拉节点选择为活跃下拉节点，同时保持其他非活跃下拉节点的电位为低电平。
在一个示例中，经由下拉选择控制信号端CK3所接收的第三时钟信号可以设置晚于经由第二时钟信号端CK2所接收的第二时钟信号(例如，可以使第三时钟信号的高电平的上升沿与第二时钟信号的高电平的下降沿对齐，并 且使第一时钟信号和第二时钟信号在第三时钟信号为高电平时均处于低电平状态)，以确保第一下拉电路104和第二下拉电路105在第一输出电路102和第二输出电路103两者均完成输出操作之后才开始工作。在包含更多的输出电路的情况下，可以将第三时钟信号设置为晚于用于所有输出电路中最后完成输出的输出电路的时钟信号。例如，可以使第三时钟信号的高电平的上升沿与用于所有输出电路中最后完成输出的输出电路的时钟信号的高电平的下降沿对齐，并且使用于所有输出电路的时钟信号在第三时钟信号为高电平时均处于低电平状态，以确保所有下拉电路在所有输出电路均完成输出操作之后才开始工作。
图4示出移位寄存器100的一种示例性的电路结构。如图4所示，在移位寄存器100中，输入电路101_1可以包括第一输入开关元件SW1和第一下拉节点复位开关元件SW2，其中，第一输入开关元件SW1的控制端、第一端和第二端分别与移位寄存器的输入端IN、第一扫描方向控制端CN和上拉节点PU0相连，第一下拉节点复位开关元件SW2的控制端、第一端和第二端分别与上拉节点PU0、第一下拉节点PD1和参考信号端RS相连。
复位电路101_2可以包括第二输入开关元件SW8和第二下拉节点复位开关元件SW3，其中，第二输入开关元件SW8的控制端、第一端和第二端分别与移位寄存器的复位端RESET、第二扫描方向控制端CNB和上拉节点PU0相连，第二下拉节点复位开关元件SW3的控制端、第一端和第二端分别与上拉节点PU0、第二下拉节点PD2和参考信号端RS相连。
第一输出电路102可以包括第二输出开关元件SW4、第一输出开关元件SW5和第一输出电容器C1，其中，第二输出开关元件SW4的控制端、第一端和第二端分别与节点PU1、第一时钟信号端CK1和第一输出端OUT1相连，第一输出电容器C1的两端分别与节点PU1和第一输出端OUT1相连，第一输出开关元件SW5的控制端、第一端和第二端分别与工作电位端VGH、上拉节点PU0和节点PU1相连。
第二输出电路103可以包括第四输出开关元件SW6、第三输出开关元件SW7和第二输出电容器C2，其中，第四输出开关元件SW6的控制端、第一端和第二端分别与节点PU2、第二时钟信号端CK2和第二输出端OUT2相连，第二输出电容器C2的两端分别与节点PU2和第二输出端OUT2相连，第三输出开关元件SW7的控制端、第一端和第二端分别与工作电位端VGH、上 拉节点PU0和节点PU2相连。
在第一输出电路102和第二输出电路103中，第一输出开关元件SW5和第三输出开关元件SW7的控制端与工作电位端VGH相连，第一输出开关元件SW5和第三输出开关元件SW7始终处于导通状态，使得第一输出电路103中的节点PU1和第二输出电路104中的节点PU2的电位始终与上拉节点PU0的电位相同。另外，第一输出开关元件SW5和第三输出开关元件SW7是可选的，在不设置第一输出开关元件SW5和第三输出开关元件SW7的情况下，节点PU1与节点PU0(或图1中的上拉节点PU)为同一点。由于节点PU0、PU1和PU2的电位始终相同，所以可以将节点PU0、PU1和PU2视为移位寄存器100的上拉节点PU在移位寄存器电路中的不同位置处的反映。实际上，在图4所示的电路中，在任何时刻均与节点PU0和/或PU1和/或PU2具有相同电位的节点均可被视为上拉节点PU，在下文中简单地使用“上拉节点PU”来代表这些节点。
第一下拉电路103可以包括第一下拉开关元件SW14、第二下拉开关元件SW15和第三下拉开关元件SW16，其中，第一下拉开关元件SW14、第二下拉开关元件SW15和第三下拉开关元件SW16的控制端均与第一下拉节点PD1相连，第一下拉开关元件SW14、第二下拉开关元件SW15和第三下拉开关元件SW16的第一端均与参考信号端RS相连，第一下拉开关元件SW14、第二下拉开关元件SW15和第三下拉开关元件SW16的第二端分别与节点PU0(或上拉节点PU)、第一输出端OUT1和第二输出端OUT2相连。
第二下拉电路104可以包括第四下拉开关元件SW17、第六下拉开关元件SW18和第五下拉开关元件SW19，其中，第四下拉开关元件SW17、第六下拉开关元件SW18和第五下拉开关元件SW19的控制端均与第二下拉节点PD2相连，第四下拉开关元件SW17、第六下拉开关元件SW18和第五下拉开关元件SW19的第一端均与参考信号端RS相连，第四下拉开关元件SW17、第六下拉开关元件SW18和第五下拉开关元件SW19的第二端分别与节点PU0(或上拉节点PU)、第二输出端OUT2和第一输出端OUT1相连。
下拉节点选择电路106可以包括选择控制开关元件SW9、第一下拉选择开关元件SW10、第二下拉选择开关元件SW11、第三下拉选择开关元件SW12、第四下拉选择开关元件SW13和第一电容器C3、第二电容器C4，其中，选择控制开关元件SW9的控制端和第一端均连接到移位寄存器的下拉 选择控制信号端CK3，选择控制开关元件SW9的第二端与第一下拉选择开关元件SW10的第一端和第三下拉选择开关元件SW12的第一端相连，第一下拉选择开关元件SW10的控制端和第二端分别与第一下拉节点选择信号端PDS1和第一下拉节点PD1相连，第三下拉选择开关元件SW12的控制端和第二端分别与第二下拉节点选择信号端PDS2和第二下拉节点PD2相连，第二下拉选择开关元件SW11的控制端、第一端和第二端分别与第一下拉节点选择信号端PDS1、第二下拉节点PD2和参考信号端RS相连，第四下拉选择开关元件SW13的控制端、第一端和第二端分别与第二下拉节点选择信号端PDS2、第一下拉节点PD1和参考信号端RS相连，第一电容器C3设置在第一下拉节点PD1和参考信号端RS之间，第二电容器C4设置在第二下拉节点PD2和参考信号端RS之间。
图4所示的结构仅是示例性的，根据本公开的实施例的移位寄存器100可以采用其他的实现方式。例如，在不需要支持双向扫描功能的情况下，在复位电路101_2中，开关元件SW8可以与参考信号端RS而不是第二扫描信号端CNB相连，并且还可以包括另外的开关元件，例如可以使该另外的开关元件的控制端、第一端和第二端分别与复位端RESET、第一输出端OUT1(和/或第二输出端OUT2)和参考信号端RS相连。在另外的示例中，可以设置更多的下拉节点，并且相应地设置更多的下拉电路。在另外的示例中，可以设置更多的输出端，并且相应地设置更多的输出电路。本公开不局限于图4所示的示例性的电路结构。
图5示出采用图1、图2或图4所示的移位寄存器100在正向扫描模式(第一扫描方向控制端CN为高电平，第二扫描方向控制端CNB为低电平)下的相继的两个帧(第i帧和第i+1帧)期间的工作时序。
在第i帧期间，第一下拉节点选择信号端PDS1为高电平，第二下拉节点选择信号端PDS2为低电平。在下拉节点选择电路106中，第一下拉选择开关元件SW10和第二下拉选择开关元件SW11导通，而第三下拉选择开关元件SW12和第四下拉选择开关元件SW13截止，从而选择第一下拉节点PD1作为活路下拉节点，并使得第二下拉节点PD2始终为低电平。相应地，在第i帧期间，控制端与第二下拉节点PD2相连的第二下拉电路105中的第四下拉选择开关元件SW17、第五下拉选择开关元件SW19和第六下拉选择开关元件SW18均截止，使得第二下拉电路105在第i帧期间不工作。
当移位寄存器100经由输入端IN接收到输入信号时，输入电路101_1中的第一输入开关元件SW1和第一下拉节点复位开关元件SW2导通，使得上拉节点PU的电位成为高电平，第一下拉节点PD1的电位成为低电平。第一输出电路102和第二输出电路103中的第一输出电容器C1和第二输出电容器C2开始充电，并且第二输出开关元件SW4和第四输出开关元件SW6导通。此时，第一时钟信号端CK1和第二时钟信号端CK2的电位均为低电平，因此在第一输出端OUT1和第二输出端OUT2均无栅极驱动信号输出。
随后，输入端IN的电位成为低电平。上拉节点PU的电位通过第一输出电容器C1和第二输出电容器C2继续保持为高电平状态，使得第一输出电路102中的第二输出开关元件SW4和第二输出电路103中的第四输出开关元件SW6仍处于导通状态。此时，第一时钟信号端CK1的电位成为高电平，使得第一输出端OUT1的电位成为高电平，从而在第一输出端OUT1输出栅极驱动信号，而第二时钟信号端CK2仍为低电平，因此在第二输出端OUT2仍无栅极驱动信号输出。随后，第一时钟信号端CK1的电位成为低电平，而第二时钟信号端CK2的电位成为高电平，使得第一输出端OUT1的电位成为低电平，而第二输出端OUT2的电位成为高电平，从而在第二输出端OUT2输出栅极驱动信号。
在第一输出电路102和第二输出电路103分别通过第一输出端OUT1和第二输出端OUT2相继地输出栅极驱动信号之后，移位寄存器100的复位端RESET的电位成为高电平，使得复位电路101_2中第二输入开关元件SW8导通，从而使上拉节点PU的电位成为低电平。与此同时，下拉选择控制信号端CK3的电位成为高电平，下拉节点选择电路106中的选择控制开关元件SW9导通，使得第一下拉节点PD1成为高电平，并且下拉节点选择电路106中的第一电容器C3开始充电。当第一下拉节点PD1成为高电平时，第一下拉电路104中的第一下拉开关元件SW14、第二下拉开关元件SW15和第三下拉开关元件SW16导通，使得上拉节点PU、第一输出端OUT1和第二输出端OUT2的电位成为低电平。
随后，当下拉选择控制信号端CK3的电位成为低电平时，第一下拉节点PD1的电位通过下拉节点选择电路106中的第一电容器C3而继续保持在高电平状态，当下拉选择控制信号端CK3的电位再次成为高电平时，第一上拉节点PD1的电位为高电平，并且下拉节点选择电路106中的第一电容器C3 再次开始充电。如此反复，使得第一下拉节点PD1的电位一直处于高电平状态。
在第i帧之后的第i+1帧期间，第一下拉节点选择信号端PDS1为低电平，第二下拉节点选择信号端PDS2为高电平。在下拉节点选择电路106中，第一下拉选择开关元件SW10和第二下拉选择开关元件SW11截止，而第三下拉选择开关元件SW12和第四下拉选择开关元件SW13导通，从而选择第二下拉节点PD2作为活跃下拉节点，并使得第一下拉节点PD1始终为低电平。相应地，在第i+1帧期间，控制端与第一下拉节点PD1相连的第一下拉电路104中的第一下拉开关元件SW14、第二下拉开关元件SW15和第三下拉开关元件SW16均截止，使得第一下拉电路104在第i+1帧期间不工作。
在第i+1帧期间，移位寄存器的工作时序与第i帧期间的工作时序相似，相同之处不再重复。不同之于在于，当下拉选择控制信号端CK3的电位成为高电平时，下拉节点选择电路106中的选择控制开关元件SW9导通，第二下拉节点PD2成为高电平，并且下拉节点选择电路106中的第二电容器C4开始充电。当第二下拉节点PD2成为高电平时，第二下拉电路105中的第四下拉开关元件SW17、第六下拉开关元件SW18和第五下拉开关元件SW19导通，使得上拉节点PU、第二输出端OUT2和第一输出端OUT1的电位成为低电平。
随后，当下拉选择控制信号端CK3的电位成为低电平时，第二下拉节点PD2的电位通过下拉节点选择电路106中的第二电容器C4而继续保持在高电平状态，当下拉选择控制信号端CK3的电位再次成为高电平时，第二上拉节点PD2的电位为高电平，并且下拉节点选择电路106中的第二电容器C4再次开始充电。如此反复，使得第二下拉节点PD2的电位一直处于高电平状态。
通过定期地改变第一下拉节点选择信号端PDS1和第二下拉节点选择信号端PDS2的电位，能够交替地使用移位寄存器内的两个下拉节点和两个下拉电路，从而有利于提高电路的可靠性。
在反向扫描模式下，移位寄存器的第一扫描方向控制端CN为低电平，而第二扫描方向控制端CNB为高电平。此时，复位电路101_2相当于正向扫描的情况下的输入电路101_1，输入电路101_1相当于正向扫描的情况下的复位电路101_2。移位寄存器在反向扫描模式下的工作时序与其在正向扫 描模式下的工作时序类似，在本文中省略相关描述。
图5仅示出了以一个帧为单位交替地使用两个下拉节点的情况。如前文所述，还可以根据需要以多个帧为单位交替地使用两个下拉节点(例如，可以在相邻的两帧和两帧之间交替使用两个下拉节点，或者也可以在相邻的一帧和三帧之间交替使用两个下拉节点，等等)，或者设置更多的下拉节点，并且以预先设置的一个或多个帧为单位依次使用这些下拉节点。这些变型的移位寄存器的工作时序与图5所示的情况类似，不同之处于下拉节点的切换的周期和/或下拉节点的数量，在本文中省略相关描述。
在图5所示的示例中，每个时钟信号的占空比可以为1/3。在考虑多个移位寄存器一起工作(例如，在下文中参照图7描述的栅极驱动电路)的情况下，或者在考虑支持更多的输出端/输出电路的情况下，每个时钟信号的占空比可以根据需要设置为更小，例如1/4。例如，在使多个移位寄存器100(包括两个输出端OUT1和OUT2)一起工作的情况下，可以将每个时钟信号的占空比设置为1/4。在考虑使每个移位寄存器支持三个输出的情况下，可以将每个时钟信号的占空比设置为1/5，以此类推。
图6示出用于驱动根据本公开的实施例的移位寄存器的方法。
该示例性方法开始于步骤601。在步骤601中，移位寄存器将第一下拉节点和第二下拉节点中的一个选择为活跃下拉节点，并将另一个的电位设置为复位电位。例如，对于图1、图2或图4所示的示例性移位寄存器100，可以向该移位寄存器100的第一下拉节点选择信号端PDS1和第二下拉节点选择信号端PDS2提供相应的信号。下拉节点选择电路106根据第一下拉节点选择信号端PDS1和第二下拉节点选择信号端PDS2的电位，将第一下拉节点PD1和第二下拉节点PD2中的一个设置为活跃下拉节点，并将另一个的电位设置为始终保持在低电平状态。如前文所述，可以按照预先设定的数量的帧，交替使用第一下拉节点PD1和第二下拉节点PD2作为活跃下拉节点。
在步骤605中，移位寄存器接收输入信号，并将上拉节点的电位设置为工作电位。例如，对于图1、图2或图4所示的示例性移位寄存器100，移位寄存器100可以在经由输入端IN接收到输入信号时，将上拉节点PU(包括节点PU0、PU1和PU2)的电位设置为高电平。此时，第一输出端OUT1和第二输出端OUT2均无栅极驱动信号输出。
然后，响应于接收到第一时钟信号，方法继续到步骤610。在步骤610 中，移位寄存器响应于接收到第一时钟信号，在第一输出端输出第一栅极驱动信号。例如，对于图1、图2或图4所示的示例性移位寄存器100，移位寄存器100可以在经由第一时钟信号端CK1端接收到第一时钟信号时，在第一输出端OUT1输出栅极驱动信号。此时，上拉节点PU(包括节点PU0、PU1和PU2)的电位可以通过第一输出电路102和第二输出电路103中的电容而保持在高电平状态，并且在第二输出端OUT2无栅极驱动信号输出。
然后，响应于在第一时钟信号之后所接收的第二时钟信号，方法继续到步骤615。在步骤615中，移位寄存器响应于在第一时钟信号之后所接收的第二时钟信号，在第二输出端输出第二栅极驱动信号。例如，对于图1、图2或图4所示的示例性移位寄存器100，移位寄存器100可以在经由第二时钟信号端CK2端接收到第二时钟信号时，在第二输出端OUT2输出栅极驱动信号。此时，上拉节点PU(包括节点PU0、PU1和PU2)的电位仍然通过第一输出电路102和第二输出电路103中的电容器而保持在高电平状态，并且在第一输出端OUT1无栅极驱动信号输出。
然后，响应于在第二时钟信号之后所接收的参考信号，方法继续到步骤620。在步骤620中，移位寄存器响应于在第二时钟信号之后所接收的参考信号，将活跃下拉节点的电位设置为工作电位。例如，对于图1、图2或图4所示的示例性移位寄存器100，移位寄存器100可以在经由复位端RESET接收到参考信号时，使上拉节点PU(包括节点PU0、PU1和PU2)成为低电平。同时，移位寄存器100中的下拉节点选择电路106可以响应于移位寄存器100经由下拉选择控制信号端CK3接收到第三时钟信号，将被选择为活跃下拉节点的第一下拉节点PD1或第二下拉节点PD2的电位设置为高电平。
然后，在步骤625中，移位寄存器将上拉节点、第一输出端和第二输出端的电位设置为复位电位。例如，对于图1、图2或图4所示的示例性移位寄存器100，当活跃下拉节点(第一下拉节点PD1或第二下拉节点PD2)的电位被设置为高电平时，与活跃下拉节点相对应的下拉电路(第一下拉电路104或第二下拉电路105)开始工作，并将上拉节点PU(包括节点PU0、PU1和PU2)、第一输出端OUT1和第二输出端OUT2的电位设置为低电平。当移位寄存器100经由下拉选择控制信号端CK3接收到第三时钟信号时，下拉节点选择电路106中的电容器在活跃下拉节点的电位被设置为高电平的同时被充电，当移位寄存器100的下拉选择控制信号端CK3的电位为低电平时， 活跃下拉节点的电位通过下拉节点选择电路106中的电容器而继续保持在高电平状态，使得活跃下拉节点相对应的下拉电路(第一下拉电路104或第二下拉电路105)仍处于工作状态，从而使上拉节点PU(包括节点PU0、PU1和PU2)、第一输出端OUT1和第二输出端OUT2的电位继续保持在低电平状态。
图7示出包括根据本公开的实施例的移位寄存器的栅极驱动电路的一种示例性的连接方式。移位寄存器的参考信号端RS、工作电位端VGH、第一扫描方向控制端CN、第二扫描方向控制端CNB、第一下拉节点选择信号端PDS1和第二下拉节点选择信号端PDS2等端子主要用于接收外部控制信号，因此在用于例示移位寄存器的级联方式的图7中没有示出移位寄存器的这些端子。另外，在图7所示的示例中，每个移位寄存器为图1、图2或图4所示的示例性移位寄存器100。然而，如前文所述，根据本公开的实施例的移位寄存器可以具有其他变型，例如可以具有更多的输出端以及时钟信号端，并且可以根据前面所述的各时钟信号之间的关系来设置这些时钟信号。
如图7所示，在根据本公开的实施例的栅极驱动电路中，第一级移位寄存器SR1的输入端IN接收帧起始信号STV。第一级之外的各级移位寄存器(例如，图7中的SR2、SR3、SR4、SR5)的输入端IN分别与对应的上一级移位寄存器(例如，图7中的SR1、SR2、SR3、SR4)的第二输出端OUT2相连，即第一级之外的各级移位寄存器接收来自对应的上一级移位寄存器的第二输出端OUT2的栅极驱动信号，作为其输入信号。最后一级之外的各级移位寄存器(例如，图7中的SR1、SR2、SR3和SR4)的复位端RESET分别与对应的下一级移位寄存器(例如，图7中的SR2、SR3、SR4和SR5)的第一输出端OUT1相连，即最后一级之外的各级移位寄存器接收来自对应的下一级移位寄存器的第一输出端OUT1的栅极驱动信号，作为其参考信号。最后一组的移位寄存器(图7中未示出)的复位端RESET例如可以接收反向扫描时的帧起始信号STV(图7中未示出)。
另外，如图7所示，可以通过时序控制电路向栅极驱动电路的各级移位寄存器提供时钟信号。在通过如图1、图2或图4所示的示例性的移位寄存器100形成栅极驱动电路的情况下，可以通过与时序控制电路701相连的四条时钟信号线(CLOCK1、CLOCK2、CLOCK3和CLOCK4)向各级移位寄存器的第一时钟信号端CK1、第二时钟信号端CK2和下拉节点选择信号端 CK3提供时钟信号。
例如，可以将每个时钟信号的占空比设置为1/4，并且使经由CLOCK1所提供的时钟信号的高电平的下降沿与经由CLOCK2所提供的时钟信号的高电平的上升沿对齐，使经由CLOCK2所提供的时钟信号的高电平的下降沿与经由CLOCK3所提供的时钟信号的高电平的上升沿对齐，使经由CLOCK3所提供的时钟信号的高电平的下降沿与经由CLOCK4所提供的时钟信号的高电平的上升沿对齐，并且使经由CLOCK4所提供的时钟信号的高电平的下降沿与经由CLOCK1所提供的时钟信号的高电平的上升沿对齐。
可以将级联在奇数级的移位寄存器的第一时钟信号端CK1、第二时钟信号端CK2和下拉节点选择信号端CK3分别与时钟信号线CLOCK1、CLOCK2和CLOCK3相连，将级联在偶数级的移位寄存器的第一时钟信号端CK1、第二时钟信号端CK2和下拉节点选择信号端CK3分别与时钟信号线CLOCK3、CLOCK4和CLOCK1相连。通过如图7所示的配置方式向栅极驱动电路的各级移位寄存器提供时钟信号，可以实现单边栅极驱动电路的逐行扫描输出。
图8示意性地示出了如图7所示的栅极驱动电路在相邻两帧(第i帧和第i+1帧)期间的工作时序图。在图8中，CLOCK1至CLOCK4是占空比为1/4的时钟信号，并且如前所述，CLOCK1所提供的时钟信号的高电平的下降沿与CLOCK2所提供的时钟信号的高电平的上升沿对齐，CLOCK2所提供的时钟信号的高电平的下降沿与CLOCK3所提供的时钟信号的高电平的上升沿对齐，CLOCK3所提供的时钟信号的高电平的下降沿与CLOCK4所提供的时钟信号的高电平的上升沿对齐，并且CLOCK4所提供的时钟信号的高电平的下降沿与CLOCK1所提供的时钟信号的高电平的上升沿对齐。
在第i帧内，PSD1为高电平，使得第一下拉节点PD1被选择为活跃下拉节点，而第二下拉节点PD2的电位被设置为复位电位，并且PD1节点的电位可以在下拉节点选择信号端CK3为高电平时被设置为工作电位。而在第i+1帧内，PSD2为高电平，使得第二下拉节点PD2被选择为活跃下拉节点，而第一下拉节点PD1的电位被设置为复位电位，并且PD2节点的电位可以在下拉节点选择信号端CK3为高电平时被设置为工作电位。
按照如图7所示的时钟信号的配置方式，该栅极驱动电路可以实现如图8所示中SR1OUT1-SR4OUT2的8路逐行扫描输出。
图9示出包括根据本公开的实施例的移位寄存器的栅极驱动电路的另一种示例性的连接方式。具体地，图9示出了以每级移位寄存器具有两个输出端OUT1和OUT2为例的用于双边栅极驱动电路的逐行扫描输出的时钟信号的配置方式。如图9所示，该双边栅极驱动电路包括第一栅极驱动电路和第二栅极驱动电路，每个栅极驱动电路包括多个移位寄存器。图9仅示意性地示出了每个栅极驱动电路各包括4个移位寄存器(SR1-1、SR1-2、SR1-3、SR1-4和SR2-1、SR2-2、SR2-3、SR2-4)，而实际应用中可以包括更多个移位寄存器。
图9所示的双边栅极驱动电路中各级移位寄存器的连接如下：
第一栅极驱动电路的第一级移位寄存器的输入端连接帧起始信号，第一栅极驱动电路的第一级移位寄存器的复位端连接第二栅极驱动电路的第一级移位寄存器的第一输出端OUT1；
第一栅极驱动电路的第i级移位寄存器的输入端连接第二栅极驱动电路的第i-1级移位寄存器的第二输出端OUT2，第一栅极驱动电路的第i级移位寄存器的复位端连接第二栅极驱动电路的第i级移位寄存器的第一输出端OUT1，其中1<i≤N；
第二栅极驱动电路的第j级移位寄存器的输入端连接第一栅极驱动电路的第j级移位寄存器的第二输出端OUT2，第二栅极驱动电路的第j级移位寄存器的复位端连接第一栅极驱动电路的第j+1级移位寄存器的第一输出端OUT1，其中，1≤j<N。
具体地，如图9所示，SR1-1的输入端IN与帧起始信号STV相连，SR1-1的第二输出端OUT2与SR2-1的输入端IN相连，SR1-1的复位端RESET与SR2-1的第一输出端OUT1相连，SR1-2的输入端与SR2-1的第二输出端OUT相连，SR2-1的复位端RESET与SR1-2的第一输出端OUT1相连，以此类推。
在时钟信号的配置方面，第一栅极驱动电路的各级移位寄存器的第一时钟信号端CK1、第二时钟信号端CK2和下拉选择信号端CK3分别与由时序控制电路901提供的时钟信号线CLOCK1、CLOCK2和CLOCK3相连，而第二栅极驱动电路的各级移位寄存器的第一时钟信号端CK1、第二时钟信号端CK2和下拉选择信号端CK3分别与由时序控制电路902提供的时钟信号线CLOCK7、CLOCK8和CLOCK5相连。
应当了解，可以使用如图9所示的两个时序控制电路901和902分别输 出4路时钟信号(CLOCK1-CLOCK8)来控制各自的栅极驱动电路，也可以使用同一时序控制电路输出4路时钟信号来控制栅极驱动电路。具体地，在使用同一时序控制电路输出4路时钟信号时，图9所示的时钟信号线CLOCK7对应于CLOCK3，时钟信号线CLOCK8对应于CLOCK4，时钟信号线CLOCK5对应于CLOCK1。
通过如图9所示的栅极驱动电路的各级移位寄存器的连接方式以及提供给各级移位寄存器的时钟信号的配置方式，该栅极驱动电路可以实现双边扫描输出。
图7或图9所示的栅极驱动电路中的每一级移位寄存器的工作过程与图5所示的示例性移位寄存器100的工作过程相似，不同之处在于，图5中的每个时钟信号的占空比为1/3，而图7或图9中的每一级移位寄存器所接收的时钟信号的占空比为1/4。
例如，在栅极驱动电路中的每一级移位寄存器支持n(n为正整数)个输出并相应地包括n+1个时钟信号端的情况下，可以通过时序控制电路向栅极驱动电路提供2*n个时钟信号，其中每个时钟信号的占空比可以设置为等于或小于1/(2n)，并且按照与图7或图9类似的方式将这些时钟信号分别提供给每一级移位寄存器的n+1个时钟信号端。
图10示出根据本公开的实施例的显示装置，其包括两个栅极驱动电路：第一栅极驱动电路1001和第二栅极驱动电路1002。在图10中未示出栅极驱动电路内部的级联结构，而仅是示例性地示出其中的若干移位寄存器SR1-SR3。例如，图10所示的显示装置中的两个栅极驱动电路的各级移位寄存器的连接方式可以是图9所示出的方式。
如图10所示，在该示例性的显示装置的显示区域1005中，针对每对相交的数据信号线(也称为数据线，与数据信号提供电路1003相连)和扫描信号线(也称为栅线，与第一栅极驱动电路1001和第二栅极驱动电路1002相连)，设置一个像素P，并且时序控制器1004向数据信号提供电路1003和两个栅极驱动电路1001、1002提供时钟信号。
在从上到下对扫描信号线依次进行编号(例如，图10中的扫描线1、扫描线2、扫描线3等)的情况下，在第一栅极驱动电路1001中，级联在第i级(i为正整数)的移位寄存器的第一输出端OUT1和第二输出端OUT2分别连接到第4i-3条和第4i-2条扫描信号线，在第二栅极驱动电路1002中， 级联在第j级(j为正整数)的移位寄存器的第一输出端OUT1和第二输出端OUT2分别连接到第4j-1条和第4j条扫描信号线。例如，在图10所示的示例中，第一栅极驱动电路1001中的第1级移位寄存器SR1的第一输出端OUT1和第二输出端OUT2分别连接到扫描信号线1和扫描信号线2，而第二栅极驱动电路1002中的第1级移位寄存器SR1的第一输出端OUT1和第二输出端OUT2分别连接到扫描信号线3和扫描信号线4，以此类推。
例如，在第一栅极驱动电路1001和第二栅极驱动电路1002中的每个移位寄存器包括三个输出端的情况下，可以按照与图10所示相类似的方式，使第一栅极驱动电路1001中的第1级移位寄存器的三个输出端分别与第1至第3条扫描信号线相连，使第二栅极驱动电路1002中的第1级移位寄存器的三个输出端分别与第4至第6条扫描信号线相连，使第一栅极驱动电路1001中的第2级移位寄存器的三个输出端分别与第7至第9条扫描信号线相连，使第二栅极驱动电路1002中的第2级移位寄存器的三个输出端分别与第10至第12条扫描信号线相连，以此类推。
另外，在显示装置中，可以设置计数器(图10中未示出)。每当向第一栅极驱动电路901发出一个帧起始信号时，计数器的值就加1。当计数器的值达到预先设置(例如，预先设置在显示装置的控制芯片或控制器中)的值时，可以通过显示装置中的控制电路或处理器(图10中未示出)改变提供给第一栅极驱动电路1001和第二栅极驱动电路1002中的各级移位寄存器的第一下拉节点选择信号端PDS1和第二下拉节点选择信号端PDS2的信号，从而使第一栅极驱动电路1001和第二栅极驱动电路1002中的所有移位寄存器改变相应的活跃下拉节点。
根据本公开的实施例的移位寄存器可以支持多输出；并且可以通过在移位寄存器中设置两个或多个下拉节点，并以预定数量的帧为单位交替地使用这些下拉节点，使电路的可靠性更高。根据本公开的实施例的移位寄存器可以通过相对较少的开关元件，增强单级移位寄存器的驱动控制能力。采用根据本公开的实施例的移位寄存器的栅极驱动电路和显示装置可靠性更高，更有利于实现窄边框车载显示产品。
以上描述了本公开的一些实施例。然而，本公开并不局限于所描述的这些示例，而是可以做出各种变型和改进，这些变型和改进也均在本公开的范围内。

Claims (14)

  1. 一种移位寄存器，包括：
    输入和复位电路，与输入端、上拉节点、复位端相连，被配置为在输入端的电位为工作电位的情况下，将上拉节点的电位设置为工作电位，并且在复位端的电位为工作电位的情况下，将上拉节点的电位设置为复位电位；
    第一输出电路，与上拉节点、第一控制信号端、第一输出端相连，被配置为在上拉节点的电位和第一控制信号端的电位为工作电位的情况下，在第一输出端输出第一栅极驱动信号；
    第二输出电路，与上拉节点、第二控制信号端、第二输出端相连，被配置为在上拉节点的电位和第二控制信号端的电位为工作电位的情况下，在第二输出端输出第二栅极驱动信号；
    第一下拉电路，与第一下拉节点、上拉节点、第一输出端、第二输出端相连，被配置为在第一下拉节点的电位为工作电位的情况下，将上拉节点、第一输出端和第二输出端的电位设置为复位电位；
    第二下拉电路，与第二下拉节点、上拉节点、第一输出端、第二输出端相连，被配置为在第二下拉节点的电位为工作电位的情况下，将上拉节点、第一输出端和第二输出端的电位设置为复位电位；以及
    下拉节点选择电路，与第一下拉节点选择信号端、第二下拉节点选择信号端、第一下拉节点、第二下拉节点相连，被配置为根据第一下拉节点选择信号端的电位和第二下拉节点选择信号端的电位，将第一下拉节点和第二下拉节点中的一个选择为活跃下拉节点。
  2. 根据权利要求1所述的移位寄存器，其中，下拉节点选择电路包括：
    第一下拉选择开关元件(SW10)，其控制端与第一下拉节点选择信号端相连，其第一端和第二端中的一个与第一下拉节点相连；
    第二下拉选择开关元件(SW11)，其控制端与第一下拉节点选择信号端相连，其第一端和第二端中的一个与第二下拉节点相连，其第一端和第二端中的另一个与参考信号端相连；
    第三下拉选择开关元件(SW12)，其控制端与第二下拉节点选择信号端相连，其第一端和第二端中的一个与第二下拉节点相连，其第一端和第二端中的另一个与第一下拉选择开关元件的第一端和第二端中的另一个相连；以 及
    第四下拉选择开关元件(SW13)，其控制端与第二下拉节点选择信号端相连，其第一端和第二端中的一个与第一下拉节点相连，其第一端和第二端中的另一个与参考信号端相连。
  3. 根据权利要求2所述的移位寄存器，其中，下拉节点选择电路还包括：
    第一电容器(C3)，连接在第一下拉节点与参考信号端之间；以及
    第二电容器(C4)，连接在第二下拉节点与参考信号端之间。
  4. 根据权利要求2所述的移位寄存器，其中，下拉节点选择电路还包括：
    选择控制开关元件(SW9)，其控制端以及第一端和第二端中的一个都与下拉选择控制信号端相连，其第一端和第二端中的另一个与第一下拉选择开关元件(SW10)的第一端和第二端中的另一个相连，并且与第三下拉选择开关元件(SW12)的第一端和第二端中的另一个相连。
  5. 根据权利要求1至3中的任一项所述的移位寄存器，其中，输入和复位电路包括：
    第一输入开关元件(SW1)，其控制端与输入端相连，其第一端和第二端中的一个与第一扫描控制信号端相连，其第一端和第二端中的另一个与上拉节点相连；以及，
    第二输入开关元件(SW8)，其控制端与复位端相连，其第一端和第二端中的一个与第二扫描控制信号端相连，其第一端和第二端中的另一个与上拉节点相连，
    其中，正向扫描时，第一扫描控制信号的电位为工作电位，第二扫描控制信号的电位为复位电位，而反向扫描时，第一扫描控制信号的电位为复位电位，第二扫描控制信号的电位为工作电位。
  6. 根据权利要求5所述的移位寄存器，其中，输入和复位电路还包括：
    第一下拉节点复位开关元件(SW2)，其控制端与上拉节点相连，其第一端和第二端中的一个与第一下拉节点相连，其第一端和第二端中的另一个与参考信号端相连；以及，
    第二下拉节点复位开关元件(SW3)，其控制端与上拉节点相连，其第一端和第二端中的一个与第二下拉节点相连，其第一端和第二端中的另一个与参考信号端相连。
  7. 根据权利要求1至3中的任一项所述的移位寄存器，其中，第一输出 电路包括：
    第一输出开关元件(SW5)，其控制端与工作电位端相连，其第一端和第二端中的一个与上拉节点相连；
    第二输出开关元件(SW4)，其控制端与第一输出开关元件的第一端和第二端中的另一个相连，其第一端和第二端中的一个与第一控制信号端相连，其第一端和第二端中的另一个与第一输出端相连；以及
    第一输出电容器(C1)，其连接在第二输出开关元件的控制端与第一输出端之间。
  8. 根据权利要求1至4中的任一项所述的移位寄存器，其中，第二输出电路包括：
    第三输出开关元件(SW7)，其控制端与工作电位端相连，其第一端和第二端中的一个与上拉节点相连；
    第四输出开关元件(SW6)，其控制端与第三输出开关元件的第一端和第二端中的另一个相连，其第一端和第二端中的一个与第二控制信号端相连，其第一端和第二端中的另一个与第二输出端相连；以及
    第二输出电容器(C2)，其连接在第四输出开关元件的控制端与第二输出端之间。
  9. 根据权利要求1至4中的任一项所述的移位寄存器，其中，第一下拉电路包括：
    第一下拉开关元件(SW14)，其控制端与第一下拉节点相连，其第一端和第二端中的一个与上拉节点相连，其第一端和第二端中的另一个与参考信号端相连；
    第二下拉开关元件(SW15)，其控制端与第一下拉节点相连，其第一端和第二端中的一个与第一输出端相连，其第一端和第二端中的另一个与参考信号端相连；以及
    第三下拉开关元件(SW16)，其控制端与第一下拉节点相连，其第一端和第二端中的一个与第二输出端相连，其第一端和第二端中的另一个与参考信号端相连。
  10. 根据权利要求1至4中的任一项所述的移位寄存器，其中，第二下拉电路包括：
    第四下拉开关元件(SW17)，其控制端与第二下拉节点相连，其第一端 和第二端中的一个与上拉节点相连，其第一端和第二端中的另一个与参考信号端相连；
    第五下拉开关元件(SW19)，其控制端与第二下拉节点相连，其第一端和第二端中的一个与第一输出端相连，其第一端和第二端中的另一个与参考信号端相连；以及
    第六下拉开关元件(SW18)，其控制端与第二下拉节点相连，其第一端和第二端中的一个与第二输出端相连，其第一端和第二端中的另一个与参考信号端相连。
  11. 一种栅极驱动电路，包括多个级联的根据权利要求1至10中的任一项所述的移位寄存器，其中，
    除第一级移位寄存器以外，其它各级移位寄存器的输入端与级联在其前一级的移位寄存器的第二输出端相连，并且
    除最后一级移位寄存器以外，其它各级移位寄存器的复位端与级联在其后一级的移位寄存器的第一输出端相连。
  12. 一种显示装置，包含第一栅极驱动电路和第二栅极驱动电路，所述第一栅极驱动电路包括N个级联的根据权利要求1至10中的任一项所述的移位寄存器，所述第二栅极驱动电路包括N个级联的根据权利要求1至10中的任一项所述的移位寄存器；其中，
    第一栅极驱动电路的第1级移位寄存器的复位端连接第二栅极驱动电路的第1级移位寄存器的第一输出端；
    第一栅极驱动电路的第i级移位寄存器的输入端连接第二栅极驱动电路的第i-1级移位寄存器的第二输出端，第一栅极驱动电路的第i级移位寄存器的复位端连接第二栅极驱动电路的第i级移位寄存器的第一输出端，其中1<i≤N；
    第二栅极驱动电路的第j级移位寄存器的输入端连接第一栅极驱动电路的第j级移位寄存器的第二输出端，第二栅极驱动电路的第j级移位寄存器的复位端连接第一栅极驱动电路的第j+1级移位寄存器的第一输出端，其中，1≤j<N。
  13. 一种用于驱动根据权利要求1至10中的任一项所述的移位寄存器的方法，包括：
    在相邻两帧中，将第一下拉节点和第二下拉节点中的一个交替设置为活 跃下拉节点，在将其中一个下拉节点设置为活跃下拉节点的情况下，将另一个下拉节点的电位设置为复位电位；
    在每一帧中，对于每级移位寄存器，
    第一阶段中，响应于接收到输入信号，将上拉节点的电位上拉为工作电位；
    第二阶段中，响应于接收到第一时钟信号，在第一输出端输出第一栅极驱动信号，并且响应于在第一时钟信号之后所接收的第二时钟信号，在第二输出端输出第二栅极驱动信号；
    第三阶段中，响应于在第二时钟信号之后所接收的参考信号，将活跃下拉节点的电位设置为工作电位；以及
    将上拉节点、第一输出端和第二输出端的电位设置为复位电位。
  14. 根据权利要求13所述的方法，其中，按照预先设定的数量的帧，交替使用第一下拉节点和第二下拉节点作为活跃下拉节点。
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