WO2019188901A1

WO2019188901A1 - Production method for semiconductor substrate, and set such as polishing composition set

Info

Publication number: WO2019188901A1
Application number: PCT/JP2019/012358
Authority: WO
Inventors: 野口　直人
Original assignee: 株式会社フジミインコーポレーテッド
Priority date: 2018-03-30
Filing date: 2019-03-25
Publication date: 2019-10-03
Also published as: TW202004884A; JPWO2019188901A1; JP7421470B2

Abstract

Provided is a production method for a semiconductor substrate. The production method makes it possible to control the post-production shape of the substrate to a high degree. This production method for a semiconductor substrate includes a back surface processing step for processing a back surface of a wafer-shaped processing target. After the back surface processing step, there is a processing distortion layer on the back surface. The depth of the processing distortion layer that is on the back surface is greater than the depth of a processing distortion layer that is on a front surface of the semiconductor substrate, or there is no processing distortion layer on the front surface.

Description

Set of semiconductor substrate manufacturing method and polishing composition set

The present invention relates to a method for producing a semiconductor substrate, and a polishing composition set and other sets preferably used in the production method. This application claims priority based on Japanese Patent Application No. 2018-68524 filed on Mar. 30, 2018, the entire contents of which are incorporated herein by reference.

A semiconductor substrate material composed of silicon, gallium nitride, silicon carbide, or the like is usually cut out from an ingot and then formed into a thin semiconductor substrate (semiconductor wafer) having a smooth surface through a lapping process or a polishing process. The For example, in the manufacture of a silicon carbide semiconductor substrate, a polishing slurry is supplied between the polishing pad and an object to be processed using a polishing pad after lapping using diamond abrasive grains or instead of lapping. Polishing to be performed is performed. The manufactured semiconductor substrate is used as a semiconductor device after an epitaxial growth film (epitaxial film) or the like is formed on its front surface. Patent documents 1 to 5 are cited as documents disclosing this type of prior art.

Japanese Patent Application Publication No. 2013-27960 Japanese Patent No. 6011340 Japanese Patent Application Publication No. 2015-205819 Japanese Patent Application Publication No. 2016-64980 Japanese Patent Application Publication No. 2017-81813

In recent years, higher quality shape control has been required for semiconductor substrates such as silicon carbide. For example, in Patent Document 1, polishing is performed on the front surface of a silicon carbide single crystal substrate on which a processing damage layer has been formed, and etching is performed on the back surface of the silicon carbide single crystal substrate. It has been proposed to suppress the warpage of the substrate while adjusting. In Patent Documents 2 to 5, by adjusting the average value and standard deviation of the surface roughness of the front and back surfaces of a silicon carbide single crystal substrate having a diameter of 110 mm or more, a good epitaxial film can be formed, and the warp is warped. It describes that a substrate in which the above is suppressed is manufactured. However, as described in the above prior art document, if the surface quality of both sides of the substrate is improved to reduce the warpage based on internal factors, it will take place when an epitaxial film or the like is subsequently formed on the front surface of the substrate. The influence of the substrate deformation stress due to external factors such as the formed film tends to become obvious. It has been clarified that the deformation stress due to such an external factor can be a limiting factor for high-level control of the substrate shape after manufacturing the substrate or in the semiconductor device.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor substrate manufacturing method capable of highly controlling the substrate shape after manufacturing. Another related object is to provide a polishing composition set, a composition set, and a semiconductor substrate manufacturing set used in the manufacturing method. Yet another related object is to provide a semiconductor substrate whose shape after manufacture is highly controlled.

According to the present specification, a semiconductor substrate manufacturing method including a back surface processing step for processing a back surface of a wafer-like workpiece is provided. A processed strain layer exists on the back surface that has undergone the back surface processing step. The depth of the working strain layer existing on the back surface is larger than the depth of the working strain layer on the front surface of the semiconductor substrate, or there is no working strain layer on the front surface. A workpiece to be a semiconductor substrate generates a compressive stress corresponding to the depth of the processing strain layer. By setting the depth of the back surface processed strain layer quantitatively using this action, the shape of the semiconductor substrate in the semiconductor device after manufacturing or in the semiconductor device can be highly controlled. For example, a semiconductor substrate on which an epitaxial film or the like is formed on the front surface can be made flatter by offsetting the compressive stress caused by the formation film on the front surface and the compressive stress of the back surface processed strain layer. it can. Thereby, for example, the defect density such as dislocation of the formed film can be reduced, and the film quality can be improved.

In a preferred aspect of the manufacturing method disclosed herein, the back surface processing step is a step (surface roughness reduction step) in which the arithmetic average surface roughness Ra of the back surface is 10 nm or less. In order to make the front surface have a higher quality surface or perform a higher level of shape control, it is desirable that the surface roughness of the back surface is limited. From such a viewpoint, in the above configuration, while the Ra on the back surface of the substrate is limited to 10 nm or less, the processing is performed so that the depth of the processing strain layer is a predetermined value or more. As a result, the shape of the semiconductor substrate in the semiconductor device after manufacturing or in the semiconductor device can be controlled to a higher degree, and a higher quality semiconductor substrate can be obtained.

In a preferred embodiment of the manufacturing method disclosed herein, the depth of the processed strain layer existing on the back surface is 0.1 μm or more. By setting the depth of the processing strain layer to 0.1 μm or more, high-level control of the shape of the semiconductor substrate is preferably realized in a typical semiconductor device in which an epitaxial film with a predetermined thickness is formed on the front surface can do.

In a preferred embodiment of the manufacturing method disclosed herein, the back surface processing step includes a chemical mechanical polishing step. In another preferred embodiment, the back surface processing step includes a lapping step. In still another aspect, the back surface processing step includes a grinding step. By adopting any one process selected from chemical mechanical polishing (CMP), lapping and grinding as the back surface processing step, the effect of the technique disclosed herein is preferably exhibited.

In a preferable aspect of the manufacturing method disclosed herein, a front surface processing step of processing the front surface of the workpiece is included. Further, both the front surface processing step and the back surface processing step include a step of using abrasive grains. In one aspect thereof, the abrasive grains used in the back surface processing step have higher hardness than the abrasive grains used in the front surface processing step. In another aspect, the abrasive grains used in the back surface processing step have a larger particle diameter than the abrasive grains used in the front surface processing step. By adopting the method as described above, it is possible to preferably manufacture a substrate in which the depth of the processed strain layer on the back surface side is larger than that on the front surface side.

In a preferred aspect of the manufacturing method disclosed herein, the semiconductor substrate is a semiconductor substrate made of silicon carbide. The effect by the technique disclosed here is preferably exhibited in a semiconductor substrate made of silicon carbide.

Also, according to the present specification, a polishing composition set used in any of the production methods disclosed herein is provided. This polishing composition set includes a composition Q1 as a back surface polishing composition used in the back surface processing step and a composition Q2 as a front surface polishing composition used in the front surface processing step. Including. The composition Q1 and the composition Q2 are stored separately from each other. By performing the back surface processing step and the front surface processing step using the polishing composition set having such a configuration, it is possible to suitably manufacture a semiconductor substrate whose shape after manufacturing is highly controlled. The semiconductor substrate may also have a high surface quality.

In the polishing composition set according to one preferred embodiment, the back surface polishing composition contains abrasive grains A _BF. Further, the front surface polishing composition contains abrasive grains A _FF. The abrasive grains _ABF are alumina particles or green silicon carbide particles, and the abrasive grains _AFF are silica particles or alumina particles. According to the above configuration, the effects of the technology disclosed herein are preferably realized.

In the polishing composition set according to a preferred embodiment, the backside polishing composition contains a polishing aid _CBF . The front surface polishing composition contains a polishing aid _CFF . The grinding aid C _BF is permanganic acid or a salt thereof, wherein grinding aid C _FF is hydrogen peroxide and vanadium acids. According to the above configuration, it is possible to preferably achieve both the polishing rate and the surface quality in the polishing of the front surface and the back surface of the object to be polished.

Moreover, according to this specification, the composition set used for one of the manufacturing methods disclosed here is provided. This composition set includes a composition Q3 as a lapping composition used in the back surface processing step and a composition Q4 as a front surface polishing composition used in the front surface processing step. . The composition Q3 and the composition Q4 are stored separately from each other. By performing the back surface processing step and the front surface processing step using the composition set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. The semiconductor substrate may also have a high surface quality.

In the composition set according to one preferred embodiment, the lapping composition contains abrasive grains A _BF. Further, the front surface polishing composition contains abrasive grains A _FF. The abrasive grains _ABF are diamond particles, and the abrasive grains _AFF are silica particles or alumina particles. According to the above configuration, the effects of the technology disclosed herein are preferably realized.

In the composition set according to a preferred embodiment, the front surface polishing composition contains a polishing aid _CFF . Further, the grinding aid C _FF is at least one selected from the group consisting of permanganic acid, permanganates, hydrogen peroxide and vanadium acids. According to the above configuration, in polishing the front surface of the object to be polished, both the polishing rate and the surface quality can be preferably achieved.

Also, according to the present specification, a set for manufacturing a semiconductor substrate used in any of the manufacturing methods disclosed herein is provided. This set includes abrasive grains for grinding used in the back surface processing step, and a composition Q5 as a front surface polishing composition used in the front surface processing step. The abrasive grains for grinding and the composition Q5 are stored separately from each other. By performing the back surface processing step and the front surface processing step using the set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. The semiconductor substrate front surface may have a high surface quality.

In a set according to a preferred embodiment, the abrasive grains for grinding are diamond particles, and the abrasive grains _AFF are silica particles or alumina particles. According to the above configuration, the effects of the technology disclosed herein are preferably realized.

In the set according to a preferred embodiment, the front surface polishing composition contains a polishing aid _CFF . The grinding aid C _FF is at least one selected from the group consisting of permanganic acid, permanganates, hydrogen peroxide and vanadium acids. According to the above configuration, in polishing the front surface of the object to be polished, both the polishing rate and the surface quality can be preferably achieved.

Also according to the present specification, a semiconductor substrate is provided. This semiconductor substrate has a front surface and a back surface. A working strain layer is present on the back surface. Further, the depth of the working strain layer existing on the back surface is larger than the depth of the working strain layer on the front surface, or no working strain layer exists on the front surface. The semiconductor substrate having such a configuration can be highly controlled in shape after manufacturing or in a semiconductor device. For example, what formed the epitaxial film in the front surface of the said semiconductor substrate can become a board | substrate excellent in flatness after the said formation film.

Hereinafter, preferred embodiments of the present invention will be described. Note that matters other than matters specifically mentioned in the present specification and necessary for the implementation of the present invention can be grasped as design matters of those skilled in the art based on the prior art in this field. The present invention can be carried out based on the contents disclosed in this specification and common technical knowledge in the field.

≪Semiconductor substrate≫
The semiconductor substrate disclosed here has a front surface and a back surface, and a processing strain layer exists on the back surface. In addition, the depth of the processing strain layer existing on the back surface is larger than the depth of the processing strain layer on the front surface, or there is no processing strain layer on the front surface of the semiconductor substrate. Here, the front surface of the semiconductor substrate is usually a surface on which an epitaxial film, a semiconductor element or the like is formed, and the back surface of the semiconductor substrate is a surface located on the side opposite to the front surface. . Note that the shape of the semiconductor substrate is not particularly limited, and usually has a disk shape (a circular shape as viewed from above). The semiconductor substrate may have a polygonal shape such as a quadrangle when viewed from above.

As a constituent material of the semiconductor substrate, a known semiconductor substrate material can be used without particular limitation. The constituent material of the semiconductor substrate is, for example, a single element semiconductor such as silicon or germanium; II-VI compound semiconductor substrate material such as cadmium telluride, zinc selenide, cadmium sulfide, cadmium mercury telluride, zinc cadmium telluride; III-V group compound semiconductor substrate materials such as gallium, gallium arsenide, gallium phosphide, indium phosphide, aluminum gallium arsenide, gallium indium arsenide, indium gallium arsenide, aluminum gallium indium phosphide; silicon carbide, silicon IV-IV compound semiconductor substrate material such as germanium hydride; Of these, a plurality of materials may be used. Especially, it is preferable that the semiconductor substrate is comprised from silicon carbide. Silicon carbide is expected as a semiconductor substrate material with low power loss and excellent heat resistance, and the practical advantage of highly controlling the substrate shape is particularly great. A semiconductor substrate according to a preferred embodiment is made of a single crystal whose front surface is silicon carbide.

The semiconductor substrate according to one aspect is made of a material having a Vickers hardness of 500 Hv or more. By providing a working strain layer on the back surface of a semiconductor substrate made of such a high hardness material, the shape of the high hardness substrate can be controlled to a high degree. The Vickers hardness of the constituent material of the semiconductor substrate is preferably 700 Hv or higher (for example, 1000 Hv or higher, typically 1500 Hv or higher). Examples of the material having a Vickers hardness of 1500 Hv or higher include diamond, silicon carbide, silicon nitride, titanium nitride, and gallium nitride. The substrate disclosed herein may have a single crystal surface of the above material that is mechanically and chemically stable. In particular, the surface of the semiconductor substrate is preferably composed of any one of diamond, silicon carbide, and gallium nitride, and more preferably composed of silicon carbide. The upper limit of Vickers hardness is not particularly limited, but may be about 7000 Hv or less (for example, 5000 Hv or less, typically 3000 Hv or less). In the present specification, the Vickers hardness can be measured based on JIS R 1610: 2003. The international standard corresponding to the JIS standard is ISO 14705: 2000.

The semiconductor substrate disclosed herein has a processing strain layer at least on the back surface. In the present specification, the “work strain layer” refers to a layered region defined by regarding the depth of the work strain (specifically, the work scratch) formed by the work on the semiconductor substrate surface as the layer thickness, It is a layer (surface layer) existing on the surface of the semiconductor substrate. The depth of the working strain layer can be measured by observation with a differential interference microscope and polishing. Specifically, it is measured by the method described in Examples described later.

The depth of the processed strain layer existing on the back surface of the semiconductor substrate is not limited to a specific range, and is relatively determined in relation to the properties of the front surface. For example, the difference (D _BF −D _FF ) between the processing strain layer depth D _FF [μm] on the front surface and the processing strain layer depth D _BF [μm] on the back surface is the difference in the processing strain layer depth. From the viewpoint of obtaining the deformation stress based on this, it is appropriate to be about 0.1 μm or more. In a preferred embodiment, the difference (D _BF −D _FF ) is about 0.2 μm or more, more preferably about 0.3 μm or more, for example, about 0.5 μm or more (typically about 0.7 μm or more). It may be about 1 μm or more (for example, about 1.3 μm or more). The difference (D _BF −D _FF ) is a typical semiconductor in which an epitaxial film having a predetermined thickness (for example, approximately 5 to 50 μm, typically approximately 10 to 30 μm) is formed on the front surface. Suitable for devices. In another aspect, the difference (D _BF −D _FF ) is about 2 μm or more, for example, about 3 μm or more, or about 3.5 μm or more (for example, about 3.8 μm or more). Good. Such a difference is preferably employed for a semiconductor substrate in which the deformation stress that makes the front surface convex after manufacture becomes relatively large.

The difference (D _BF −D _FF ) is suitably about 10 μm or less, for example. In a preferred embodiment, the difference (D _BF −D _FF ) is about 5 μm or less, more preferably about 2.5 μm or less (eg, about 2 μm or less), for example, about 1.2 μm or less (typically about 1 μm). Or about 0.7 μm or less (for example, about 0.5 μm or less). The difference (D _BF −D _FF ) is a typical semiconductor in which an epitaxial film having a predetermined thickness (for example, approximately 5 to 50 μm, typically approximately 10 to 30 μm) is formed on the front surface. Suitable for devices. In another aspect, the difference (D _BF −D _FF ) is about 4.5 μm or less, for example, about 4 μm or less, or about 3.5 μm or less. In the case where there is no working strain layer on the front surface, the difference (D _BF −D _FF ) can be obtained by setting the working strain layer depth D _FF to 0 μm.

The depth of the processing strain layer on the back surface of the semiconductor substrate is not particularly limited except that the processing strain layer is present on the front surface and is larger than the front surface side. For example, the processing strain layer depth D _BF on the back surface is suitably about 0.1 μm or more, preferably about 0.2 μm or more, more preferably about 0.3 μm or more, for example, about 0.5 μm. It may be above (typically about 0.7 μm or more), or about 1 μm or more (for example, about 1.3 μm or more). In a typical semiconductor device in which an epitaxial film having a predetermined thickness (for example, about 5 to 50 μm, typically about 10 to 30 μm) is formed on the front surface, the processing strain layer depth D _BF is Is preferred. In another aspect, the processed strain layer depth _DBF is about 2 μm or more, for example, about 3 μm or more, or about 3.5 μm or more (for example, about 3.8 μm or more). The processing strain layer depth _DBF is preferably used for a semiconductor substrate in which the deformation stress that makes the front surface convex after manufacture becomes relatively large.

Further, the back surface of the processing strain layer depth D _BF is appropriate that example is about 10μm or less. In a preferred embodiment, the working strain layer depth _DBF is about 5 μm or less, more preferably about 2.5 μm or less (for example, about 2 μm or less), for example, about 1.2 μm or less (typically about 1 μm or less). Or about 0.7 μm or less (for example, about 0.5 μm or less). Processing strain layer depth D _BF of the above range, a predetermined thickness (e.g., approximately 5 ~ 50 [mu] m thick, 10 ~ 30 [mu] m thick approximately typically) epitaxial film is typically as formed on the front surface of the Suitable for semiconductor devices. In another aspect, the working strain layer depth _DBF is about 4.5 μm or less, for example, about 4 μm or less, or about 3.5 μm or less.

When the processing strain layer exists on the front surface of the semiconductor substrate, the processing strain layer depth D _FF on the front surface is not particularly limited as long as it is smaller than the processing strain layer depth D _BF on the back surface. For example, processing strain layer depth _{D FF} of the front surface is suitably less than 10 [mu] m, preferably less than 5 [mu] m, more preferably less than 1 [mu] m, more preferably less than 0.3 [mu] m (e.g., less than 0.1 [mu] m) It is. The lower limit of the working strain layer depth _{D FF} of the front surface is more than 0 .mu.m (e.g. 0 .mu.m greater), may be about 0.1μm or more. Such a front surface is easy to obtain a high-quality surface, and is suitable for a typical semiconductor device in which an epitaxial film having a predetermined thickness is formed on the front surface.

The arithmetic average surface roughness Ra of the front surface of the semiconductor substrate disclosed herein is set according to the required surface quality and is not limited to a specific range. For example, the Ra is suitably about 10 nm or less, and in applications where a higher quality surface is required, it is preferably less than 5 nm, more preferably less than 1 nm, and even more preferably less than about 0.3 nm. The thickness is preferably less than 0.1 nm (for example, less than 0.07 nm, typically about 0.05 nm). The lower limit of Ra on the front surface can be, for example, 0.01 nm or more.

The arithmetic average surface roughness Ra of the back surface of the semiconductor substrate disclosed herein is not particularly limited, and is usually about 20 nm or less. Ra of the back surface according to a preferred embodiment is about 10 nm or less (typically less than 10 nm), more preferably less than 5 nm, for example, less than 3 nm, less than 2 nm, or less than 1 nm. (For example, less than 0.3 nm, typically about 0.1 nm). From the viewpoint of productivity and the like, the lower limit of Ra on the back surface may be, for example, approximately 0.05 nm or more, approximately 0.5 nm or more, or approximately 1 nm or more.

Ra of the front surface and the back surface of the semiconductor substrate can be measured using a commercially available atomic force microscope under a measurement area of 10 μm × 10 μm. More specifically, it can be measured by the method described in Examples described later.

As the length of the semiconductor substrate increases and the thickness of the substrate decreases, the influence of deformation such as warpage increases in the subsequent processing for semiconductor device manufacturing (formation of epitaxial films, semiconductor elements, etc.). Cheap. The effect of applying the technology disclosed herein to such a semiconductor substrate is preferably exhibited. From such a viewpoint, it is appropriate that the ratio (L / T) of the substrate length (longest length. Diameter in the case of a disk) L [mm] to the substrate thickness T [mm] is approximately 50 or more. Preferably, it is about 100 or more, more preferably about 150 or more, still more preferably about 200 or more, for example, about 250 or more. The upper limit of the ratio (L / T) is suitably about 600 or less, for example, from the viewpoints of substrate strength, handleability, etc., preferably about 400 or less, more preferably about 300 or less, for example about 250. It may be the following.

The length of the semiconductor substrate disclosed herein (the longest length; the diameter in the case of a disc shape) is not limited to a specific range. From the viewpoint of preferably obtaining the effects of the technology disclosed herein, the length of the substrate is suitably about 20 mm or more, preferably about 45 mm or more, more preferably about 70 mm or more, for example, about It may be 100 mm or more, about 200 mm or more, about 300 mm or more, or about 450 mm or more. The large-diameter semiconductor substrate is also excellent in production efficiency. The upper limit of the length of the semiconductor substrate is suitably about 500 mm or less, for example, and is preferably about 300 mm or less, more preferably about 220 mm or less, and still more preferably about 200 mm or less from the viewpoint of substrate strength, handleability, and the like. It is 120 mm or less (for example, less than 110 mm), for example, it may be about 100 mm or less, and may be about 80 mm or less.

The thickness of the semiconductor substrate is appropriately set according to the size (diameter, etc.). The thickness of the substrate is usually about 100 μm or more, suitably about 300 μm or more (for example, about 350 μm or more), for example, about 500 μm or more. Further, the thickness is usually about 1500 μm or less, suitably about 1000 μm or less, preferably about 800 μm or less, for example about 500 μm or less (typically less than 500 μm). It may be about 400 μm or less.

The semiconductor substrate disclosed herein may be warped in an arc shape so that the front side is concave due to compressive stress caused by the processing strain layer. By forming a film such as an epitaxial film on the front surface of the semiconductor substrate in which such deformation stress is inherent, the deformation caused by the compressive stress of the film formed on the front surface and the intentionally provided back surface The compressive stress of the processing strain layer cancels out, and the semiconductor substrate can have a highly controlled shape in the semiconductor device. For example, a semiconductor substrate having an epitaxial film or the like formed on the front surface can be made flatter, and the defect density such as dislocations in the formed film can be reduced to improve the film quality.

The warpage that makes the front surface concave is suitably, for example, that the depth of the concave is about 0.5 μm or more, preferably about 1 μm or more, more preferably about 3 μm or more, and even more preferably about 5 μm or more. For example, it may be about 6 μm or more, or about 8 μm or more. The upper limit of the depth of the recess is usually less than 50 μm, suitably about 20 μm or less (for example, less than 20 μm), preferably about 15 μm or less, more preferably about 12 μm or less, It may be about 10 μm or less, about 8 μm or less, or about 6 μm or less. A semiconductor substrate having such a warp is a typical semiconductor device in which an epitaxial film having a predetermined thickness (for example, approximately 5 to 50 μm, typically approximately 10 to 30 μm) is formed on the front surface. Is preferable.

The warpage of the front surface of the semiconductor substrate can be evaluated as, for example, GBIR (Global backside ideal range) in the SEMI (Semiconductor equipment and materials international) standard. The GBIR adsorbs the entire back surface of the wafer onto a flat chuck surface, and measures the height from the reference surface with respect to the entire surface of the wafer using the back surface as a reference surface, and expresses the distance from the highest height to the lowest height. Is. GBIR can be measured using a known surface shape measuring instrument. For example, a surface shape measuring machine “SURFCOM 1500DX” manufactured by Tokyo Seimitsu Co., Ltd. can be used. Specifically, it can measure by the method as described in the below-mentioned Example.

≪Semiconductor substrate manufacturing method≫
<Processing object>
Next, a method for manufacturing a semiconductor substrate disclosed herein will be described. In this manufacturing method, first, a workpiece is prepared. Although it does not specifically limit, what was cut out by methods, such as a slice, and made into the wafer form as an object to be processed as a processing target object is used. As the constituent material of the object to be processed, those exemplified as the above-mentioned semiconductor substrate material can be used without particular limitation, and a suitable example of the semiconductor substrate material is also a preferable example of the constituent material of the object to be processed. The shape and size of the object to be processed (the shape and size when viewed from above) are the same as those of the semiconductor substrate to be manufactured. The thickness of the workpiece is appropriately set so as to obtain the thickness of the semiconductor substrate to be manufactured, and is not limited to a specific range.

<Backside processing process>
The semiconductor substrate manufacturing method disclosed herein is characterized by including a back surface processing step of processing the back surface of a wafer-like workpiece. Here, the back surface of the workpiece is a surface to be the back surface of the semiconductor substrate to be manufactured. The back surface processing step disclosed herein is not limited to a specific step, and a known surface processing technology is appropriately selected, and is performed so that a processing strain layer exists on the back surface of the manufactured semiconductor substrate. Further, when a processing strain layer exists on the front surface of the semiconductor substrate, the back surface processing is performed so that a processing strain layer having a depth larger than the depth of the processing strain layer on the front surface of the semiconductor substrate exists. The process is carried out. Specifically, the back surface processing step is performed in consideration of the material, structure, thickness, and the like of a formation film such as an epitaxial film provided on the front surface of the manufactured semiconductor substrate. Moreover, it is preferable that the depth of the processing strain layer existing on the back surface after the back surface processing step is determined based on the compressive stress that can be generated on the front surface of the manufactured semiconductor substrate. Such compressive stress can be determined by, for example, the material, structure, thickness, and the like of a formed film such as an epitaxial film provided on the front surface.

The back surface processing step is not particularly limited, and may be a grinding or polishing step such as a grinding step, a lapping step, or a CMP step. The grinding step, the lapping step, the CMP step, etc. may be carried out by one step alone or in combination of two or more steps.

(Grit for back surface processing)
The back surface processing step typically includes a step using abrasive grains (for example, a grinding step, a lapping step, or a CMP step). The material and properties of the abrasive grains _ABF used in the back surface processing step are not particularly limited. For example, the abrasive grains _ABF can be any of inorganic particles, organic particles, and organic-inorganic composite particles. For example, silica particles, alumina particles, cerium oxide particles, chromium oxide particles, titanium dioxide particles, zirconium oxide particles, magnesium oxide particles, manganese dioxide particles, zinc oxide particles, iron oxide particles and other oxide particles; silicon nitride particles, nitriding Consisting essentially of any of nitride particles such as boron particles; carbide particles such as silicon carbide particles, green silicon carbide (GC) particles and boron carbide particles; diamond particles; carbonates such as calcium carbonate and barium carbonate; Abrasive grains to be used. Abrasive grain _ABF may be used individually by 1 type, and may be used in combination of 2 or more type. Among these, diamond particles are preferable from the viewpoint of forming a work strain layer.

In the present specification, regarding the composition of the abrasive grains, “substantially consisting of X” or “substantially consisting of X” means that the proportion of X in the abrasive grains (the purity of X) is weight. It is 90% or more on the basis (preferably 95% or more, more preferably 97% or more, further preferably 98% or more, for example 99% or more).

In embodiments where the front surface processing step to be described later using abrasive A _FF, the abrasive A _BF used in the rear surface processing step, it is higher hardness than the abrasive grains A _FF used in the above front surface processing step It is preferable. Thereby, the board | substrate with which the depth of the process distortion layer of the back surface side is larger than the front surface side can be manufactured preferably. The difference between the abrasive grain _{A BF} Vickers hardness _H BF (Hv) and the abrasive grains _{A FF} Vickers hardness _{_{H FF (Hv) (H BF}} -H FF) is not particularly limited, for example, approximately 100Hv or more (e.g., about 500Hv As described above, it is typically appropriate to set it to about 700 Hv or more. In another preferred embodiment, the difference (H _BF −H _FF ) is about 1000 Hv or more (eg, about 1200 Hv or more, typically about 1800 Hv or more), more preferably about 3000 Hv or more (eg, about 3500 Hv or more, typical Specifically, it is about 4000 Hv or more. The upper limit of the difference (H _BF −H _FF ) is not particularly limited. For example, it is suitably about 10000 Hv or less (for example, about 9000 Hv or less), and is preferably about 5000 Hv or less from the viewpoint of the surface smoothness of the back surface. (For example, about 4000 Hv or less, typically about 3500 Hv or less), more preferably about 2000 Hv or less (for example, about 1500 Hv or less, typically about 1000 Hv or less).

The hardness of the abrasive grains _ABF is not particularly limited. From the viewpoint of adjusting the depth of the work strain layer on the back side to a suitable range, the Vickers hardness H _BF (Hv) of the abrasive grains A _BF is, for example, about 1000 Hv or more (for example, about 1200 Hv or more, typically about 1500 Hv or more. ), Preferably about 2000 Hv or more (for example, about 2200 Hv or more, typically about 2400 Hv or more), more preferably about 4000 Hv or more. The Vickers hardness H _BF (Hv) is suitably about 12000 Hv or less (for example, about 10000 Hv or less), for example, and is preferably about 5000 Hv or less (for example, about 4000 Hv or less) from the viewpoint of the surface smoothness of the back surface. , Typically about 3000 Hv or less), more preferably about 2500 Hv or less (for example, about 2000 Hv or less, typically about 1700 Hv or less).
The Vickers hardness of the abrasive grains is a value measured based on JIS R 1610: 2003 for the material used as the abrasive grains.

In embodiments where the front surface processing step to be described later using abrasive A _FF, abrasives A _BF used in the back surface processing step, larger particle size than the abrasive grain A _FF used in the front surface processing step. Thereby, the board | substrate with which the depth of the process distortion layer of the back surface side is larger than the front surface side can be manufactured preferably. In such embodiments, abrasive _{A FF} abrasive _{A BF} particle size _{P BF} ratio _{_(P} BF _/ P _FF) of relative particle size _{P FF} of is suitably greater than 1. In a preferred embodiment, the ratio (P _BF / P _FF ) is about 2 or more, about 3 or more (for example, about 4 or more), about 5 or more, or about 8 or more (for example, about 9 or more), or about 20 or more (for example, 25 or more). The upper limit of the ratio (P _BF / P _FF ) is not particularly limited, and may be about 100 or less (for example, 50 or less), about 30 or less, about 15 or less, and about It may be 10 or less (for example, approximately 5 or less).

The particle diameter _PBF of the abrasive grain _ABF is not particularly limited. From the viewpoint of adjusting the depth of the working strain layer on the back side to a suitable range, the particle diameter P _BF of the abrasive grains A _BF is suitably about 0.05 μm or more, preferably about 0.2 μm or more, More preferably, it is about 0.3 μm or more, for example, about 0.4 μm or more. In another preferred embodiment, the particle diameter _PBF of the abrasive grains _ABF is about 0.8 μm or more, more preferably about 2 μm or more, and further preferably about 2.5 μm or more. Further, the upper limit of the particle diameter P _BF of the abrasive grains A _BF is not particularly limited, and is suitably about 10 μm or less, preferably about 5 μm or less. In another preferred embodiment, the particle diameter _PBF of the abrasive grains _ABF is about 2 μm or less, more preferably about 1.5 μm or less, and still more preferably about 1.2 μm or less. In still another preferred embodiment, the particle diameter _PBF of the abrasive grains _ABF is about 0.7 μm or less, more preferably about 0.5 μm or less, and still more preferably about 0.3 μm or less.
The particle size P _BF abrasive A _BF referred to herein, can be measured in each of the methods described below. When the abrasive grains _ABF have primary and secondary particle diameters, the secondary particle diameter value is defined as the particle diameter _PBF .

(Grinding process)
The back surface processing step according to a preferred embodiment includes a grinding step. In this specification, the “grinding step” refers to a step of placing fixed abrasive grains on a surface plate and pressing the fixed abrasive grains against the surface of the workpiece. Fixed abrasive grains are usually aggregates in which abrasive grains are hardened with a binder such as vitrified or resinoid, and are also called grinding wheels. Abrasive grains are usually dispersed and fixed in a binder. Moreover, as a surface plate used at this process, a well-known thru | or usual thing can be used. The grinding process is carried out while supplying a working fluid comprising an aqueous solution as necessary.

Examples of the abrasive grains _ABF used in the grinding step include one or more of the above-described abrasive grains for back surface processing. A diamond particle is mentioned as a suitable example of the abrasive grain _ABF used for a grinding process. The content of the abrasive A _BF in fixed abrasive is not particularly limited, an appropriate range is adopted on the basis of common general knowledge. Note that grinding using a grinding wheel such as a diamond wheel may be referred to as wheel grinding.

Particle size P _BF abrasive A _BF used in the grinding step is not particularly limited. From the viewpoint of adjusting the depth of the working strain layer on the back side to a suitable range, it is appropriate that the particle diameter P _BF of the abrasive grains _ABF used in this step is about 0.1 μm or more. In a preferred embodiment, the particle diameter P _BF of the abrasive grains A _BF is about 0.2 μm or more, for example, about 0.3 μm or more. In another preferred embodiment, the particle diameter _PBF of the abrasive grains _ABF is about 0.8 μm or more, for example, about 2 μm or more, or about 2.5 μm or more. Further, the upper limit of the particle diameter P _BF of the abrasive grains A _BF is not particularly limited, and is suitably about 10 μm or less, preferably about 5 μm or less. In another preferred embodiment, the particle diameter _PBF of the abrasive grains _ABF is about 2 μm or less, more preferably about 1 μm or less, and still more preferably about 0.7 μm or less.

The particle diameter of the abrasive grains used in the grinding process is an average particle diameter based on the electrical resistance test method (JIS R6002). The average particle diameter can be determined using, for example, “Multisizer III” manufactured by Beckman Coulter.

In addition, when the back surface processing step is composed of a plurality of processing steps including a grinding step, the grinding step can be the final step of the back surface processing step. In that case, there is no processing step after the grinding step in the back surface processing step.

(Lapping process)
The back surface processing step according to a preferred embodiment includes a lapping step. In this specification, the “lapping step” is performed by arranging a carrier (also referred to as a carrier plate) holding an object to be polished between opposing polishing surface plates and rotating at least one of the polishing surface plate and the carrier. A processing process. The polishing surface plate and / or the carrier is rotated so that both of them rotate relatively. The lapping step is typically performed by supplying loose abrasive grains (for example, diamond particles) between the polishing surface plate and the workpiece. The loose abrasive grains are usually supplied to the object to be processed in the form of a liquid composition containing a solvent such as water called a polishing slurry. A polishing pad is not used in the lapping process.

The polishing surface plate used in the lapping process disclosed here is usually made of metal. The polishing surface plate used for lapping is required to be easily processed to maintain the accuracy of the surface surface (surface facing the object to be processed). For this reason, a polishing surface plate in which at least the surface plate surface is made of a metal such as cast iron, tin, tin alloy, copper or copper alloy is preferably used. As the polishing platen, a plate having a groove on the surface of the platen may be used for the purpose of stably supplying the polishing composition and adjusting the processing pressure. The shape and depth of the groove are arbitrary, and for example, a groove in which a groove is engraved in a lattice shape or a radial shape can be used.

As the abrasive grains _ABF used in the lapping step, one or more kinds of the abrasive grains for backside processing exemplified above may be mentioned. A diamond particle is mentioned as a suitable example of the abrasive grain _ABF used for this process. The content of the abrasive grains _ABF in the wrapping composition is not particularly limited, and an appropriate range is adopted based on common technical knowledge. For example, the content of abrasive grains _ABF in the wrapping composition is suitably about 1% by weight or more, preferably about 5% by weight or more, and about 50% by weight or less, preferably about 30% by weight or less.

Particle size P _BF abrasive A _BF used in the lapping process is not particularly limited. From the viewpoint of adjusting the depth of the working strain layer on the back side to a suitable range, the particle diameter P _BF of the abrasive grains _ABF used in this step is suitably about 0.1 μm or more, preferably about It is 0.2 μm or more. In another preferred embodiment, the particle diameter _PBF of the abrasive grains _ABF is about 0.8 μm or more, for example, about 2 μm or more, or about 2.5 μm or more. The upper limit of the particle diameter P _BF of the abrasive grains A _BF is not particularly limited and is suitably about 10 μm or less, preferably about 5 μm or less, more preferably about 2 μm or less, and further preferably about 1.2 μm. It is as follows. In another preferred embodiment, the particle size _{P BF} abrasive _{A BF} is at approximately 2μm or less, more preferably about 0.3μm or less. The particle diameter of the abrasive grains used in the lapping process can be measured by the same method as that of the abrasive grains used in the grinding process. The same applies to the embodiments described later.

In addition, when the back surface processing step is composed of a plurality of processing steps including a lapping step (for example, a plurality of processing steps including a grinding step), the lapping step may be the final step of the back surface processing step. In that case, there is no processing step after the lapping step in the back surface processing step.

(CMP process)
The back surface processing step according to a preferred embodiment includes a CMP step. In this specification, the “chemical mechanical polishing (CMP) process” refers to a polishing (polishing) process performed by supplying a polishing slurry between the polishing pad and a workpiece using a polishing pad. By adopting the CMP process, a high-quality back surface is easily obtained.

The CMP step is preferably performed by supplying a polishing slurry (also referred to as a polishing liquid) composed of a polishing composition as described later to the surface of the workpiece. Specifically, the polishing liquid is supplied to the surface of the object to be processed and polished by a conventional method. For example, an object to be processed is set in a general polishing apparatus, and the polishing liquid is supplied to the surface (surface to be polished) of the object to be processed through a polishing pad of the polishing apparatus. Typically, while continuously supplying the polishing liquid, the polishing pad is pressed against the back surface of the workpiece and the two are relatively moved (for example, rotated).

(Back polishing composition)
The backside polishing composition disclosed herein is not limited to a specific composition, and may be a composition that can have a working strain layer on the backside that has undergone a backside processing step that is performed using the backside polishing composition, or In the case where a working strain layer is present on the front surface, a composition that allows a working strain layer having a depth larger than the processing strain layer depth of the front surface to be present on the back surface is employed. Such a backside polishing composition contains, for example, abrasive grains _ABF and a solvent such as water, and may further contain a polishing aid _CBF such as an oxidizing agent.

As the abrasive grains _ABF for the back surface CMP process, one or more of the above-described back surface processing abrasive grains types can be used. A preferable example of the abrasive grains _ABF used in this step is alumina particles. Alumina particles may be used alone or in combination of two or more. From the viewpoint of workability, the alumina particles preferably contain α-alumina, and more preferably contain α-alumina as a main component (a component that is contained most in the constituent components). In another preferred embodiment, GC is used as the abrasive grains _ABF .

As the abrasive grains _ABF contained in the backside polishing composition, those having an average secondary particle diameter larger than 0.01 μm can be preferably employed. From the viewpoint of polishing efficiency and the like, the average secondary particle diameter of the abrasive grains _ABF is preferably 0.05 μm or more, more preferably 0.1 μm or more, further preferably 0.2 μm or more, and particularly preferably 0.3 μm or more. is there. By using the abrasive grains _ABF having the average secondary particle diameter, it is easy to adjust the processing strain layer depth on the back surface within a suitable range. The upper limit of the average secondary particle diameter of the abrasive grains _ABF is not particularly limited, and is suitably about 5 μm or less. For example, the polishing efficiency and in terms of surface quality, an average secondary particle size preferably 5μm or less of the abrasive _{A BF} than 0.05 .mu.m, preferably 3μm or less of the abrasive _{A BF} least 0.1 [mu] m, 0.3 [mu] m or more 1μm The following abrasive grains _ABF are particularly preferred. For example, an average secondary particle diameter may be less abrasive _{A BF} 0.4 .mu.m or 0.8 [mu] m.

The average secondary particle size of the abrasive grains A _BF used in the CMP process, unless otherwise stated, are measured based on a laser diffraction scattering method. The measurement can be performed using a laser diffraction / scattering particle size distribution measuring apparatus (trade name “LA-950”) manufactured by Horiba.

The content of the abrasive grains _ABF in the back-side polishing composition (when multiple types of abrasive grains are included, the total content thereof) is not particularly limited, but is typically 0.1% by weight or more. In view of shortening the processing time, it is preferably 0.5% by weight or more, more preferably 1% by weight or more, and further preferably 3% by weight or more. By including a predetermined amount or more of abrasive grains _ABF , it is easy to adjust the depth of the processed strain layer on the back surface within a suitable range. From the viewpoint of polishing stability and cost reduction, the content of abrasive grains _{ABF is} usually 20% by weight or less, preferably 15% by weight or less, more preferably 12% by weight or less, and still more preferably. 10% by weight or less. The technique disclosed here is preferable in an embodiment in which the content of abrasive grains _ABF in the backside polishing composition is, for example, 0.1 wt% or more and 20 wt% or less (preferably 3 wt% or more and 8 wt% or less). Can be implemented.

The backside polishing composition disclosed herein preferably contains a polishing aid (typically an oxidizing agent) _CBF . The polishing aid _CBF is a component that enhances the effect of polishing, and typically a water-soluble one is used. Although the polishing aid _CBF is not particularly limited, the polishing aid CBF exhibits an action of altering the surface of the workpiece (for example, oxidative alteration) in polishing, thereby causing weakening of the surface of the workpiece. It is thought that it contributes to the polishing by the grain _ABF .

The polishing aid _CBF includes peroxides such as hydrogen peroxide; nitric acid, nitrates thereof such as iron nitrate, silver nitrate, aluminum nitrate, nitrate complexes such as cerium ammonium nitrate as complexes thereof; potassium peroxomonosulfate, peroxodioxide Persulfuric acid such as sulfuric acid, persulfuric acid compounds such as ammonium persulfate and potassium persulfate; chloric acid and salts thereof, perchloric acid and chlorine compounds such as potassium perchlorate as salts thereof; bromic acid and salts thereof Bromine compounds such as potassium bromate; iodine compounds such as iodic acid, its salts ammonium iodate, periodic acid, its salts such as sodium periodate, potassium periodate; iron acids, its salts Ferric acids such as potassium ferrate; permanganic acid, its salt, permanganate such as sodium permanganate, potassium permanganate; chromic acid, its salt Chromic acids such as potassium chromate and potassium dichromate; vanadic acid and its salts vanadate such as ammonium vanadate, sodium vanadate, sodium metavanadate and potassium vanadate; ruthenium such as perruthenic acid and its salts Molybdic acids such as molybdic acid and its salts ammonium molybdate and disodium molybdate; rhenic acids such as perrhenium and its salts; tungstic acids such as tungstic acid and its salt such as disodium tungstate; It is done. These may be used alone or in combination of two or more. Among these, from the viewpoint of polishing efficiency and the like, permanganic acid or a salt thereof, peroxide, vanadic acid or a salt thereof, periodic acid or a salt thereof is preferable, and sodium permanganate or potassium permanganate is particularly preferable.

In a preferred embodiment, the backside polishing composition contains a composite metal oxide as the polishing aid _CBF . Examples of the composite metal oxide include nitrate metal salts, iron acids, permanganic acids, chromic acids, vanadic acids, ruthenium acids, molybdic acids, rhenic acids, and tungstic acids. Among these, iron acids, permanganic acids, and chromic acids are more preferable, and permanganic acids are more preferable.

In a more preferable embodiment, the composite metal oxide includes a monovalent or divalent metal element (excluding transition metal elements) and a fourth periodic transition metal element in the periodic table. CMO is used. Preferred examples of the monovalent or divalent metal element (excluding transition metal elements) include Na, K, Mg, and Ca. Of these, Na and K are more preferable. Preferable examples of the fourth periodic transition metal element in the periodic table include Fe, Mn, Cr, V, and Ti. Among these, Fe, Mn, and Cr are more preferable, and Mn is more preferable.

Backside polishing composition disclosed herein is, when the composite metal oxide as a grinding aid C _BF (preferably the composite metal oxide CMO) containing, further comprise a grinding aid C _BF except complex metal oxide Well, it does not have to be included. Techniques disclosed herein for the back polishing composition composite metal oxide as a grinding aid C _BF (preferably a composite metal oxide CMO) other than the grinding aid (for example, hydrogen peroxide) C _BF a substantially An embodiment that does not include it can also be preferably implemented.

The concentration (content) of the polishing aid _CBF in the backside polishing composition is usually suitably 0.1% by weight or more. The concentration is preferably 0.3% by weight or more, more preferably 0.5% by weight or more (eg, 0.8% by weight or more) from the viewpoint of achieving both a polishing rate and flatness at a high level and efficiency. From the viewpoint of improving smoothness, the concentration of the polishing aid _CBF is usually suitably 10% by weight or less, preferably 8% by weight or less, and preferably 6% by weight or less (for example, 5%). It is more preferable that the content be less than or equal to 3% by weight.

The backside polishing composition disclosed herein is a chelating agent, a thickener, a dispersant, a surface protective agent, a wetting agent, a pH adjuster, and a surfactant as long as the effects of the technology disclosed herein are not impaired. , Organic acid, organic acid salt, inorganic acid, inorganic acid salt, rust preventive, preservative, antifungal agent, etc., polishing composition (typically for polishing a semiconductor substrate, eg, silicon carbide substrate polishing) You may further contain the well-known additive which can be used for a composition) as needed. The content of the additive may be set as appropriate according to the purpose of the addition, and does not characterize the present invention, so a detailed description is omitted.

The pH of the backside polishing composition is usually about 8.0-12. When the pH of the backside polishing composition is within the above range, a practical polishing rate is easily achieved and handling is easy. The pH of the backside polishing composition is preferably 8.0 to 11, more preferably 8.0 to 10, particularly preferably 8.5 to 9.5 (eg, about 9.0).

In addition, when the back surface processing step is composed of a plurality of processing steps including a CMP step (for example, a plurality of processing steps including a grinding step and a lapping step), the CMP step can be the final step of the back surface processing step. In that case, there is no processing step after the CMP step in the back surface processing step.

A processed strain layer exists on the back surface of the workpiece (which may be a semiconductor substrate) that has undergone the back surface processing step. When a work strain layer is present on the front surface of the workpiece, a work strain layer having a depth greater than the depth of the work strain layer on the front surface is present on the back surface. This makes it possible to highly control the shape of the semiconductor substrate after manufacturing and in the semiconductor device. In addition, the workpiece that has undergone the back surface processing step may have a predetermined surface roughness Ra. The depth of the processing strain layer existing on the back surface that has undergone the back processing step, the difference in processing strain layer depth between the back surface and the front surface, and Ra on the back surface are the depth D of the processing strain layer on the back surface of the semiconductor substrate described above. _Since values similar to _BF , difference (D _BF -D _FF ), and Ra on the back surface can be taken, overlapping description is omitted.

<Front surface machining process>
The semiconductor substrate manufacturing method disclosed herein typically includes a front surface processing step. In the front surface processing step, the front surface of the processing object is processed. Here, the front surface of the object to be processed is a surface that becomes the front surface of the manufactured semiconductor substrate. The front surface processing step is typically a step of making the front surface of the object to be processed a smooth surface, and more specifically, a step of finishing to a high quality surface that becomes a mirror surface.

The front surface processing step disclosed here is not limited to a specific configuration, and a known surface processing technology is appropriately selected in consideration of the above-mentioned back surface processing step, and a processing strain layer is formed on the front surface. It is implemented so that there is no processing strain layer having a depth smaller than the processing strain layer depth of the back surface. Although it does not specifically limit as a front surface processing process, One or two or more processes among a grinding process, a lapping process, a CMP process, etc. may be employ | adopted. The details of the grinding step and the lapping step that can be performed in the front surface processing step are as described in the back surface processing step, and so that the effects of the technique disclosed herein can be preferably obtained, The grinding step and the lapping step in the front surface processing step can be performed by making conditions and matters such as hardness and particle diameter different from those in the back surface processing step.

(Front surface processing abrasive)
Front surface processing step typically includes the step of using the abrasive A _FF. The abrasive A _FF, 1 or more kinds of backside processing abrasive species exemplified above can be mentioned. Of these, silica particles and alumina particles are preferable.

In a preferred embodiment, the abrasive grains _AFF contain silica abrasive grains (silica particles). The silica abrasive grains can be used by appropriately selecting from various known silica particles. Examples of such known silica particles include colloidal silica and dry silica. Of these, the use of colloidal silica is preferred. According to the silica abrasive grains containing colloidal silica, a high polishing rate and good surface accuracy can be suitably achieved.

The shape (outer shape) of the abrasive grain A _FF (eg, silica abrasive grain) may be spherical or non-spherical. For example, specific examples of non-spherical silica abrasive grains include peanut shapes (that is, peanut shell shapes), bowl shapes, confetti shapes, rugby ball shapes, and the like. In the technique disclosed herein, the abrasive grains A _FF (for example, silica abrasive grains) may be in the form of primary particles or may be in the form of secondary particles in which a plurality of primary particles are associated. Further, abrasive grains in the form of primary particles (for example, silica abrasive grains) and abrasive grains in the form of secondary particles (for example, silica abrasive grains) may be mixed. In a preferred embodiment, at least a part of the abrasive grains A _FF (for example, silica abrasive grains) is contained in the polishing composition in the form of secondary particles.

The hardness of the abrasive grains A _FF used in the front surface processing step is not particularly limited. The Vickers hardness H _FF (Hv) of the abrasive grain A _FF is preferably about 200 Hv or more (eg, about 400 Hv or more, typically about 600 Hv or more), for example. In another embodiment, the Vickers hardness H _FF (Hv) of the abrasive grain A _FF is, for example, about 1000 Hv or more (for example, about 1200 Hv or more, typically about 1500 Hv or more). In one embodiment, the Vickers hardness H _FF (Hv) is, for example, about 2500 Hv or less (for example, about 2000 Hv or less, typically about 1700 Hv or less) from the viewpoint of setting the depth of the processed strain layer to a predetermined value or less. It is preferable. In another aspect, the Vickers hardness H _FF (Hv) is preferably about 1500 Hv or less (for example, about 1000 Hv or less, typically about 800 Hv or less). By using abrasive grains whose hardness is lower than that of the front surface of the workpiece, a higher quality surface can be obtained.

As the abrasive grains A _FF (for example, silica abrasive grains), those having an average primary particle diameter (hereinafter sometimes simply referred to as “D1”) larger than 5 nm can be preferably used. From the viewpoint of polishing efficiency and the like, D1 is preferably 15 nm or more, more preferably 20 nm or more, still more preferably 25 nm or more, and particularly preferably 30 nm or more. The upper limit of D1 is not particularly limited, but is appropriately about 120 nm or less, preferably 100 nm or less, more preferably 85 nm or less. For example, from the viewpoint of achieving both the polishing efficiency and surface quality at a higher level, preferably (silica abrasive grains typically) D1 is 80nm or less of the abrasive _{A FF} least 12 nm, 15 nm or more 60nm less abrasive _{A FF} ( Typically, silica abrasive grains) are preferred.

In the technology disclosed herein, the average primary particle diameter of the abrasive grains _{AFF is} the average primary particle diameter (nm) = 6000 / (true density (BET value) from the specific surface area (BET value) measured by the BET method. g / cm ³ ) × BET value (m ² / g)) refers to the particle diameter calculated by the equation. For example, in the case of silica abrasive grains, the average primary particle diameter can be calculated from the average primary particle diameter (nm) = 2727 / BET value (m ² / g). The specific surface area can be measured using, for example, a surface area measuring device manufactured by Micromeritex Corporation, a trade name “Flow Sorb II 2300”.

The average secondary particle diameter of the abrasive grains A _FF (for example, silica abrasive grains) (hereinafter sometimes simply referred to as “D2”) is not particularly limited, but is preferably 20 nm or more from the viewpoint of polishing efficiency and the like. Preferably it is 50 nm or more, More preferably, it is 70 nm or more. Further, from the viewpoint of obtaining a higher quality surface, the average secondary particle diameter D2 of the abrasive grains A _FF (eg, silica abrasive grains) is suitably 500 nm or less, preferably 300 nm or less, more preferably 200 nm or less, More preferably, it is 130 nm or less, Especially preferably, it is 110 nm or less (for example, 100 nm or less).

Incidentally, in the art disclosed herein, the average secondary particle size of the abrasive grains A _FF, for example, by Nikkiso Co. model dynamic light scattering method using "UPA-UT151", volume average particle diameter (volume It can be measured as a standard arithmetic mean diameter; Mv).

In a preferred embodiment, the front surface processing step includes a CMP step. By employing the CMP process, the semiconductor substrate disclosed herein can be easily obtained, and a high-quality surface can be easily obtained. The CMP process according to a preferred embodiment is performed by supplying a polishing slurry (also referred to as a polishing liquid) composed of a polishing composition described later to the surface of the workpiece. Specifically, it may be a step of supplying the polishing liquid to the surface of the object to be processed and polishing by a conventional method as in the case of the CMP step in the back surface polishing composition.

(Front surface polishing composition)
The front surface polishing composition disclosed herein is not limited to a specific composition, and has a depth that is smaller than the back surface processing strain layer depth so that there is no processing strain layer on the front surface. A composition that can be used as a working strain layer is employed. Such polishing composition, for example, abrasive grains, a solvent such as water, comprise may further comprise a grinding aid C _FF such oxidizing agent.

The abrasive A _FF used in the CMP process of the front side, one or more backside processing abrasive species exemplified above can be mentioned. Of these, silica particles and alumina particles are preferable, silica particles are more preferable, and colloidal silica is more preferable. The average primary particle diameter and average secondary particle diameter of the abrasive grains A _FF (for example, silica abrasive grains) that are preferably used are as described above, and redundant description will not be repeated.

The content of the abrasive grains A _FF in the front surface polishing composition, for example, in the case of silica abrasive grains is approximately 12% by weight or more. From the viewpoint of polishing efficiency and the like, the content is preferably 15% by weight or more. In some embodiments, the content may be, for example, 20% by weight or more. Further, from the viewpoint of having both the polishing rate and surface quality at a high level, the content of the abrasive grains A _FF, for example, in the case of silica abrasive grains is approximately 50% by weight or less. The content is preferably 40% by weight or less, more preferably 35% by weight or less. In some embodiments, the content may be, for example, 42% by weight or less, and typically 38% by weight (eg, 35% by weight or less). The technique disclosed here is, for example, an embodiment in which the content of silica abrasive grains in the front surface polishing composition is 12% by weight or more and 35% by weight or less (further 15% by weight or more and 30% by weight or less). It can be preferably implemented.

The content of the abrasive grains A _FF in the front surface polishing composition, for example, in the case of alumina abrasive grains is generally 0.1 wt% or more. From the viewpoint of polishing efficiency and the like, the content is preferably 0.5% by weight or more. In some embodiments, the content may be, for example, 1% by weight or more. Further, from the viewpoint of having both the polishing rate and surface quality at a high level, the content of abrasive grains A _FF, for example if the alumina abrasive grains, is generally 20 wt% or less. The content is preferably 15% by weight or less, more preferably 12% by weight or less. In some embodiments, the content may be, for example, 13% by weight or less, and typically 10% by weight or less (eg, 8% by weight or less). In the technique disclosed herein, for example, the content of alumina abrasive grains in the front surface polishing composition is 0.1 wt% or more and 20 wt% or less (further 3 wt% or more and 8 wt% or less). The embodiment can be preferably implemented.

The front surface polishing composition disclosed herein preferably contains a polishing aid (for example, an oxidizing agent) _CFF . The grinding aids C _FF, can be used without limitation one or more of the grinding aid C _FF exemplified by backside polishing composition. From the viewpoint of achieving both a polishing rate and surface quality at a high level, hydrogen peroxide and vanadic acids are preferable, and it is particularly preferable to use hydrogen peroxide and vanadic acids (for example, sodium metavanadate) in combination.

In a particularly preferred embodiment, the ratio of the content of hydrogen peroxide and vanadic acids (for example, sodium metavanadate) used in combination, that is, the ratio of the content C2 of hydrogen peroxide to the content C1 of vanadic acids (C2 / C1) is: It is not particularly limited, and is suitably 0.5 or more and 2 or less on a weight basis, preferably 0.6 or more and 1.9 or less, more preferably 0.6 or more and 1.5 or less. . By using the above compounds in combination so as to have a specific content ratio, both the polishing rate and the surface quality can be realized at a higher level. In some embodiments, the ratio (C2 / C1) may be, for example, 0.6 or more and 1.2 or less, and typically 0.6 or more and 0.9 or less.

The concentration of grinding aid C _FF in the front surface polishing composition (content) is usually suitable to be 0.1 wt% or more. From the viewpoint of achieving both high and efficient polishing rate and surface quality, the concentration in a preferred embodiment is 1% by weight or more, more preferably 1.5% by weight or more, still more preferably 2% by weight or more, Especially preferably, it is 2.5 weight% or more (for example, 2.8 weight% or more). Further, from the viewpoint of improving smoothness, the concentration of the grinding aid C _FF is usually suitable to be 10 wt% or less, preferably 8 wt% or less, 6.5 wt% or less More preferably, it is more preferably 6% by weight or less, and particularly preferably 5.5% by weight or less. In some embodiments, the concentration may be, for example, 4.5% by weight or less, and typically 4% by weight or less.

The front surface polishing composition disclosed herein is a chelating agent, a thickener, a dispersant, a surface protecting agent, a wetting agent, a pH adjusting agent, as long as the effects of the technology disclosed herein are not impaired. Known additives that can be used for polishing compositions (for example, compositions for polishing silicon carbide substrates) such as surfactants, organic acids, inorganic acids, rust preventives, antiseptics, fungicides, etc., if necessary It may be further contained. The content of the additive may be set as appropriate according to the purpose of the addition, and does not characterize the present invention, so a detailed description is omitted.

The pH of the front surface polishing composition is usually about 2-12. When the pH of the front surface polishing composition is within the above range, a practical polishing rate is easily achieved. The pH of the front surface polishing composition is preferably 3 or more, more preferably 4 or more, and still more preferably 5.5 or more. Although the upper limit of pH is not specifically limited, Preferably it is 12 or less, More preferably, it is 10 or less, More preferably, it is 9.5 or less. The pH is preferably 3 to 11, more preferably 4 to 10, and still more preferably 5.5 to 9.5. The pH of the front surface polishing composition may be, for example, 9 or less, typically 7.5 or less.

In addition, when the front surface processing step is composed of a plurality of processing steps including the CMP step, the CMP step can be the final step of the front surface processing step. In that case, there is no processing step after the CMP step in the front surface processing step. Moreover, when performing the etching process which does not use an abrasive grain in a front surface process process, this etching process can be implemented before and behind the said CMP process.

In one aspect, the front surface processing step may include a step of performing preliminary polishing (preliminary polishing step) and a step of performing final polishing (finishing polishing step). The preliminary polishing step here is a step of performing preliminary polishing on the workpiece. In a typical embodiment, the preliminary polishing process is a polishing process that is arranged immediately before the finishing polishing process. The preliminary polishing process may be a single-stage polishing process or a multi-stage polishing process of two or more stages. In addition, the finish polishing step referred to here is a step of performing finish polishing on the workpiece that has been subjected to preliminary polishing, and is the last of the polishing steps performed using the polishing composition (that is, most) This refers to a polishing step disposed on the downstream side. Thus, in the method including the preliminary polishing step and the finishing polishing step, the above-described front surface polishing composition is typically used in the finishing polishing step. It may be used in both the preliminary polishing process and the finishing polishing process.

Further, the front surface processing step disclosed herein may include any other step in addition to the preliminary polishing step and the finishing polishing step. Examples of such a process include a grinding process and a lapping process performed before the preliminary polishing process. Further, the front surface processing step disclosed herein may include an additional step (cleaning step or polishing step) before the preliminary polishing step or between the preliminary polishing step and the finishing polishing step.

There is no processing strain layer on the front surface of the workpiece (which may be a semiconductor substrate) that has undergone the front surface processing step. Alternatively, when a work strain layer exists on the front surface of the workpiece, the depth of the work strain layer on the front surface is smaller than the depth of the work strain layer on the back surface. This makes it possible to highly control the shape of the semiconductor substrate after manufacturing and in the semiconductor device. In addition, the workpiece that has undergone the front surface machining step may have a predetermined surface roughness Ra. The depth and Ra of the processed strain layer existing on the front surface after the front surface processing step have the same values as the depths _DFF and Ra of the processed strain layer on the front surface of the semiconductor substrate. Since it is obtained, the overlapping description is omitted.

The solvent used in the lapping composition or polishing composition (including backside polishing composition and front surface polishing composition. The same shall apply hereinafter unless otherwise specified) is used for abrasive grains and optional components. There is no particular limitation as long as it can disperse the polishing aid. As the solvent, ion exchange water (deionized water), pure water, ultrapure water, distilled water and the like can be preferably used. The wrapping composition and polishing composition disclosed herein may further contain an organic solvent (lower alcohol, lower ketone, etc.) that can be mixed with water as required. Usually, 90% by volume or more of the solvent contained in the composition is preferably water, and more preferably 95% by volume (typically 99 to 100% by volume) is water.

Moreover, the lapping composition and the polishing composition disclosed herein may be a one-part type or a multi-part type including a two-part type. For example, the liquid A containing a part of the constituent components (typically components other than the solvent) of the polishing composition and the liquid B containing the remaining components are mixed to polish the polishing object. It may be configured to be used. Further, the wrapping composition and polishing composition disclosed herein may be in a concentrated form (that is, in the form of a wrapping liquid or a concentrated liquid of polishing liquid) before being supplied to the object to be processed. Good. The wrapping composition and polishing composition in such a concentrated form are advantageous from the viewpoints of convenience, cost reduction, and the like during production, distribution, storage, and the like. The concentration rate can be, for example, about 2 to 5 times in terms of volume.
In addition, preparation of a wrapping composition or polishing composition may include preparation of a wrapping liquid or polishing liquid by adding operations such as concentration adjustment (for example, dilution) and pH adjustment. Alternatively, the wrapping composition may be used as it is as a wrapping liquid, or the polishing composition may be used as it is as a polishing liquid. In the case of a multi-drug type polishing composition, the above-mentioned polishing liquid is prepared by mixing these agents, diluting one or more agents before the mixing, and after the mixing. Diluting the mixture, etc. can be included.

Also, in the processing steps disclosed herein, a single-side grinding device or a single-side polishing device can be used. In a single-side grinding apparatus, for example, a workpiece is held using a holder called a carrier, and fixed abrasive grains (grinding grindstones) fixed to a surface plate are pressed against one side of the workpiece to relatively hold both of them. One side of the workpiece is ground by moving (for example, rotating). During grinding, a machining fluid composed of an aqueous solution is usually supplied to the surface of the workpiece. Also, in a single-side polishing machine, the workpiece is affixed to the ceramic plate with wax, the workpiece is held using a holder called a carrier, and abrasive grains (polishing composition in the case of polishing) are supplied. On the other hand, one surface of the workpiece is polished by pressing a surface plate or a polishing pad against one surface of the workpiece and relatively moving (for example, rotating) the two.

Also, the processing steps disclosed herein can use a double-side grinding device or a double-side polishing device. In a double-sided grinding machine, a workpiece called a carrier is used to hold a workpiece, and fixed abrasive grains (grinding stones) fixed to a surface plate are pressed against the opposite surface of the workpiece to move them in a relative direction. By rotating, both sides of the workpiece are ground simultaneously. During grinding, a machining fluid composed of an aqueous solution is usually supplied to the surface of the workpiece. Also, in a double-side polishing apparatus, a workpiece is held using a holder called a carrier, and polishing is performed on the opposite surface of the workpiece while supplying abrasive grains (a polishing composition in the case of polishing) from above. By pressing the pad and rotating them in the relative direction, both surfaces of the workpiece are polished simultaneously.

The polishing pad used in the CMP process disclosed herein is not particularly limited. For example, any of a non-woven fabric type, a suede type, a rigid foamed polyurethane type, a product containing abrasive grains, a product containing no abrasive grains, and the like may be used.

The workpiece processed by the method disclosed herein is typically washed after polishing. This washing can be performed using an appropriate washing solution. The cleaning liquid to be used is not particularly limited, and a known and commonly used cleaning liquid can be appropriately selected and used.

<Polishing composition set>
The technology disclosed herein can include, for example, providing the following polishing composition set. That is, according to the technique disclosed herein, a polishing composition set including the composition Q1 and the composition Q2 stored separately from each other is provided. The composition Q1 may be a backside polishing composition (including a concentrated liquid) used in the backside processing step disclosed herein. The composition Q2 may be a front surface polishing composition (including a concentrated liquid) used in the front surface processing step disclosed herein. When a multistage processing process including a back surface processing step and a front surface processing step is performed using the polishing composition set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be preferably manufactured. . Moreover, the obtained semiconductor substrate can have a high surface quality.

<Composition set>
The technology disclosed herein can include, for example, providing the following composition set. That is, according to the technique disclosed here, a composition set including the composition Q3 and the composition Q4 stored separately from each other is provided. The composition Q3 may be a wrapping composition (including a concentrated solution) used in the back surface processing step disclosed herein. The composition Q4 may be a front surface polishing composition (including a concentrated liquid) used in the front surface processing step disclosed herein. When a multistage processing process including a back surface processing step and a front surface processing step is performed using the composition set having such a configuration, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. . Moreover, the obtained semiconductor substrate can have a high surface quality.

<Semiconductor substrate manufacturing set>
The technology disclosed herein can include, for example, providing a semiconductor substrate manufacturing set as follows. That is, according to the technique disclosed herein, a set for manufacturing a semiconductor substrate is provided that includes abrasive grains for grinding and a composition Q5 that are stored separately from each other. The abrasive grains for grinding may be abrasive grains for grinding used in the back surface processing step disclosed herein. The composition Q5 may be a front surface polishing composition (including a concentrated liquid) used in the front surface processing step disclosed herein. When a multistage processing process including a back surface processing step and a front surface processing step is performed using such a set of configurations, a semiconductor substrate whose shape after manufacturing is highly controlled can be manufactured with high processing efficiency. Moreover, the obtained semiconductor substrate can have a high surface quality.

Hereinafter, some examples related to the present invention will be described, but the present invention is not intended to be limited to the examples shown in the examples. In the following description, “%” is based on weight unless otherwise specified.

<Preparation of polishing composition>
(Preparation Example 1)
Polishing composition A was prepared by mixing colloidal silica, sodium metavanadate, hydrogen peroxide, and deionized water. The colloidal silica content was 23%, the sodium metavanadate content was 1.9%, and the hydrogen peroxide content was 1.2%. The pH of the polishing composition was adjusted to 6.5 using potassium hydroxide (KOH). In addition, the colloidal silica used the spherical thing whose average secondary particle diameter is 97 nm.

(Preparation Example 2)
Abrasive composition B was prepared by mixing alumina abrasive grains (α-alumina, average secondary particle size: 0.5 μm), potassium permanganate (KMnO ₄ ) as a polishing aid, and deionized water. The content of alumina abrasive grains was 6%, and the content of KMnO ₄ was 1.2%. The pH of the polishing composition was adjusted to 9.0 using KOH.

<Example 1 to Example 10>
The processing shown in Table 1 was performed on the front and back surfaces of the workpiece. The processing conditions are as follows. In the CMP process, polishing compositions A and B were used as slurries A and B, respectively. GC is a slurry containing green silicon carbide particles as abrasive grains. As a processing object, a 3-inch SiC wafer (conductivity type: n-type, crystal type 4H 4 ° off) was used.

[CMP conditions]
Polishing machine: Product name “SPM-11” manufactured by Fujikoshi Machinery Co., Ltd.
Polishing pad: “SURFIN 019-3” manufactured by Fujimi Incorporated
Polishing pressure: 300 g / cm ²
Surface plate rotation speed: 60 rotations / minute Head rotation speed: 40 rotations / minute (forced drive)
Polishing liquid supply rate: ≧ 20 mL / min (flowing)
Polishing liquid temperature: 25 ° C
Polishing time: until Ra becomes constant

[Wrapping conditions]
Polishing device: Single-side polishing device manufactured by Nippon Engis Co., Ltd. Model “EJ-380IN”
Polishing surface plate: Copper Polishing pressure: 300 g / cm ²
Surface plate rotation speed: 70 rotations / minute Head rotation speed: 40 rotations / minute (forced drive)
Abrasive grain concentration in polishing liquid: 10%
Polishing liquid supply rate: 10 mL / min (flowing)
Polishing liquid temperature: 25 ° C
Polishing time: until Ra becomes constant

[Grinding conditions]
Grinding equipment: Product name “MHG-2000” manufactured by Shuwa Kogyo
Grinding wheel: Diamond wheel (Binder: Vibrido)
Grinding wheel rotation speed: 2000 rotations / minute Workpiece rotation speed: 200 rotations / minute Grinding time: Until Ra becomes constant

<Measurement of processing strain layer depth>
The depth of the processed strain layer on the front and back surfaces of the workpiece was measured by observation (observation magnification: 10 to 200 times) and polishing with a differential interference microscope (trade name “OPTIPHOTO300” manufactured by Nikon Corporation). Specifically, a processing flaw is specified by a differential interference microscope, the specified processing flaw is removed by polishing, and the depth corresponding to the polishing allowance required for the removal is the depth of the processing strain layer [μm]. It was. A method for calculating polishing conditions and polishing allowance is shown below.
[Policing condition]
Polishing device: Single-side polishing device manufactured by Nippon Engis Co., Ltd. Model “EJ-380IN”
Polishing pad: “SUBA800” manufactured by Nitta Haas
Polishing pressure: 300 g / cm ²
Surface plate rotation speed: 80 rotations / minute Polishing time: Until the processing scratch disappears Head rotation speed: 40 rotations / minute Polishing liquid supply rate: 20 mL / minute (flowing)
Polishing liquid temperature: 25 ° C
Polishing liquid: colloidal silica + vanadate + hydrogen peroxide (pH 8)
[Polishing allowance]
Polishing allowance [cm] = SiC wafer weight difference before and after polishing [g] / SiC density [g / cm ³ ] (= 3.21 g / cm ³ ) / Polishing target area [cm ² ] (= 19. 62cm ² )
The measurement results are shown in Table 1.

<Surface roughness Ra>
The surface roughness Ra [nm] was measured on the surface of the processed workpiece according to each example using an atomic force microscope (AFM; trade name “D3100 Nano Scope V”, manufactured by Veeco) under the condition of a measurement area of 10 μm × 10 μm. ] Was measured. The results are shown in Table 1.

<Evaluation of substrate shape>
The warpage of the semiconductor substrate manufactured by the processing method according to each example (unevenness with respect to the front surface) and its degree [μm] were measured by GBIR. For the measurement, a surface shape measuring machine “SURFCOM 1500DX” manufactured by Tokyo Seimitsu Co., Ltd. was used. The warp where the front side is convex is described as “+ X μm”, and the warp where the front side is concave is described as “−X μm”. The results are shown in Table 1.

<Evaluation of substrate shape after film formation>
An epitaxial film was formed on the front surface of the semiconductor substrate manufactured by the processing method according to each example, and the shape of the semiconductor substrate after the epitaxial film was formed was measured by GBIR. An n ⁻ -type SiC layer having a thickness of 30 μm was formed as an epitaxial film. Based on the obtained GBIR measurement results, the following criteria were used for evaluation. The results are shown in Table 1.
[Evaluation criteria]
◎: GBIR 3 μm or less ○: GBIR more than 3 μm and 10 μm or less Δ: GBIR more than 10 μm and 14 μm or less ×: GBIR more than 14 μm

As shown in Table 1, in Examples 1 to 3 and Examples 5 to 8 in which there was no processed strain layer on the front surface and a processed strain layer on the back surface, the evaluation results of the semiconductor substrate shape after film formation Was in an excellent or practically acceptable range. Further, in Example 4 in which the depth of the back-side processed strain layer is larger than that of the front surface even in the substrate having the processed strain layer on the front surface, the evaluation result of the shape of the semiconductor substrate after film formation Was good. This effect can be obtained by appropriately setting the method and conditions for the back surface processing step. In particular, in Example 5, Example 7 and Example 8 in which abrasive grains having a relatively small particle diameter were used in the grinding step and the lapping step, the evaluation results of the semiconductor substrate shape after film formation were excellent. On the other hand, in Examples 9 and 10 where the processing strain layer does not exist on the back surface, the evaluation result of the shape of the semiconductor substrate after film formation was poor.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

Claims

A method for manufacturing a semiconductor substrate including a back surface processing step for processing a back surface of a wafer-like workpiece,
There is a processing strain layer on the back surface that has undergone the back surface processing step,
Manufacturing of a semiconductor substrate, wherein the depth of the processing strain layer existing on the back surface is greater than the depth of the processing strain layer on the front surface of the semiconductor substrate, or there is no processing strain layer on the front surface Method.
The manufacturing method according to claim 1, wherein the back surface processing step is a step of setting the arithmetic average surface roughness Ra of the back surface to 10 nm or less.
The manufacturing method according to claim 1 or 2, wherein the depth of the processing strain layer existing on the back surface is 0.1 µm or more.
The manufacturing method according to any one of claims 1 to 3, wherein the back surface processing step includes a chemical mechanical polishing step.
The manufacturing method according to any one of claims 1 to 3, wherein the back surface processing step includes a lapping step.
The manufacturing method according to any one of claims 1 to 3, wherein the back surface processing step includes a grinding step.
Including a front surface processing step of processing the front surface of the object to be processed;
Both the front surface processing step and the back surface processing step include a step of using abrasive grains,
The manufacturing method according to any one of claims 1 to 6, wherein the abrasive grains used in the back surface processing step have higher hardness than the abrasive grains used in the front surface processing step.
Including a front surface processing step of processing the front surface of the object to be processed;
Both the front surface processing step and the back surface processing step include a step of using abrasive grains,
The manufacturing method according to any one of claims 1 to 7, wherein the abrasive grains used in the back surface processing step have a larger particle diameter than the abrasive grains used in the front surface processing step.
The manufacturing method according to any one of claims 1 to 8, wherein the semiconductor substrate is a semiconductor substrate made of silicon carbide.
A polishing composition set used in the production method according to any one of claims 7 to 9,
A composition Q1 as a back surface polishing composition used in the back surface processing step;
A composition Q2 as a front surface polishing composition used in the front surface processing step,
The polishing composition set in which the composition Q1 and the composition Q2 are stored separately from each other.
The back polishing composition contains abrasive grains A BF,
The front surface polishing composition contains abrasive grains A FF,
The polishing composition set according to claim 10, wherein the abrasive grains ABF are alumina particles or green silicon carbide particles, and the abrasive grains AFF are silica particles or alumina particles.
The backside polishing composition contains a polishing aid CBF ,
The front surface polishing composition contains a polishing aid CFF ,
The grinding aid C BF is permanganic acid or a salt thereof, wherein grinding aid C FF is hydrogen peroxide and vanadium acids, polishing composition set according to claim 11.
A composition set for use in the production method according to any one of claims 7 to 9,
A composition Q3 as a wrapping composition used in the back surface processing step;
Including a composition Q4 as a front surface polishing composition used in the front surface processing step,
The composition set in which the composition Q3 and the composition Q4 are stored separately from each other.
The lapping composition contains abrasive grains A BF,
The front surface polishing composition contains abrasive grains A FF,
The composition set according to claim 13, wherein the abrasive grains ABF are diamond particles, and the abrasive grains AFF are silica particles or alumina particles.
The front surface polishing composition contains a polishing aid CFF ,
The grinding aid C FF is permanganate, permanganate is at least one selected from the group consisting of hydrogen peroxide and vanadium acids composition set forth in claim 14.
A semiconductor substrate manufacturing set used in the manufacturing method according to any one of claims 7 to 9,
Abrasive particles for grinding used in the back surface processing step;
A composition Q5 as a front surface polishing composition used in the front surface processing step,
The set for manufacturing a semiconductor substrate, wherein the abrasive grains for grinding and the composition Q5 are stored separately from each other.
The set for manufacturing a semiconductor substrate according to claim 16, wherein the abrasive grains for grinding are diamond particles, and the abrasive grains AFF are silica particles or alumina particles.
The front surface polishing composition contains a polishing aid CFF ,
The grinding aid C FF is permanganate, permanganate is at least one selected from the group consisting of hydrogen peroxide and vanadium acids, Set for manufacturing a semiconductor substrate according to claim 17.
A semiconductor substrate having a front surface and a back surface,
There is a processing strain layer on the back surface,
The depth of the processing strain layer existing on the back surface is greater than the depth of the processing strain layer on the front surface, or the semiconductor substrate has no processing strain layer on the front surface.