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WO2019163276A1 - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device Download PDF

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Publication number
WO2019163276A1
WO2019163276A1 PCT/JP2018/046786 JP2018046786W WO2019163276A1 WO 2019163276 A1 WO2019163276 A1 WO 2019163276A1 JP 2018046786 W JP2018046786 W JP 2018046786W WO 2019163276 A1 WO2019163276 A1 WO 2019163276A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
semiconductor light
substrate
emitting device
adhesive layer
Prior art date
Application number
PCT/JP2018/046786
Other languages
French (fr)
Japanese (ja)
Inventor
裕幸 萩野
信一郎 能崎
Original Assignee
パナソニック株式会社
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Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to JP2020502052A priority Critical patent/JP7232239B2/en
Publication of WO2019163276A1 publication Critical patent/WO2019163276A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/024Arrangements for thermal management
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/40Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30

Definitions

  • the present disclosure relates to a semiconductor light emitting device including an array type semiconductor light emitting element.
  • this application is the 2016 New Energy and Industrial Technology Development Organization, "High-brightness and high-efficiency next-generation laser technology development / New light source and element technology development for next-generation processing / for high-efficiency processing”
  • semiconductor light-emitting elements such as semiconductor laser elements have been used as light sources for image display devices such as displays and projectors, light sources for in-vehicle headlamps, light sources for industrial lighting and consumer lighting, or laser welding devices, thin film annealing devices, and lasers. It attracts attention as a light source for various uses such as a light source for industrial equipment such as processing equipment.
  • a semiconductor laser element used as a light source for the above applications is desired to have a high output that greatly exceeds 1 watt.
  • a technique for increasing the output of a semiconductor laser element As a technique for increasing the output of a semiconductor laser element, a technique of forming an array by arranging a plurality of wide waveguides in parallel is widely used.
  • a high-power semiconductor laser device In such a high-power semiconductor laser device, a large amount of heat is generated during a high-power operation. Therefore, it is important to efficiently dissipate the heat generated in the waveguide in order to increase the power.
  • heat is diffused by connecting a material having high thermal conductivity in the vicinity of the waveguide, and the heat is radiated to the outside through a metal package or the like.
  • Patent Document 1 discloses a conventional array type semiconductor laser element.
  • FIG. 7 is a schematic front view showing a configuration of a conventional array type semiconductor laser device 1010 disclosed in Patent Document 1.
  • FIG. 7 is a schematic front view showing a configuration of a conventional array type semiconductor laser device 1010 disclosed in Patent Document 1.
  • a conventional array type semiconductor laser device 1010 has a plurality of stripes 1011 to 1014 arranged in a line at a predetermined interval. Each of the plurality of stripes 1011 to 1014 is a light emitting portion that becomes a waveguide of laser light.
  • the array type semiconductor laser element 1010 has a plurality of laser electrodes 1008 provided separately corresponding to each stripe.
  • the plurality of laser electrodes 1008 of the array type semiconductor laser element 1010 are arranged at positions facing the plurality of metal wiring bodies 1007 provided on the support body 1003, respectively.
  • the plurality of laser electrodes 1008 are thermocompression bonded via a plurality of metal wiring bodies 1007 and conductive adhesives 1006 such as solder.
  • the plurality of laser electrodes 1008 and the plurality of metal wiring bodies 1007 are electrically connected, and the array type semiconductor laser element 1010 is physically fixed to the support body 1003. Further, a resin 1009 having good thermal conductivity is filled between the array type semiconductor laser element 1010 and the support 1003.
  • the temperature distribution of the plurality of waveguides becomes non-uniform. Specifically, among the plurality of waveguides, the temperature of the waveguide located on the center side in the arrangement direction of the plurality of waveguides becomes higher than the temperature of the waveguide located on the end side.
  • the temperature distribution is non-uniform, so that the deterioration of the light output characteristics of the waveguide in the high-temperature portion proceeds faster than the low-temperature portion due to the non-uniform temperature distribution.
  • This disclosure is intended to provide a semiconductor light emitting device that suppresses deterioration in reliability by suppressing nonuniformity of temperature distribution between light emitting portions.
  • one aspect of a semiconductor light emitting device includes a semiconductor light emitting element including a substrate and three or more light emitting units arranged along an upper surface of the substrate, and the substrate. And a first adhesive layer that bonds the semiconductor light emitting element to the first base, and the substrate has a thermal conductivity higher than that of the first adhesive layer.
  • the thickness of the first adhesive layer is higher at the center side in the arrangement direction of the three or more light emitting portions than at both end portions.
  • the heat dissipation at the center side of the first adhesive layer is enhanced from both end portions. Can do. Thereby, it can suppress that the light emission part of the center side of an arrangement direction among three or more light emission parts becomes high temperature rather than the light emission part of both edge parts due to the thermal interference with an adjacent light emission part. . Therefore, since the nonuniformity of the temperature distribution in three or more light emitting units can be suppressed, deterioration of the reliability of the semiconductor light emitting device can be suppressed.
  • the thickness of the substrate may be larger than both end portions on the central side in the arrangement direction.
  • the lower surface of the substrate may be inclined so that a central side in the arrangement direction is convex.
  • the upper surface of the substrate may be parallel to a bonding surface with the first adhesive layer of the first base in the arrangement direction.
  • the propagation direction of the emitted light from the semiconductor light emitting element and the upper surface of the first base are substantially parallel, the upper surface of the first base can be used as a reference for alignment of the optical axis. Therefore, it is possible to realize a semiconductor light emitting device that can easily adjust the optical axis.
  • a second base disposed on the opposite side of the first base across the semiconductor light emitting element, and the semiconductor light emitting element in the second A second adhesive layer that adheres to the base.
  • both sides of the semiconductor light emitting element are sandwiched between the bases. Therefore, the heat dissipation of the semiconductor light emitting device can be further improved by forming each base with a member having high thermal conductivity.
  • the first base may have a thermal conductivity higher than that of the first adhesive layer.
  • one aspect of a semiconductor light emitting device includes a semiconductor light emitting element including a substrate and three or more light emitting units arranged along an upper surface of the substrate, and the substrate. And a first adhesive layer that adheres the semiconductor light-emitting element to the first base, the first base being more heated than the first adhesive layer.
  • the conductivity is high, and the thickness of the first adhesive layer is smaller than both end portions on the center side in the arrangement direction of the three or more light emitting portions.
  • the heat dissipation at the center side of the first adhesive layer is reduced at both end sides. Can be increased. Thereby, it can suppress that the light emission part of the center side of an arrangement direction among three or more light emission parts becomes high temperature rather than the light emission part of both edge parts due to the thermal interference with an adjacent light emission part. . Therefore, since the nonuniformity of the temperature distribution in three or more light emitting units can be suppressed, deterioration of the reliability of the semiconductor light emitting device can be suppressed.
  • the thickness of the first base may be larger than both end portions on the center side in the arrangement direction.
  • deterioration in reliability can be suppressed by suppressing nonuniformity of the temperature distribution between the light emitting units.
  • FIG. 1A is a schematic top view illustrating a configuration of a semiconductor light emitting element according to an embodiment.
  • FIG. 1B is a schematic cross-sectional view showing the configuration of the semiconductor light emitting element according to the embodiment.
  • FIG. 2A is a cross-sectional view illustrating a process of forming each of the first semiconductor layer, the light emitting layer, and the second semiconductor layer in the method for manufacturing a semiconductor light emitting element according to the embodiment.
  • FIG. 2B is a cross-sectional view showing a step of forming a first protective film in the method for manufacturing a semiconductor light emitting element according to the embodiment.
  • FIG. 2C is a cross-sectional view showing a step of patterning the first protective film in the method for manufacturing the semiconductor light emitting device according to the embodiment.
  • FIG. 2D is a cross-sectional view illustrating a process of forming a waveguide portion and a flat portion in the method for manufacturing a semiconductor light emitting element according to the embodiment.
  • FIG. 2E is a cross-sectional view showing a step of forming a dielectric layer in the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 2F is a cross-sectional view showing the step of forming the p-side electrode in the method for manufacturing the semiconductor light emitting device according to the embodiment.
  • FIG. 2G is a cross-sectional view showing a step of forming a pad electrode in the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 2H is a cross-sectional view showing a step of forming a convex shape on the lower surface of the substrate in the method for manufacturing a semiconductor light emitting element according to the embodiment.
  • FIG. 2I is a cross-sectional view illustrating a process of forming an n-side electrode in the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 3A is a schematic cross-sectional view showing the configuration of the semiconductor light emitting device according to the embodiment.
  • FIG. 3B is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to a modification of the embodiment.
  • FIG. 4 is a graph showing an outline of the temperature of each waveguide portion of the semiconductor light emitting device according to the embodiment.
  • FIG. 5A is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 1.
  • FIG. 5B is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 2.
  • FIG. 5C is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 3.
  • FIG. 5D is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 4.
  • FIG. 6 is a schematic cross-sectional view showing a configuration of a semiconductor light emitting device according to Modification 5.
  • FIG. 7 is a schematic front view showing a configuration of a conventional array type semiconductor laser device.
  • the X axis, the Y axis, and the Z axis represent the three axes of the three-dimensional orthogonal coordinate system.
  • the X axis and the Y axis are orthogonal to each other, and both are orthogonal to the Z axis.
  • FIGS. 1A and 1B are a schematic top view and a cross-sectional view showing the configuration of the semiconductor light emitting device 1 according to the present embodiment, respectively.
  • 1B is a cross-sectional view of the semiconductor light emitting device 1 taken along the line IB-IB in FIG. 1A.
  • the semiconductor light emitting element 1 is an element having a substrate 10 and three or more light emitting units arranged along the upper surface of the substrate 10. As shown in FIG. 1B, in the present embodiment, the semiconductor light emitting element 1 has five light emitting portions 71 to 75 arranged in the X-axis direction of FIG. 1B along the main surface of the substrate 10. The arrangement direction of the five light emitting units 71 to 75 coincides with the X-axis direction shown in each drawing. Hereinafter, the arrangement direction of the five light emitting portions 71 to 75 is also simply referred to as “the arrangement direction”.
  • the semiconductor light emitting device 1 is a semiconductor laser device including a nitride semiconductor material. As shown in FIG. 1B, the substrate 10, the first semiconductor layer 20, the light emitting layer 30, and the second A semiconductor layer 40, an electrode member 50, a dielectric layer 60, and an n-side electrode 80 are provided.
  • the second semiconductor layer 40 includes waveguide portions 40a1 to 40a5 composed of stripe-shaped convex portions extending in the laser resonator length direction (Y-axis direction in FIG. 1B), and each waveguide portion. And a flat portion 40b extending in the horizontal direction (in other words, in the X-axis direction in FIG. 1B).
  • the positions of the waveguide portions 40a1 to 40a5 correspond to the positions of the light emitting portions 71 to 75, respectively.
  • the number of waveguide portions provided in the semiconductor light emitting device 1 may be three or more, and may be five or more in order to operate the semiconductor light emitting device 1 with high light output (for example, watt class). .
  • the semiconductor light emitting element 1 has five waveguide portions 40a1 to 40a5.
  • the waveguide portions 40a1 to 40a5 are arranged in parallel to each other. Thereby, light is emitted in the same direction from each light emitting part corresponding to each waveguide part.
  • each waveguide part (the distance between the centers of each waveguide part) are not particularly limited.
  • the width of each waveguide portion in the X-axis direction is 1 ⁇ m or more and 100 ⁇ m or less, and the interval between adjacent waveguide portions is 50 ⁇ m or more and 1000 ⁇ m or less.
  • the width of each waveguide portion may be 10 ⁇ m or more and 50 ⁇ m or less, and the interval between adjacent waveguide portions may be 300 ⁇ m or more and 500 ⁇ m or less.
  • the width of each waveguide portion is 30 ⁇ m and the interval is 400 ⁇ m.
  • the intervals between the waveguide portions need not be equal in the semiconductor light emitting device 1. In consideration of the influence of temperature distribution, stress, etc. in the semiconductor light emitting device 1, the intervals between the waveguide portions may be made non-uniform.
  • each waveguide part is not particularly limited, but as an example, it is 100 nm or more and 1 ⁇ m or less.
  • the semiconductor light emitting element 1 may have a thickness of 300 nm to 800 nm. In the present embodiment, the height of each waveguide portion is 600 nm.
  • the substrate 10 is, for example, a GaN substrate.
  • an n-type hexagonal GaN substrate whose main surface is a (0001) plane is used as the substrate 10.
  • the first semiconductor layer 20 is disposed above the substrate 10.
  • the first semiconductor layer 20 is an n-side cladding layer made of n-type AlGaN, for example.
  • the light emitting layer 30 is disposed above the first semiconductor layer 20.
  • the light emitting layer 30 is made of a nitride semiconductor.
  • the light emitting layer 30 includes, in order from the first semiconductor layer 20 side, an n-side light guide layer 31 made of n-GaN, an active layer 32 made of an InGaN quantum well layer, and p-GaN.
  • the p-side light guide layer 33 is made of a laminated structure.
  • the light emitting layer 30 includes light emitting portions 71 to 75.
  • the light emitting portions 71 to 75 are portions disposed at positions corresponding to the waveguide portions 40a1 to 40a5, and are portions where most of the light emitted from the semiconductor light emitting element 1 is generated and propagated.
  • each light emitting section is arranged below each waveguide section (that is, the lower side in FIG. 1B).
  • the width of each light emitting section (that is, the width in the X-axis direction in FIG. 1B) is approximately the same as the width of each waveguide section (that is, the width in the X-axis direction in FIG. 1B). Note that light may be generated or propagated in portions other than the light emitting portions 71 to 75.
  • the second semiconductor layer 40 is disposed above the light emitting layer 30.
  • the second semiconductor layer 40 includes, in order from the light emitting layer 30 side, an electron barrier layer 41 made of AlGaN, a p-side cladding layer 42 made of a p-type AlGaN layer, and p-type GaN.
  • a p-side contact layer 43 is laminated. The p-side contact layer 43 is formed as the uppermost layer of the waveguide portions 40a1 to 40a5.
  • These layers can be formed with a substantially uniform film thickness by adjusting the growth conditions.
  • the p-side cladding layer 42 has a convex portion.
  • the convex portions of the p-side cladding layer 42 and the p-side contact layer 43 constitute striped waveguide portions 40a1 to 40a5.
  • the p-side cladding layer 42 has a flat portion as a flat portion 40b on both sides of each waveguide portion. That is, the uppermost surface of the flat portion 40b is the surface of the p-side cladding layer 42, and the p-side contact layer 43 is not formed on the uppermost surface of the flat portion 40b.
  • the electrode member 50 is disposed above the second semiconductor layer 40.
  • the electrode member 50 is wider than each waveguide part. That is, the width of the electrode member 50 (width in the X-axis direction) is larger than the width of each waveguide portion (width in the X-axis direction).
  • the electrode member 50 is in contact with the dielectric layer 60 and the upper surface of each waveguide portion.
  • the electrode member 50 includes a p-side electrode 51 for supplying a current to each light emitting portion, and a pad electrode 52 disposed above the p-side electrode 51.
  • the p-side electrode 51 is in contact with the upper surface of each waveguide part.
  • the p-side electrode 51 is an ohmic electrode that is in ohmic contact with the p-side contact layer 43 above each waveguide portion, and is in contact with the upper surface of the p-side contact layer 43 that is the upper surface of each waveguide portion.
  • the p-side electrode 51 is formed using a metal material such as Pd, Pt, or Ni, for example. In the present embodiment, the p-side electrode 51 has a two-layer structure of Pd / Pt.
  • the pad electrode 52 is wider than each waveguide part and is in contact with the dielectric layer 60. That is, the pad electrode 52 is formed so as to cover each waveguide part and the dielectric layer 60.
  • the pad electrode 52 is formed using a metal material such as Ti, Ni, Pt, or Au, for example. In the present embodiment, the pad electrode 52 has a three-layer structure of Ti / Pt / Au.
  • the pad electrode 52 is formed on the inner side of the dielectric layer 60 (that is, the first electrode) in the top view of the semiconductor light emitting device 1 in order to improve the yield when the semiconductor light emitting device 1 is separated. 2 inside the semiconductor layer 40). That is, when the semiconductor light emitting element 1 is viewed from above, the pad electrode 52 is not formed on the peripheral edge of the semiconductor light emitting element 1. Thereby, the semiconductor light emitting device 1 has a non-current injection region where no current is supplied to the periphery of the end portion. Moreover, the cross-sectional shape perpendicular
  • the dielectric layer 60 is an insulating film disposed on the side surface of each waveguide portion in order to confine light. Specifically, the dielectric layer 60 is continuously formed from the side surface (that is, the surface intersecting the X-axis direction in FIG. 1B) of each waveguide portion to the flat portion 40b. In the present embodiment, the dielectric layer 60 is continuous over the side surface of the p-side contact layer 43, the side surface of the convex portion of the p-side cladding layer 42, and the upper surface of the p-side cladding layer 42 around each waveguide portion. Is formed. In this embodiment, the dielectric layer 60 is formed of SiO 2.
  • the shape of the dielectric layer 60 is not particularly limited, but the dielectric layer 60 may be in contact with the side surface of each waveguide portion and the flat portion 40b. Thereby, it is possible to stably confine light emitted directly under each waveguide portion.
  • an end face coating film such as a dielectric multilayer film is formed on the light emitting end face.
  • This end face coating film is difficult to be formed only on the end face, and also extends around the upper surface of the semiconductor light emitting element 1.
  • the pad electrode 52 is not formed at the end of the semiconductor light emitting element 1 in the laser resonator length direction (that is, the Y-axis direction in FIGS. 1A and 1B)
  • the end face coat film does not reach the upper surface.
  • the dielectric layer 60 and the end face coating film may be in contact with each other at the end in the longitudinal direction of the semiconductor light emitting device 1.
  • the film thickness of the dielectric layer 60 may be 100 nm or more.
  • the thickness of the dielectric layer 60 may be less than the height of each waveguide portion.
  • etching damage may remain on the side surface and the flat portion 40b of each waveguide portion in the etching process when forming each waveguide portion, resulting in leakage current.
  • generation of unnecessary leakage current can be reduced by covering each waveguide portion and the flat portion 40b with the dielectric layer 60.
  • the n-side electrode 80 is an electrode disposed below the substrate 10 and is an ohmic electrode in ohmic contact with the substrate 10.
  • the n-side electrode 80 is a laminated film made of Ti / Pt / Au, for example.
  • the configuration of the n-side electrode 80 is not limited to this.
  • the n-side electrode 80 may be a laminated film in which Ti and Au are laminated.
  • the thickness of the substrate 10 varies depending on the position of the waveguide portions 40a1 to 40a5 in the arrangement direction (X-axis direction).
  • the thickness of the substrate 10 immediately below each waveguide portion is defined as d1, d2, d3, d4, and d5 in order from directly below the leftmost waveguide portion.
  • the thickness of the substrate 10 immediately below the light emitting portions 71 to 75 is defined as d1 to d5, respectively.
  • the substrate thickness immediately below each waveguide portion is perpendicular to the boundary surface between the substrate 10 and the first semiconductor layer 20 through the center in the width direction (X-axis direction) of each waveguide portion (or each light emitting portion).
  • the thickness of the substrate 10 is between the leftmost waveguide portion 40a1 and the central waveguide portion 40a3, and between the rightmost waveguide portion 40a5 and the central waveguide portion 40a3. Changes continuously, and there is a relationship of d3> d1 and d3> d5. That is, the thickness of the substrate 10 is larger than both end portions on the center side in the arrangement direction. Further, the lower surface of the substrate 10 (the lower surface in FIG. 1B) is inclined so that the central side in the arrangement direction is convex. The operation and effect of the semiconductor light emitting device 1 having the substrate 10 as described above will be described later.
  • FIGS. 2A to 2I are cross-sectional views showing each step in the method for manufacturing the semiconductor light emitting device 1 according to the embodiment.
  • a substrate 10 which is an n-type hexagonal GaN substrate having a (0001) plane as a main surface, using an organic metal vapor deposition method (MOCVD method), The first semiconductor layer 20, the light emitting layer 30, and the second semiconductor layer 40 are sequentially formed.
  • MOCVD method organic metal vapor deposition method
  • an n-side cladding layer made of n-type AlGaN is grown as a first semiconductor layer 20 on the substrate 10 having a thickness of 400 ⁇ m by 3 ⁇ m.
  • an n-side light guide layer 31 made of n-GaN is grown by 0.1 ⁇ m.
  • an active layer 32 having three periods of a barrier layer made of InGaN and an InGaN quantum well layer is grown.
  • a p-side light guide layer 33 made of p-GaN is grown by 0.1 ⁇ m.
  • an electron barrier layer 41 made of AlGaN is grown by 10 nm.
  • a p-side contact layer 43 made of p-GaN is grown by 0.05 ⁇ m.
  • TMG trimethylgallium
  • TMA trimethylammonium
  • TMI trimethylindium
  • NH 3 ammonia
  • a first protective film 91 is formed on the second semiconductor layer 40. Specifically, a 300 nm thick silicon oxide film (SiO 2 ) is formed as the first protective film 91 on the p-side contact layer 43 by plasma CVD (Chemical Vapor Deposition) using silane (SiH 4 ). To do.
  • SiO 2 silicon oxide film
  • the film formation method of the first protective film 91 is not limited to the plasma CVD method.
  • a known film formation method such as a thermal CVD method, a sputtering method, a vacuum evaporation method, or a pulse laser film formation method is used. Can be used.
  • the material for forming the first protective film 91 is not limited to the above, and for example, a second semiconductor layer 40 (a p-side cladding layer 42 and a p-side contact layer 43) described later, such as a dielectric or a metal. Any material may be used as long as it is selective with respect to the etching.
  • the first protective film 91 is selectively removed by using a photolithography method and an etching method so that the first protective film 91 remains in a strip shape.
  • an etching method for example, dry etching by reactive ion etching (RIE) using a fluorine-based gas such as CF 4 or wet etching using hydrofluoric acid (HF) diluted to about 1:10 is used. Can be used.
  • the p-side contact layer 43 and the p-side cladding layer 42 are etched using the first protective film 91 formed in a band shape as a mask, so that the waveguide portion is formed in the second semiconductor layer 40.
  • 40a1 to 40a5 and a flat portion 40b are formed.
  • dry etching by RIE using a chlorine-based gas such as Cl 2 may be used.
  • the strip-shaped first protective film 91 is removed by wet etching using hydrofluoric acid or the like, and then the dielectric is formed so as to cover the p-side contact layer 43 and the p-side cladding layer 42.
  • the body layer 60 is formed. That is, the dielectric layer 60 is formed on the waveguide portions 40a1 to 40a5 and the flat portion 40b.
  • a silicon oxide film (SiO 2 ) having a thickness of 300 nm is formed by a plasma CVD method using silane (SiH 4 ).
  • the film formation method of the dielectric layer 60 is not limited to the plasma CVD method, and a film formation method such as a thermal CVD method, a sputtering method, a vacuum deposition method, or a pulse laser film formation method may be used.
  • the p-side electrode 51 made of Pd / Pt is formed only on the waveguide portions 40a1 to 40a5 by using a vacuum deposition method and a lift-off method. Specifically, the p-side electrode 51 is formed on the p-side contact layer 43 exposed from the dielectric layer 60.
  • the film formation method of the p-side electrode 51 is not limited to the vacuum evaporation method, and may be a sputtering method or a pulse laser film formation method.
  • the electrode material of the p-side electrode 51 may be any material that is in ohmic contact with the second semiconductor layer 40 (p-side contact layer 43), such as Ni / Au or Pt.
  • a pad electrode 52 is formed so as to cover the p-side electrode 51 and the dielectric layer 60.
  • a resist is patterned on a portion other than a portion to be formed by a photolithography method or the like, and a pad electrode 52 made of Ti / Pt / Au is formed on the entire upper surface of the substrate 10 by a vacuum deposition method or the like. Use to remove unnecessary portions of the electrode.
  • a pad electrode 52 having a predetermined shape can be formed on the p-side electrode 51 and the dielectric layer 60.
  • the electrode member 50 including the p-side electrode 51 and the pad electrode 52 is formed.
  • the substrate 10 is thinned. This is for the purpose of facilitating singulation and improving heat dissipation.
  • the substrate 10 can be thinned by physical and chemical polishing using abrasive grains and a chemical solution.
  • the substrate 10 having a thickness of 400 ⁇ m is thinned to a thickness of about 85 ⁇ m.
  • the thickness distribution of the substrate can be controlled by installing the substrate 10 obliquely with respect to the polishing surface. Specifically, the substrate was polished with an inclination of about 0.1 degree with respect to the polishing table so that the center portion of the substrate was about 3 ⁇ m thicker than the end portion of the substrate.
  • d1 85 ⁇ m
  • d2 87 ⁇ m
  • d3 88 ⁇ m
  • d4 86 ⁇ m
  • d5 84 ⁇ m by polishing.
  • a convex shape can be formed on the lower surface of the substrate 10.
  • the substrate thickness distribution can be adjusted by a method other than polishing, for example, dry etching.
  • Plasma is generated by applying a high voltage to the reactive gas, and etching proceeds when ions or radicals in the plasma collide with the wafer. At this time, if there is a difference in plasma density or energy, the etching amount can be adjusted according to the position of the substrate 10.
  • the etching amount can be adjusted according to the position of the substrate 10 by supplying the gas to be supplied from the edge of the wafer and exhausting it from the center of the wafer.
  • a lot of plasma is generated on the upstream side of the gas supply and decreases on the downstream side.
  • a large amount of etching proceeds on the upstream side and a small amount proceeds on the downstream side.
  • the etching amount can be adjusted according to the position of the substrate 10 by changing the distribution of the applied high voltage.
  • the etching amount can be changed in accordance with the position of the substrate 10 by applying a high voltage to the edge of the wafer and applying a voltage lower than this at the center.
  • an n-side electrode 80 is formed on the lower surface of the substrate 10. Specifically, an n-side electrode 80 made of Ti / Pt / Au is formed on the back surface of the substrate 10 by vacuum deposition or the like, and patterned by using a photolithography method and an etching method, whereby an n-side electrode having a predetermined shape is formed. 80 is formed. Thereby, the semiconductor light emitting element 1 according to the present embodiment can be manufactured.
  • FIG. 3A is a schematic cross-sectional view showing the configuration of the semiconductor light emitting device 2 according to the present embodiment.
  • the semiconductor light emitting device 2 includes a semiconductor light emitting element 1 and a submount 100.
  • the submount 100 includes a first base 101, a first electrode 102a, a third electrode 102b, a first adhesive layer 103a, and a third adhesive layer 103b.
  • the first base is a base disposed below the substrate 10 of the semiconductor light emitting element 1 and functions as a heat sink.
  • the material of the first base 101 is not particularly limited, but ceramics such as aluminum nitride (AlN) and silicon carbide (SiC), diamond (C) formed by CVD, Cu, Al, etc.
  • the metal may be composed of a material having a thermal conductivity equivalent to or higher than that of the semiconductor light emitting device 1 such as a simple metal or an alloy such as CuW.
  • the first electrode 102 a is disposed on one surface of the first base 101.
  • the third electrode 102 b is disposed on the other surface of the first base 101.
  • the first electrode 102 a is disposed on the surface of the first base 101 on the semiconductor light emitting element 1 side.
  • the first electrode 102a and the third electrode 102b are, for example, a laminated film composed of three metal films of Ti having a thickness of 0.1 ⁇ m, Pt having a thickness of 0.2 ⁇ m, and Au having a thickness of 0.2 ⁇ m.
  • the first adhesive layer 103a is an adhesive layer that adheres the semiconductor light emitting element 1 to the first base.
  • the first adhesive layer 103a is disposed above the first electrode 102a.
  • the third adhesive layer 103b is formed above the third electrode 102b.
  • the first adhesive layer 103a and the third adhesive layer 103b are eutectic solder made of a gold-tin alloy containing, for example, 70% and 30% content of Au and Sn, respectively.
  • the maximum thickness of the first adhesive layer 103a and the third adhesive layer 103b is about 6 ⁇ m.
  • the first adhesive layer 103 a has a lower thermal conductivity than the substrate 10 and the first base 101 of the semiconductor light emitting device 1.
  • the semiconductor light emitting device 1 is mounted on the submount 100.
  • the n-side electrode 80 of the semiconductor light-emitting element 1 is connected to the submount 100.
  • the first adhesive layer 103a To the first adhesive layer 103a.
  • the upper surface of the substrate 10 of the semiconductor light emitting element 1 is parallel to the bonding surface of the first base 101 with the first adhesive layer 103a in the arrangement direction of the light emitting portions 71 to 75.
  • the semiconductor light-emitting device 2 with easy optical axis adjustment is realizable.
  • the thickness of the first adhesive layer 103a immediately below the five waveguide portions 40a1 to 40a5 is set to s1, s2, s3 in order from the left. , S4 and s5.
  • s1 4.2 ⁇ m
  • s2 2.1 ⁇ m
  • s3 1.0 ⁇ m
  • s4 2.9 ⁇ m
  • s5 4.8 ⁇ m.
  • s3 ⁇ s1 and s3 ⁇ s5 between s1, s3, and s5. That is, the thickness s3 of the first adhesive layer 103a at the center is thinner than the thicknesses s1 and s5 of the first adhesive layer 103a at the end. Further, the thickness of the first adhesive layer 103 a is thicker than the difference in thickness between the center portion of the substrate 10 and the end portion of the substrate 10.
  • the gold tin solder when mounting on the first adhesive layer 103a using gold tin solder, the gold tin solder causes a eutectic reaction with the gold of the n-side electrode 80 and the gold of the first electrode 102a. , It may be difficult to determine the boundary.
  • the thickness of the first adhesive layer 103a here is a layer that does not eutectic react with gold tin of the first electrode 102a from a layer that does not eutectic react with gold tin of the n-side electrode 80 (for example, Pt). It is defined as the distance to (for example, Pt).
  • the submount 100 is mounted on, for example, a metal package for the purpose of improving heat dissipation and simplifying handling. That is, it adheres to the metal package by the third adhesive layer 103b.
  • the first base 101 itself may function as a package. In this case, the submount 100 may not include the third adhesive layer 103b.
  • the semiconductor light emitting element 1 is junction-up mounted, but a mounting form in which the electrode member 50 side of the semiconductor light emitting element 1 is connected to the submount 100, that is, junction down mounting is applied. May be.
  • junction down mounting a mounting form in which the electrode member 50 side of the semiconductor light emitting element 1 is connected to the submount 100, that is, junction down mounting is applied. May be.
  • FIG. 3B such an implementation will be described with reference to FIG. 3B.
  • FIG. 3B is a schematic cross-sectional view showing a configuration of a semiconductor light emitting device 3 according to a modification of the present embodiment.
  • the semiconductor light emitting device 3 according to this modification includes a semiconductor light emitting element 1, a submount 300, and a heat dissipation part 200.
  • the submount 300 includes a second base 301, a second electrode 302a, a fourth electrode 302b, a second adhesive layer 303a, and a fourth adhesive layer 303b.
  • the heat radiating unit 200 includes a first base 201 and a first adhesive layer 203.
  • the first base 201 is a base disposed below (upper side of FIG. 3B) below the lower surface (upper side surface of FIG. 3B) of the substrate 10 of the semiconductor light emitting element 1.
  • the first adhesive layer 203 is an adhesive layer that adheres the semiconductor light emitting element 1 to the first base 201.
  • the second base 301 is a base disposed on the opposite side of the first base 201 with the semiconductor light emitting element 1 interposed therebetween.
  • the second adhesive layer 303 a is an adhesive layer that adheres the semiconductor light emitting element 1 to the second base 301.
  • the second electrode 302 a is disposed on one surface of the second base 301.
  • the fourth electrode 302b is disposed on the other surface of the second base 301.
  • the second electrode 302a is disposed on the surface of the second base 301 on the semiconductor light emitting element 1 side.
  • the second base 301 and the first base 201 according to this modification have the same configuration as the first base 101 of the semiconductor light emitting device 2. Further, the second electrode 302a and the fourth electrode 302b according to this modification have the same configuration as the first electrode 102a and the third electrode 102b of the semiconductor light emitting device 2.
  • the fourth adhesive layer 303b has the same configuration as the third adhesive layer 103b of the semiconductor light emitting device 2.
  • the electrode member 50 of the semiconductor light emitting element 1 is connected to the second adhesive layer 303 a of the submount 300.
  • the second adhesive layer 303a is eutectic solder having a maximum thickness of about 3 ⁇ m made of, for example, a gold-tin alloy of Au (70%) and Sn (30%).
  • the heat dissipation part 200 is also connected to the n-side electrode 80 side.
  • a first adhesive layer 203 is formed on one surface of the heat radiating portion 200, and the first adhesive layer 203 is connected to the n-side electrode 80.
  • the heat dissipation of the semiconductor light-emitting device 3 can be improved by sandwiching both sides of the semiconductor light-emitting element 1 with a material having high thermal conductivity.
  • the thickness of the first adhesive layer 203 to which the n-side electrode 80 of the semiconductor light emitting element 1 is connected differs between the center portion and the end portion.
  • the thickness of the first adhesive layer 203 is defined as w1, w2, w3, w4, and w5.
  • the thickness (d1 to d5) of the substrate 10 is the same as that of the semiconductor light emitting device 2.
  • w1 4.3 ⁇ m
  • w2 2.2 ⁇ m
  • w3 1.2 ⁇ m
  • w4 3.1 ⁇ m
  • w5 5.1 ⁇ m.
  • the first adhesive layer 203 is formed on a laminated film composed of three metal films of Ti having a thickness of 0.1 ⁇ m, Pt having a thickness of 0.2 ⁇ m, and Au having a thickness of 0.2 ⁇ m. Further, a eutectic solder having a maximum thickness of about 6 ⁇ m made of a gold-tin alloy containing Au and Sn at a content of 70% and 30%, respectively, is formed. In this case, since the n-side electrode 80 and the heat dissipation part 200 can be firmly connected, the heat from the semiconductor light emitting element 1 can be efficiently exhausted.
  • the first adhesive layer 203 for example, a soft material such as gold for the first base 201 and the substrate 10 can be used.
  • the semiconductor light emitting device 1 since the first adhesive layer 203 and the n-side electrode 80 are only in contact with each other, the semiconductor light emitting device 1 cannot be fixed, but heat from the laser can be exhausted. Further, in this configuration, unnecessary stress applied to the semiconductor light emitting element can be reduced, so that reliability is improved.
  • a gold-tin alloy is shown as the material of each adhesive layer.
  • the substrate 10, the first bases 101 and 201, and the second base, such as Sn—Ag series and Sn—Cu series solder, are shown.
  • a material used for known semiconductor bonding may be used.
  • FIG. 4 is a graph showing an outline of the temperature of each waveguide portion of the semiconductor light emitting device 2 according to the embodiment.
  • the temperature of each waveguide part of the semiconductor light emitting element 1 in the semiconductor light emitting device 2 according to the present embodiment is indicated by a solid line
  • the semiconductor of the comparative example having the configuration described in Patent Document 1 The temperature of each waveguide part of the light emitting device is indicated by a broken line.
  • the temperature of the central waveguide portion 40a3 is higher than the temperature of the end waveguide portion. This is because the waveguide portion closer to the center is affected by the heat generated in the outer waveguide portion.
  • the semiconductor light emitting device includes the semiconductor light emitting element 1, the first base 101 disposed below the lower surface of the substrate 10, and the semiconductor light emitting element 1 as the first.
  • the substrate 10 has higher thermal conductivity than the first adhesive layer 103a, and the thickness of the first adhesive layer 103a is smaller than both end portions on the center side in the arrangement direction of three or more light emitting portions.
  • the heat dissipation on the center side of the first adhesive layer 103a is reduced on both end sides.
  • the light emitting portion on the center side in the arrangement direction becomes higher in temperature than the light emitting portions on both end sides due to thermal interference with the adjacent light emitting portions.
  • the first adhesive layer 103a is made of a gold-tin alloy and has a thermal conductivity of 57 W / m ⁇ K.
  • the substrate 10 is made of GaN, and its thermal conductivity is 200 W / m ⁇ K. Since the first adhesive layer 103a used for bonding in this manner has a lower thermal conductivity than the substrate 10, the heat dissipation improves as the first adhesive layer 103a becomes thinner.
  • the first adhesive layer 103a needs to have a certain thickness, and thus the first adhesive layer 103a is uniformly thinned. It is not possible.
  • the first adhesive layer 103a immediately below is thinned, and only the central portion in the arrangement direction has heat dissipation properties. It is improving.
  • the same effect can be obtained also in the semiconductor light emitting device 3 according to the above-described modified example in which both sides of the semiconductor light emitting element 1 are sandwiched.
  • the temperature distribution is made uniform by reducing the thickness of the first adhesive layer 203 at the center in the arrangement direction.
  • the semiconductor light emitting device 2 according to the present embodiment and the semiconductor light emitting device 3 according to the modification it is possible to suppress nonuniform temperature distribution in three or more light emitting units, and thus the reliability of the semiconductor light emitting device is improved. Deterioration can be suppressed.
  • the substrate 10 of the semiconductor light emitting element 1 has the maximum thickness of the substrate 10 immediately below the central waveguide portion 40a3 (that is, directly below the light emitting portion 73).
  • the configuration of the substrate 10 is not limited to this.
  • FIGS. 5A to 5D and FIG. 5A to 5D are schematic cross-sectional views showing the configurations of the semiconductor light emitting devices 2a to 2d according to the modified examples 1 to 4, respectively.
  • FIG. 6 is a schematic cross-sectional view showing a configuration of a semiconductor light emitting device 402 according to Modification 5. The semiconductor light emitting devices 2a to 2c shown in FIGS.
  • 5A to 5C are different from the semiconductor light emitting device 2 according to the embodiment in the shapes of the substrates 10a to 10c of the semiconductor light emitting elements 1a to 1c, respectively, and are identical in other points.
  • the semiconductor light emitting device 2d shown in FIG. 5D is different from the semiconductor light emitting device 2 according to the embodiment in the number of waveguide portions (that is, light emitting portions) of the semiconductor light emitting element 1d, and is identical in other points.
  • the thickness of the substrate 10a may not be the maximum immediately below the central waveguide portion 40a3. Even with such a configuration, d1 ⁇ d2 ⁇ d3 and d3> d4> d5 can be satisfied with respect to the thicknesses d1 to d5 of the substrate 10a immediately below the waveguide portions 40a1 to 40a5. Accordingly, s1> s2> s3 and s3 ⁇ s4 ⁇ s5 are established with respect to the thicknesses s1 to s5 of the first adhesive layer 103a immediately below each of the waveguide portions 40a1 to 40a5. For this reason, also in the semiconductor light-emitting device 2a which concerns on this modification, the effect similar to the semiconductor light-emitting device 2 which concerns on the said embodiment is acquired.
  • the thickness of the substrate 10b may be uniform in the vicinity immediately below the central waveguide portion 40a3.
  • the lower surface of the substrate 10b may be parallel to the upper surface near the center in the arrangement direction.
  • the thickness of the substrate 10c may be changed stepwise. In other words, the thickness of the substrate 10c may change discretely. Even in such a configuration, s1> s2> s3 and s3 ⁇ s4 ⁇ s5 are satisfied with respect to the thicknesses s1 to s5 of the first adhesive layer 103a immediately below the waveguide portions 40a1 to 40a5. obtain. For this reason, also in the semiconductor light-emitting device 2c which concerns on this modification, the effect similar to the semiconductor light-emitting device 2 which concerns on the said embodiment is acquired.
  • the number of waveguide portions and light emitting portions may be an even number. Even with such a configuration, s1> s2 and s3 ⁇ s4 can be satisfied with respect to the thicknesses s1 to s4 of the first adhesive layer 103a immediately below the waveguide portions 40a1 to 40a4. That is, the thickness of the first adhesive layer 103a is smaller than both end portions on the center side in the arrangement direction of the three or more light emitting portions 71 to 74. For this reason, also in the semiconductor light-emitting device 2d which concerns on this modification, the effect similar to the semiconductor light-emitting device 2 which concerns on the said embodiment is acquired.
  • the semiconductor light emitting element 401 having the substrate 410 with a uniform thickness and the submount 500 may be provided.
  • the submount 500 includes a first base 501, a first electrode 502a, a first adhesive layer 503a, a third electrode 502b, and a third adhesive layer 503b.
  • the thicknesses t1 to t5 of the first base 501 directly below the waveguide portions 40a1 to 40a5 according to this modification are large on the center side in the arrangement direction of the light emitting portions 71 to 75 of the semiconductor light emitting element 401, and are on the end side Is small.
  • the central portion in the arrangement direction of the surface of the first base 501 on the semiconductor light emitting element 401 side protrudes. More specifically, the surface of the first base 501 on the semiconductor light emitting element 401 side is inclined so that the center side in the arrangement direction is convex. For this reason, the thickness of the first adhesive layer 503a is smaller than both end portions on the center side in the arrangement direction of the light emitting portions 71 to 75. Also in this modification, the first base 501 has higher thermal conductivity than the first adhesive layer 503a, as in the above embodiment.
  • the first adhesive layer 503a having a lower thermal conductivity than the first base 501 is reduced in thickness on the center side in the arrangement direction, thereby reducing the first adhesion.
  • the heat dissipation at the center side of the layer 503a can be enhanced from both end sides.
  • the light emitting portion on the center side in the arrangement direction becomes higher in temperature than the light emitting portions on both end sides due to thermal interference with the adjacent light emitting portions. Can be suppressed.
  • the said embodiment and each modification had the structure in which only one of a board
  • the second base may protrude in a convex shape toward the semiconductor light emitting element at the center in the arrangement direction of the three or more light emitting units.
  • the thickness of a 2nd contact bonding layer can be made smaller than the both edge part side in the center side of the sequence direction of three or more light emission parts.
  • the heat dissipation in the center side of an arrangement direction can be improved from both end side.
  • the semiconductor light emitting device has a quantum well structure in which an active layer is made of GaAs and AlGaAs, and may emit red laser light, or has a quantum well structure in which an active layer is made of InP and InGaAsP, Laser light may be emitted.
  • the first adhesive layer and the second adhesive layer have a thickness larger than zero, but may have a region where the thickness is zero.
  • the thickness of the first adhesive layer and the second adhesive layer may be zero at the center in the arrangement direction of three or more light emitting parts.
  • the substrate of the semiconductor light emitting element may be in contact with the first base and the second base.
  • the semiconductor substrate is used as the substrate of the semiconductor light emitting element, but the substrate of the semiconductor light emitting element may not be a semiconductor.
  • the substrate may be formed of sapphire or the like.
  • the electrode on the first conductive side may be disposed on the upper surface side of the substrate.
  • current confinement is realized using a stripe structure formed in the second semiconductor layer, but means for realizing current confinement is not limited to this. Without limitation, an electrode stripe structure, a buried structure, or the like may be used.
  • the semiconductor light emitting device can be used as a light source for an image display device, illumination, or industrial equipment, and is particularly useful as a light source for equipment that requires a relatively high light output.

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Abstract

This semiconductor light-emitting device (2) comprises: a semiconductor light-emitting element (1) having a substrate (10) and three or more light-emitting sections (71 to 75) aligned to follow the upper surface of the substrate (10); a first base (101) disposed below the lower surface of the substrate (10); and a first adhesive layer (103a) that adheres the semiconductor light-emitting element (1) onto the first base(101). The substrate (10) has a higher thermal conductivity than the first adhesive layer (103a). In the alignment direction of the three or more light-emitting sections (71 to 75), the thickness of the first adhesive layer (103a) is smaller toward the center than toward the two end sections.

Description

半導体発光装置Semiconductor light emitting device
 本開示は、アレイ型の半導体発光素子を備える半導体発光装置に関する。 The present disclosure relates to a semiconductor light emitting device including an array type semiconductor light emitting element.
 なお、本願は、平成28年度、国立研究開発法人新エネルギー・産業技術総合開発機構 「高輝度・高効率次世代レーザー技術開発/次々世代加工に向けた新規光源・要素技術開発/高効率加工用GaN系高出力・高ビーム品質半導体レーザーの開発」委託研究、産業技術力強化法第19条の適用を受ける特許出願である。 In addition, this application is the 2016 New Energy and Industrial Technology Development Organization, "High-brightness and high-efficiency next-generation laser technology development / New light source and element technology development for next-generation processing / for high-efficiency processing" This is a patent application that is subject to Article 19 “Contract research, Industrial Technology Strengthening Law Article 19”, “Development of GaN-based high-power, high-beam quality semiconductor laser”.
 近年、半導体レーザ素子などの半導体発光素子は、ディスプレイやプロジェクターなどの画像表示装置の光源、車載ヘッドランプの光源、産業用照明や民生用照明の光源、又は、レーザ溶接装置や薄膜アニール装置、レーザ加工装置などの産業機器の光源など、様々な用途の光源として注目されている。また、上記用途の光源として用いられる半導体レーザ素子には、光出力が1ワットを大きく超える高出力化が望まれている。 In recent years, semiconductor light-emitting elements such as semiconductor laser elements have been used as light sources for image display devices such as displays and projectors, light sources for in-vehicle headlamps, light sources for industrial lighting and consumer lighting, or laser welding devices, thin film annealing devices, and lasers. It attracts attention as a light source for various uses such as a light source for industrial equipment such as processing equipment. In addition, a semiconductor laser element used as a light source for the above applications is desired to have a high output that greatly exceeds 1 watt.
 半導体レーザ素子の高出力化の手法として、幅の広い導波路を複数並列に配列することによってアレイを形成する手法が広く利用されている。このような高出力の半導体レーザ素子では、高出力動作時には多量の熱が発生するため、高出力化のためには、導波路で発生した熱を効率よく放熱させることが肝要となる。一般的には、導波路の近傍に熱伝導率の高い材料を接続することで熱を拡散させ、金属パッケージなどを介して外部に放熱する。 As a technique for increasing the output of a semiconductor laser element, a technique of forming an array by arranging a plurality of wide waveguides in parallel is widely used. In such a high-power semiconductor laser device, a large amount of heat is generated during a high-power operation. Therefore, it is important to efficiently dissipate the heat generated in the waveguide in order to increase the power. Generally, heat is diffused by connecting a material having high thermal conductivity in the vicinity of the waveguide, and the heat is radiated to the outside through a metal package or the like.
 特許文献1に、従来のアレイ型半導体レーザ素子が開示されている。図7は、特許文献1に開示された従来のアレイ型半導体レーザ素子1010の構成を示す模式的な正面図である。 Patent Document 1 discloses a conventional array type semiconductor laser element. FIG. 7 is a schematic front view showing a configuration of a conventional array type semiconductor laser device 1010 disclosed in Patent Document 1. In FIG.
 図7に示すように、従来のアレイ型半導体レーザ素子1010は、所定間隔をおいて一列に配列された複数のストライプ1011~1014を有する。複数のストライプ1011~1014は、それぞれ、レーザ光の導波路となる発光部である。アレイ型半導体レーザ素子1010は、各ストライプに対応して分離されて設けられた複数のレーザ電極1008を有する。アレイ型半導体レーザ素子1010の複数のレーザ電極1008は、それぞれ支持体1003上に設けられた複数の金属配線体1007と対向する位置に配置される。複数のレーザ電極1008は、それぞれ複数の金属配線体1007と半田等の導電性接着材1006を介して熱圧着されている。これにより、複数のレーザ電極1008と複数の金属配線体1007とを電気的に導通し、かつ、アレイ型半導体レーザ素子1010を支持体1003に物理的に固定している。さらに、アレイ型半導体レーザ素子1010と支持体1003との間に熱伝導性の良い樹脂1009が充填されている。 As shown in FIG. 7, a conventional array type semiconductor laser device 1010 has a plurality of stripes 1011 to 1014 arranged in a line at a predetermined interval. Each of the plurality of stripes 1011 to 1014 is a light emitting portion that becomes a waveguide of laser light. The array type semiconductor laser element 1010 has a plurality of laser electrodes 1008 provided separately corresponding to each stripe. The plurality of laser electrodes 1008 of the array type semiconductor laser element 1010 are arranged at positions facing the plurality of metal wiring bodies 1007 provided on the support body 1003, respectively. The plurality of laser electrodes 1008 are thermocompression bonded via a plurality of metal wiring bodies 1007 and conductive adhesives 1006 such as solder. Accordingly, the plurality of laser electrodes 1008 and the plurality of metal wiring bodies 1007 are electrically connected, and the array type semiconductor laser element 1010 is physically fixed to the support body 1003. Further, a resin 1009 having good thermal conductivity is filled between the array type semiconductor laser element 1010 and the support 1003.
特開平1-164084号公報Japanese Laid-Open Patent Publication No. 1-164084
 しかしながら、このような構造の場合、それぞれの導波路で発生した熱が互いに干渉するため、複数の導波路(つまり、発光部)の温度分布が不均一となる。具体的には、複数の導波路のうち、複数の導波路の配列方向における中央側に位置する導波路の温度が、端部側に位置する導波路の温度よりも高くなる。その結果、従来のアレイ型半導体レーザ素子1010では、温度分布の不均一が生じるため、温度分布の不均一に起因して、高温部の導波路の光出力特性の劣化が低温部よりも早く進行し、素子の破損につながるという信頼性悪化の課題がある。 However, in the case of such a structure, since the heat generated in each waveguide interferes with each other, the temperature distribution of the plurality of waveguides (that is, the light emitting portions) becomes non-uniform. Specifically, among the plurality of waveguides, the temperature of the waveguide located on the center side in the arrangement direction of the plurality of waveguides becomes higher than the temperature of the waveguide located on the end side. As a result, in the conventional array-type semiconductor laser device 1010, the temperature distribution is non-uniform, so that the deterioration of the light output characteristics of the waveguide in the high-temperature portion proceeds faster than the low-temperature portion due to the non-uniform temperature distribution. However, there is a problem of deterioration of reliability that leads to damage of the element.
 本開示は、発光部間の温度分布の不均一を抑制することで信頼性の悪化を抑えた半導体発光装置を提供することを目的とする。 This disclosure is intended to provide a semiconductor light emitting device that suppresses deterioration in reliability by suppressing nonuniformity of temperature distribution between light emitting portions.
 上記目的を達成するために、本開示に係る半導体発光装置の一態様は、基板と、前記基板の上面に沿って配列された三つ以上の発光部と、を有する半導体発光素子と、前記基板の下面の下方に配置された第1基台と、前記半導体発光素子を前記第1基台に接着する第1接着層と、を備え、前記基板は、前記第1接着層より熱伝導率が高く、前記第1接着層の厚さは、前記三つ以上の発光部の配列方向の中央側において、両方の端部側より小さい。 In order to achieve the above object, one aspect of a semiconductor light emitting device according to the present disclosure includes a semiconductor light emitting element including a substrate and three or more light emitting units arranged along an upper surface of the substrate, and the substrate. And a first adhesive layer that bonds the semiconductor light emitting element to the first base, and the substrate has a thermal conductivity higher than that of the first adhesive layer. The thickness of the first adhesive layer is higher at the center side in the arrangement direction of the three or more light emitting portions than at both end portions.
 このように、基板より熱伝導率が低い第1接着層の配列方向の中央側における厚さを小さくすることで、第1接着層の中央側での放熱性を両方の端部側より高めることができる。これにより、三つ以上の発光部のうち配列方向の中央側の発光部が、隣接する発光部との熱干渉に起因して、両方の端部側の発光部より高温となることを抑制できる。したがって、三つ以上の発光部における温度分布の不均一を抑制できるため、半導体発光装置の信頼性の悪化を抑制できる。 Thus, by reducing the thickness at the center side in the arrangement direction of the first adhesive layer having a lower thermal conductivity than that of the substrate, the heat dissipation at the center side of the first adhesive layer is enhanced from both end portions. Can do. Thereby, it can suppress that the light emission part of the center side of an arrangement direction among three or more light emission parts becomes high temperature rather than the light emission part of both edge parts due to the thermal interference with an adjacent light emission part. . Therefore, since the nonuniformity of the temperature distribution in three or more light emitting units can be suppressed, deterioration of the reliability of the semiconductor light emitting device can be suppressed.
 また、本開示に係る半導体発光装置の一態様において、前記基板の厚さは、前記配列方向の中央側において両方の端部側より大きくてもよい。 Moreover, in one aspect of the semiconductor light emitting device according to the present disclosure, the thickness of the substrate may be larger than both end portions on the central side in the arrangement direction.
 また、本開示に係る半導体発光装置の一態様において、前記基板の前記下面は、前記配列方向の中央側が凸状になるよう傾斜していてもよい。 Further, in one aspect of the semiconductor light emitting device according to the present disclosure, the lower surface of the substrate may be inclined so that a central side in the arrangement direction is convex.
 また、本開示に係る半導体発光装置の一態様において、前記基板の前記上面は、前記配列方向において、前記第1基台の前記第1接着層との接合面と平行であってもよい。 Further, in one aspect of the semiconductor light emitting device according to the present disclosure, the upper surface of the substrate may be parallel to a bonding surface with the first adhesive layer of the first base in the arrangement direction.
 これにより、半導体発光素子からの出射光の伝播方向と、第1基台の上面と、がほぼ平行になるため、第1基台の上面を光軸のアライメントの基準として利用できる。このため、光軸調整が容易な半導体発光装置を実現できる。 Thereby, since the propagation direction of the emitted light from the semiconductor light emitting element and the upper surface of the first base are substantially parallel, the upper surface of the first base can be used as a reference for alignment of the optical axis. Therefore, it is possible to realize a semiconductor light emitting device that can easily adjust the optical axis.
 また、本開示に係る半導体発光装置の一態様において、さらに、前記半導体発光素子を挟んで前記第1基台とは反対側に配置された第2基台と、前記半導体発光素子を前記第2基台に接着する第2接着層と、を備えてもよい。 Moreover, in one aspect of the semiconductor light emitting device according to the present disclosure, a second base disposed on the opposite side of the first base across the semiconductor light emitting element, and the semiconductor light emitting element in the second A second adhesive layer that adheres to the base.
 このように、本開示に係る半導体発光装置では、半導体発光素子の両側が基台で挟まれる。したがって、各基台を熱伝導性の高い部材で形成することで、半導体発光素子の放熱性をさらに向上させることができる。 Thus, in the semiconductor light emitting device according to the present disclosure, both sides of the semiconductor light emitting element are sandwiched between the bases. Therefore, the heat dissipation of the semiconductor light emitting device can be further improved by forming each base with a member having high thermal conductivity.
 また、本開示に係る半導体発光装置の一態様において、前記第1基台は、前記第1接着層より熱伝導率が高くてもよい。 Moreover, in one aspect of the semiconductor light emitting device according to the present disclosure, the first base may have a thermal conductivity higher than that of the first adhesive layer.
 上記目的を達成するために、本開示に係る半導体発光装置の一態様は、基板と、前記基板の上面に沿って配列された三つ以上の発光部と、を有する半導体発光素子と、前記基板の下面の下方に配置された第1基台と、前記半導体発光素子を前記第1基台に接着する第1接着層と、を備え、前記第1基台は、前記第1接着層より熱伝導率が高く、前記第1接着層の厚さは、前記三つ以上の発光部の配列方向の中央側において、両方の端部側より小さい。 In order to achieve the above object, one aspect of a semiconductor light emitting device according to the present disclosure includes a semiconductor light emitting element including a substrate and three or more light emitting units arranged along an upper surface of the substrate, and the substrate. And a first adhesive layer that adheres the semiconductor light-emitting element to the first base, the first base being more heated than the first adhesive layer. The conductivity is high, and the thickness of the first adhesive layer is smaller than both end portions on the center side in the arrangement direction of the three or more light emitting portions.
 このように、第1基台より熱伝導率が低い第1接着層の配列方向の中央側における厚さを小さくすることで、第1接着層の中央側での放熱性を両方の端部側より高めることができる。これにより、三つ以上の発光部のうち配列方向の中央側の発光部が、隣接する発光部との熱干渉に起因して、両方の端部側の発光部より高温となることを抑制できる。したがって、三つ以上の発光部における温度分布の不均一を抑制できるため、半導体発光装置の信頼性の悪化を抑制できる。 Thus, by reducing the thickness at the center side in the arrangement direction of the first adhesive layer having a lower thermal conductivity than the first base, the heat dissipation at the center side of the first adhesive layer is reduced at both end sides. Can be increased. Thereby, it can suppress that the light emission part of the center side of an arrangement direction among three or more light emission parts becomes high temperature rather than the light emission part of both edge parts due to the thermal interference with an adjacent light emission part. . Therefore, since the nonuniformity of the temperature distribution in three or more light emitting units can be suppressed, deterioration of the reliability of the semiconductor light emitting device can be suppressed.
 また、本開示に係る半導体発光装置の一態様において、前記第1基台の厚さは、前記配列方向の中央側において両方の端部側より大きくてもよい。 Also, in one aspect of the semiconductor light emitting device according to the present disclosure, the thickness of the first base may be larger than both end portions on the center side in the arrangement direction.
 本開示によれば、発光部間の温度分布の不均一を抑制することで信頼性の悪化を抑えることができる。 According to the present disclosure, deterioration in reliability can be suppressed by suppressing nonuniformity of the temperature distribution between the light emitting units.
図1Aは、実施の形態に係る半導体発光素子の構成を示す模式的な上面図である。FIG. 1A is a schematic top view illustrating a configuration of a semiconductor light emitting element according to an embodiment. 図1Bは、実施の形態に係る半導体発光素子の構成を示す模式的な断面図である。FIG. 1B is a schematic cross-sectional view showing the configuration of the semiconductor light emitting element according to the embodiment. 図2Aは、実施の形態に係る半導体発光素子の製造方法における第1半導体層、発光層及び第2半導体層の各層を形成する工程を示す断面図である。FIG. 2A is a cross-sectional view illustrating a process of forming each of the first semiconductor layer, the light emitting layer, and the second semiconductor layer in the method for manufacturing a semiconductor light emitting element according to the embodiment. 図2Bは、実施の形態に係る半導体発光素子の製造方法における第1保護膜を成膜する工程を示す断面図である。FIG. 2B is a cross-sectional view showing a step of forming a first protective film in the method for manufacturing a semiconductor light emitting element according to the embodiment. 図2Cは、実施の形態に係る半導体発光素子の製造方法における第1保護膜をパターニングする工程を示す断面図である。FIG. 2C is a cross-sectional view showing a step of patterning the first protective film in the method for manufacturing the semiconductor light emitting device according to the embodiment. 図2Dは、実施の形態に係る半導体発光素子の製造方法における導波路部及び平坦部を形成する工程を示す断面図である。FIG. 2D is a cross-sectional view illustrating a process of forming a waveguide portion and a flat portion in the method for manufacturing a semiconductor light emitting element according to the embodiment. 図2Eは、実施の形態に係る半導体発光素子の製造方法における誘電体層を成膜する工程を示す断面図である。FIG. 2E is a cross-sectional view showing a step of forming a dielectric layer in the method for manufacturing a semiconductor light emitting device according to the embodiment. 図2Fは、実施の形態に係る半導体発光素子の製造方法におけるp側電極を形成する工程を示す断面図である。FIG. 2F is a cross-sectional view showing the step of forming the p-side electrode in the method for manufacturing the semiconductor light emitting device according to the embodiment. 図2Gは、実施の形態に係る半導体発光素子の製造方法におけるパッド電極を成膜する工程を示す断面図である。FIG. 2G is a cross-sectional view showing a step of forming a pad electrode in the method for manufacturing a semiconductor light emitting device according to the embodiment. 図2Hは、実施の形態に係る半導体発光素子の製造方法における基板の下面に凸形状を形成する工程を示す断面図である。FIG. 2H is a cross-sectional view showing a step of forming a convex shape on the lower surface of the substrate in the method for manufacturing a semiconductor light emitting element according to the embodiment. 図2Iは、実施の形態に係る半導体発光素子の製造方法におけるn側電極を形成する工程を示す断面図である。FIG. 2I is a cross-sectional view illustrating a process of forming an n-side electrode in the method for manufacturing a semiconductor light emitting device according to the embodiment. 図3Aは、実施の形態に係る半導体発光装置の構成を示す模式的な断面図である。FIG. 3A is a schematic cross-sectional view showing the configuration of the semiconductor light emitting device according to the embodiment. 図3Bは、実施の形態の変形例に係る半導体発光装置の構成を示す模式的な断面図である。FIG. 3B is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to a modification of the embodiment. 図4は、実施の形態に係る半導体発光装置の各導波路部の温度の概要を示すグラフである。FIG. 4 is a graph showing an outline of the temperature of each waveguide portion of the semiconductor light emitting device according to the embodiment. 図5Aは、変形例1に係る半導体発光装置の構成を示す模式的な断面図である。FIG. 5A is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 1. 図5Bは、変形例2に係る半導体発光装置の構成を示す模式的な断面図である。FIG. 5B is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 2. 図5Cは、変形例3に係る半導体発光装置の構成を示す模式的な断面図である。FIG. 5C is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 3. 図5Dは、変形例4に係る半導体発光装置の構成を示す模式的な断面図である。FIG. 5D is a schematic cross-sectional view illustrating a configuration of a semiconductor light emitting device according to Modification 4. 図6は、変形例5に係る半導体発光装置の構成を示す模式的な断面図である。FIG. 6 is a schematic cross-sectional view showing a configuration of a semiconductor light emitting device according to Modification 5. 図7は、従来のアレイ型半導体レーザ素子の構成を示す模式的な正面図である。FIG. 7 is a schematic front view showing a configuration of a conventional array type semiconductor laser device.
 以下、本開示の実施の形態について、図面を参照しながら説明する。なお、以下に説明する実施の形態は、いずれも本開示の好ましい一具体例を示すものである。したがって、以下の実施の形態で示される、数値、形状、材料、構成要素、構成要素の配置位置及び接続形態、並びに、ステップ(工程)及びステップの順序などは、一例であって本開示を限定する主旨ではない。よって、以下の実施の形態における構成要素のうち、本開示の最上位概念を示す独立請求項に記載されていない構成要素については、任意の構成要素として説明される。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a preferred specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, component arrangement positions and connection forms, steps (steps) and order of steps, and the like shown in the following embodiments are merely examples and limit the present disclosure. It is not the purpose to do. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements.
 各図は、模式図であり、必ずしも厳密に図示されたものではない。したがって、各図において縮尺などは必ずしも一致していない。各図において、実質的に同一の構成に対しては同一の符号を付しており、重複する説明は省略又は簡略化する。 Each figure is a schematic diagram and is not necessarily shown strictly. Accordingly, the scales and the like do not necessarily match in each drawing. In each figure, substantially the same components are denoted by the same reference numerals, and redundant descriptions are omitted or simplified.
 また、本明細書及び図面において、X軸、Y軸及びZ軸は、三次元直交座標系の三軸を表している。X軸及びY軸は、互いに直交し、且つ、いずれもZ軸に直交する軸である。 In the present specification and drawings, the X axis, the Y axis, and the Z axis represent the three axes of the three-dimensional orthogonal coordinate system. The X axis and the Y axis are orthogonal to each other, and both are orthogonal to the Z axis.
 (実施の形態)
 実施の形態に係る半導体発光装置について説明する。
(Embodiment)
A semiconductor light emitting device according to an embodiment will be described.
 [半導体発光素子の構成]
 まず、本実施の形態に係る半導体発光装置が備える半導体発光素子の構成について、図1A及び図1Bを用いて説明する。図1A及び図1Bは、それぞれ本実施の形態に係る半導体発光素子1の構成を示す模式的な上面図及び断面図である。図1Bは、図1AのIB-IB線における半導体発光素子1の断面図である。
[Configuration of Semiconductor Light Emitting Element]
First, the structure of the semiconductor light emitting element included in the semiconductor light emitting device according to this embodiment will be described with reference to FIGS. 1A and 1B. 1A and 1B are a schematic top view and a cross-sectional view showing the configuration of the semiconductor light emitting device 1 according to the present embodiment, respectively. 1B is a cross-sectional view of the semiconductor light emitting device 1 taken along the line IB-IB in FIG. 1A.
 本実施の形態に係る半導体発光素子1は、基板10と、基板10の上面に沿って配列された三つ以上の発光部と、を有する素子である。図1Bに示すように、本実施の形態では、半導体発光素子1は、基板10の主面に沿って図1BのX軸方向に配列された五つの発光部71~75を有する。五つの発光部71~75の配列方向は、各図に示されるX軸方向と一致する。以下、五つの発光部71~75の配列方向を単に「配列方向」ともいう。本実施の形態では、半導体発光素子1は、窒化物半導体材料を含む半導体レーザ素子であって、図1Bに示すように、基板10と、第1半導体層20と、発光層30と、第2半導体層40と、電極部材50と、誘電体層60と、n側電極80と、を備える。 The semiconductor light emitting element 1 according to the present embodiment is an element having a substrate 10 and three or more light emitting units arranged along the upper surface of the substrate 10. As shown in FIG. 1B, in the present embodiment, the semiconductor light emitting element 1 has five light emitting portions 71 to 75 arranged in the X-axis direction of FIG. 1B along the main surface of the substrate 10. The arrangement direction of the five light emitting units 71 to 75 coincides with the X-axis direction shown in each drawing. Hereinafter, the arrangement direction of the five light emitting portions 71 to 75 is also simply referred to as “the arrangement direction”. In the present embodiment, the semiconductor light emitting device 1 is a semiconductor laser device including a nitride semiconductor material. As shown in FIG. 1B, the substrate 10, the first semiconductor layer 20, the light emitting layer 30, and the second A semiconductor layer 40, an electrode member 50, a dielectric layer 60, and an n-side electrode 80 are provided.
 第2半導体層40は、図1Bに示すように、レーザ共振器長方向(図1BのY軸方向)に延在するストライプ状の凸部からなる導波路部40a1~40a5と、各導波路部の根元から横方向(言い換えると、図1BのX軸方向)に広がる平坦部40bと、を有する。導波路部40a1~40a5の位置は、それぞれ、発光部71~75の位置に対応する。 As shown in FIG. 1B, the second semiconductor layer 40 includes waveguide portions 40a1 to 40a5 composed of stripe-shaped convex portions extending in the laser resonator length direction (Y-axis direction in FIG. 1B), and each waveguide portion. And a flat portion 40b extending in the horizontal direction (in other words, in the X-axis direction in FIG. 1B). The positions of the waveguide portions 40a1 to 40a5 correspond to the positions of the light emitting portions 71 to 75, respectively.
 半導体発光素子1内に設けられる導波路部の個数は、三つ以上であればよく、半導体発光素子1を高い光出力(例えばワットクラス)で動作させるには、5本以上であってもよい。本実施の形態では、半導体発光素子1は、5本の導波路部40a1~40a5を有する。導波路部40a1~40a5は互いに平行に配置される。これにより、各導波路部に対応する各発光部から同じ方向に光が出射される。 The number of waveguide portions provided in the semiconductor light emitting device 1 may be three or more, and may be five or more in order to operate the semiconductor light emitting device 1 with high light output (for example, watt class). . In the present embodiment, the semiconductor light emitting element 1 has five waveguide portions 40a1 to 40a5. The waveguide portions 40a1 to 40a5 are arranged in parallel to each other. Thereby, light is emitted in the same direction from each light emitting part corresponding to each waveguide part.
 各導波路部の幅及び間隔(各導波路部の中心間距離)は、特に限定されるものではない。例えば、各導波路部のX軸方向の幅は1μm以上100μm以下で、隣り合う導波路部の間隔は、50μm以上1000μm以下である。半導体発光素子1を高い光出力(例えばワットクラス)で動作させるには、各導波路部の幅を10μm以上50μm以下とし、隣合う導波路部の間隔を300μm以上500μm以下にしてもよい。本実施の形態では、各導波路部の幅は、30μmであり、間隔は400μmである。また、各導波路部の間隔は、半導体発光素子1内において等間隔である必要はない。半導体発光素子1内の温度分布や応力等の影響を考慮して、各導波路部の間隔を不均一にしてもよい。 The width and interval of each waveguide part (the distance between the centers of each waveguide part) are not particularly limited. For example, the width of each waveguide portion in the X-axis direction is 1 μm or more and 100 μm or less, and the interval between adjacent waveguide portions is 50 μm or more and 1000 μm or less. In order to operate the semiconductor light emitting device 1 with a high light output (for example, watt class), the width of each waveguide portion may be 10 μm or more and 50 μm or less, and the interval between adjacent waveguide portions may be 300 μm or more and 500 μm or less. In the present embodiment, the width of each waveguide portion is 30 μm and the interval is 400 μm. Further, the intervals between the waveguide portions need not be equal in the semiconductor light emitting device 1. In consideration of the influence of temperature distribution, stress, etc. in the semiconductor light emitting device 1, the intervals between the waveguide portions may be made non-uniform.
 各導波路部の高さは、特に限定されることはないが、一例として、100nm以上1μm以下である。半導体発光素子1を高い光出力(例えばワットクラス)で動作させるには、300nm以上800nm以下にしてもよい。本実施の形態では、各導波路部の高さは600nmである。 The height of each waveguide part is not particularly limited, but as an example, it is 100 nm or more and 1 μm or less. In order to operate the semiconductor light emitting element 1 with a high light output (for example, watt class), the semiconductor light emitting element 1 may have a thickness of 300 nm to 800 nm. In the present embodiment, the height of each waveguide portion is 600 nm.
 基板10は、例えば、GaN基板である。本実施の形態では、基板10として、主面が(0001)面であるn型六方晶GaN基板を用いている。 The substrate 10 is, for example, a GaN substrate. In the present embodiment, an n-type hexagonal GaN substrate whose main surface is a (0001) plane is used as the substrate 10.
 第1半導体層20は、基板10の上方に配置されている。第1半導体層20は、例えば、n型AlGaNからなるn側クラッド層である。 The first semiconductor layer 20 is disposed above the substrate 10. The first semiconductor layer 20 is an n-side cladding layer made of n-type AlGaN, for example.
 発光層30は、第1半導体層20の上方に配置されている。発光層30は、窒化物半導体によって構成される。発光層30は、例えば、図1Bに示すように、第1半導体層20側から順に、n-GaNからなるn側光ガイド層31と、InGaN量子井戸層からなる活性層32と、p-GaNからなるp側光ガイド層33とが積層された積層構造を有する。発光層30は、発光部71~75を含む。発光部71~75は、導波路部40a1~40a5に対応する位置に配置される部分であり、半導体発光素子1から出射される光の大部分が発生かつ伝播する部分である。本実施の形態では、各発光部は、各導波路部の下方(つまり、図1Bにおける下側)に配置される。各発光部の幅(つまり、図1BのX軸方向の幅)は、各導波路部の幅(つまり、図1BのX軸方向の幅)と同程度である。なお、発光部71~75以外の部分においても、光が発生又は伝播してもよい。 The light emitting layer 30 is disposed above the first semiconductor layer 20. The light emitting layer 30 is made of a nitride semiconductor. For example, as shown in FIG. 1B, the light emitting layer 30 includes, in order from the first semiconductor layer 20 side, an n-side light guide layer 31 made of n-GaN, an active layer 32 made of an InGaN quantum well layer, and p-GaN. The p-side light guide layer 33 is made of a laminated structure. The light emitting layer 30 includes light emitting portions 71 to 75. The light emitting portions 71 to 75 are portions disposed at positions corresponding to the waveguide portions 40a1 to 40a5, and are portions where most of the light emitted from the semiconductor light emitting element 1 is generated and propagated. In the present embodiment, each light emitting section is arranged below each waveguide section (that is, the lower side in FIG. 1B). The width of each light emitting section (that is, the width in the X-axis direction in FIG. 1B) is approximately the same as the width of each waveguide section (that is, the width in the X-axis direction in FIG. 1B). Note that light may be generated or propagated in portions other than the light emitting portions 71 to 75.
 第2半導体層40は、発光層30の上方に配置されている。第2半導体層40は、例えば、図1Bに示すように、発光層30側から順に、AlGaNからなる電子障壁層41と、p型AlGaN層からなるp側クラッド層42と、p型GaNからなるp側コンタクト層43とが積層された積層構造を有する。p側コンタクト層43は、導波路部40a1~40a5の最上層として形成されている。 The second semiconductor layer 40 is disposed above the light emitting layer 30. For example, as illustrated in FIG. 1B, the second semiconductor layer 40 includes, in order from the light emitting layer 30 side, an electron barrier layer 41 made of AlGaN, a p-side cladding layer 42 made of a p-type AlGaN layer, and p-type GaN. A p-side contact layer 43 is laminated. The p-side contact layer 43 is formed as the uppermost layer of the waveguide portions 40a1 to 40a5.
 これらの各層は、成長条件を調整することで、ほぼ均一な膜厚で形成することができる。 These layers can be formed with a substantially uniform film thickness by adjusting the growth conditions.
 図1Bに示すように、p側クラッド層42は、凸部を有している。このp側クラッド層42の凸部とp側コンタクト層43とによってストライプ状の導波路部40a1~40a5が構成されている。また、p側クラッド層42は、各導波路部の両側方に、平坦部40bとして平面部を有している。つまり、平坦部40bの最上面は、p側クラッド層42の表面であり、平坦部40bの最上面にはp側コンタクト層43が形成されていない。 As shown in FIG. 1B, the p-side cladding layer 42 has a convex portion. The convex portions of the p-side cladding layer 42 and the p-side contact layer 43 constitute striped waveguide portions 40a1 to 40a5. The p-side cladding layer 42 has a flat portion as a flat portion 40b on both sides of each waveguide portion. That is, the uppermost surface of the flat portion 40b is the surface of the p-side cladding layer 42, and the p-side contact layer 43 is not formed on the uppermost surface of the flat portion 40b.
 電極部材50は、第2半導体層40の上方に配置されている。電極部材50は、各導波路部よりも幅広である。つまり、電極部材50の幅(X軸方向の幅)は、各導波路部の幅(X軸方向の幅)よりも大きい。電極部材50は、誘電体層60及び各導波路部の上面と接触している。 The electrode member 50 is disposed above the second semiconductor layer 40. The electrode member 50 is wider than each waveguide part. That is, the width of the electrode member 50 (width in the X-axis direction) is larger than the width of each waveguide portion (width in the X-axis direction). The electrode member 50 is in contact with the dielectric layer 60 and the upper surface of each waveguide portion.
 本実施の形態において、電極部材50は、各発光部への電流供給のためのp側電極51と、p側電極51の上方に配置されたパッド電極52と、を有する。 In the present embodiment, the electrode member 50 includes a p-side electrode 51 for supplying a current to each light emitting portion, and a pad electrode 52 disposed above the p-side electrode 51.
 p側電極51は、各導波路部の上面と接触している。p側電極51は、各導波路部の上方においてp側コンタクト層43とオーミック接触するオーミック電極であり、各導波路部の上面であるp側コンタクト層43の上面と接触している。p側電極51は、例えば、Pd、Pt、Niなどの金属材料を用いて形成される。本実施の形態において、p側電極51は、Pd/Ptの2層構造を有する。 The p-side electrode 51 is in contact with the upper surface of each waveguide part. The p-side electrode 51 is an ohmic electrode that is in ohmic contact with the p-side contact layer 43 above each waveguide portion, and is in contact with the upper surface of the p-side contact layer 43 that is the upper surface of each waveguide portion. The p-side electrode 51 is formed using a metal material such as Pd, Pt, or Ni, for example. In the present embodiment, the p-side electrode 51 has a two-layer structure of Pd / Pt.
 パッド電極52は、各導波路部よりも幅広であって、誘電体層60と接触している。つまり、パッド電極52は、各導波路部及び誘電体層60を覆うように形成されている。パッド電極52は、例えば、Ti、Ni、Pt、Auなどの金属材料を用いて形成される。本実施の形態において、パッド電極52は、Ti/Pt/Auの3層構造を有する。 The pad electrode 52 is wider than each waveguide part and is in contact with the dielectric layer 60. That is, the pad electrode 52 is formed so as to cover each waveguide part and the dielectric layer 60. The pad electrode 52 is formed using a metal material such as Ti, Ni, Pt, or Au, for example. In the present embodiment, the pad electrode 52 has a three-layer structure of Ti / Pt / Au.
 なお、図1Aに示すように、パッド電極52は、半導体発光素子1を個片化する際の歩留まりを向上させるために、半導体発光素子1の上面視において、誘電体層60の内側(つまり第2半導体層40の内側)に形成されている。すなわち、半導体発光素子1を上面視した場合に、パッド電極52は、半導体発光素子1の端部周縁には形成されていない。これにより、半導体発光素子1は、端部周縁に電流が供給されない非電流注入領域を有する。また、パッド電極52が形成されている領域の各導波路部の長手方向(つまりY軸方向)に垂直な断面形状は、どの部分でも図1Bに示される形状となる。 As shown in FIG. 1A, the pad electrode 52 is formed on the inner side of the dielectric layer 60 (that is, the first electrode) in the top view of the semiconductor light emitting device 1 in order to improve the yield when the semiconductor light emitting device 1 is separated. 2 inside the semiconductor layer 40). That is, when the semiconductor light emitting element 1 is viewed from above, the pad electrode 52 is not formed on the peripheral edge of the semiconductor light emitting element 1. Thereby, the semiconductor light emitting device 1 has a non-current injection region where no current is supplied to the periphery of the end portion. Moreover, the cross-sectional shape perpendicular | vertical to the longitudinal direction (namely, Y-axis direction) of each waveguide part of the area | region in which the pad electrode 52 is formed becomes a shape shown by FIG. 1B in any part.
 誘電体層60は、光を閉じ込めるために、各導波路部の側面に配置された絶縁膜である。具体的には、誘電体層60は、各導波路部の側面(つまり、図1BのX軸方向と交差する面)から平坦部40bにわたって連続的に形成されている。本実施の形態において、誘電体層60は、各導波路部の周辺において、p側コンタクト層43の側面とp側クラッド層42の凸部の側面とp側クラッド層42の上面とにわたって連続して形成されている。本実施の形態では、誘電体層60は、SiOで形成される。 The dielectric layer 60 is an insulating film disposed on the side surface of each waveguide portion in order to confine light. Specifically, the dielectric layer 60 is continuously formed from the side surface (that is, the surface intersecting the X-axis direction in FIG. 1B) of each waveguide portion to the flat portion 40b. In the present embodiment, the dielectric layer 60 is continuous over the side surface of the p-side contact layer 43, the side surface of the convex portion of the p-side cladding layer 42, and the upper surface of the p-side cladding layer 42 around each waveguide portion. Is formed. In this embodiment, the dielectric layer 60 is formed of SiO 2.
 誘電体層60の形状は、特に限定されるものではないが、誘電体層60は、各導波路部の側面及び平坦部40bと接していてもよい。これにより、各導波路部の直下で発光した光を安定的に閉じ込めることができる。 The shape of the dielectric layer 60 is not particularly limited, but the dielectric layer 60 may be in contact with the side surface of each waveguide portion and the flat portion 40b. Thereby, it is possible to stably confine light emitted directly under each waveguide portion.
 また、高い光出力で動作させること(つまり高出力動作)を目的とした半導体発光素子では、光出射端面には誘電体多層膜などの端面コート膜が形成される。この端面コート膜は、端面のみに形成することが難しく、半導体発光素子1の上面にも回りこむ。この場合、半導体発光素子1のレーザ共振器長方向(つまり、図1A及び図1BのY軸方向)の端部では、パッド電極52が形成されていないため、端面コート膜が上面にまで回りこんでしまうと、半導体発光素子1の長手方向の端部で誘電体層60と端面コート膜とが接してしまう場合がある。この際、誘電体層60が形成されていない場合、又は、誘電体層60の膜厚が光閉じ込めに対して薄い場合には、端面コート膜の影響を受けるため、光損失の原因となる。そこで、発光層30で発生した光を十分に閉じ込めるには、誘電体層60の膜厚は、100nm以上にしてもよい。一方、誘電体層60の膜厚が厚すぎると、パッド電極52の形成が困難となるため、誘電体層60の膜厚は、各導波路部の高さ以下にしてもよい。 Also, in a semiconductor light emitting device intended to operate with high light output (that is, high output operation), an end face coating film such as a dielectric multilayer film is formed on the light emitting end face. This end face coating film is difficult to be formed only on the end face, and also extends around the upper surface of the semiconductor light emitting element 1. In this case, since the pad electrode 52 is not formed at the end of the semiconductor light emitting element 1 in the laser resonator length direction (that is, the Y-axis direction in FIGS. 1A and 1B), the end face coat film does not reach the upper surface. As a result, the dielectric layer 60 and the end face coating film may be in contact with each other at the end in the longitudinal direction of the semiconductor light emitting device 1. At this time, if the dielectric layer 60 is not formed or if the film thickness of the dielectric layer 60 is thin relative to the optical confinement, it is affected by the end face coating film, which causes light loss. Therefore, in order to sufficiently confine the light generated in the light emitting layer 30, the film thickness of the dielectric layer 60 may be 100 nm or more. On the other hand, if the dielectric layer 60 is too thick, it is difficult to form the pad electrode 52. Therefore, the thickness of the dielectric layer 60 may be less than the height of each waveguide portion.
 また、各導波路部の側面及び平坦部40bには、各導波路部を形成する際のエッチング工程でエッチングダメージが残存してリーク電流が発生する場合がある。しかしながら、本実施の形態では、各導波路部及び平坦部40bを誘電体層60で被覆することで、不要なリーク電流の発生を低減できる。 In addition, etching damage may remain on the side surface and the flat portion 40b of each waveguide portion in the etching process when forming each waveguide portion, resulting in leakage current. However, in the present embodiment, generation of unnecessary leakage current can be reduced by covering each waveguide portion and the flat portion 40b with the dielectric layer 60.
 n側電極80は、基板10の下方に配置された電極であり、基板10とオーミック接触するオーミック電極である。n側電極80は、例えば、Ti/Pt/Auからなる積層膜である。n側電極80の構成はこれに限定されない。n側電極80は、Ti及びAuが積層された積層膜であってもよい。 The n-side electrode 80 is an electrode disposed below the substrate 10 and is an ohmic electrode in ohmic contact with the substrate 10. The n-side electrode 80 is a laminated film made of Ti / Pt / Au, for example. The configuration of the n-side electrode 80 is not limited to this. The n-side electrode 80 may be a laminated film in which Ti and Au are laminated.
 基板10は、図1Bに示すように、導波路部40a1~40a5の配列方向(X軸方向)の位置に応じてその厚さが異なる。本実施例では、各導波路部直下の基板10の厚さを、左端の導波路部の直下から順番にd1、d2、d3、d4及びd5と定義する。言い換えると、発光部71~75の直下の基板10の厚さをそれぞれd1~d5と定義する。なお、各導波路部直下の基板厚さとは、各導波路部(又は各発光部)の幅方向(X軸方向)の中心を通り、基板10と第1半導体層20の境界面に垂直な線上の、基板10と第1半導体層20との境界から、基板10とn側電極80との境界までの距離のことである。本実施の形態では、左端の導波路部40a1と中央の導波路部40a3との間及び右端の導波路部40a5と中央の導波路部40a3との導波路部の間において、基板10の厚さは連続的に変化しており、d3>d1及びd3>d5の関係がある。つまり、基板10の厚さは、配列方向の中央側において両方の端部側より大きい。また、基板10の下面(図1Bの下方の面)は、配列方向の中央側が凸状になるよう傾斜している。以上のような基板10を有する半導体発光素子1が奏する作用及び効果については後述する。 As shown in FIG. 1B, the thickness of the substrate 10 varies depending on the position of the waveguide portions 40a1 to 40a5 in the arrangement direction (X-axis direction). In this embodiment, the thickness of the substrate 10 immediately below each waveguide portion is defined as d1, d2, d3, d4, and d5 in order from directly below the leftmost waveguide portion. In other words, the thickness of the substrate 10 immediately below the light emitting portions 71 to 75 is defined as d1 to d5, respectively. The substrate thickness immediately below each waveguide portion is perpendicular to the boundary surface between the substrate 10 and the first semiconductor layer 20 through the center in the width direction (X-axis direction) of each waveguide portion (or each light emitting portion). This is the distance on the line from the boundary between the substrate 10 and the first semiconductor layer 20 to the boundary between the substrate 10 and the n-side electrode 80. In the present embodiment, the thickness of the substrate 10 is between the leftmost waveguide portion 40a1 and the central waveguide portion 40a3, and between the rightmost waveguide portion 40a5 and the central waveguide portion 40a3. Changes continuously, and there is a relationship of d3> d1 and d3> d5. That is, the thickness of the substrate 10 is larger than both end portions on the center side in the arrangement direction. Further, the lower surface of the substrate 10 (the lower surface in FIG. 1B) is inclined so that the central side in the arrangement direction is convex. The operation and effect of the semiconductor light emitting device 1 having the substrate 10 as described above will be described later.
 [半導体発光素子の製造方法]
 次に、実施の形態に係る半導体発光素子1の製造方法について、図2A~図2Iを用いて説明する。図2A~図2Iは、実施の形態に係る半導体発光素子1の製造方法における各工程を示す断面図である。
[Method for Manufacturing Semiconductor Light-Emitting Element]
Next, a method for manufacturing the semiconductor light emitting device 1 according to the embodiment will be described with reference to FIGS. 2A to 2I. 2A to 2I are cross-sectional views showing each step in the method for manufacturing the semiconductor light emitting device 1 according to the embodiment.
 まず、図2Aに示すように、主面が(0001)面であるn型六方晶GaN基板である基板10上に、有機金属気層成長法(Metalorganic Chemical Vapor Deposition;MOCVD法)を用いて、第1半導体層20、発光層30及び第2半導体層40を順次成膜する。 First, as shown in FIG. 2A, on a substrate 10 which is an n-type hexagonal GaN substrate having a (0001) plane as a main surface, using an organic metal vapor deposition method (MOCVD method), The first semiconductor layer 20, the light emitting layer 30, and the second semiconductor layer 40 are sequentially formed.
 具体的には、厚さ400μmの基板10の上に、第1半導体層20としてn型AlGaNからなるn側クラッド層を3μm成長させる。続いて、n-GaNからなるn側光ガイド層31を0.1μm成長させる。続いて、InGaNからなるバリア層とInGaN量子井戸層との3周期からなる活性層32を成長させる。続いて、p-GaNからなるp側光ガイド層33を0.1μm成長させる。続いて、AlGaNからなる電子障壁層41を10nm成長させる。続いて、膜厚1.5nmのp-AlGaN層と膜厚1.5nmのGaN層とを160周期繰り返して形成した厚さ0.48μmの歪超格子からなるp側クラッド層42を成長させる。続いて、p-GaNからなるp側コンタクト層43を0.05μm成長させる。ここで、各層において、Ga、Al及びInを含む有機金属原料には、例えば、それぞれトリメチルガリウム(TMG)、トリメチルアンモニウム(TMA)、トリメチルインジウム(TMI)を用いる。また、窒素原料には、アンモニア(NH)を用いる。 Specifically, an n-side cladding layer made of n-type AlGaN is grown as a first semiconductor layer 20 on the substrate 10 having a thickness of 400 μm by 3 μm. Subsequently, an n-side light guide layer 31 made of n-GaN is grown by 0.1 μm. Subsequently, an active layer 32 having three periods of a barrier layer made of InGaN and an InGaN quantum well layer is grown. Subsequently, a p-side light guide layer 33 made of p-GaN is grown by 0.1 μm. Subsequently, an electron barrier layer 41 made of AlGaN is grown by 10 nm. Subsequently, a p-side cladding layer 42 made of a strained superlattice having a thickness of 0.48 μm formed by repeating a 160-cycle p-AlGaN layer having a thickness of 1.5 nm and a GaN layer having a thickness of 1.5 nm is grown. Subsequently, a p-side contact layer 43 made of p-GaN is grown by 0.05 μm. Here, in each layer, for example, trimethylgallium (TMG), trimethylammonium (TMA), and trimethylindium (TMI) are used as organometallic raw materials containing Ga, Al, and In, respectively. In addition, ammonia (NH 3 ) is used as the nitrogen raw material.
 次に、図2Bに示すように、第2半導体層40上に、第1保護膜91を成膜する。具体的には、p側コンタクト層43の上に、シラン(SiH)を用いたプラズマCVD(Chemical Vapor Deposition)法によって、第1保護膜91として、シリコン酸化膜(SiO)を300nm成膜する。 Next, as shown in FIG. 2B, a first protective film 91 is formed on the second semiconductor layer 40. Specifically, a 300 nm thick silicon oxide film (SiO 2 ) is formed as the first protective film 91 on the p-side contact layer 43 by plasma CVD (Chemical Vapor Deposition) using silane (SiH 4 ). To do.
 なお、第1保護膜91の成膜方法は、プラズマCVD法に限るものではなく、例えば、熱CVD法、スパッタ法、真空蒸着法、又は、パルスレーザ成膜法など、公知の成膜方法を用いることができる。また、第1保護膜91の成膜材料は、上記のものに限るものではなく、例えば、誘電体や金属など、後述する第2半導体層40(p側クラッド層42、p側コンタクト層43)のエッチングに対して、選択性のある材料であればよい。 The film formation method of the first protective film 91 is not limited to the plasma CVD method. For example, a known film formation method such as a thermal CVD method, a sputtering method, a vacuum evaporation method, or a pulse laser film formation method is used. Can be used. In addition, the material for forming the first protective film 91 is not limited to the above, and for example, a second semiconductor layer 40 (a p-side cladding layer 42 and a p-side contact layer 43) described later, such as a dielectric or a metal. Any material may be used as long as it is selective with respect to the etching.
 次に、図2Cに示すように、フォトリソグラフィー法及びエッチング法を用いて、第1保護膜91が帯状に残るように、第1保護膜91を選択的に除去する。エッチング法としては、例えば、CFなどのフッ素系ガスを用いた反応性イオンエッチング(RIE)によるドライエッチング、又は、1:10程度に希釈した弗化水素酸(HF)などを用いたウェットエッチングを用いることができる。 Next, as shown in FIG. 2C, the first protective film 91 is selectively removed by using a photolithography method and an etching method so that the first protective film 91 remains in a strip shape. As an etching method, for example, dry etching by reactive ion etching (RIE) using a fluorine-based gas such as CF 4 or wet etching using hydrofluoric acid (HF) diluted to about 1:10 is used. Can be used.
 次に、図2Dに示すように、帯状に形成された第1保護膜91をマスクとして、p側コンタクト層43及びp側クラッド層42をエッチングすることで、第2半導体層40に導波路部40a1~40a5及び平坦部40bを形成する。p側コンタクト層43及びp側クラッド層42のエッチングとしては、Clなどの塩素系ガスを用いたRIE法によるドライエッチングを用いてもよい。 Next, as shown in FIG. 2D, the p-side contact layer 43 and the p-side cladding layer 42 are etched using the first protective film 91 formed in a band shape as a mask, so that the waveguide portion is formed in the second semiconductor layer 40. 40a1 to 40a5 and a flat portion 40b are formed. As the etching of the p-side contact layer 43 and the p-side cladding layer 42, dry etching by RIE using a chlorine-based gas such as Cl 2 may be used.
 次に、図2Eに示すように、帯状の第1保護膜91を弗化水素酸などを用いたウェットエッチングによって除去した後、p側コンタクト層43及びp側クラッド層42を覆うように、誘電体層60を成膜する。つまり、導波路部40a1~40a5及び平坦部40bの上に誘電体層60を形成する。誘電体層60としては、例えば、シラン(SiH)を用いたプラズマCVD法によって、シリコン酸化膜(SiO)を300nm成膜する。 Next, as shown in FIG. 2E, the strip-shaped first protective film 91 is removed by wet etching using hydrofluoric acid or the like, and then the dielectric is formed so as to cover the p-side contact layer 43 and the p-side cladding layer 42. The body layer 60 is formed. That is, the dielectric layer 60 is formed on the waveguide portions 40a1 to 40a5 and the flat portion 40b. As the dielectric layer 60, for example, a silicon oxide film (SiO 2 ) having a thickness of 300 nm is formed by a plasma CVD method using silane (SiH 4 ).
 なお、誘電体層60の成膜方法は、プラズマCVD法に限るものではなく、熱CVD法、スパッタ法、真空蒸着法、又は、パルスレーザ成膜法などの成膜方法を用いてもよい。 The film formation method of the dielectric layer 60 is not limited to the plasma CVD method, and a film formation method such as a thermal CVD method, a sputtering method, a vacuum deposition method, or a pulse laser film formation method may be used.
 次に、図2Fに示すように、フォトリソグラフィー法と弗化水素酸を用いたウェットエッチングとにより、導波路部40a1~40a5上の誘電体層60のみを除去して、p側コンタクト層43の上面を露出させる。その後、真空蒸着法及びリフトオフ法を用いて、導波路部40a1~40a5上のみにPd/Ptからなるp側電極51を形成する。具体的には、誘電体層60から露出させたp側コンタクト層43の上にp側電極51を形成する。 Next, as shown in FIG. 2F, only the dielectric layer 60 on the waveguide portions 40a1 to 40a5 is removed by photolithography and wet etching using hydrofluoric acid, and the p-side contact layer 43 is removed. Expose the top surface. Thereafter, the p-side electrode 51 made of Pd / Pt is formed only on the waveguide portions 40a1 to 40a5 by using a vacuum deposition method and a lift-off method. Specifically, the p-side electrode 51 is formed on the p-side contact layer 43 exposed from the dielectric layer 60.
 なお、p側電極51の成膜方法は、真空蒸着法に限るものではなく、スパッタ法又はパルスレーザ成膜法などであってもよい。また、p側電極51の電極材料は、Ni/Au系、Pt系など、第2半導体層40(p側コンタクト層43)とオーミック接触する材料であればよい。 In addition, the film formation method of the p-side electrode 51 is not limited to the vacuum evaporation method, and may be a sputtering method or a pulse laser film formation method. The electrode material of the p-side electrode 51 may be any material that is in ohmic contact with the second semiconductor layer 40 (p-side contact layer 43), such as Ni / Au or Pt.
 次に、図2Gに示すように、p側電極51、誘電体層60を覆うようにパッド電極52を形成する。具体的には、フォトリソグラフィー法などによって、形成したい部分以外にレジストをパターニングし、基板10の上方の全面に真空蒸着法などによってTi/Pt/Auからなるパッド電極52を形成し、リフトオフ法を用いて不要な部分の電極を除去する。これにより、p側電極51、誘電体層60の上に所定形状のパッド電極52を形成できる。以上のように、p側電極51及びパッド電極52からなる電極部材50が形成される。 Next, as shown in FIG. 2G, a pad electrode 52 is formed so as to cover the p-side electrode 51 and the dielectric layer 60. Specifically, a resist is patterned on a portion other than a portion to be formed by a photolithography method or the like, and a pad electrode 52 made of Ti / Pt / Au is formed on the entire upper surface of the substrate 10 by a vacuum deposition method or the like. Use to remove unnecessary portions of the electrode. Thereby, a pad electrode 52 having a predetermined shape can be formed on the p-side electrode 51 and the dielectric layer 60. As described above, the electrode member 50 including the p-side electrode 51 and the pad electrode 52 is formed.
 次に、図2Hに示すように、基板10を薄膜化する。これは、個片化を容易にするため、及び放熱性を向上させるのが目的である。基板10は、砥粒と薬液とを用いた物理的及び化学的研磨により薄膜化できる。本実施の形態では、厚さ400μmの基板10を厚さ約85μmまで薄膜化した。この際に、基板10を研磨面に対して斜めに設置することで、基板の厚さ分布を制御できる。具体的には、基板の中央部が基板の端部よりも約3μm厚くなるように、基板を研磨台に対して約0.1度傾けて研磨した。本実施の形態では、研磨により、図1Bで定義した基板厚さ(d1~d5)を、d1=85μm、d2=87μm、d3=88μm、d4=86μm、d5=84μmとした。このように、基板10の下面に凸形状を形成することができる。 Next, as shown in FIG. 2H, the substrate 10 is thinned. This is for the purpose of facilitating singulation and improving heat dissipation. The substrate 10 can be thinned by physical and chemical polishing using abrasive grains and a chemical solution. In the present embodiment, the substrate 10 having a thickness of 400 μm is thinned to a thickness of about 85 μm. At this time, the thickness distribution of the substrate can be controlled by installing the substrate 10 obliquely with respect to the polishing surface. Specifically, the substrate was polished with an inclination of about 0.1 degree with respect to the polishing table so that the center portion of the substrate was about 3 μm thicker than the end portion of the substrate. In this embodiment, the substrate thicknesses (d1 to d5) defined in FIG. 1B are set to d1 = 85 μm, d2 = 87 μm, d3 = 88 μm, d4 = 86 μm, and d5 = 84 μm by polishing. Thus, a convex shape can be formed on the lower surface of the substrate 10.
 なお、研磨以外の手法でも、例えば、ドライエッチングなどでも基板厚さの分布を調整できる。反応性ガスに高電圧を印加することでプラズマを発生させ、このプラズマ中のイオン又はラジカルがウエハに衝突することでエッチングが進行する。このときに、プラズマの密度又はエネルギーに差があれば、基板10の位置に応じてエッチング量を調整できる。 It should be noted that the substrate thickness distribution can be adjusted by a method other than polishing, for example, dry etching. Plasma is generated by applying a high voltage to the reactive gas, and etching proceeds when ions or radicals in the plasma collide with the wafer. At this time, if there is a difference in plasma density or energy, the etching amount can be adjusted according to the position of the substrate 10.
 例えば、供給するガスをウエハの端部から供給し、ウエハの中央部から排気することで、基板10の位置に応じてエッチング量を調整できる。この手法ではガス供給の上流側でプラズマが多く生成され、下流側では少なくなる。この結果、上流側でエッチングが多く進行し、下流側で少なく進行する。 For example, the etching amount can be adjusted according to the position of the substrate 10 by supplying the gas to be supplied from the edge of the wafer and exhausting it from the center of the wafer. In this method, a lot of plasma is generated on the upstream side of the gas supply and decreases on the downstream side. As a result, a large amount of etching proceeds on the upstream side and a small amount proceeds on the downstream side.
 別の手法として、ガス供給を均一にした場合でも、印加する高電圧の分布を変えることで、基板10の位置に応じてエッチング量を調整できる。例えば、ウエハの端部に高電圧を印加し、中央部では、これよりも小さい電圧を印加することで、基板10の位置に応じてエッチング量を変えることができる。 As another method, even when the gas supply is made uniform, the etching amount can be adjusted according to the position of the substrate 10 by changing the distribution of the applied high voltage. For example, the etching amount can be changed in accordance with the position of the substrate 10 by applying a high voltage to the edge of the wafer and applying a voltage lower than this at the center.
 次に、図2Iに示すように、基板10の下面にn側電極80を形成する。具体的には、基板10の裏面に真空蒸着法などによってTi/Pt/Auからなるn側電極80を形成し、フォトリソグラフィー法及びエッチング法を用いてパターニングすることで、所定形状のn側電極80を形成する。これにより、本実施の形態に係る半導体発光素子1を製造することができる。 Next, as shown in FIG. 2I, an n-side electrode 80 is formed on the lower surface of the substrate 10. Specifically, an n-side electrode 80 made of Ti / Pt / Au is formed on the back surface of the substrate 10 by vacuum deposition or the like, and patterned by using a photolithography method and an etching method, whereby an n-side electrode having a predetermined shape is formed. 80 is formed. Thereby, the semiconductor light emitting element 1 according to the present embodiment can be manufactured.
 [半導体発光装置]
 次に、本実施の形態に係る半導体発光素子1が実装された半導体発光装置について、図3Aを用いて説明する。図3Aは、本実施の形態に係る半導体発光装置2の構成を示す模式的な断面図である。図3Aに示すように、半導体発光装置2は、半導体発光素子1と、サブマウント100と、を備える。サブマウント100は、第1基台101と、第1電極102aと、第3電極102bと、第1接着層103aと、第3接着層103bと、を有する。
[Semiconductor light emitting device]
Next, a semiconductor light emitting device on which the semiconductor light emitting element 1 according to the present embodiment is mounted will be described with reference to FIG. 3A. FIG. 3A is a schematic cross-sectional view showing the configuration of the semiconductor light emitting device 2 according to the present embodiment. As shown in FIG. 3A, the semiconductor light emitting device 2 includes a semiconductor light emitting element 1 and a submount 100. The submount 100 includes a first base 101, a first electrode 102a, a third electrode 102b, a first adhesive layer 103a, and a third adhesive layer 103b.
 第1基台は、半導体発光素子1の基板10の下方に配置された基台であり、ヒートシンクとして機能する。第1基台101の材料は、特に限定されるものではないが、アルミナイトライド(AlN)、シリコンカーバイト(SiC)などのセラミック、CVDで成膜されたダイヤモンド(C)、CuやAlなどの金属単体、又は、CuWなどの合金など、半導体発光素子1と比べて熱伝導率が同等かそれ以上の材料で構成されていてもよい。 The first base is a base disposed below the substrate 10 of the semiconductor light emitting element 1 and functions as a heat sink. The material of the first base 101 is not particularly limited, but ceramics such as aluminum nitride (AlN) and silicon carbide (SiC), diamond (C) formed by CVD, Cu, Al, etc. The metal may be composed of a material having a thermal conductivity equivalent to or higher than that of the semiconductor light emitting device 1 such as a simple metal or an alloy such as CuW.
 第1電極102aは、第1基台101の一方の面に配置される。また、第3電極102bは、第1基台101の他方の面に配置される。本実施の形態では、第1電極102aは、第1基台101の半導体発光素子1側の面に配置される。第1電極102a及び第3電極102bは、例えば、膜厚0.1μmのTi、膜厚0.2μmのPt及び膜厚0.2μmのAuの三つの金属膜からなる積層膜である。 The first electrode 102 a is disposed on one surface of the first base 101. The third electrode 102 b is disposed on the other surface of the first base 101. In the present embodiment, the first electrode 102 a is disposed on the surface of the first base 101 on the semiconductor light emitting element 1 side. The first electrode 102a and the third electrode 102b are, for example, a laminated film composed of three metal films of Ti having a thickness of 0.1 μm, Pt having a thickness of 0.2 μm, and Au having a thickness of 0.2 μm.
 第1接着層103aは、半導体発光素子1を第1基台に接着する接着層である。第1接着層103aは、第1電極102aの上方に配置される。第3接着層103bは、第3電極102bの上方に形成される。第1接着層103a及び第3接着層103bは、例えば、Au及びSnがそれぞれ70%及び30%の含有率で含まれる金スズ合金からなる共晶半田である。本実施の形態では、第1接着層103a及び第3接着層103bの最大厚さは、6μm程度である。第1接着層103aは、半導体発光素子1の基板10及び第1基台101より熱伝導率が低い。 The first adhesive layer 103a is an adhesive layer that adheres the semiconductor light emitting element 1 to the first base. The first adhesive layer 103a is disposed above the first electrode 102a. The third adhesive layer 103b is formed above the third electrode 102b. The first adhesive layer 103a and the third adhesive layer 103b are eutectic solder made of a gold-tin alloy containing, for example, 70% and 30% content of Au and Sn, respectively. In the present embodiment, the maximum thickness of the first adhesive layer 103a and the third adhesive layer 103b is about 6 μm. The first adhesive layer 103 a has a lower thermal conductivity than the substrate 10 and the first base 101 of the semiconductor light emitting device 1.
 半導体発光素子1は、サブマウント100に実装される。本実施の形態では、半導体発光素子1のn側電極80側の面がサブマウント100に接続される実装形態、つまりジャンクションアップ実装であるので、半導体発光素子1のn側電極80がサブマウント100の第1接着層103aに接続される。ここで、半導体発光素子1の基板10の上面は、発光部71~75の配列方向において、第1基台101の第1接着層103aとの接合面と平行である。これにより、半導体発光素子1からの出射光の伝播方向と、第1基台101の上面と、がほぼ平行になるため、第1基台101の上面を光軸のアライメントの基準として利用できる。このため、光軸調整が容易な半導体発光装置2を実現できる。 The semiconductor light emitting device 1 is mounted on the submount 100. In the present embodiment, since the surface on the n-side electrode 80 side of the semiconductor light-emitting element 1 is connected to the submount 100, that is, junction-up mounting, the n-side electrode 80 of the semiconductor light-emitting element 1 is connected to the submount 100. To the first adhesive layer 103a. Here, the upper surface of the substrate 10 of the semiconductor light emitting element 1 is parallel to the bonding surface of the first base 101 with the first adhesive layer 103a in the arrangement direction of the light emitting portions 71 to 75. Thereby, since the propagation direction of the emitted light from the semiconductor light emitting element 1 and the upper surface of the first base 101 are substantially parallel, the upper surface of the first base 101 can be used as a reference for alignment of the optical axis. For this reason, the semiconductor light-emitting device 2 with easy optical axis adjustment is realizable.
 図1Bで示したように、配列方向中央の導波路部40a3の直下の基板10の厚さd3、右端の導波路部40a5直下の厚さd5、左端の導波路部40a1直下の厚さd1の間には、d3>d1及びd3>d5の関係がある。ここで、図3Aに示すように、5つの導波路部40a1~40a5直下(つまり、発光部71~75直下)の第1接着層103aの厚さを、左から順番に、s1、s2、s3、s4及びs5と定義する。本実施の形態では、s1=4.2μm、s2=2.1μm、s3=1.0μm、s4=2.9μm、s5=4.8μmである。s1、s3、s5の間には、s3<s1及びs3<s5の関係がある。つまり、中央部の第1接着層103aの厚さs3が、端部の第1接着層103aの厚さs1及びs5よりも薄くなっている。また、第1接着層103aの厚さは、基板10の中央部と基板10の端部間の厚さの差よりも厚い。なお、本実施の形態のように、第1接着層103aに金スズ半田を用いて実装する場合、金スズ半田がn側電極80の金及び第1電極102aの金と共晶反応を起こすため、境界を判別するのが困難となることがある。その場合は、ここでの第1接着層103aの厚さは、n側電極80の金スズと共晶反応しない層(例えば、Pt)から、第1電極102aの金スズと共晶反応しない層(例えば、Pt)までの距離と定義する。なお、図示しないが、サブマウント100は、放熱性の向上及び取り扱いの簡便化の目的で、例えば、金属パッケージに実装される。つまり、第3接着層103bによって金属パッケージに接着される。なお、第1基台101自体がパッケージとして機能してもよい。この場合、サブマウント100は、第3接着層103bを備えなくてもよい。 As shown in FIG. 1B, the thickness d3 of the substrate 10 immediately below the waveguide section 40a3 at the center in the arrangement direction, the thickness d5 immediately below the waveguide section 40a5 at the right end, and the thickness d1 directly below the waveguide section 40a1 at the left end. There is a relationship between d3> d1 and d3> d5. Here, as shown in FIG. 3A, the thickness of the first adhesive layer 103a immediately below the five waveguide portions 40a1 to 40a5 (that is, immediately below the light emitting portions 71 to 75) is set to s1, s2, s3 in order from the left. , S4 and s5. In this embodiment, s1 = 4.2 μm, s2 = 2.1 μm, s3 = 1.0 μm, s4 = 2.9 μm, and s5 = 4.8 μm. There is a relationship of s3 <s1 and s3 <s5 between s1, s3, and s5. That is, the thickness s3 of the first adhesive layer 103a at the center is thinner than the thicknesses s1 and s5 of the first adhesive layer 103a at the end. Further, the thickness of the first adhesive layer 103 a is thicker than the difference in thickness between the center portion of the substrate 10 and the end portion of the substrate 10. Note that, as in the present embodiment, when mounting on the first adhesive layer 103a using gold tin solder, the gold tin solder causes a eutectic reaction with the gold of the n-side electrode 80 and the gold of the first electrode 102a. , It may be difficult to determine the boundary. In this case, the thickness of the first adhesive layer 103a here is a layer that does not eutectic react with gold tin of the first electrode 102a from a layer that does not eutectic react with gold tin of the n-side electrode 80 (for example, Pt). It is defined as the distance to (for example, Pt). Although not shown, the submount 100 is mounted on, for example, a metal package for the purpose of improving heat dissipation and simplifying handling. That is, it adheres to the metal package by the third adhesive layer 103b. Note that the first base 101 itself may function as a package. In this case, the submount 100 may not include the third adhesive layer 103b.
 また、図3Aに示した半導体発光装置2では、半導体発光素子1はジャンクションアップ実装されたが、半導体発光素子1の電極部材50側がサブマウント100に接続される実装形態、すなわちジャンクションダウン実装を適用してもよい。以下、このような実装形態について図3Bを用いて説明する。 Further, in the semiconductor light emitting device 2 shown in FIG. 3A, the semiconductor light emitting element 1 is junction-up mounted, but a mounting form in which the electrode member 50 side of the semiconductor light emitting element 1 is connected to the submount 100, that is, junction down mounting is applied. May be. Hereinafter, such an implementation will be described with reference to FIG. 3B.
 図3Bは、本実施の形態の変形例に係る半導体発光装置3の構成を示す模式的な断面図である。図3Bに示すように、本変形例に係る半導体発光装置3は、半導体発光素子1と、サブマウント300と、放熱部200と、を備える。サブマウント300は、第2基台301と、第2電極302aと、第4電極302bと、第2接着層303aと、第4接着層303bと、を有する。放熱部200は、第1基台201と、第1接着層203と、を有する。 FIG. 3B is a schematic cross-sectional view showing a configuration of a semiconductor light emitting device 3 according to a modification of the present embodiment. As shown in FIG. 3B, the semiconductor light emitting device 3 according to this modification includes a semiconductor light emitting element 1, a submount 300, and a heat dissipation part 200. The submount 300 includes a second base 301, a second electrode 302a, a fourth electrode 302b, a second adhesive layer 303a, and a fourth adhesive layer 303b. The heat radiating unit 200 includes a first base 201 and a first adhesive layer 203.
 第1基台201は、半導体発光素子1の基板10の下面(図3Bの上側面)の下方(図3Bの上側)に配置された基台である。第1接着層203は、半導体発光素子1を第1基台201に接着する接着層である。 The first base 201 is a base disposed below (upper side of FIG. 3B) below the lower surface (upper side surface of FIG. 3B) of the substrate 10 of the semiconductor light emitting element 1. The first adhesive layer 203 is an adhesive layer that adheres the semiconductor light emitting element 1 to the first base 201.
 第2基台301は、半導体発光素子1を挟んで第1基台201とは反対側に配置された基台である。第2接着層303aは、半導体発光素子1を第2基台301に接着する接着層である。第2電極302aは、第2基台301の一方の面に配置される。また、第4電極302bは、第2基台301の他方の面に配置される。本実施の形態では、第2電極302aは、第2基台301の半導体発光素子1側の面に配置される。 The second base 301 is a base disposed on the opposite side of the first base 201 with the semiconductor light emitting element 1 interposed therebetween. The second adhesive layer 303 a is an adhesive layer that adheres the semiconductor light emitting element 1 to the second base 301. The second electrode 302 a is disposed on one surface of the second base 301. The fourth electrode 302b is disposed on the other surface of the second base 301. In the present embodiment, the second electrode 302a is disposed on the surface of the second base 301 on the semiconductor light emitting element 1 side.
 本変形例に係る第2基台301及び第1基台201は、半導体発光装置2の第1基台101と同様の構成を有する。また、本変形例に係る第2電極302a及び第4電極302bは、半導体発光装置2の第1電極102a及び第3電極102bと同様の構成を有する。第4接着層303bは、半導体発光装置2の第3接着層103bと同様の構成を有する。 The second base 301 and the first base 201 according to this modification have the same configuration as the first base 101 of the semiconductor light emitting device 2. Further, the second electrode 302a and the fourth electrode 302b according to this modification have the same configuration as the first electrode 102a and the third electrode 102b of the semiconductor light emitting device 2. The fourth adhesive layer 303b has the same configuration as the third adhesive layer 103b of the semiconductor light emitting device 2.
 半導体発光装置3では、半導体発光素子1の電極部材50がサブマウント300の第2接着層303aに接続される。このように、半導体発光素子1をジャンクションダウン実装することで、発熱源に近い電極部材50側がサブマウント300に接続されるので、半導体発光素子1の放熱性を向上させることができる。第2接着層303aは、例えば、Au(70%)及びSn(30%)の金スズ合金からなる最大厚さ3μm程度の共晶半田である。さらに、放熱性を向上させるため、n側電極80側にも放熱部200を接続する。放熱部200上の一面には、第1接着層203が形成されており、この第1接着層203がn側電極80と接続されている。このように、半導体発光素子1の両側を熱伝導率が高い材料で挟むことで、半導体発光装置3の放熱性を向上させることができる。 In the semiconductor light emitting device 3, the electrode member 50 of the semiconductor light emitting element 1 is connected to the second adhesive layer 303 a of the submount 300. As described above, by mounting the semiconductor light emitting element 1 in a junction-down manner, the electrode member 50 side close to the heat source is connected to the submount 300, so that the heat dissipation of the semiconductor light emitting element 1 can be improved. The second adhesive layer 303a is eutectic solder having a maximum thickness of about 3 μm made of, for example, a gold-tin alloy of Au (70%) and Sn (30%). Furthermore, in order to improve heat dissipation, the heat dissipation part 200 is also connected to the n-side electrode 80 side. A first adhesive layer 203 is formed on one surface of the heat radiating portion 200, and the first adhesive layer 203 is connected to the n-side electrode 80. Thus, the heat dissipation of the semiconductor light-emitting device 3 can be improved by sandwiching both sides of the semiconductor light-emitting element 1 with a material having high thermal conductivity.
 本変形例では、半導体発光素子1のn側電極80が接続される第1接着層203の厚さが、中央部と端部で異なる。図3Bに示すように、第1接着層203の厚さを、w1、w2、w3、w4及びw5と定義する。基板10の厚さ(d1~d5)は、半導体発光装置2と同様である。本変形例では、w1=4.3μm、w2=2.2μm、w3=1.2μm、w4=3.1μm、w5=5.1μmであった。 In the present modification, the thickness of the first adhesive layer 203 to which the n-side electrode 80 of the semiconductor light emitting element 1 is connected differs between the center portion and the end portion. As shown in FIG. 3B, the thickness of the first adhesive layer 203 is defined as w1, w2, w3, w4, and w5. The thickness (d1 to d5) of the substrate 10 is the same as that of the semiconductor light emitting device 2. In this modification, w1 = 4.3 μm, w2 = 2.2 μm, w3 = 1.2 μm, w4 = 3.1 μm, and w5 = 5.1 μm.
 第1接着層203は、例えば、半導体発光装置2と同様に、膜厚0.1μmのTi、膜厚0.2μmのPt及び膜厚0.2μmのAuの三つの金属膜からなる積層膜上に、Au及びSnがそれぞれ70%及び30%の含有率で含まれる金スズ合金からなる最大厚さ6μm程度の共晶はんだが形成された構造である。この場合、n側電極80と放熱部200とを強固に接続できるため、半導体発光素子1からの熱を効率よく排熱することができる。また、第1接着層203として、例えば、金などの第1基台201及び基板10に対して柔らかい材料を用いることもできる。この場合、第1接着層203とn側電極80は接触しているだけなので半導体発光素子1の固定はできないが、レーザからの熱を排熱することができる。また、この構成では半導体発光素子にかかる不要な応力を減らすことができるため、信頼性が向上する。 For example, as in the semiconductor light emitting device 2, the first adhesive layer 203 is formed on a laminated film composed of three metal films of Ti having a thickness of 0.1 μm, Pt having a thickness of 0.2 μm, and Au having a thickness of 0.2 μm. Further, a eutectic solder having a maximum thickness of about 6 μm made of a gold-tin alloy containing Au and Sn at a content of 70% and 30%, respectively, is formed. In this case, since the n-side electrode 80 and the heat dissipation part 200 can be firmly connected, the heat from the semiconductor light emitting element 1 can be efficiently exhausted. Further, as the first adhesive layer 203, for example, a soft material such as gold for the first base 201 and the substrate 10 can be used. In this case, since the first adhesive layer 203 and the n-side electrode 80 are only in contact with each other, the semiconductor light emitting device 1 cannot be fixed, but heat from the laser can be exhausted. Further, in this configuration, unnecessary stress applied to the semiconductor light emitting element can be reduced, so that reliability is improved.
 また、本実施の形態では、各接着層の材料として金スズ合金を示したが、Sn-Ag系、Sn-Cu系半田など、基板10、第1基台101及び201、並びに、第2基台301より熱伝導率が低い材料であれば、公知の半導体接合に用いられている材料を用いてもよい。 In this embodiment, a gold-tin alloy is shown as the material of each adhesive layer. However, the substrate 10, the first bases 101 and 201, and the second base, such as Sn—Ag series and Sn—Cu series solder, are shown. As long as the material has a lower thermal conductivity than that of the table 301, a material used for known semiconductor bonding may be used.
 [半導体発光装置の作用効果]
 次に、本実施の形態に係る半導体発光装置2の作用効果について、図4を用いて説明する。図4は、実施の形態に係る半導体発光装置2の各導波路部の温度の概要を示すグラフである。図4において、本実施の形態に係る半導体発光装置2における半導体発光素子1の各導波路部の温度が実線で示されており、特許文献1に記載されたような構成を有する比較例の半導体発光装置の各導波路部の温度が破線で示されている。比較例の半導体発光装置では、図4に破線で示すように、中央部の導波路部40a3の温度が、端部の導波路部の温度よりも高い。これは、中央に近い導波路部ほど外側の導波路部で発生した熱の影響を受けるためである。
[Effects of semiconductor light emitting device]
Next, functions and effects of the semiconductor light emitting device 2 according to the present embodiment will be described with reference to FIG. FIG. 4 is a graph showing an outline of the temperature of each waveguide portion of the semiconductor light emitting device 2 according to the embodiment. In FIG. 4, the temperature of each waveguide part of the semiconductor light emitting element 1 in the semiconductor light emitting device 2 according to the present embodiment is indicated by a solid line, and the semiconductor of the comparative example having the configuration described in Patent Document 1 The temperature of each waveguide part of the light emitting device is indicated by a broken line. In the semiconductor light emitting device of the comparative example, as indicated by a broken line in FIG. 4, the temperature of the central waveguide portion 40a3 is higher than the temperature of the end waveguide portion. This is because the waveguide portion closer to the center is affected by the heat generated in the outer waveguide portion.
 これに対し、本実施の形態に係る半導体発光装置は、上述したように、半導体発光素子1と、基板10の下面の下方に配置された第1基台101と、半導体発光素子1を第1基台101に接着する第1接着層103aと、を備える。また、基板10は、第1接着層103aより熱伝導率が高く、第1接着層103aの厚さは、三つ以上の発光部の配列方向の中央側において、両方の端部側より小さい。 On the other hand, as described above, the semiconductor light emitting device according to the present embodiment includes the semiconductor light emitting element 1, the first base 101 disposed below the lower surface of the substrate 10, and the semiconductor light emitting element 1 as the first. A first adhesive layer 103a that adheres to the base 101. Further, the substrate 10 has higher thermal conductivity than the first adhesive layer 103a, and the thickness of the first adhesive layer 103a is smaller than both end portions on the center side in the arrangement direction of three or more light emitting portions.
 このように、基板10より熱伝導率が低い第1接着層103aの配列方向の中央側における厚さを小さくすることで、第1接着層103aの中央側での放熱性を両方の端部側より高めることができる。これにより、三つ以上の発光部71~75のうち配列方向の中央側の発光部が、隣接する発光部との熱干渉に起因して、両方の端部側の発光部より高温となることを抑制できる。このため、図4に実線で示すように、配列方向の中央部の導波路部の温度を下げることで、ほぼ均一な温度分布を実現できる。 Thus, by reducing the thickness of the first adhesive layer 103a having a lower thermal conductivity than that of the substrate 10 on the center side in the arrangement direction, the heat dissipation on the center side of the first adhesive layer 103a is reduced on both end sides. Can be increased. As a result, among the three or more light emitting portions 71 to 75, the light emitting portion on the center side in the arrangement direction becomes higher in temperature than the light emitting portions on both end sides due to thermal interference with the adjacent light emitting portions. Can be suppressed. For this reason, as shown by a solid line in FIG. 4, a substantially uniform temperature distribution can be realized by lowering the temperature of the central waveguide portion in the arrangement direction.
 この効果について、より具体的に説明する。第1接着層103aは、金スズ合金で構成されており、その熱伝導率は57W/m・Kである。また、基板10は、GaNで構成されており、その熱伝導率は200W/m・Kである。このように接合に用いられている第1接着層103aは基板10より熱伝導率が低いため、第1接着層103aが薄くなるにしたがって放熱性は向上する。一方、半導体発光素子1と第1基台101との接合強度を保つためには、第1接着層103aにはある程度の厚さが必要となるため、一様に第1接着層103aを薄くすることはできない。そこで本実施の形態では、第1接着層103aより熱伝導率の高い基板10の中央部を厚くすることで、その直下の第1接着層103aを薄くし、配列方向の中央部のみ放熱性を向上させている。なお、半導体発光素子1の両側を挟み込んだ上記変形例に係る半導体発光装置3においても同様の効果を得られる。半導体発光装置3においては、配列方向の中央部の第1接着層203の厚さを薄くすることで、温度分布を均一化している。 This effect will be explained more specifically. The first adhesive layer 103a is made of a gold-tin alloy and has a thermal conductivity of 57 W / m · K. The substrate 10 is made of GaN, and its thermal conductivity is 200 W / m · K. Since the first adhesive layer 103a used for bonding in this manner has a lower thermal conductivity than the substrate 10, the heat dissipation improves as the first adhesive layer 103a becomes thinner. On the other hand, in order to maintain the bonding strength between the semiconductor light emitting element 1 and the first base 101, the first adhesive layer 103a needs to have a certain thickness, and thus the first adhesive layer 103a is uniformly thinned. It is not possible. Therefore, in the present embodiment, by thickening the central portion of the substrate 10 having a higher thermal conductivity than the first adhesive layer 103a, the first adhesive layer 103a immediately below is thinned, and only the central portion in the arrangement direction has heat dissipation properties. It is improving. The same effect can be obtained also in the semiconductor light emitting device 3 according to the above-described modified example in which both sides of the semiconductor light emitting element 1 are sandwiched. In the semiconductor light emitting device 3, the temperature distribution is made uniform by reducing the thickness of the first adhesive layer 203 at the center in the arrangement direction.
 以上のように、本実施の形態に係る半導体発光装置2及び変形例に係る半導体発光装置3では、三つ以上の発光部における温度分布の不均一を抑制できるため、半導体発光装置の信頼性の悪化を抑制できる。 As described above, in the semiconductor light emitting device 2 according to the present embodiment and the semiconductor light emitting device 3 according to the modification, it is possible to suppress nonuniform temperature distribution in three or more light emitting units, and thus the reliability of the semiconductor light emitting device is improved. Deterioration can be suppressed.
 (変形例)
 以上、本開示に係る半導体発光装置について、実施の形態及び変形例に基づいて説明したが、本開示は、上記実施の形態等に限定されるものではない。
(Modification)
Although the semiconductor light emitting device according to the present disclosure has been described based on the embodiments and the modifications, the present disclosure is not limited to the above embodiments and the like.
 例えば、上記実施の形態等に対して当業者が思い付く各種変形を施して得られる形態や、本開示の趣旨を逸脱しない範囲で実施の形態及び変形例における構成要素及び機能を任意に組み合わせることで実現される形態も本開示に含まれる。 For example, it is possible to arbitrarily combine the components and functions in the embodiments and modifications without departing from the spirit of the present disclosure, or forms obtained by making various modifications conceived by those skilled in the art with respect to the above-described embodiments and the like. Implemented forms are also included in the present disclosure.
 例えば、上記実施の形態に係る半導体発光装置2においては、半導体発光素子1の基板10は、中央の導波路部40a3の直下(つまり、発光部73の直下)における基板10の厚さが最大であったが、基板10の構成はこれに限定されない。以下、各変形例について図5A~5D及び図6を用いて説明する。図5A~図5Dは、それぞれ変形例1~4に係る半導体発光装置2a~2dの構成を示す模式的な断面図である。図6は、変形例5に係る半導体発光装置402の構成を示す模式的な断面図である。図5A~図5Cに示す半導体発光装置2a~2cは、それぞれ半導体発光素子1a~1cの基板10a~10cの形状において、実施の形態に係る半導体発光装置2と相違しその他の点において一致する。また、図5Dに示す半導体発光装置2dは、半導体発光素子1dの導波路部(つまり、発光部)の個数において、実施の形態に係る半導体発光装置2と相違しその他の点において一致する。 For example, in the semiconductor light emitting device 2 according to the above embodiment, the substrate 10 of the semiconductor light emitting element 1 has the maximum thickness of the substrate 10 immediately below the central waveguide portion 40a3 (that is, directly below the light emitting portion 73). However, the configuration of the substrate 10 is not limited to this. Each modification will be described below with reference to FIGS. 5A to 5D and FIG. 5A to 5D are schematic cross-sectional views showing the configurations of the semiconductor light emitting devices 2a to 2d according to the modified examples 1 to 4, respectively. FIG. 6 is a schematic cross-sectional view showing a configuration of a semiconductor light emitting device 402 according to Modification 5. The semiconductor light emitting devices 2a to 2c shown in FIGS. 5A to 5C are different from the semiconductor light emitting device 2 according to the embodiment in the shapes of the substrates 10a to 10c of the semiconductor light emitting elements 1a to 1c, respectively, and are identical in other points. Further, the semiconductor light emitting device 2d shown in FIG. 5D is different from the semiconductor light emitting device 2 according to the embodiment in the number of waveguide portions (that is, light emitting portions) of the semiconductor light emitting element 1d, and is identical in other points.
 図5Aに示す変形例1に係る半導体発光装置2aのように、基板10aの厚さは、中央の導波路部40a3の直下で最大とならなくてもよい。このような構成であっても、導波路部40a1~40a5のそれぞれの直下の基板10aの厚さd1~d5に対して、d1<d2<d3、かつ、d3>d4>d5が成り立ち得る。これに伴い、導波路部40a1~40a5のそれぞれの直下の第1接着層103aの厚さs1~s5に対して、s1>s2>s3、かつ、s3<s4<s5が成り立つ。このため、本変形例に係る半導体発光装置2aにおいても、上記実施の形態に係る半導体発光装置2と同様の効果を得られる。 As in the semiconductor light emitting device 2a according to the first modification illustrated in FIG. 5A, the thickness of the substrate 10a may not be the maximum immediately below the central waveguide portion 40a3. Even with such a configuration, d1 <d2 <d3 and d3> d4> d5 can be satisfied with respect to the thicknesses d1 to d5 of the substrate 10a immediately below the waveguide portions 40a1 to 40a5. Accordingly, s1> s2> s3 and s3 <s4 <s5 are established with respect to the thicknesses s1 to s5 of the first adhesive layer 103a immediately below each of the waveguide portions 40a1 to 40a5. For this reason, also in the semiconductor light-emitting device 2a which concerns on this modification, the effect similar to the semiconductor light-emitting device 2 which concerns on the said embodiment is acquired.
 また、図5Bに示す変形例2に係る半導体発光装置2bのように、基板10bの厚さは、中央の導波路部40a3の直下付近で一様となってもよい。言い換えると、基板10bの下面は、配列方向の中央付近で上面と平行であってもよい。このような構成であっても、導波路部40a1~40a5のそれぞれの直下の第1接着層103aの厚さs1~s5に対して、s1>s2>s3、かつ、s3<s4<s5が成り立ち得る。このため、本変形例に係る半導体発光装置2bにおいても、上記実施の形態に係る半導体発光装置2と同様の効果を得られる。 Further, as in the semiconductor light emitting device 2b according to Modification 2 shown in FIG. 5B, the thickness of the substrate 10b may be uniform in the vicinity immediately below the central waveguide portion 40a3. In other words, the lower surface of the substrate 10b may be parallel to the upper surface near the center in the arrangement direction. Even in such a configuration, s1> s2> s3 and s3 <s4 <s5 are satisfied with respect to the thicknesses s1 to s5 of the first adhesive layer 103a immediately below the waveguide portions 40a1 to 40a5. obtain. For this reason, also in the semiconductor light-emitting device 2b which concerns on this modification, the effect similar to the semiconductor light-emitting device 2 which concerns on the said embodiment is acquired.
 また、図5Cに示す変形例3に係る半導体発光装置2cのように、基板10cの厚さは、ステップ状に変化してもよい。言い換えると、基板10cの厚さは、離散的に変化してもよい。このような構成であっても、導波路部40a1~40a5のそれぞれの直下の第1接着層103aの厚さs1~s5に対して、s1>s2>s3、かつ、s3<s4<s5が成り立ち得る。このため、本変形例に係る半導体発光装置2cにおいても、上記実施の形態に係る半導体発光装置2と同様の効果を得られる。 Further, as in the semiconductor light emitting device 2c according to Modification 3 shown in FIG. 5C, the thickness of the substrate 10c may be changed stepwise. In other words, the thickness of the substrate 10c may change discretely. Even in such a configuration, s1> s2> s3 and s3 <s4 <s5 are satisfied with respect to the thicknesses s1 to s5 of the first adhesive layer 103a immediately below the waveguide portions 40a1 to 40a5. obtain. For this reason, also in the semiconductor light-emitting device 2c which concerns on this modification, the effect similar to the semiconductor light-emitting device 2 which concerns on the said embodiment is acquired.
 また、図5Dに示す変形例4に係る半導体発光装置2dのように、導波路部及び発光部の個数は偶数であってもよい。このような構成であっても、導波路部40a1~40a4のそれぞれの直下の第1接着層103aの厚さs1~s4に対して、s1>s2、かつ、s3<s4が成り立ち得る。つまり、第1接着層103aの厚さは、三つ以上の発光部71~74の配列方向の中央側において、両方の端部側より小さい。このため、本変形例に係る半導体発光装置2dにおいても、上記実施の形態に係る半導体発光装置2と同様の効果を得られる。 Further, as in the semiconductor light emitting device 2d according to the modified example 4 shown in FIG. 5D, the number of waveguide portions and light emitting portions may be an even number. Even with such a configuration, s1> s2 and s3 <s4 can be satisfied with respect to the thicknesses s1 to s4 of the first adhesive layer 103a immediately below the waveguide portions 40a1 to 40a4. That is, the thickness of the first adhesive layer 103a is smaller than both end portions on the center side in the arrangement direction of the three or more light emitting portions 71 to 74. For this reason, also in the semiconductor light-emitting device 2d which concerns on this modification, the effect similar to the semiconductor light-emitting device 2 which concerns on the said embodiment is acquired.
 また、図6に示す変形例5に係る半導体発光装置402のように、厚さの一様な基板410を有する半導体発光素子401と、サブマウント500と、を備えてもよい。サブマウント500は、第1基台501と、第1電極502aと、第1接着層503aと、第3電極502bと、第3接着層503bと、を有する。本変形例に係る導波路部40a1~40a5のそれぞれ直下における第1基台501の厚さt1~t5は、半導体発光素子401の発光部71~75の配列方向の中央側において大きく、端部側において小さい。これに伴い、第1基台501の半導体発光素子401側の面における配列方向の中央部が突出する。より詳しくは、第1基台501の半導体発光素子401側の面は、配列方向の中央側が凸状になるよう傾斜している。このため、第1接着層503aの厚さは、発光部71~75の配列方向の中央側において、両方の端部側より小さい。また、本変形例においても、上記実施の形態と同様に、第1基台501は、第1接着層503aより熱伝導率が高い。このように、本変形例に係る半導体発光装置402においては、第1基台501より熱伝導率が低い第1接着層503aの配列方向の中央側における厚さを小さくすることで、第1接着層503aの中央側での放熱性を両方の端部側より高めることができる。これにより、三つ以上の発光部71~75のうち配列方向の中央側の発光部が、隣接する発光部との熱干渉に起因して、両方の端部側の発光部より高温となることを抑制できる。 Further, as in the semiconductor light emitting device 402 according to the modified example 5 shown in FIG. 6, the semiconductor light emitting element 401 having the substrate 410 with a uniform thickness and the submount 500 may be provided. The submount 500 includes a first base 501, a first electrode 502a, a first adhesive layer 503a, a third electrode 502b, and a third adhesive layer 503b. The thicknesses t1 to t5 of the first base 501 directly below the waveguide portions 40a1 to 40a5 according to this modification are large on the center side in the arrangement direction of the light emitting portions 71 to 75 of the semiconductor light emitting element 401, and are on the end side Is small. Accordingly, the central portion in the arrangement direction of the surface of the first base 501 on the semiconductor light emitting element 401 side protrudes. More specifically, the surface of the first base 501 on the semiconductor light emitting element 401 side is inclined so that the center side in the arrangement direction is convex. For this reason, the thickness of the first adhesive layer 503a is smaller than both end portions on the center side in the arrangement direction of the light emitting portions 71 to 75. Also in this modification, the first base 501 has higher thermal conductivity than the first adhesive layer 503a, as in the above embodiment. As described above, in the semiconductor light emitting device 402 according to this modification, the first adhesive layer 503a having a lower thermal conductivity than the first base 501 is reduced in thickness on the center side in the arrangement direction, thereby reducing the first adhesion. The heat dissipation at the center side of the layer 503a can be enhanced from both end sides. As a result, among the three or more light emitting portions 71 to 75, the light emitting portion on the center side in the arrangement direction becomes higher in temperature than the light emitting portions on both end sides due to thermal interference with the adjacent light emitting portions. Can be suppressed.
 また、上記実施の形態及び各変形例では、三つ以上の発光部の配列方向の中央部において基板及び第1基台の一方だけが凸状に突出する構成を有したが、基板及び第1基台の両方が凸状に突出してもよい。また、三つ以上の発光部の配列方向の中央部において、第2基台が半導体発光素子に向かって凸状に突出してもよい。これにより、第2接着層の厚さを、三つ以上の発光部の配列方向の中央側において、両方の端部側より小さくすることができる。これにより、第2基台側においても、第1基台側と同様に、配列方向の中央側での放熱性を両方の端部側より高めることができる。 Moreover, in the said embodiment and each modification, it had the structure in which only one of a board | substrate and a 1st base protruded in the center part of the sequence direction of three or more light emission parts, but a board | substrate and 1st Both bases may protrude in a convex shape. In addition, the second base may protrude in a convex shape toward the semiconductor light emitting element at the center in the arrangement direction of the three or more light emitting units. Thereby, the thickness of a 2nd contact bonding layer can be made smaller than the both edge part side in the center side of the sequence direction of three or more light emission parts. Thereby, also on the 2nd base side, like the 1st base side, the heat dissipation in the center side of an arrangement direction can be improved from both end side.
 また、上記実施の形態及び各変形例に係る各半導体発光素子においては、窒化物半導体が用いられたが、半導体発光素子において用いられる半導体材料は、これに限定されない。例えば、半導体発光素子は、活性層がGaAs及びAlGaAsからなる量子井戸構造を有し、赤色レーザ光を出射してもよいし、活性層がInP及びInGaAsPからなる量子井戸構造を有し、赤外レーザ光を出射してもよい。 In each of the semiconductor light emitting devices according to the above-described embodiments and modifications, a nitride semiconductor is used. However, the semiconductor material used in the semiconductor light emitting device is not limited to this. For example, the semiconductor light emitting device has a quantum well structure in which an active layer is made of GaAs and AlGaAs, and may emit red laser light, or has a quantum well structure in which an active layer is made of InP and InGaAsP, Laser light may be emitted.
 また、上記実施の形態及び各変形例では、第1接着層及び第2接着層は、ゼロより大きい厚さを有したが、厚さがゼロの領域を有してもよい。例えば、三つ以上の発光部の配列方向の中央部において第1接着層及び第2接着層の厚さはゼロであってもよい。この場合、半導体発光素子の基板と第1基台及び第2基台とが接してもよい。 In the embodiment and each modification described above, the first adhesive layer and the second adhesive layer have a thickness larger than zero, but may have a region where the thickness is zero. For example, the thickness of the first adhesive layer and the second adhesive layer may be zero at the center in the arrangement direction of three or more light emitting parts. In this case, the substrate of the semiconductor light emitting element may be in contact with the first base and the second base.
 また、上記実施の形態及び各変形例では、半導体発光素子の基板として半導体基板を用いたが、半導体発光素子の基板は、半導体でなくてもよい。例えば、基板は、サファイアなどで形成されてもよい。この場合、第1導電側の電極は、基板の上面側に配置されてもよい。 Further, in the above-described embodiment and each modification, the semiconductor substrate is used as the substrate of the semiconductor light emitting element, but the substrate of the semiconductor light emitting element may not be a semiconductor. For example, the substrate may be formed of sapphire or the like. In this case, the electrode on the first conductive side may be disposed on the upper surface side of the substrate.
 また、上記実施の形態及び各変形例に係る半導体発光素子においては、第2半導体層に形成されたストライプ構造を用いて電流狭窄を実現したが、電流狭窄を実現するための手段は、これに限定されず、電極ストライプ構造、埋め込み型構造などを使用してもよい。 In addition, in the semiconductor light emitting device according to the above-described embodiment and each modification, current confinement is realized using a stripe structure formed in the second semiconductor layer, but means for realizing current confinement is not limited to this. Without limitation, an electrode stripe structure, a buried structure, or the like may be used.
 本開示に係る半導体発光装置は、画像表示装置、照明又は産業機器などの光源として利用することができ、特に、比較的に高い光出力を必要とする機器の光源として有用である。 The semiconductor light emitting device according to the present disclosure can be used as a light source for an image display device, illumination, or industrial equipment, and is particularly useful as a light source for equipment that requires a relatively high light output.
 1、1a、1b、1c、1d、401 半導体発光素子
 2、2a、2b、2c、2d、3、402 半導体発光装置
 10、10a、10b、10c、410 基板
 20 第1半導体層
 30 発光層
 31 n側光ガイド層
 32 活性層
 33 p側光ガイド層
 40 第2半導体層
 40a1、40a2、40a3、40a4、40a5 導波路部
 40b 平坦部
 41 電子障壁層
 42 p側クラッド層
 43 p側コンタクト層
 50 電極部材
 51 p側電極
 52 パッド電極
 60 誘電体層
 71、72、73、74、75 発光部
 80 n側電極
 91 第1保護膜
 100、300、500 サブマウント
 101、201、501 第1基台
 102a、502a 第1電極
 102b、502b 第3電極
 103a、203、503a 第1接着層
 103b、503b 第3接着層
 200 放熱部
 301 第2基台
 302a 第2電極
 302b 第4電極
 303a 第2接着層
 303b 第4接着層
 1003 支持体
 1006 導電性接着材
 1007 金属配線体
 1008 レーザ電極
 1009 樹脂
 1010 アレイ型半導体レーザ素子
 1011、1012、1013、1014 ストライプ
1, 1a, 1b, 1c, 1d, 401 Semiconductor light emitting element 2, 2a, 2b, 2c, 2d, 3, 402 Semiconductor light emitting device 10, 10a, 10b, 10c, 410 Substrate 20 First semiconductor layer 30 Light emitting layer 31 n Side light guide layer 32 Active layer 33 P side light guide layer 40 Second semiconductor layer 40a1, 40a2, 40a3, 40a4, 40a5 Waveguide portion 40b Flat portion 41 Electron barrier layer 42 p side cladding layer 43 p side contact layer 50 Electrode member 51 p-side electrode 52 pad electrode 60 dielectric layer 71, 72, 73, 74, 75 light emitting part 80 n-side electrode 91 first protective film 100, 300, 500 submount 101, 201, 501 first base 102a, 502a First electrode 102b, 502b Third electrode 103a, 203, 503a First adhesive layer 103b, 503b First Adhesive layer 200 Radiation part 301 Second base 302a Second electrode 302b Fourth electrode 303a Second adhesive layer 303b Fourth adhesive layer 1003 Support body 1006 Conductive adhesive material 1007 Metal wiring body 1008 Laser electrode 1009 Resin 1010 Array type semiconductor laser Element 1011, 1012, 1013, 1014 stripe

Claims (8)

  1.  基板と、前記基板の上面に沿って配列された三つ以上の発光部と、を有する半導体発光素子と、
     前記基板の下面の下方に配置された第1基台と、
     前記半導体発光素子を前記第1基台に接着する第1接着層と、を備え、
     前記基板は、前記第1接着層より熱伝導率が高く、
     前記第1接着層の厚さは、前記三つ以上の発光部の配列方向の中央側において、両方の端部側より小さい
     半導体発光装置。
    A semiconductor light emitting device having a substrate and three or more light emitting portions arranged along the upper surface of the substrate;
    A first base disposed below the lower surface of the substrate;
    A first adhesive layer for adhering the semiconductor light emitting element to the first base,
    The substrate has a higher thermal conductivity than the first adhesive layer,
    The thickness of the said 1st contact bonding layer is a semiconductor light-emitting device smaller than both the edge part sides in the center side of the sequence direction of the said three or more light-emitting parts.
  2.  前記基板の厚さは、前記配列方向の中央側において両方の端部側より大きい
     請求項1記載の半導体発光装置。
    The semiconductor light emitting device according to claim 1, wherein a thickness of the substrate is larger than both end portions on a central side in the arrangement direction.
  3.  前記基板の前記下面は、前記配列方向の中央側が凸状になるよう傾斜している
     請求項2記載の半導体発光装置。
    The semiconductor light emitting device according to claim 2, wherein the lower surface of the substrate is inclined so that a central side in the arrangement direction is convex.
  4.  前記基板の前記上面は、前記配列方向において、前記第1基台の前記第1接着層との接合面と平行である
     請求項2又は3記載の半導体発光装置。
    The semiconductor light emitting device according to claim 2, wherein the upper surface of the substrate is parallel to a bonding surface of the first base with the first adhesive layer in the arrangement direction.
  5.  さらに、前記半導体発光素子を挟んで前記第1基台とは反対側に配置された第2基台と、
     前記半導体発光素子を前記第2基台に接着する第2接着層と、を備える
     請求項1~4の何れか1項に記載の半導体発光装置。
    Furthermore, a second base disposed on the opposite side of the first base across the semiconductor light emitting element,
    The semiconductor light-emitting device according to any one of claims 1 to 4, further comprising: a second adhesive layer that adheres the semiconductor light-emitting element to the second base.
  6.  前記第1基台は、前記第1接着層より熱伝導率が高い
     請求項1~5の何れか1項に記載の半導体発光装置。
    6. The semiconductor light emitting device according to claim 1, wherein the first base has a higher thermal conductivity than the first adhesive layer.
  7.  基板と、前記基板の上面に沿って配列された三つ以上の発光部と、を有する半導体発光素子と、
     前記基板の下面の下方に配置された第1基台と、
     前記半導体発光素子を前記第1基台に接着する第1接着層と、を備え、
     前記第1基台は、前記第1接着層より熱伝導率が高く、
     前記第1接着層の厚さは、前記三つ以上の発光部の配列方向の中央側において、両方の端部側より小さい
     半導体発光装置。
    A semiconductor light emitting device having a substrate and three or more light emitting portions arranged along the upper surface of the substrate;
    A first base disposed below the lower surface of the substrate;
    A first adhesive layer for adhering the semiconductor light emitting element to the first base,
    The first base has a higher thermal conductivity than the first adhesive layer,
    The thickness of the said 1st contact bonding layer is a semiconductor light-emitting device smaller than both the edge part sides in the center side of the sequence direction of the said three or more light-emitting parts.
  8.  前記第1基台の厚さは、前記配列方向の中央側において両方の端部側より大きい
     請求項7記載の半導体発光装置。
    The semiconductor light emitting device according to claim 7, wherein a thickness of the first base is larger than both end portions on a central side in the arrangement direction.
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