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WO2019037782A1 - 极化码的译码方法和译码器 - Google Patents

极化码的译码方法和译码器 Download PDF

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Publication number
WO2019037782A1
WO2019037782A1 PCT/CN2018/102297 CN2018102297W WO2019037782A1 WO 2019037782 A1 WO2019037782 A1 WO 2019037782A1 CN 2018102297 W CN2018102297 W CN 2018102297W WO 2019037782 A1 WO2019037782 A1 WO 2019037782A1
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Prior art keywords
decoding
scl
result
data
circuit
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PCT/CN2018/102297
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English (en)
French (fr)
Inventor
郭晗
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华为技术有限公司
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Publication of WO2019037782A1 publication Critical patent/WO2019037782A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • the present application relates to the field of communications and, more particularly, to a decoding method and decoder for a polarization code in the field of communications.
  • the Polar code is the first code that theoretically proves that Shannon capacity can be obtained and has low decoding complexity.
  • the Polar code is a linear block code, and its decoding can be serially cancelled (SC).
  • SC serially cancelled
  • a decoding method or a serial cancellation list (SCL) decoding method performs decoding.
  • SC decoding and SCL decoding each have their own strengths. From the perspective of decoding performance, SC decoding can achieve good performance when the code length is long, but when the code length is short or medium length, the SC decoding performance of the Polar code is poor. For SCL decoding, the performance of SCL decoding is improved relative to the performance of SC decoding. However, from the processing delay of decoding, the complexity of SCL decoding is higher than that of SC decoding. The time is large, and the SC decoding complexity is low, the decoding accuracy is low, but the decoding delay is small.
  • the present application provides a decoding method and decoder for a polarization code.
  • the data to be decoded is subjected to SCL decoding and SC decoding, respectively.
  • the SC decoding result is output as the final decoding result of the data, and stops.
  • SCL decoding of the data is performed.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • a method for decoding a polarization code comprising: acquiring data to be decoded; respectively starting a serial cancellation list SCL decoding and serial cancellation SC decoding on the data; The decoding result of the SC decoding; if it is determined that the decoding result of the SC decoding is correct, the SCL decoding is stopped; and the decoding result of the SC decoding is output.
  • the method for decoding a polarization code performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the method further includes: performing the SCL decoding; and outputting the decoding result of the SCL decoding. .
  • the separately performing serial cancellation list SCL decoding and serial cancellation SC decoding on the data includes: performing the SCL decoding on the data in parallel and the SC Decoding.
  • the method further includes: performing a cyclic redundancy CRC check on the decoding result of the SC decoding; and determining, in the case that the CRC check passes, determining the SC decoding The decoding result is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • the search width of the SCL decoding is 8 decoding paths.
  • the decoding delay is lower and the decoding accuracy is relatively better.
  • a decoder for performing the decoding method of the polarization code in the first aspect and various implementations described above.
  • the decoder includes an acquisition circuit, an SCL decoding circuit, an SC decoding circuit, and an output circuit.
  • the acquisition circuit is configured to acquire data to be decoded;
  • the SCL decoding circuit is configured to perform serial cancellation list SCL decoding on the data;
  • the SC decoding circuit is configured to perform serial cancellation SC translation on the data.
  • the SC decoding circuit is further configured to obtain a decoding result of the SC decoding; and when determining that the decoding result of the SC decoding is correct, the SCL decoding circuit is further configured to stop the SCL decoding;
  • an output circuit configured to output a decoding result of the SC decoding.
  • a decoder comprising a processor, a transceiver and a memory for supporting the decoder to perform a corresponding function in the above decoding method.
  • the memory stores instructions for performing specific signal transceiving under the driving of a processor for invoking the instruction to implement the decoding method of the polarization code in the first aspect and various implementations thereof.
  • a fourth aspect provides a decoder, including a processing module, a storage module, and a transceiver module, for supporting the decoder to perform the functions in the foregoing first aspect or any possible implementation manner of the first aspect, the function may be
  • the hardware implementation may also be implemented by hardware, and the hardware or software includes one or more modules corresponding to the above functions.
  • a readable medium for storing instructions comprising instructions for performing the decoding method of the first aspect or any of the possible implementations of the first aspect.
  • 1 is a schematic diagram of an SC decoding path.
  • FIG. 2 is a schematic diagram of an SCL decoding path.
  • FIG. 3 is a schematic flow chart of a typical SCL decoding processing manner.
  • FIG. 4 is a schematic diagram of a communication system of a decoding method and a decoder applicable to the polarization code of the present application.
  • FIG. 5 is a schematic flowchart of a method for decoding a polarization code according to an embodiment of the present invention.
  • FIG. 6 is a schematic flow chart of a method for decoding a polarization code according to another embodiment of the present invention.
  • Figure 7 is a schematic block diagram of a decoder in accordance with one embodiment of the present invention.
  • Figure 8 is a schematic block diagram of a decoder in accordance with another embodiment of the present invention.
  • Figure 9 is a schematic block diagram of a decoder in accordance with another embodiment of the present invention.
  • a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer.
  • an application running on a computing device and a computing device can be a component.
  • One or more components can reside within a process and/or execution thread, and the components can be located on one computer and/or distributed between two or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • a component may, for example, be based on signals having one or more data packets (eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems) Communicate through local and/or remote processes.
  • data packets eg, data from two components interacting with another component between the local system, the distributed system, and/or the network, such as the Internet interacting with other systems
  • LTE long term evolution
  • FDD frequency division duplex
  • LTE/LTE LTE/LTE.
  • -A time division duplex (TDD) system LTE/LTE-A frequency division duplex (FDD) system
  • UMTS universal mobile telecommunication system
  • WiMAX worldwide interoperability for microwave access
  • PLMN public land mobile network
  • D2D device to device
  • M2M machine to machine
  • Wi-Fi wireless local area network
  • WLAN Wireless local area networks
  • the terminal device may also be referred to as a user equipment (UE), a mobile station (MS), a mobile terminal, etc., and the terminal device may be connected by using a wireless device.
  • a radio access network (RAN) communicates with one or more core network devices, for example, the terminal device may include various handheld devices with wireless communication capabilities, in-vehicle devices, wearable devices, computing devices, or connected to a wireless modem. Other processing equipment. It may also include a subscriber unit, a cellular phone, a smart phone, a wireless data card, a personal digital assistant (PDA) computer, a tablet computer, a wireless modem, and a handheld device.
  • PDA personal digital assistant
  • MTC machine type communication
  • STA station in wireless local area networks
  • WLAN wireless local area networks
  • It can be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (WLL) station, and a next-generation communication system, for example, a terminal device in a 5G network or a future evolution.
  • SIP Session Initiation Protocol
  • WLL wireless local loop
  • next-generation communication system for example, a terminal device in a 5G network or a future evolution.
  • PLMN public land mobile network
  • the base station may also be referred to as a network side device or an access network device
  • the network side device may be a device for communicating with the terminal device
  • the network device may be an evolved base station (evolutional Node B, eNB) in the LTE system.
  • eNodeB evolved base station
  • gNB evolved base station
  • gNB access point in NR
  • base transceiver station transceiver node
  • in-vehicle device wearable device
  • network device in future 5G network or network side device in future evolved PLMN system
  • the network side device may be an access point (AP) in the WLAN, or may be a global system for mobile communication (GSM) or code dvision multiple access (CDMA).
  • GSM global system for mobile communication
  • CDMA code dvision multiple access
  • BTS Base Transceiver Station
  • eNB evolved NodeB
  • eNodeB evolved NodeB
  • LTE Long Term Evolution
  • the network device may also be a Node B of a 3rd Generation (3G) system.
  • the network device may also be a relay station or an access point, or an in-vehicle device, a wearable device, and a future 5G network.
  • the embodiments of the present invention are not limited herein. For convenience of description, in all embodiments of the present invention, the above devices for providing wireless communication functions to the MS are collectively referred to as network devices.
  • Polar code is a high-performance channel coding scheme proposed in recent years. It has the characteristics of high performance, low complexity and flexible rate matching. It has become the coding method of control information in 5G systems.
  • the decoding method of the Polar code is SCL decoding and SC decoding.
  • a Polar code having a code length of N may correspond to a binary decoding code tree composed of N layer edges. SC coding can be described as a decoding path search process on the code tree.
  • FIG. 1 is a schematic diagram of an SC decoding path.
  • SC decoding starts from the root node of the code tree and gradually expands on the decoding code tree, and each layer selects a relative probability from two candidate paths. The one with a large value, that is, the search width is 1. And the path expansion of the next layer is performed on the basis of the selected decoding path.
  • a decoding result is finally obtained through the decoding path, and the decoding result is verified to determine whether the decoding result is correct.
  • FIG. 2 is a schematic diagram of an SCL decoding path.
  • SCL decoding allows multiple candidate decoding paths to be reserved.
  • the SCL decoding starts from the root node of the code tree and is gradually expanded on the code tree.
  • Each layer selects L strips from 2L candidate decoding paths, that is, the search width is L.
  • the path expansion of the next layer is performed on the basis of the selected L decoding paths.
  • the four black solid lines in Figure 2 indicate the selected four SCL decoding paths.
  • one path with the largest reliability metric is selected from the four SCL decoding paths, and the corresponding bit estimation sequence is the decoding result.
  • FIG. 3 is a schematic flow chart of a typical SCL decoding processing manner, and FIG. 3 shows the whole process of processing a hard bit. All hard bit processing starts from the first stage to the last stage. End the loop process until all hard bit processing is complete. The stage is equivalent to the layer of the decoding code tree in FIG. 1 or FIG. 2.
  • L ie, the search width is L
  • the maximum log likelihood ratio (LLR) of the decoding path is obtained as a branch metric and a path metric for each decoding path, wherein the branch metric is used to calculate the cumulative metric.
  • the decoding result of the most accurate decoding path is selected by the hard bit stream check routing of the L decoding paths, as the final Output the result.
  • the flow of a typical SCL decoding processing method mainly includes the following steps:
  • m is a positive integer greater than 1, and select the LLR and the metric cumulative value of each stage cache of stage(1) to stage(m).
  • Each decoding path is synchronized from stage(1) to stage(m) to obtain LLR by stage.
  • the path formed from the root node of the code tree to any node in the decoding process corresponds to a path metric.
  • the information bit (bit) is extended to the path.
  • each layer selects L strips with larger path metric values in the current layer.
  • the path with the smallest absolute value of the metric in the path through the cyclic redundancy check is selected as the decoding result.
  • the present application provides a method for decoding a polarization code, so that the polarization code is decoded.
  • the decoding delay is reduced while maintaining good decoding performance. Considering the accuracy of the decoding result, the delay in the decoding process is considered, and the effect of reducing the decoding delay and ensuring the accuracy of the decoding result is achieved.
  • the communication system 100 includes a network device 102 that can include multiple antennas, such as antennas 104, 106, 108, 110, 112, and 114. Additionally, network device 102 may additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which may include multiple components related to signal transmission and reception (eg, processor, modulator, multiplexer) , encoder, demultiplexer or antenna, etc.).
  • a network device 102 can include multiple antennas, such as antennas 104, 106, 108, 110, 112, and 114.
  • network device 102 may additionally include a transmitter chain and a receiver chain, as will be understood by those of ordinary skill in the art, which may include multiple components related to signal transmission and reception (eg, processor, modulator, multiplexer) , encoder, demultiplexer or antenna, etc.).
  • Network device 102 can communicate with a plurality of terminal devices, such as terminal device 116 and terminal device 122. However, it will be appreciated that network device 102 can communicate with any number of terminal devices similar to terminal device 116 or 122.
  • Terminal devices 116 and 122 can be, for example, cellular telephones, smart phones, portable computers, handheld communication devices, handheld computing devices, satellite radios, global positioning systems, PDAs, and/or any other for communicating over wireless communication system 100. Suitable for equipment.
  • terminal device 116 is in communication with antennas 112 and 114, wherein antennas 112 and 114 transmit information to terminal device 116 over forward link 118 and receive information from terminal device 116 over reverse link 120.
  • terminal device 122 is in communication with antennas 104 and 106, wherein antennas 104 and 106 transmit information to terminal device 122 over forward link 124 and receive information from terminal device 122 over reverse link 126.
  • the forward link 118 can utilize a different frequency band than that used by the reverse link 120, and the forward link 124 can utilize a different frequency band than that used by the reverse link 126.
  • the forward link 118 and the reverse link 120 can use a common frequency band
  • the forward link 124 and the reverse link 126 can use a common frequency band
  • Each antenna (or set of antennas consisting of multiple antennas) and/or regions designed for communication is referred to as a sector of network device 102.
  • the antenna group can be designed to communicate with terminal devices in sectors of the network device 102 coverage area.
  • the transmit antenna of network device 102 may utilize beamforming to improve the signal to noise ratio of forward links 118 and 124.
  • the network device 102 uses beamforming to transmit signals to the randomly dispersed terminal devices 116 and 122 in the relevant coverage area, the network device 102 uses a single antenna to transmit signals to all of its terminal devices. Mobile devices are subject to less interference.
  • network device 102, terminal device 116, or terminal device 122 may be a wireless communication transmitting device and/or a wireless communication receiving device.
  • the wireless communication transmitting device can encode the data for transmission.
  • the wireless communication transmitting device may acquire (eg, generate, receive from other communication devices, or store in memory, etc.) a certain number of data bits to be transmitted over the channel to the wireless communication receiving device.
  • Such data bits may be included in a transport block (or multiple transport blocks) of data that may be segmented to produce multiple code blocks.
  • the communication system 100 can be a PLMN network or a D2D network or an M2M network or other network.
  • FIG. 4 is only a simplified schematic diagram of an example, and the network may also include other network devices, which are not drawn in FIG. 4 .
  • FIG. 5 is a schematic flowchart of a method for decoding a polarization code 200 according to an embodiment of the present invention.
  • the method 200 can be applied to FIG.
  • the embodiment of the present invention is not limited thereto.
  • the decoding method 200 includes:
  • the data to be decoded when decoding the data to be decoded, the data to be decoded is first acquired, and then the data to be decoded is respectively subjected to serial offset list SCL decoding and serial offset SC translation.
  • the code that is, the data to be decoded is decoded in parallel by using two decoding methods. Due to the low complexity of the SC decoding process, there is only one candidate decoding path in the decoding process, which is relatively short in time. Therefore, the decoding result of the SC decoding (SC decoding result) is first obtained. When the SC decoding result is obtained, the SCL decoding of the data is in progress, that is, the SCL decoding has not ended yet, and the SCL decoding result has not been obtained yet.
  • the SC decoding result is not necessarily accurate, and it is necessary to determine whether to stop the SCL decoding of the data according to the SC decoding result. That is, in the case that it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and the decoding result of the SC decoding is output, that is, the decoding result of the SC decoding is used as the final decoding. result.
  • the method for decoding a polarization code performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the method 200 further includes:
  • the decoding result is assumed SC obtained at time T 1, at this time, the decoded data SCL ongoing process, i.e., SCL translation The code has not finished yet, and the SCL decoding result has not been obtained yet. Therefore, in the case that it is determined that the decoding result of the SC decoding is incorrect, it is necessary to continue SCL decoding the data, and it is assumed that the SCL decoding result of the data is obtained at time T 2 , wherein the T 2 time is later than T At 1 o'clock, the decoding result of the SCL decoding is output, that is, the SCL decoding result is output as the final decoding result of the data.
  • the data start serial cancellation list SCL decoding and serial cancellation SC decoding respectively are performed, including:
  • serial offset list SCL decoding and the serial cancellation SC decoding are performed in parallel on the data.
  • SCL decoding and SC decoding may be performed on the data in parallel, that is, the time for performing SCL decoding and SC decoding on the data at least partially overlaps. Since the time taken for SC decoding is short, when the time for performing SCL decoding and SC decoding on the data at least partially overlaps, the length of time for obtaining the decoding result can be further shortened as a whole.
  • SCL decoding and SC decoding may be started on the data at the same time, so that the decoding delay may be further reduced.
  • the SC decoding result when performing SCL decoding and SC decoding on the data in parallel, the SC decoding result may be obtained earlier than the SCL decoding result.
  • the embodiments of the present invention are not limited herein.
  • the method for decoding a polarization code provided by the present application performs SCL decoding and SC decoding in parallel on the data to be decoded, and performs verification on the decoding result of the SC decoding first, and determines that the SC decoding result is correct. At the time, the SC decoding result is output as the final result of the decoding.
  • the decoding delay can be further reduced to improve the decoding efficiency.
  • the decoding method 200 further includes:
  • the SC decoding result is subjected to CRC check. That is, the CRC auxiliary code is used as an inner code, and is input into the data information to perform polarization code encoding as a part of the information symbol.
  • the SC decoding algorithm first generates an alternative decoding codeword, that is, the decoding result of the SC decoding, and then performs CRC decoding on the decoding result of the SC decoding, and decodes the CRC. The result is compared with the actually received CRC auxiliary code. If the two are the same, that is, the CRC check passes, it is determined that the decoding result of the SC decoding is correct. If the two are not the same, that is, the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • the decoding result of the SC decoding may be verified by other methods, for example, by using parity check (parity check,
  • parity check The embodiment of the present invention is not limited herein.
  • the search width of the SCL decoding is 8 decoding paths.
  • the search width in the SCL decoding process is 8, that is, there are 8 decoding paths simultaneously. The code delay is low and the decoding accuracy is relatively good.
  • the value of the search width in the SCL decoding process may be other values, for example, 2, or 4, or 16, or the like.
  • the embodiment of the present invention is not limited herein as long as the positive integer of the value of the decoding width is 2.
  • FIG. 6 is a schematic flow chart of a method for decoding a polarization code according to an embodiment of the present invention.
  • the flow of the typical SCL decoding processing mode is shown, and the lower half of the dotted line frame is the flow of the typical SC decoding processing mode.
  • the essence of SC decoding is SCL decoding of a single decoding path, and the two parts are executed in parallel. Since the number of decoding paths (path) of SC decoding is small, only two-choice path selection is needed, so the calculation is simple. Compared with the SCL decoding processing delay, the SC decoding result will be obtained earlier.
  • the SCL decoding is terminated by the decoding end decision, and the output is the SC decoding result.
  • the SCL needs to be executed, and finally the result of the SCL decoding is output.
  • the SCL decoding process is similar to the steps described in FIG. 3, and is not described here for brevity.
  • m is a positive integer greater than 1, and select the LLR and the metric cumulative value of each stage cache of stage(1) to stage(m).
  • Each decoding path is synchronized from stage(1) to stage(m) to obtain LLR by stage.
  • the method for decoding a polarization code utilizes the features of simple SC decoding, small delay, and high accuracy of SCL decoding, and performs SC decoding and SCL decoding in parallel through data to be decoded.
  • the SC decoding result obtained first is correct
  • the SC decoding result is taken as the final decoding result.
  • the decoding speed is improved, the decoding delay is reduced, the accuracy of the decoding result is ensured, and the decoding efficiency is improved.
  • the decoding method of the polarization code provided by the embodiment of the present invention is described in detail above with reference to FIG. 1 to FIG. 6.
  • the decoder provided by the embodiment of the present invention will be described in detail below with reference to FIG. 7 to FIG.
  • FIG. 7 shows a schematic block diagram of a decoder 300 according to an embodiment of the present invention.
  • the decoder 300 includes an acquisition circuit 310, an SCL decoding circuit 320, an SC decoding circuit 330, and an output circuit. 340.
  • the obtaining circuit 310 is configured to acquire data to be decoded.
  • the SCL decoding circuit 320 is configured to perform serial cancellation list SCL decoding on the data.
  • the SC decoding circuit 330 is configured to perform serial cancellation SC decoding on the data.
  • the SC decoding circuit 330 is also used to obtain the SC decoding result.
  • the SCL decoding circuit 320 is further configured to stop the SCL decoding.
  • the output circuit 340 is configured to output the decoded result of the SC decoding.
  • the decoder provided by the present application performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded, respectively. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the SCL decoding circuit 320 is further configured to continue the SCL decoding.
  • the output circuit 340 is further configured to: output the decoded result of the SCL decoding.
  • the SCL decoding circuit 320 and the SC decoding circuit 330 decode the data in parallel.
  • the decoder 300 further includes a check circuit 350, configured to perform a cyclic redundancy CRC check on the decoded result of the SC decoding; In the case of passing, it is determined that the decoding result of the SC decoding is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • a check circuit 350 configured to perform a cyclic redundancy CRC check on the decoded result of the SC decoding; In the case of passing, it is determined that the decoding result of the SC decoding is correct, or if the CRC check fails, it is determined that the decoding result of the SC decoding is incorrect.
  • the SCL decoding circuit 320 has a search width of eight decoding paths.
  • each circuit included in the decoder 300 may be composed of logic devices for supporting each circuit to perform the above various functions.
  • FIG. 8 is a schematic block diagram of a decoder 400 in accordance with an embodiment of the present invention.
  • the decoder 400 includes a processor 410, a memory 420, and a transceiver 430.
  • the processor 410, the memory 420, and the transceiver 430 communicate with each other through an internal connection path to transfer control and/or data signals. .
  • This memory 410 is used to store program code.
  • the transceiver 430 is configured to perform specific signal transceiving under the driving of the processor 410 to implement the decoding method in the above embodiments.
  • the processor 420 is configured to invoke the program code to implement the decoding method in the above embodiments of the present invention.
  • the decoder provided by the present application performs serial cancellation list SCL decoding and serial cancellation SC decoding in parallel by data to be decoded, respectively. Since the SC decoding delay is small, the decoding accuracy is low and the bit error rate is high. The delay of SCL decoding is larger, but the decoding accuracy is higher and the bit error rate is lower. Therefore, the data to be decoded is subjected to SC decoding and SCL decoding, respectively, and the SC decoding result is obtained first. When it is determined that the decoding result of the SC decoding is correct, the SCL decoding of the data is stopped, and The decoding result of the SC decoding is used as the final decoding result.
  • the polar code decoding reduces the decoding delay and improves the decoding efficiency under the premise of ensuring accurate decoding performance.
  • the various components in decoder 400 communicate with one another via a communication connection, i.e., processor 410, memory 420, and transceiver 430, through internal connection paths, to communicate control and/or data signals.
  • a communication connection i.e., processor 410, memory 420, and transceiver 430
  • the foregoing method embodiments of the present application may be applied to a processor, or the processor may implement the steps of the foregoing method embodiments.
  • the processor may be an integrated circuit chip with signal processing capabilities.
  • each step of the foregoing method embodiments may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software. To avoid repetition, it will not be described in detail here.
  • the above processor may be a central processing unit (CPU), a network processor (NP) or a combination of a CPU and an NP, a digital signal processor (DSP), an application specific integrated circuit (application). Specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component.
  • CPU central processing unit
  • NP network processor
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in connection with the present application may be directly embodied by the execution of the hardware decoding processor or by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.
  • the memory 420 can include read only memory and random access memory and provides instructions and data to the processor 410. A portion of the memory 420 may also include a non-volatile random access memory. For example, the memory 420 can also store information of the device type.
  • a person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.
  • the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (ROMM), an erasable programmable read only memory (erasable PROM, EPROM), or an electrical Erase programmable EPROM (EEPROM) or flash memory.
  • ROM read-only memory
  • PROM programmable read only memory
  • EEPROM electrical Erase programmable EPROM
  • the processor 410 may be implemented by a processing module
  • the memory 420 may be implemented by a storage module
  • the transceiver 430 may be implemented by a transceiver module.
  • the decoder 500 may include a processing module 510.
  • the decoder 400 shown in FIG. 8 or the decoder 500 shown in FIG. 9 can implement the steps shown in FIG. 5 and FIG. 6 described above. To avoid repetition, details are not described herein again.
  • the embodiment of the present invention further provides a readable medium for storing program code, the program code comprising instructions for executing the decoding method of the polarization code of the embodiment of the present invention in FIG. 5 and FIG.
  • the readable medium may be a ROM or a RAM, which is not limited in the embodiment of the present invention.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种极化码的译码方法和译码器。该译码方法包括：获取待译码的数据；分别开始对该数据进行串行抵消列表SCL译码和串行抵消SC译码；得到该SC译码的译码结果；在确定该SC译码的译码结果正确的情况下，停止该SCL译码；输出该SC译码的译码结果。提供的极化码的译码方法，能够对待译码的数据分别进行SCL译码和SC译码，在确定该SC译码的译码结果正确的情况下，输出该SC译码结果，作为该数据最终的译码结果，并停止进行该数据的SCL译码。使得polar码译码在保证译码准确性能的前提下，减少了译码时延，提高了译码的效率。

Description

极化码的译码方法和译码器
本申请要求于2017年8月25日提交中国专利局、申请号为201710738822.3、申请名称为“极化码的译码方法和译码器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，并且更具体地，涉及通信领域中极化码的译码方法和译码器。
背景技术
通信系统通常采用信道编码来提高数据传输的可靠性，以保证通信的质量。极化码(Polar code)是第一个理论上证明可以取得香农容量并且具有低译码复杂度的码，Polar码为一种线性块码，其译码可以用串行抵消(successive cancellation，SC)译码方法或者串行抵消列表(successive cancellation list，SCL)译码方法进行译码。
SC译码和SCL译码各有所长。从译码性能看，SC译码在码长很长的情况下能够取得好的性能，但是当码长较短或者为中等长度时，Polar码的SC译码的性能较差。对于SCL译码来说，SCL译码相对于SC译码的性能有一定提高，但是从译码的处理延时看，由于SCL译码的复杂度要比SC译码复杂度高，译码延时较大，而SC译码复杂度较低，译码准确度较低，但是译码延时较小。
发明内容
本申请提供一种极化码的译码方法和译码器。能够对待译码的数据分别进行SCL译码和SC译码，在确定先得到SC译码的译码结果正确的情况下，输出该SC译码结果，作为该数据最终的译码结果，并停止进行该数据的SCL译码。使得polar码译码在保证译码准确性能的前提下，减少了译码时延，提高了译码的效率。
第一方面，提供了一种极化码的译码方法，该方法包括：获取待译码的数据；分别开始对该数据进行串行抵消列表SCL译码和串行抵消SC译码；得到该SC译码的译码结果；在确定该SC译码的译码结果正确的情况下，停止该SCL译码；输出该SC译码的译码结果。
第一方面提供的极化码的译码方法，通过对待译码的数据分别并行进行串行抵消列表SCL译码和串行抵消SC译码。由于SC译码延时较小，但是译码的准确度低，误码率较高。SCL译码的延时较大，但是译码的准确度较高，误码率较低。因此，对待译码的数据分别进行SC译码和SCL译码，先得到SC译码结果，在确定该SC译码的译码结果正确的情况下，停止对该数据进行SCL译码，并将该SC译码的译码结果作为最终的译码结果。使得polar码译码在保证译码准确性能的前提下，减少了译码时延，提高了译码的效率。
在第一方面的一种可能的实现方式中，在确定该SC译码的译码结果不正确的情况下， 该方法还包括：继续进行该SCL译码；输出该SCL译码的译码结果。
在第一方面的一种可能的实现方式中，该分别开始对该数据进行串行抵消列表SCL译码和串行抵消SC译码，包括：对该数据并行的进行该SCL译码和该SC译码。
在第一方面的一种可能的实现方式中，该方法还包括：对该SC译码的译码结果进行循环冗余CRC校验；在该CRC校验通过的情况下，确定该SC译码的译码结果正确，或在该CRC校验不通过的情况下，确定该SC译码的译码结果不正确。
在第一方面的一种可能的实现方式中，该SCL译码的搜索宽度为8条译码路径。在该实现方式中，译码的延时较低，译码准确性也相对较好。
第二方面，提供了一种译码器，用于执行上述第一方面及各种实现方式中的极化码的译码方法。该译码器包括获取电路、SCL译码电路、SC译码电路和输出电路。该获取电路，用于获取待译码的数据；该SCL译码电路，用于对该数据进行串行抵消列表SCL译码；该SC译码电路，用于对该数据进行串行抵消SC译码；该SC译码电路还用于得到该SC译码的译码结果；在确定该SC译码的译码结果正确的情况下，该SCL译码电路还用于停止该SCL译码；该输出电路，用于输出该SC译码的译码结果。
第三方面，提供了一种译码器，包括处理器、收发器和存储器，用于支持该译码器执行上述译码方法中相应的功能。该存储器存储指令，该收发器用于在处理器的驱动下执行具体的信号收发，该处理器用于调用该指令实现上述第一方面及其各种实现方式中的极化码的译码方法。
第四方面，提供了一种译码器，包括处理模块、存储模块和收发模块，用于支持该译码器执行上述第一方面或第一方面的任意可能的实现方式中的功能，功能可以通过硬件实现，也可以通过硬件执行相应的软件实现，硬件或软件包括一个或者多个与上述功能相对应的模块。
第五方面，提供了一种可读介质，用于存储指令，该指令包括用于执行上述第一方面或第一方面的任一种可能的实现方式中的译码方法的指令。
附图说明
图1是SC译码路径的示意图。
图2是SCL译码路径的示意图。
图3是典型的SCL译码处理方式的示意性流程图。
图4是适用于本申请的极化码的译码方法和译码器的通信系统的示意图。
图5是本发明一个实施例的极化码的译码方法的示意性流程图。
图6是本发明另一个实施例的极化码的译码方法示意性流程图。
图7是本发明一个实施例的译码器的示意性框图。
图8是本发明另一个实施例的译码器的示意性框图。
图9是本发明另一个实施例的译码器的示意性框图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
在本说明书中使用的术语“部件”、“模块”、“系统”等用于表示计算机相关的实体、硬 件、固件、硬件和软件的组合、软件、或执行中的软件。例如，部件可以是但不限于，在处理器上运行的进程、处理器、对象、可执行文件、执行线程、程序和/或计算机。通过图示，在计算设备上运行的应用和计算设备都可以是部件。一个或多个部件可驻留在进程和/或执行线程中，部件可位于一个计算机上和/或分布在2个或更多个计算机之间。此外，这些部件可从在上面存储有各种数据结构的各种计算机可读介质执行。部件可例如根据具有一个或多个数据分组(例如来自与本地系统、分布式系统和/或网络间的另一部件交互的二个部件的数据，例如通过信号与其它系统交互的互联网)的信号通过本地和/或远程进程来通信。
应理解，本申请的技术方案可以应用于各种通信系统，例如：长期演进(long term evolution，LTE)系统、LTE/LTE-A频分双工(frequency division duplex，FDD)系统、LTE/LTE-A时分双工(time division duplex，TDD)系统、通用移动通信系统(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信系统、公共陆地移动网络(public land mobile network，PLMN)系统、设备对设备(device to device，D2D)网络系统或者机器对机器(machine to machine，M2M)网络系统、无线保真(wireless fidelity，Wi-Fi)系统、无线局域网(wireless local area networks，WLAN)以及未来的5G通信系统等。
还应理解，在本发明实施例中，终端设备也可称之为用户设备(user equipment，UE)、移动台mobile station，MS)、移动终端(mobile terminal)等，该终端设备可以经无线接入网(radio access network，RAN)与一个或多个核心网设备进行通信，例如，终端设备可以包括各种具有无线通信功能的手持设备、车载设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。还可以包括用户单元、蜂窝电话(cellular phone)、智能手机(smart phone)、无线数据卡、个人数字助理(Personal Digital Assistant，PDA)电脑、平板型电脑、无线调制解调器(modem)、手持设备(handset)、膝上型电脑(laptop computer)、机器类型通信(machine type communication,MTC)终端、无线局域网(wireless local area networks，WLAN)中的站点(station，STA)。可以是蜂窝电话、无绳电话、会话启动协议(Session Initiation Protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站以及下一代通信系统，例如，5G网络中的终端设备或者未来演进的公共陆地移动网络(public land mobile network，PLMN)网络中的终端设备等。本发明实施例在此不作限制。
还应理解，基站也可以称之为网络侧设备或者接入网设备，网络侧设备可以是用于与终端设备通信的设备，网络设备可以是LTE系统中的演进型基站(evolutional Node B，eNB或eNodeB)，NR中的gNB或接入点，基站收发器、收发节点等，或者车载设备、可穿戴设备，未来5G网络中的网络设备或者未来演进的PLMN系统中的网络侧设备。例如，网络侧设备可以是WLAN中的接入点(access point，AP)，也可以是全球移动通信系统(global system for mobile communication，GSM)或码分多址(code dvision multiple access，CDMA)，CDMA中的基站(Base Transceiver Station，BTS)。还可以是LTE系统中的演进的节点B(evolved NodeB，eNB或者eNodeB)。或者，网络设备还可以是第三代(3rd Generation，3G)系统的节点B(Node B)，另外，该网络设备还可以是中继站或接入点，或者车载设备、可穿戴设备以及未来5G网络中的网络设备或者未来演进的PLMN网络中的网络设备等。本发明实施例在此不作限制。为方便描述，本发明所有实施例中，上述为 MS提供无线通信功能的装置统称为网络设备。
Polar码是近年提出的高性能信道编码方案，具有高性能、较低复杂度，速率匹配方式灵活的特点，目前已经成为5G系统中控制信息的编码方式。实际工程中Polar码的译码方法有SCL译码和SC译码。一个码长为N的Polar码可以对应一个由N层边构成的二叉译码码树。SC译码能够被描述为在该码树上的译码路径搜索过程。
图1是SC译码路径的示意图，从图1中可以看出，SC译码是从码树的根节点开始，在译码码树上逐步扩展，每层从两条候选路径选择具有相对概率值大的一条，即搜索宽度是1。并在选择上的那一条译码路径的基础上进行下一层的路径扩展。图1中示出了一个简单的码长N＝4时的SC译码路径例子，图1中的黑实线表示选中的一条SC译码路径。通过这条译码路径最终得到一个译码结果，通过对该译码结果进行校验，确定该译码结果是否正确。
由上述SC译码过程可知，SC译码过程中无论在码树的哪一层，都只会从两条候选的译码路径中选择一条，最终得到一个比特估计序列，即译码结果。因此，SC译码计算的复杂度较低，译码延时较小。由于每次只是从可能的两条候选的译码路径中选择一条，因此译码结果的可靠性不高，译码结果不一定准确。因此，SC译码的性能较低。
图2是SCL译码路径的示意图。作为SC译码的改良，SCL译码允许保留多条候选译码路径。从图2可以看出，SCL译码从码树的根节点开始，在码树上逐步扩展，每层都是从2L条候选译码路径选择L条，即搜索宽度是L。并在选择的L条译码路径的基础上进行下一层的路径扩展。图2中示出了一个简单的码长N＝4，搜索宽度是4的SCL译码过程的示意图。图2中的4条黑实线表示选中的4条SCL译码路径。在译码结束时，从4条SCL译码路径中选择可靠性度量值最大的一条路径，其对应的比特估计序列即为译码结果。
图3是典型的SCL译码处理方式的示意性流程图，图3中示出了一个硬比特的处理的全过程，所有的硬比特处理都要从第一阶(stage)开始到最后一个stage结束的循环处理过程，直至所有的硬比特处理完成。阶(stage)相当于图1或图2中的译码码树的层，典型的SCL译码过程中同时存在L(即搜索宽度为L)条译码路径|(path)，通过计算每条译码路径的最大对数似然比(log likelihood ration，LLR)，得到每条译码路径的分支度量值和路径度量值，其中，分支度量值用于计算累积度量值。通过对备选的2L条译码路中每条译码路径的路径度量值的比较，从备选的2L条译码路径中选择L条译码路径，迭代到下一次的硬比特(硬值)的计算中，当所有的硬比特全部计算完成后，通过对L条译码路径的硬比特码流校验选路，选择一条准确性最高的译码路径的译码结果，作为最终的输出结果。
典型的SCL译码处理方式的流程主要包括以下步骤：
1、计算当前译码硬比特需要的stage编号m，m为大于1的正整数，选择stage(1)～stage(m)各阶缓存的LLR和度量累积值。
2、各条译码路径同步从stage(1)～stage(m)逐stage求出LLR。
3、计算各条译码路径的分支度量(branch metric，BM)值和路径度量(path metric,PM)值，共有2L个备选的译码路径度量值，代表2L个备选的译码路径。
4、从2L个备选的译码路径中选择L条译码路径，得到当前译码硬比特的L个译码值。
5、判断当前的需要译码的硬比特(硬值)是否全部译出。
6、如果没有全部译出，计算stage(1)～stage(m)的度量累积值(psum),然后继续处理下一个硬比特。
7、如果全部处理，根据码流校验选路的结果，得到最优的译码结果。
由上述可知，SCL译码的基本特点如下：
1、译码过程中从码树的根节点到任何一个节点所形成的路径，均对应一个路径度量值。
2、从根节点出发，在信息比特(bit)对路径进行扩展。
3、每一层向下一层扩展时，每一层选择当前层中具有较大路径度量值的L条。
4、译码过程中直到扩展到最后一层。如果是循环冗余校验(cyclic redundancy check，CRC)协助译码，选择通过循环冗余校验的路径中度量值绝对值最小的路径作为译码结果。
由上述SCL译码过程可知，SCL译码过程中始终无论在码树的哪一层，都会从2L条候选路径选择L条候选译码路径，最终得到L个比特估计序列，通过对L条候选译码路径可靠性度量值的计算，得到最终译码结果。因此，SCL译码计算的复杂度较高，译码延时较大，由于每次从2L条候选路径选择L条，因此译码结果的可靠性较高，译码结果的准确性较好。因此，SCL的性能较高。
基于SCL译码延时较大但是译码精度高，而SC译码的性能较低却延时较小的问题，本申请提供了一种极化码的译码方法，使得极化码译码时在保持较好的译码性能的前提下减少译码延时。在考虑译码结果准确性的同时考虑译码过程中的延时，达到减小译码延和保证译码结果准确性效果。
图4是适用于本申请的极化码的译码方法和译码器的通信系统的示意图。如图4所示，该通信系统100包括网络设备102，网络设备102可包括多个天线例如，天线104、106、108、110、112和114。另外，网络设备102可附加地包括发射机链和接收机链，本领域普通技术人员可以理解，它们均可包括与信号发送和接收相关的多个部件(例如处理器、调制器、复用器、编码器、解复用器或天线等)。
网络设备102可以与多个终端设备(例如终端设备116和终端设备122)通信。然而，可以理解，网络设备102可以与类似于终端设备116或122的任意数目的终端设备通信。终端设备116和122可以是，例如蜂窝电话、智能电话、便携式电脑、手持通信设备、手持计算设备、卫星无线电装置、全球定位系统、PDA和/或用于在无线通信系统100上通信的任意其它适合设备。
如图4所示，终端设备116与天线112和114通信，其中天线112和114通过前向链路118向终端设备116发送信息，并通过反向链路120从终端设备116接收信息。此外，终端设备122与天线104和106通信，其中天线104和106通过前向链路124向终端设备122发送信息，并通过反向链路126从终端设备122接收信息。
例如，在FDD系统中，例如，前向链路118可利用与反向链路120所使用的不同频带，前向链路124可利用与反向链路126所使用的不同频带。
再例如，在TDD系统和全双工(full duplex)系统中，前向链路118和反向链路120 可使用共同频带，前向链路124和反向链路126可使用共同频带。
被设计用于通信的每个天线(或者由多个天线组成的天线组)和/或区域称为网络设备102的扇区。例如，可将天线组设计为与网络设备102覆盖区域的扇区中的终端设备通信。在网络设备102通过前向链路118和124分别与终端设备116和122进行通信的过程中，网络设备102的发射天线可利用波束成形来改善前向链路118和124的信噪比。此外，与网络设备通过单个天线向它所有的终端设备发送信号的方式相比，在网络设备102利用波束成形向相关覆盖区域中随机分散的终端设备116和122发送信号时，相邻小区中的移动设备会受到较少的干扰。
在给定时间，网络设备102、终端设备116或终端设备122可以是无线通信发送装置和/或无线通信接收装置。当发送数据时，无线通信发送装置可对数据进行编码以用于传输。具体地，无线通信发送装置可获取(例如生成、从其它通信装置接收、或在存储器中保存等)要通过信道发送至无线通信接收装置的一定数目的数据比特。这种数据比特可包含在数据的传输块(或多个传输块)中，传输块可被分段以产生多个码块。
此外，该通信系统100可以是PLMN网络或者D2D网络或者M2M网络或者其他网络，图4只是举例的简化示意图，网络中还可以包括其他网络设备，图4中未予以画
下面结合图5详细说明本申请提供的极化码的译码方法，图5是本发明一个实施例的极化码的译码方法200的示意性流程图，该方法200可以应用在图4所示的场景中，当然也可以应用在其他通信场景中，本发明实施例在此不作限制。
如图5所示，该译码方法200包括：
S210，获取待译码的数据。
S220，分别开始对该数据进行串行抵消列表SCL译码和串行抵消SC译码。
S230，得到该SC译码的译码结果。
S240，在确定该SC译码的译码结果正确的情况下，停止该SCL译码。
S250，输出该SC译码的译码结果。
具体而言，在本申请中，在对待译码的数据进行译码时，首先获取待译码的数据，然后开始对待译码的数据分别进行串行抵消列表SCL译码和串行抵消SC译码，即利用两种译码方法并行的对待译码的数据进行译码。由于SC译码过程复杂度低，译码过程中只有一条备选的译码路径，耗时比较短，因此首先会获得SC译码的译码结果(SC译码结果)。在获得SC译码结果时，该数据的SCL译码正在进行的过程中，即SCL译码还没结束，SCL译码结果还没有得到。由于SC译码的精确度低，因此，SC译码结果并不一定是准确的，需要根据该SC译码结果，确定是否停止该数据的SCL译码。即在确定该SC译码的译码结果正确的情况下，停止对该数据进行SCL译码，并输出该SC译码的译码结果，即将该SC译码的译码结果作为最终的译码结果。
本申请提供的极化码的译码方法，通过对待译码的数据分别并行进行串行抵消列表SCL译码和串行抵消SC译码。由于SC译码延时较小，但是译码的准确度低，误码率较高。SCL译码的延时较大，但是译码的准确度较高，误码率较低。因此，对待译码的数据分别进行SC译码和SCL译码，先得到SC译码结果，在确定该SC译码的译码结果正确的情况下，停止对该数据进行SCL译码，并将该SC译码的译码结果作为最终的译码结果。使得polar码译码在保证译码准确性能的前提下，减少了译码时延，提高了译码的效率。
可选的，作为一个实施例，在确定该SC译码的译码结果不正确的情况下，该方法200还包括：
S260，继续进行该SCL译码。
S270，输出该SCL译码的译码结果。
具体而言，由于SC译码延时小，因此会首先获得SC译码结果，假设在T 1时刻获得SC译码结果，此时，该数据的SCL译码正在进行的过程中，即SCL译码还没结束，SCL译码结果还没有得到。因此，在确定该SC译码的译码结果不正确的情况下，需要继续对该数据进行SCL译码，假设在T 2时刻获得该数据的SCL译码结果，其中，T 2时刻晚于T 1时刻，会输出该SCL译码的译码结果，即将该SCL译码结果作为最终的该数据的译码结果输出。
可选的，作为一个实施例，该分别开始对该数据进行串行抵消列表SCL译码和串行抵消SC译码，包括：
对该数据并行的进行串行抵消列表SCL译码和串行抵消SC译码。
具体而言，在本发明的实施例中，可以并行的对该数据进行SCL译码和SC译码，即对该数据进行SCL译码和SC译码的时间至少部分重叠。由于SC译码所用的时间较短，当对该数据进行SCL译码和SC译码的时间至少部分重叠时，可以从整体上进一步的缩短得到译码结果所用的时长。可选的，作为一个实施例，可以同时开始对该数据进行SCL译码和SC译码，这样可以进一步的减少译码时延。例如，假设在T 1时刻开始对该数据进行SCL译码和SC译码，T 3时刻获得SC译码结果，假设SC译码结果正确，则本次译码所用的时长为T 3-T 1。假设在T 1时刻开始对该数据进行SCL译码，T 2时刻开始SC译码，T 4时刻获得SC译码结果，其中，T 1时刻、T 2时刻、T 3时刻和T 4时刻按时间顺序依次后延，假设SC译码结果正确，则本次译码所用的时长为T 4-T 1。相比于同时开始SCL译码和SC译码，所用的译码时长增大，即译码延时较大。
应理解，在本发明实施例中，对该数据并行的进行SCL译码和SC译码时，只要SC译码结果早于SCL译码结果得到即可。本发明实施例在此不作限制。
本申请提供的极化码的译码方法，对待译码的数据并行的进行SCL译码和SC译码，通过对先得到SC译码的译码结果进行校验，当确定SC译码结果正确时，输出SC译码结果作为译码的最终结果。可以进一步减少译码延时，提高译码效率。
可选的，作为一个实施例，该译码方法200还包括:
S231，对该SC译码的译码结果进行循环冗余CRC校验。
S232，在该CRC校验通过的情况下，确定该SC译码的译码结果正确，或
在该CRC校验不通过的情况下，确定该SC译码的译码结果不正确。
具体而言，在得到SC译码的译码结果后，会对SC译码结果进行CRC校验。即将CRC辅助码作为内码，输入该数据信息中，作为信息码元的一部分进行极化码编码。在译码端，先由SC译码算法产生1条备选的译码码字，即SC译码的译码结果，然后对SC译码的译码结果进行CRC译码，将CRC译码的结果和实际接收到的CRC辅助码进行比较，如果两者相同，即该CRC校验通过，确定该SC译码的译码结果正确。如果两者不相同，即该CRC校验不通过，确定该SC译码的译码结果不正确。
应理解，对该SC译码的译码结果除了可以利用CRC校验来确定SC译码的译码结果是否正确外，还可以通过其他方式进行校验，例如，利用奇偶校验(parity check，PC)等，本发明实施例在此不作限制。
可选的，作为一个实施例，该SCL译码的搜索宽度为8条译码路径。
具体而言，由图2和图3所示的SCL译码过程可知，在SCL译码过程中，搜索宽度越大，则SCL译码路径就越多，译码的结果的准确的概率就越大，即译码结果的精确度越高，误码率也越低，但是，搜索宽度越大，即译码的路径越多，计算量也会越大，因此，延时也越大。在SC译码结果不正确的情况下，考虑到SCL译码延时和译码准确性的平衡，因此，SCL译码的过程中的搜索宽度为8，即同时存在8条译码路径时译码延时较低，译码准确性也相对较好。
应理解，在本发明的实施例中，该SCL译码过程中的搜索宽度的值为可以其他值，例如，为2，或4，或16等。只要满足该译码宽度的值为2的正整数次方即可，本发明实施例在此不作限制。
下面结合图6来说明本发明实施例的极化码的译码方法。图6是本发明一个实施例的极化码的译码方法示意性流程图。图6中的上半部分虚线框内为典型的SCL译码处理方式的流程，下半部分虚线框内为典型的SC译码处理方式的流程。SC译码的实质为单一译码路径的SCL译码，两部分并行执行，由于SC译码的译码路径(path)数较少，只需要进行2选1的路径选择，因此计算简单，相较于SCL译码处理延时较小，SC译码结果会较早得到。当SC译码结果正确时，通过译码结束判决终止SCL译码，输出为SC译码结果。当SC译码结果错误时，SCL需要执行完成，最终输出SCL译码的结果。
其中SCL译码过程与图3中所述步骤相似，为了简洁，在此不再赘述。
SC译码过程的主要步骤如下：
1、计算当前译码硬比特需要的stage编号m，m为大于1的正整数，选择stage(1)～stage(m)各阶缓存的LLR和度量累积值。
2、各条译码路径同步从stage(1)～stage(m)逐stage求出LLR。
3、计算各条译码路径的BM和PM，共有2个备选的PM值，代表2个备选的译码路径。
4、从2个备选的译码路径中选择1条译码路径，得到当前译码硬比特的个译码值。
5、判断当前的需要译码的硬比特是否全部译出。
6、如果没有全部译出，计算stage(1)～stage(m)的度量累积值(psum),然后继续处理下一个硬比特。
7、如果全部处理，得到SC译码结果，并对SC译码结果进行校验。
8、如果经过校验，确定SC译码结果不正确，则SC译码部分结束，SCL译码继续执行，直至SCL译码结果产生并输出。
9、如果经过校验，确定SC译码结果正确，则发出SCL译码的终止信号，强行终止SCL译码部分，直接输出SC译码结果。
本发明实施例提供的极化码的译码方法，利用SC译码简单、延时小和SCL译码准确度高的特点，通过对待译码的数据并行的进行SC译码和SCL译码，在先得到的SC译码结果正确的情况下，将SC译码结果作为最终的译码结果。提高了译码的速度，减少了译 码时延，保证了译码结果的准确性，提高译码效率。
还应理解，在本发明的实施例中，上述各过程和各步骤序号的大小并不意味着执行顺序的先后，各过程的执行顺序应该以其功能和内在的逻辑而定，而不应对本发明的实施例的实施过程造成任何限制。
上文结合图1至图6，详细描述了本发明实施例提供的极化码的译码方法，下文将结合图7至图9，详细描述本发明实施例提供的译码器。
图7示出了本发明一个实施例的译码器300的示意性框图，如图7所示，该译码器300包括获取电路310、SCL译码电路320、SC译码电路330和输出电路340。
该获取电路310，用于获取待译码的数据。
该SCL译码电路320，用于对该数据进行串行抵消列表SCL译码。
该SC译码电路330，用于对该数据进行串行抵消SC译码。
该SC译码电路330还用于得到SC译码结果。
在确定该SC译码的译码结果正确的情况下，该SCL译码电路320还用于停止该SCL译码。
输出电路340，用于输出该SC译码的译码结果。
本申请提供的译码器，通过对待译码的数据分别并行进行串行抵消列表SCL译码和串行抵消SC译码。由于SC译码延时较小，但是译码的准确度低，误码率较高。SCL译码的延时较大，但是译码的准确度较高，误码率较低。因此，对待译码的数据分别进行SC译码和SCL译码，先得到SC译码结果，在确定该SC译码的译码结果正确的情况下，停止对该数据进行SCL译码，并将该SC译码的译码结果作为最终的译码结果。使得polar码译码在保证译码准确性能的前提下，减少了译码时延，提高了译码的效率。
可选的，作为一个实施例，在确定该SC译码的译码结果不正确的情况下，该SCL译码电路320还用于继续进行该SCL译码。该输出电路340还用于：输出该SCL译码的译码结果。
可选的，作为一个实施例，该SCL译码电路320和该SC译码电路330并行的对该数据进行译码。
可选的，作为一个实施例，该译码器300还包括校验电路350，该校验电路350用于：对该SC译码的译码结果进行循环冗余CRC校验；在该CRC校验通过的情况下，确定该SC译码的译码结果正确，或在该CRC校验不通过的情况下，确定该SC译码的译码结果不正确。
可选的，作为一个实施例，该SCL译码电路320的搜索宽度为8条译码路径。
应注意，在本发明实施例中，译码器300包括的各个电路可以由逻辑器件组成，用来支持各个电路完成上述的各个功能。
应理解，本发明实施例中的译码器300中的各个电路的上述和其他操作和/或功能分别实现图5和图6中的各个方法的相应流程，为了简洁，在此不再赘述。
图8是根据本发明实施例的译码器400的示意性框图。如图8所示，该译码器400包括处理器410、存储器420和收发器430，该处理器410、存储器420和收发器430之间通过内部连接通路互相通信，传递控制和/或数据信号。
该存储器410用于存储程序代码。
该收发器430用于在处理器410的驱动下执行具体的信号收发以实现上述各实施例中的译码方法。
该处理器420用于调用该程序代码以实现本发明上述各实施例中的译码方法。
本申请提供的译码器，通过对待译码的数据分别并行进行串行抵消列表SCL译码和串行抵消SC译码。由于SC译码延时较小，但是译码的准确度低，误码率较高。SCL译码的延时较大，但是译码的准确度较高，误码率较低。因此，对待译码的数据分别进行SC译码和SCL译码，先得到SC译码结果，在确定该SC译码的译码结果正确的情况下，停止对该数据进行SCL译码，并将该SC译码的译码结果作为最终的译码结果。使得polar码译码在保证译码准确性能的前提下，减少了译码时延，提高了译码的效率。
应理解，根据本发明实施例译码器400中的各个组件的上述和其他操作和/或功能分别实现图5和图6中的各个方法的相应流程，为了简洁，在此不再赘述。
译码器400中的各个组件通过通信连接，即处理器410、存储器420和收发器430之间通过内部连接通路互相通信，传递控制和/或数据信号。本申请上述方法实施例可以应用于处理器中，或者由处理器实现上述方法实施例的步骤。处理器可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。为避免重复，这里不再详细描述。上述的处理器可以是中央处理器(central processing unit，CPU)，网络处理器(network processor，NP)或者CPU和NP的组合、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
该存储器420可以包括只读存储器和随机存取存储器，并向处理器410提供指令和数据。存储器420的一部分还可以包括非易失性随机存取存储器。例如，存储器420还可以存储设备类型的信息。所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
可以理解，本发明实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
应注意，在发明实施例中，处理器410可以由处理模块实现，存储器420可以由存储 模块实现，收发器430可以由收发模块实现，如图9所示，译码器500可以包括处理模块510、存储模块520和收发模块530。
图8所示的译码器400或图9所示的译码器500能够实现前述图5和图6中所示的步骤，为避免重复，这里不再赘述。
本发明实施例还提供了一种可读介质，用于存储程序代码，该程序代码包括用于执行上述图5和图6中本发明实施例的极化码的译码方法的指令。该可读介质可以是ROM或RAM，本发明实施例对此不做限制。
应理解，本文中术语“和/或”以及“A或B中的至少一种”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (11)

  1. 一种极化码的译码方法，其特征在于，包括：
    获取待译码的数据；
    分别开始对所述数据进行串行抵消列表SCL译码和串行抵消SC译码；
    得到所述SC译码的译码结果；
    在确定所述SC译码的译码结果正确的情况下，停止所述SCL译码；
    输出所述SC译码的译码结果。
  2. 根据权利要求1所述的译码方法，其特征在于，在确定所述SC译码的译码结果不正确的情况下，所述方法还包括：
    继续进行所述SCL译码；
    输出所述SCL译码的译码结果。
  3. 根据权利要求1或2所述的译码方法，其特征在于，所述分别开始对所述数据进行串行抵消列表SCL译码和串行抵消SC译码，包括：
    对所述数据并行的进行所述SCL译码和所述SC译码。
  4. 根据权利要求1至3中任一项所述的译码方法，其特征在于，所述译码方法还包括：
    对所述SC译码的译码结果进行循环冗余CRC校验；
    在所述CRC校验通过的情况下，确定所述SC译码的译码结果正确，或
    在所述CRC校验不通过的情况下，确定所述SC译码的译码结果不正确。
  5. 根据权利要求1至4中任一项所述的译码方法，其特征在于，所述SCL译码的搜索宽度为8条译码路径。
  6. 一种译码器，其特征在于，包括：
    获取电路，用于获取待译码的数据；
    SCL译码电路，用于对所述数据进行串行抵消列表SCL译码；
    SC译码电路，用于对所述数据进行串行抵消SC译码；
    所述SC译码电路还用于得到所述SC译码的译码结果；
    在确定所述SC译码的译码结果正确的情况下，所述SCL译码电路还用于停止所述SCL译码；
    输出电路，用于输出所述SC译码的译码结果。
  7. 根据权利要求6所述的译码器，其特征在于，在确定所述SC译码的译码结果不正确的情况下，所述SCL译码电路还用于继续进行所述SCL译码；
    所述输出电路还用于输出所述SCL译码的译码结果。
  8. 根据权利要求6或7所述的译码器，其特征在于，所述SCL译码电路和所述SC译码电路并行的对所述数据进行译码。
  9. 根据权利要求6至8中任一项所述的译码器，其特征在于，所述译码器还包括校验电路，所述校验电路用于：对所述SC译码的译码结果进行循环冗余CRC校验；
    在所述CRC校验通过的情况下，确定所述SC译码的译码结果正确，或
    在所述CRC校验不通过的情况下，确定所述SC译码的译码结果不正确。
  10. 根据权利要求6至9中任一项所述的译码器，其特征在于，所述SCL译码电路的搜索宽度为8条译码路径。
  11. 一种可读存储介质，其特征在于，包括指令，当其在处理器上运行时，使得计处理器执行如权利要求1至5中任一项所述的译码方法。
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