WO2019005157A1

WO2019005157A1 - Perpendicular spin transfer torque memory (psttm) devices with enhanced stability and high tunneling magnetoresistance ratio and methods to form the same

Info

Publication number: WO2019005157A1
Application number: PCT/US2017/040496
Authority: WO
Inventors: Christopher J. WIEGAND; Tofizur RAHMAN; Daniel G. OUELLETTE; Angeline K. SMITH; Justin S. BROCKMAN; Kevin P. O'brien; Kaan OGUZ; Mark L. Doczy; Brian S. Doyle; Oleg Golonzka; Juan G. ALZATE VINASCO
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

A memory device includes a bottom electrode disposed above a substrate, a fixed magnet disposed above the bottom electrode, a tunnel barrier including a magnesium oxide disposed on the fixed magnet, a free magnet on the tunnel barrier, a cap oxide layer disposed on the free magnet, a follower magnet disposed on the oxide layer and a metallic cap disposed on the follower magnet. The metallic cap includes a metal such as Hf, W and Ta and further includes a trace amounts of an inert gas. One or more conductive nano-channels extend from the metallic cap through the free magnet and into the oxide layer, where each of the one or more conductive nano-channels include the material of the metallic cap. The memory device further includes an etch stop layer disposed on the metallic cap and a top electrode disposed on the etch stop layer.

Description

PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (PSTTM) DEVICES WITH ENHANCED STABILITY AND HIGH TUNNELING MAGNETORESISTANCE RATIO AND METHODS TO FORM

THE SAME

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit fabrication and, in particular, perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and high tunneling magnetoresistance ratio (TMR) and methods to form the same.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with pSTTM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of assembling a pSTTM stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, increasing thermal stability and increasing TMR of pSTTM devices are some important areas of development. As such, improvements are still needed in the areas of pSTTM stack development that will contribute to improving stability and TMR.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a cross-sectional view of a perpendicular spin transfer torque memory (pSTTM) device, in accordance with an embodiment of the present disclosure.

Figure IB illustrates a cross-sectional view of individual layers of a synthetic

antiferromagnetic layer, in accordance with embodiment of the present disclosure.

Figure 2 illustrates a cross-sectional view of a pSTTM device, in accordance with an embodiment of the present disclosure.

Figures 3 A-3G illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM device.

Figure 3 A illustrates a cross-sectional view of the formation of a conductive interconnect above a substrate.

Figure 3B illustrates a cross-sectional view of the structure in Figure 3 A following the formation of various layers in a material layer stack for a pSTTM device on the conductive interconnect, in accordance with an embodiment of the present disclosure.

Figure 3C illustrates a cross-sectional view of the structure in Figure 3B following the formation a metallic cap layer on the follower magnetic layer, in accordance with an embodiment of the present disclosure.

Figure 3D illustrates a cross-sectional view of the structure in Figure 3C following the formation of an etch stop layer and a top electrode layer on the etch stop layer.

Figure 3E illustrates a cross-sectional view of the structure in Figure 3D following the patterning of the top electrode layer.

Figure 3F illustrates a cross-sectional view of the structure in Figure 3E following the patterning of the pSTTM material layer stack to form a pSTTM device.

Figure 3G illustrates a cross-sectional view of the structure in Figure 3F following the formation of a dielectric spacer on sidewalls of the pSTTM device.

Figure 4 illustrates a cross-sectional view of a pSTTM device formed on a conductive interconnect coupled to a transistor, in accordance with an embodiment of the present disclosure.

Figure 5 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 6 illustrates an integrated circuit (IC) structure that includes one or more embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and high tunneling magnetoresi stance ratio (TMR) and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as transistor operations and switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

A pSTTM device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state. The resistance state of a pSTTM device is defined by the relative orientation of magnetization between a free magnetic layer and a fixed magnetic layer that are separated by a tunnel barrier. When the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that are in the same direction the pSTTM device is said to be in a low resistance state. Conversely, when the magnetization of the free magnetic layer and a fixed magnetic layer have orientations that are in opposite directions, the pSTTM device is said to be in a high resistance state. In an embodiment, resistance switching is brought about by passing a critical amount of spin polarized current through the pSTTM device so as to influence orientation of the magnetization of the free magnetic layer to align with the magnetization of the fixed magnetic layer. By changing the direction of the current, the magnetization in the free magnetic layer may be reversed relative to that of the fixed magnetic layer. Since the free magnetic layer does not need power to retain relative orientation of magnetization, the resistance state of the pSTTM device is retained even when there is no power applied to the pSTTM device. For this reason, pSTTM belongs to a class of memory known as non-volatile memory.

Integrating a non-volatile memory device such as an STTM device onto an access transistor enables the formation of embedded memory for system on chip applications.

However, approaches to integrate an STTM device onto an access transistor presents challenges that have become far more formidable with scaling. As scaling continues, the need for smaller memory devices to fit into a scaled cell size has driven the industry in the direction of

"perpendicular" STTM or pSTTM. The word "perpendicular" in pSTTM devices refers to fact that magnetic dipoles in the free and fixed magnets are directed perpendicular to a plane of a substrate above which the pSTTM device is formed. Fortunately, while pSTTM devices have high stability for small memory device sizes, improving stability along with increasing TMR continues to be a challenge. Stability of a pSTTM device refers to an ease with which the magnetic state of a pSTTM device can be inadvertently changed from a high to a low state or a low to a high state resistance state.

A material layer stack for a pSTTM device includes a fixed magnetic layer such as a CoFeB, a tunnel barrier layer such as but not limited to MgO or AI2O3 disposed above the fixed magnetic layer. In an embodiment, a cap oxide layer such as an MgO or AI2O3 above the free magnetic layer is found to improve or increase the perpendicular magnetic anisotropy (PMA) of the free magnetic layer. Specifically, the cap oxide layer is designed to enable interfacial PMA at an interface between the cap oxide layer and the free magnetic layer. Increasing PMA increases stability in pSTTM devices. The interfacial PMA arises due to bond hybridization between (a) iron in the free magnetic layer and oxygen in the cap oxide layer on top of the free layer and (b) between iron in the free magnetic layer and oxygen in the tunnel barrier at the bottom of the free layer.

An addition of a cap oxide layer such as an MgO or AI2O3 above the free magnetic layer is found to lower a property of the pSTTM device known as tunneling magnetoresi stance (TMR) ratio. The cap oxide layer adds a series resistance to the pSTTM device lowering the TMR. The TMR ratio of a pSTTM device with a cap oxide layer is given by equation (1) below:

TMR = [RHIGH - RLOW]*[1/ RLOW + RCAP], (1)

where RHIGH is a resistance of the pSTTM device when a magnetization of a free magnet is in an opposite direction to a magnetization in a fixed magnet, and where RLOW is a resistance of the pSTTM device when the magnetization of the free magnet is in the same direction as the magnetization of the fixed magnet and RCAP, is the resistance of the cap oxide layer. In an embodiment, a cap oxide that is engineered to have a lower resistance does not appreciably alter the TMR of a pSTTM device but helps to increase the PMA.

When a free magnetic layer includes an alloy such as a body-centred cubic (BCC) (001) CoFeB, boron provides a means for formation of an amorphous CoFeB. However, out-diffusion of boron from the amorphous CoFeB film allows the free magnetic layer to follow a templated crystallization of the tunnel barrier layer. For optimal crystallization of CoFeB, a sufficient amount of boron out-diffusion, through an escape path, to an adjacent layer is desirable.

Matching the crystallization between the free magnetic layer and the tunnel barrier layer leads to improved tunnel magnetoresi stance (TMR) ratio. An optimally crystallized CoFeB that is lattice matched to the tunnel barrier can provide a TMR ratio that is in excess of 100%. In an embodiment, a cap oxide layer, such as an MgO, above the free magnetic layer can improve PMA. In one embodiment, the MgO can also prevent the boron to escape from CoFeB. By engineering the cap oxide layer including MgO, to create a boron escape path, stability as well as TMR of the pSTTM device can be simultaneously improved.

In accordance with an embodiment of the present disclosure, a memory device includes a fixed magnetic layer above a substrate, a tunnel barrier above the fixed magnetic layer and a magnetic structure disposed on a tunnel barrier layer. The magnetic structure includes a free magnetic layer and a cap oxide layer disposed on the free magnetic layer. The magnetic structure further includes an ultrathin second (follower) magnetic layer disposed on the cap oxide layer to increase the PMA and a metallic cap layer on the free magnetic layer. In an

embodiment, the process used to form the metallic cap leads to the creation of one or more conductive nano-channels that extends from the metallic cap layer through the follower magnetic layer into the cap oxide layer. In an embodiment, the one or more conductive nano-channels includes the material of the metallic cap layer. In an embodiment, one or more nano-channels further extend down from metallic cap layer to an uppermost surface of the free magnetic layer. When the free magnetic layer includes boron, such extended conductive nano-channels provide a diffusion path for boron from the free magnetic layer during a crystallization process.

Figure 1A illustrates a cross-sectional illustration of a pSTTM device 100. The pSTTM device 100 includes a bottom electrode 116 disposed above a substrate 140, a fixed magnet 114 disposed above the bottom electrode 116, a tunnel barrier 112 disposed on the fixed magnet 114, and a magnetic structure 101 disposed on a tunnel barrier 112. In an embodiment, the pSTTM device 100 further includes a top electrode 120 disposed above the follower magnet 106, as illustrated in Figure 1 A.

The magnetic structure 101 includes a free magnet 102, a cap oxide layer 104 on the free magnet 102 and a second magnetic layer, also known as a follower magnet 106, disposed on the cap oxide layer 104. The magnetic structure 101 further includes a metallic cap 108 disposed on the follower magnet 106. One or more conductive nano-channels 110 extend from the metallic cap 108 through the follower magnet 106 into the cap oxide layer 104. In an embodiment, each of the one or more conductive nano-channels 110 include a material of the metallic cap 108.

In an embodiment, the metallic cap 108 includes a metal such as but not limited to Hf, W and Ta. In an embodiment, the metallic cap 108 further includes a trace element of an inert gas such as Kr and Xe. In an embodiment, the trace element in the metallic cap layer has a concentration between 2 x 10²⁰ atoms/cm³ to 4 x 10²⁰ atoms/cm³. In an embodiment, the metallic cap 108 has a thickness between 0.5nm and l .Onm.

In an embodiment, each of the one or more conductive nano-channels 110 have a cross- sectional profile that is funnel or cone shaped as illustrated in Figure 1 A. In one such embodiment, one or more conductive nano-channels 110 each has a wider portion near a lowermost surface of the metallic cap 108 and a smaller narrower portion in the cap oxide layer 104. In other embodiments, the conductive nano-channels 110 are not regularly shaped and may have a wider portion in the cap oxide layer 104 than in the follower magnet 106. The wider portion of the conductive nano-channels 110 in the cap oxide layer 104 may result from the conductive nano-channels 110 spatially coinciding with already existing defects in the cap oxide layer 104 as will be discussed further below. In an embodiment, each of the conductive nano- channels 110 have a different width. In an embodiment, each of the conductive nano-channels 110 have a width between lnm and lOnm. In an embodiment, two or more conductive nano- channels 110 may be partially joined to form a larger conductive nano-channel. The conductive nano-channels 110 are not regularly spaced apart. In an embodiment, one or more conductive nano-channels 110 are disposed on the periphery of the cap oxide layer 104 and on the periphery of the follower magnet 106. In an embodiment, at least one of the one or more conductive nano- channels 110 extend to an uppermost surface of the free magnet 102. In an embodiment, the one or more conductive nano-channels 110 also includes trace amounts of boron.

Referring again to magnetic structure 101 in Figure 1 A, the follower magnet 106 is magnetically coupled to the free magnet 102 to form a coupled system of switching magnetic layers. In an embodiment, the follower magnet 106 has a weaker perpendicular magnetic anisotropy than a perpendicular magnetic anisotropy of the free magnet 102. A follower magnet 106 having a weaker perpendicular magnetic anisotropy undergoes current induced

magnetization switching more easily than a free magnet 102 having a stronger perpendicular magnetic anisotropy. The presence of the follower magnetic layer with a weaker perpendicular magnetic anisotropy does not increase the magnitude of the switching current requirement of a pSTTM device 100 but increases the PMA of the magnetic structure 101.

In an embodiment, the follower magnet 106 has a thin uppermost portion that can be non- magnetic. In such an embodiment, the follower magnet 106 has a material composition and a thickness sufficient for perpendicular magnetic anisotropy and to remain magnetically coupled to the free magnet 102. In an embodiment, the follower magnet 106 includes an alloy such as but not limited to CoFe or CoFeB. In an embodiment the follower magnet 106 is CoFeB. In an embodiment, the follower magnet 106 has a thickness between O. lnm-0.5 nm.

Referring again to magnetic structure 101 in Figure 1 A, in an embodiment, when the free magnet 102 includes iron, the cap oxide layer 104 provides a source of oxygen that enables oxygen -iron hybridization at an interface 105 located between an uppermost surface of the free magnet 102 and a lowermost surface of the cap oxide layer 104. Oxygen-iron hybridization at the interface 105 can enable a high interfacial perpendicular magnetic anisotropy in the free magnet 102. In an embodiment, the cap oxide layer 104 is MgO. In an embodiment, the cap oxide layer 104 has a thickness that is between 0.3nm-0.7nm. In an embodiment, the cap oxide layer 104 has pinhole defects. The pinhole defects have a width of at lmeast 0.2n and are randomly distributed in the oxide layer. Some pin hole defects are aligned with the conductive nano-channels 110 to create conductive nano-channels 110 having a wider portion in the cap oxide layer 104 than in the follower magnet 106, such as a conductive nano-channel 110A illustrated in Figure 1 A. In an embodiment, when a cap oxide layer 104 includes an MgO, pinhole defects can include a region having a low Mg density In an embodiment, the presence of the conductive nano-channels 110 in the cap oxide layer 104 can reduce an electrical resistance of the pSTTM device 100.

In an embodiment, the free magnet 102 includes cobalt, boron and iron. In an

embodiment, the free magnet 102 of the pSTTM device 100 includes an alloy such as CoFe or CoFeB. In an embodiment, the free magnet 102 includes a layer of Coioo-x-_yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnet 102 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In an embodiment the free magnet 102 has a thickness that is between lnm- 2.5nm. In an embodiment, free magnet 102 having a thickness between l.Onm and 2.5nm results in the free magnet 102 having a

perpendicular magnetic anisotropy.

The tunnel barrier 112 is composed of a material suitable for allowing electron current having a majority spin to pass through the tunnel barrier 112, while impeding at least to some extent electron current having a minority spin from passing through the tunnel barrier 112. Thus, the tunnel barrier 112 (or spin filter layer) may also be referred to as a tunneling layer for electron current of a particular spin orientation. In one embodiment, the tunnel barrier 112 includes an oxide such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (AI2O3). In one embodiment, the tunnel barrier 112 is MgO and has a thickness of

approximately 1 to 2nm.

In an embodiment, the fixed magnet 114 includes materials and has a thickness sufficient for maintaining a fixed magnetization. Fixed magnetization indicates that the magnetization direction in the fixed magnet 114 does not change direction during spin transfer torque-current flow. In an embodiment, the fixed magnet 114 includes a magnetic metal such as cobalt, nickel and iron. In an embodiment, the fixed magnet 114 includes an alloy such as CoFe or CoFeB. In an embodiment, the fixed magnet 114 includes a layer of Coioo-x-_yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnet 114 is FeB, where the concentration of boron is between 10-40 atomic percent of the total composition of the FeB alloy. In another embodiment the fixed magnet 114 has a thickness that is between 1.5nm- 2.5nm. In an embodiment, a fixed magnet 114 having a thickness between 1.5nm and 2.5nm has perpendicular magnetic anisotropy.

Referring again to Figure 1 A, in an embodiment, the bottom electrode 116 is composed of a material or stack of materials suitable for electrically contacting the fixed magnet 114 side of the pSTTM device 100. In an embodiment, the bottom electrode 116 includes an amorphous conductive layer. In an embodiment, the bottom electrode 116 is a topographically smooth electrode. In a specific embodiment, the bottom electrode 116 is composed of Ru layers interleaved with Ta layers. In another embodiment, the bottom electrode 116 is TiN. In an embodiment, the bottom electrode 116 has a thickness between 20nm-50nm. In an embodiment, the top electrode 120 includes a material such as Ta or TiN. In an embodiment, the top electrode 120 has a thickness between 30-70nm. In an embodiment, the bottom electrode 116 and the top electrode 120 include a same metal such as Ta or TiN.

Referring again to Figure 1 A, the pSTTM device 100 is disposed above a conductive interconnect 130 disposed in an interlayer dielectric 132 formed above a substrate 140. In an embodiment, the conductive interconnect 130 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the interlayer dielectric 132 includes a dielectric layer such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. As illustrated in Figure 1 A, the pSTTM device 100 has a width, W_PSTTM, and the conductive interconnect 130 has a width Wei. In an

embodiment, the pSTTM device 100 has a width, W_PSTTM, that is less that the width, Wei, of the conductive interconnect 130. In an embodiment, the pSTTM device 100 has a width, W_PSTTM, that is greater that the width, Wei, of the conductive interconnect 130. In another embodiment, the pSTTM device 100 has a width, W_PSTTM, that is similar to the width, Wei, of the conductive interconnect 130. In an embodiment, the substrate 140 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 140 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Logic devices such as MOSFET transistors and access transistors and may be formed on the substrate 140. Logic devices such as access transistors may be integrated with memory devices such as pSTTM device 100 to form embedded memory. Embedded memory including pSTTM devices and logic MOSFET transistors can be combined to form functional integrated circuits such as a system on chip (SOC) and microprocessors.

Figure IB illustrates cross-sectional view of the synthetic antiferromagnetic (SAF) structure 150 in accordance of an embodiment of the present disclosure. In an embodiment, the SAF structure 150 is disposed on the bottom electrode 116 and under the fixed magnet 114 in order to prevent accidental flipping of magnetization in the fixed magnet 114. In an

embodiment, a SAF structure 150 is ferromagnetically coupled with the fixed magnet 114.

In an embodiment, the SAF structure 150 includes a non-magnetic layer 150B between a first ferromagnetic layer 150A and a second ferromagnetic layer 150C as depicted in Figure IB. The first ferromagnetic layer 150A and the second ferromagnetic layer 150C are anti- ferromagnetically coupled to each other. In an embodiment, the first ferromagnetic layer 150A includes a layer of a magnetic metal such as Co, Ni or Fe. In an embodiment, the first ferromagnetic layer 150A includes an alloy such as CoFe, CoFeB, CoFe, FeB. In an

embodiment, the second ferromagnetic layer 150C includes a layer of a magnetic metal such as Co, Ni or Fe. In an embodiment, the second ferromagnetic layer 150C includes an alloy such as CoFe, CoFeB, CoFe, FeB. In an embodiment, the non-magnetic layer 150B includes a ruthenium or an iridium layer. In an embodiment, a ruthenium based non-magnetic layer 150B has a thickness between 4-9 Angstroms to ensure that the coupling between the first

ferromagnetic layer 150A and the second ferromagnetic layer 150C is anti-ferromagnetic in nature.

In an embodiment, the SAF structure 150 includes a bilayer having a magnetic metal disposed on a non-magnetic metal such as a bilayer of Co/Pd or a bilayer of Co/Pt. In an embodiment, the SAF structure 150 includes a stack of bilayers, where each bilayer includes a magnetic metal disposed on a non-magnetic metal, where the total number of bilayers can range from 2-10.

In an embodiment, an additional layer of non-magnetic spacer material may be disposed between the SAF structure 150 and the fixed magnet 114. In an embodiment, a layer of non- magnetic spacer material may include a metal such as Ta, Ru or Ir. In an embodiment, the thickness of the layer of non-magnetic spacer material is greater than 0. lnm but less than 0.23nm. A non-magnetic spacer material having a thickness greater than 0. lnm but less than 0.23nm can enable ferromagnetic coupling between the SAF structure 150 and the fixed magnet 114.

Figure 2 illustrates a cross-sectional view of a pSTTM device 200 in accordance with an embodiment of the present disclosure. In an embodiment, pSTTM device 200 includes an additional etch stop layer 260 disposed above the metallic cap 108 compared to pSTTM device 100. In an embodiment, the etch stop layer 260 includes a material such as but not limited to ruthenium or tantalum nitride. In an embodiment, the etch stop layer 260 is between 5-10 times thicker than the metallic cap 108. In an embodiment, the etch stop layer 260 has a thickness between lnm-5nm.

Figures 3A-3G illustrate cross-sectional views representing various operations in a method of fabricating a pSTTM device.

Figure 3A illustrates a conductive interconnect 302 surrounded by a dielectric layer 301 formed above a substrate 300. In an embodiment, the conductive interconnect 302 is formed in a dielectric layer 301 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 302 includes a barrier layer, such as titanium nitride, ruthenium, tantalum, tantalum nitride, and a fill metal, such as copper, tungsten. In an embodiment, the conductive interconnect 302 is fabricated using a subtractive etch process when materials other than copper are utilized. In one such embodiment, the conductive interconnect 302 includes a material such as but not limited to titanium nitride, ruthenium, tantalum, tantalum nitride. In an embodiment, the dielectric layer 301 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer 301 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 302. In an embodiment, the dielectric layer 301 has a total thickness between 70nm-300nm. In an embodiment, conductive interconnect 302 is electrically connected to a circuit element such as an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a pSTTM device to form embedded memory.

In an embodiment, the substrate 300 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate 300 includes other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

Figure 3B illustrates a cross-sectional view of the structure in Figure 3 A following the formation of various layers of a material layer stack for a pSTTM device, in accordance with an embodiment of the present disclosure. In an embodiment, the bottom electrode layer 303 is blanket deposited onto an uppermost surface of the conductive interconnect 302 and onto an uppermost surface of the dielectric layer 301. In an embodiment, the bottom electrode layer 303 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the bottom electrode layer 303 includes a metal such as but not limited to W, Ru, Ti or Ta or an alloy such as but not limited to WN, TiN or TaN. In an embodiment, the bottom electrode layer 303 is deposited to a thickness between 20nm to 30nm.

In an embodiment the bottom electrode layer 303 is first blanket deposited on an uppermost surface of the conductive interconnect 302 and on an uppermost surface of the dielectric layer 301, and subsequently polished to achieve a surface roughness of lnm or less. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process to form a topographically smooth uppermost surface having a surface roughness of less than lnm. A surface roughness of less than lnm is sufficient to enable a subsequent fixed magnetic layer and a tunnel barrier layer to be formed with well-ordered crystal planes. In an embodiment, a material layer stack to form a SAF structure such as a SAF structure 150 is also deposited (not shown) after forming the bottom electrode layer 303.

A fixed magnetic layer 305 is deposited on the bottom electrode layer 303. In an embodiment, the fixed magnetic layer 305 is blanket deposited using a physical vapor deposition (PVD) process. The PVD deposition process ensures that the fixed magnetic layer 305 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate. In an embodiment, a fixed magnetic layer 305 deposited by a PVD process is amorphous in nature. In an embodiment, the fixed magnetic layer 305 includes an alloy such as but not limited to CoFe, CoFeB or FeB. In an embodiment, fixed magnetic layer 305 includes a layer of Coioo-x- _yFe_xBy, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the fixed magnetic layer 305 is blanket deposited to a thickness between 2nm-2.5nm.

Atunnel barrier layer 307 is then blanket deposited on the fixed magnetic layer 305. In an embodiment, the tunnel barrier layer 307 includes a material such as MgO or AI2O3. In an embodiment, the tunnel barrier layer 307 is an MgO and is deposited using a reactive sputter process. In an embodiment, the reactive sputter process is carried out at room temperature. In an embodiment, the MgO is deposited to a thickness between 0.8nm to lnm. In an embodiment, the reactive sputter deposition process is carried out in a manner that yields a tunnel barrier layer 307 having a mostly crystalline structure. In another embodiment, the tunnel barrier layer 307 is not crystalline as deposited but becomes highly crystalline after an anneal process.

A free magnetic layer 309 is deposited on the tunnel barrier layer 307. In an

embodiment, the free magnetic layer 309 is blanket deposited using a physical vapor deposition (PVD) process. The PVD deposition process ensures that the free magnetic layer 309 has thickness uniformity that is uniform to within 1% of the film thickness across an entire substrate. In an embodiment, a free magnetic layer 309 deposited by a PVD process is amorphous in nature. In an embodiment, the free magnetic layer 309 includes an alloy such as but not limited to CoFeB and FeB that is amorphous as deposited. In an embodiment, free magnetic layer 309 includes a layer of Coioo-x-_yFe_xB_y, where X and Y each represent atomic percent, further where X is between 50-80 and Y is between 10-40, and further where the sum of X and Y is less than 100. In one specific embodiment, X is 60 and Y is 20. In an embodiment, the free magnetic layer 309 is FeB, where the concentration of boron is between 10-40 atomic percent of the total

composition of the FeB alloy. In an embodiment, a free magnetic layer 309 including an alloy of a magnetic metal and boron is deposited with a boron content of 10-20% to ensure an amorphous layer is formed. In an embodiment, free magnetic layer 309 is deposited to a thickness between 1.0nm-2.8nm. Exemplary thickness of the free magnetic layer 309 is between 1.3nm-2.3nm.

A cap oxide layer 311 is then deposited on the free magnetic layer 309. The cap oxide layer 311 is formed on the uppermost surface of the free magnetic layer 309 to increase the interfacial perpendicular magnetic anisotropy of the pSTTM material layer stack 330. In an embodiment, the oxide deposition process includes blanket depositing a layer of metal onto an uppermost surface of the free magnetic layer 309 and then oxidizing the layer of metal to form the cap oxide layer 311. In an embodiment, a metal such as magnesium is first DC sputter deposited onto the surface of the free magnetic layer 309 and then oxidized. In an embodiment, the DC sputter deposition process is carried out at ambient temperatures of less than 300K. In an embodiment, the oxidation process includes subjecting the magnesium metal to an 0₂ gas at a pressure between 3mtorr-730mtorr. In an embodiment, an MgO formed by a process of depositing a layer of Mg and then oxidizing the layer of Mg can develop pin hole defects.

The deposition and oxidation process creates a cap oxide layer 311 that is not crystalline, in contrast to the crystalline cap oxide layer 311 formed by a reactive co-sputter process.

However, unlike the tunnel barrier layer 307, the cap oxide layer 311 does not act as a spin filter but acts rather as a conductive layer. In one embodiment, the cap oxide layer 311 can act as a partial spin filter. In an embodiment, the cap oxide layer 311 is deposited to a thickness between 0.3nm-0.7nm. Depositing a cap oxide layer 311 to a thickness between 0.3nm-0.7nm can help increase PMA, but can contribute to additional series resistance.

In an embodiment, the follower magnetic layer 313 is blanket deposited on the uppermost surface of the cap oxide layer 311. In an embodiment, the follower magnetic layer 313 is similar or substantially similar to the follower magnet 106. In an embodiment, the deposition process includes a physical vapor deposition (PVD) process. In an embodiment, an RF or a DC sputtering process is utilized to form the follower magnetic layer 313. The follower magnetic layer 313 is deposited to a thickness that results in a lower perpendicular magnetic anisotropy of the follower magnetic layer 313 compared to the perpendicular magnetic anisotropy of the free magnetic layer 309. In an embodiment, the follower magnetic layer 313 is deposited to a thickness to enable a lower PMA as well as promote the formation of conductive nano-channels as will be discussed below. In an embodiment, the follower magnetic layer 313 is deposited to a thickness of 0. lnm-0.5nm.

Figure 3C illustrates a cross-sectional view of the structure in Figure 3B following the formation of a metallic cap layer 315 on the follower magnetic layer 313. In an embodiment, the metallic cap layer 315 includes a metal such as tungsten or tantalum. In an embodiment, the metallic cap layer 315 is blanket deposited on the follower magnetic layer 313, using a low energy physical vapor deposition (PVD) process. In an embodiment, the metallic cap layer 315 is deposited to a thickness between 0.5nm and 1.5nm. In an embodiment, the deposition process of forming the metallic cap layer 315 includes sputter depositing the metallic cap layer 315 with an inert gas. In one embodiment, the inert gas includes a gas such as Ar, Kr and Xe. In an embodiment, the deposition process creates one or more conductive nano-channels 317 in the follower magnetic layer 313 and in the underlying cap oxide layer 311 and fills the one or more conductive nano-channels 317 with the material of the metallic cap layer 315. The creation of conductive nano-channels 317 is favorable for (a) lowering the resistance of the cap oxide layer 311 by providing an electrical conductive path and (b) providing a path for boron out diffusion from a free magnetic layer 309 that includes boron.

In an embodiment, the deposition of the metallic cap layer 315 damages portions of the follower magnetic layer 313 and also portions of the underlying cap oxide layer 311. If the damage sustained by the follower magnetic layer 313 and the underlying cap oxide layer 311 during the creation of the conductive nano-channels 317 becomes sufficiently high, a substantial loss in PMA can result. In an embodiment, a sputter gas or inert gas having a high Z such as Kr or Xe is used to deposit. When a gas having a higher atomic number (Z) such as Kr or Xe is used, during the sputter deposition process, to deposit the metallic cap layer 315, the sputtered material is found to lessen damage to the underlying follower magnetic layer 313 and to the underlying cap oxide layer 311. The use of a higher Z gas can reduce the effective kinetic energy of the deposition process resulting in a sputtered material that can favor the formation of conductive nano-channels 317 but prevent damage of the cap oxide layer 311.

In an embodiment, the process of sputter depositing with an inert gas implants trace amounts of the inert gas into the metallic cap layer 315. In an embodiment, the trace amounts of the inert gas in the metallic cap layer 315 has a concentration between 2 x 10²⁰ atoms/cm³ to 4 x 10²⁰ atoms/cm³. In an embodiment, trace amounts of the inert gas such as Kr and Xe can also be found in the conductive nano-channel.

In an embodiment, the conductive nano-channels 317 have physical characteristics that are substantially similar to conductive nano-channels 110 described in association with Figure 1 A. In an embodiment, at least one or more conductive nano-channels 317 extends all the way down to an uppermost surface of the free magnetic layer 309 and can provide a pathway for boron out-diffusion during a subsequent high temperature anneal process.

Figure 3D illustrates a cross-sectional view of the structure in Figure 3C following the formation of an etch stop layer 319 and a top electrode layer 321 to complete formation of a pSTTM material layer stack 350. In an embodiment, the etch stop layer 319 is blanket deposited on the metallic cap layer 315. The etch stop layer 319 is utilized during patterning of the top electrode layer 321 that will be formed in a subsequent operation. In an embodiment, the metallic cap layer 315 has a thickness that is 5-10 times greater than the thickness of the metallic cap. In an embodiment, the etch stop layer 319 is similar or substantially similar to the etch stop layer 260 described in association with Figure 2.

In an embodiment, the top electrode layer 321 is blanket deposited on the surface of the metallic cap layer 315. In an embodiment, the top electrode layer 321 includes a material suitable to act as a hardmask for etching pSTTM material layer stack 350 to form a pSTTM device. In an embodiment, a top electrode that will be subsequently formed will be electrically coupled to a bitline. In an embodiment, the top electrode layer 321 includes a material such as Ta. In an embodiment, the thickness of the top electrode layer 321 ranges from 30-70nm. The thickness is chosen to accommodate the various sizes of the pSTTM devices that will subsequently be fabricated as well as to provide etch resistivity during etching of the pSTTM material layer stack 350.

In an embodiment, after all the layers in the pSTTM material layer stack 350 are deposited, an anneal is performed under conditions well known in the art to promote solid phase epitaxy of the free magnetic layer 309 following a template of a crystalline layer of the tunnel barrier layer 307. A post-deposition anneal of the pSTTM material layer stack 350 is carried out in a furnace at a temperature between 300-500 degrees Celsius in a forming gas environment. In an embodiment, the anneal is performed immediately post deposition but before patterning of the pSTTM material layer stack 350 to enable a crystalline MgO-tunnel barrier layer 307 to be formed. The post-deposition anneal process also enables boron to diffuse away from an interface 323 between the tunnel barrier layer 307 and the free magnetic layer 309. The process of diffusing boron away from the interface 323 enables lattice matching between the free magnetic layer 309 and the tunnel barrier layer 307. In an embodiment, the process of boron out-diffusion enables an as-deposited amorphous free magnetic layer 309 including boron to form a (001) crystal structure by templating off of a (001) crystal structure of the tunnel barrier layer 307. In an embodiment, the boron out-diffusion from the free magnetic layer 309 is greatly enhanced by the presence of the conductive nano-channels 317. Enhanced boron out-diffusion can be observed by up to a 50% increase in TMR ratio, in a pSTTM material layer stack 350 having one or more conductive nano-channels 317 formed by sputter deposition of a metallic layer in the presence of an inert gas. In an embodiment, one or more conductive nano-channels 317 include trace amounts of boron after the anneal process.

In an embodiment, the annealing process is also performed in the presence of a magnetic field which sets the magnetization direction of the fixed magnetic layer 305 and the free magnetic layer 309. An applied magnetic field that is directed parallel to the vertical axis of the pSTTM material layer stack 350, during the annealing process, enables a perpendicular magnetic anisotropy to be set in the fixed magnetic layer 305 and in the free magnetic layer 309. The annealing process initially aligns the magnetization of the fixed magnetic layer 305 and the free magnetic layer 309 to be parallel to each other.

Figure 3E illustrates a cross-sectional view of the structure in Figure 3D following an etch process to pattern the top electrode layer 321 to form a top electrode 322. In an

embodiment, a layer photoresist (not shown) is formed above the top electrode layer 321. In an embodiment, the photoresist is patterned using well known lithographic processes known in the art. The lithography process defines the shape and size of a pSTTM device and a location where the pSTTM device is to be formed with respect the conductive interconnect 302. In an embodiment, the top electrode layer 321 is first patterned to form a top electrode 322 and the etch is stopped when an uppermost surface of the etch stop layer 319 is exposed. The photoresist is then removed.

Figure 3F illustrates a cross-sectional view of the structure in Figure 3E following an etch process to pattern the remaining layers in the pSTTM material layer stack 350 to form a pSTTM device 370. In an embodiment, a plasma etch process is utilized to etch the pSTTM material layer stack 350 and form the top electrode 322, a patterned etch stop layer 320, a metallic cap 316, a magnetic follower 314, cap oxide 312, a free magnet 310, a tunnel barrier 308, a fixed magnet 306 and a bottom electrode 304. In an embodiment, almost 30-50% of the as deposited top electrode layer 321 may be consumed during the complete etch process. In an embodiment, the plasma etch forms a pSTTM device 370 with a tapered profile (indicated by dashed lines 361). In an embodiment, the non-volatile etch residue extending from the fixed magnet 306 to the free magnet 310 may be conductive and can lead to electrical shorting between the fixed magnet 306 and the free magnet 310. In an embodiment, a second clean-up etch process is carried out to remove the etch residue from sidewalls of the tunnel barrier 308 to electrically isolate the free magnet 306 from the fixed magnet 310. It is to be appreciated that since the conductive nano-channels 317 are randomly located in the follower magnet 314, and in the cap oxide 312, after completion of patterning the pSTTM material layer stack 350, one or more conductive nano-channels 317A may be exposed on the periphery of the pSTTM device 370 as illustrated in Figure 3F.

Figure 3G illustrates a cross-sectional view of the pSTTM device 370 in Figure 3F following the formation of a dielectric spacer 380 on the sidewalls of the pSTTM material layer stack 350, and on an uppermost surface of the dielectric layer 301. In an embodiment, a dielectric spacer layer is deposited immediately following the plasma etch process utilized to form the pSTTM device 370. In an embodiment, the dielectric spacer layer is deposited immediately following the plasma etch process without breaking vacuum. In an embodiment, the dielectric spacer layer includes a material such as silicon nitride, silicon dioxide or carbon doped silicon nitride. In an embodiment, the dielectric spacer layer is chosen to exclude oxygen containing material to prevent oxidation of magnetic layers after the clean-up etch process. In an embodiment, the dielectric spacer layer is deposited at a process temperature of less than 300 degrees Celsius. In an embodiment, the dielectric spacer layer is deposited to a thickness between 10nm-20nm. In an embodiment, the dielectric spacer layer is etched by a plasma etch process to form a dielectric spacer 380 on sidewalls of the pSTTM device 370. In an embodiment, the etch process may cause an uppermost portion of the dielectric layer 301 to become partially recessed.

In an embodiment, a second anneal process can be performed after formation of the pSTTM device 370. In an embodiment, the second anneal process is carried out at a process temperature of at least 300 degrees Celsius but less than 400 degrees Celsius. In an embodiment, the post process anneal can help to recrystallize sidewalls of the tunnel barrier 308 that may have become potentially damaged during the etching process utilized to form the pSTTM device 370.

Figure 4 illustrates a cross-sectional view of a pSTTM device, such as the pSTTM device

370 formed on a conductive interconnect 302 coupled to an access transistor 408, in accordance with an embodiment. In an embodiment, the pSTTM device 370 includes the bottom electrode 304, the fixed magnet 306, the tunnel barrier 308 such as an MgO, the free magnet 310, the cap oxide 312, the follower magnet 314, the metallic cap 316, the etch stop 320 and the top electrode 322. The pSTTM device 370 includes conductive nano-channels 317 that extend from the metallic cap 316 through the follower magnet 314 and into the cap oxide 312. In an

embodiment, at least one or more conductive nano-channels 317 extend to an uppermost surface of the free magnet 310. In an embodiment, a pSTTM contact 426 is disposed on the top electrode 322. In an embodiment, the pSTTM device 370 has a width that is greater than the width of the conductive interconnect 302. In one such embodiment, a portion of the bottom electrode 304 of pSTTM device 370 is also disposed on a dielectric layer 403. In an

embodiment, the pSTTM device 370 has a width less than the width of the conductive interconnect 302. In an embodiment, the pSTTM device 370 has a width equal to the width of the conductive interconnect 302. In an embodiment, the conductive interconnect 302 is disposed on a contact structure 404 that is above and electrically coupled with a drain region 406 of an access transistor 408 disposed above a substrate 410.

In an embodiment, the underlying substrate 410 represents a surface used to manufacture integrated circuits. Suitable substrate 410 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate 410 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the access transistor 408 associated with substrate 410 are metal- oxide- semi conductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 410. In various implementations of the disclosure, the access transistor 408 may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, the access transistor 408 of substrate 410 includes a gate stack formed of at least two layers, a gate dielectric layer 414 and a gate electrode layer 412. The gate dielectric layer 414 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 414 to improve its quality when a high-k material is used.

The gate electrode layer 412 of the access transistor 408 of substrate 410 is formed on the gate dielectric layer 414 and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer 412 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode layer 412 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode layer 412 with a workfunction that is between about 4.9 eV and about 4.2 eV. For an NMOS transistor, metals that may be used for the gate electrode layer 412 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode layer 412 with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode layer 412 may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode layer 412 may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode layer 412 may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode layer 412 may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the disclosure, a pair of sidewall spacers 416 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 416 may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source region 418 and drain region 406 are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region 418 and drain region 406 are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region 418 and drain region 406. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region 418 and drain region 406. In some implementations, the source region 418 and drain region 406 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region 418 and drain region 406 may be formed using one or more alternate semiconductor materials such as germanium or a suitable group III-V compound. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region 418 and drain region 406.

In an embodiment, a gate contact 420 and a source contact 422 are formed in a second dielectric layer 424 and in the dielectric layer 403 above the gate electrode layer 412 and source region 418, respectively.

Figure 5 illustrates a computing device 500 in accordance with one embodiment of the disclosure. The computing device 500 houses a motherboard 502. The motherboard 502 may include a number of components, including but not limited to a processor 504 and at least one communication chip 506. The processor 504 is physically and electrically coupled to the motherboard 502. In some implementations the at least one communication chip 506 is also physically and electrically coupled to the motherboard 502. In further implementations, the communication chip 506 is part of the processsor 504.

Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to the motherboard 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 506 enables wireless communications for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more memory devices, such as an pSTTM device 370, fabricated using a pSTTM material layer stack 350 in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. In accordance with another implementation of an embodiment of the disclosure, the integrated circuit die of the communication chip includes pSTTM elements such as pSTTM device 370 integrated with access transistors, built in accordance with embodiments of the present disclosure.

In further implementations, another component housed within the computing device 500 may contain a stand-alone integrated circuit memory die that includes one or more memory elements such as pSTTM device 370, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 500 may be any other electronic device that processes data.

Figure 6 illustrates an integrated circuit (IC) structure 600 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 600 is an intervening structure used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 maybe, for instance, an integrated circuit die. The second substrate 604 maybe, for instance, a memory module, a computer mother, or another integrated circuit die. The memory module may include one or more memory devices such as a pSTTM device 100 or a pSTTM device 370. Generally, the purpose of an integrated circuit (IC) structure 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the integrated circuit (IC) structure 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the integrated circuit (IC) structure 600. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 600.

The integrated circuit (IC) structure 600 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 600 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a

semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure 600 may include metal interconnects 608 and via

610, including but not limited to through-silicon vias (TSVs) 610. The integrated circuit (IC) structure 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, pSTTM devices such as pSTTM devices 100 and 370, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 600. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein maybe used in the fabrication of integrated circuit (IC) structure 600.

Accordingly, one or more embodiments of the present disclosure relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present disclosure relate to the fabrication of a pSTTM device 370. A large array of consisting of pSTTM device 370 may be used in an embedded non-volatile memory application.

Thus, embodiments of the present disclosure include perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and high tunneling magnetoresi stance (TMR) ratio and methods to form the same.

Example 1 : A magnetic structure includes a magnetic layer disposed above a substrate, an oxide layer on the magnetic layer, a second magnetic layer on the oxide layer, a metallic cap layer on the second magnetic layer, and one or more conductive nano-channels extending from the metallic cap layer through the second magnetic layer into the oxide layer, wherein each of the one or more conductive nano-channels include the material of the metallic cap layer.

Example 2: The magnetic structure of example 1, wherein the metallic cap layer includes a metal selected from the group consisting of Hf, W and Ta.

Example 3 : The magnetic structure of example 1 or 2, wherein the metallic cap layer further includes a trace element selected from the group consisting of Kr and Xe.

Example 4: The magnetic structure of example 1, 2 or 3, wherein the trace element in the metallic cap layer has a concentration between 2 x 10²⁰ atoms/cm³ to 4 x 10²⁰ atoms/cm³.

Example 5: The magnetic structure of example 1, 2, 3, or 4, wherein the metallic cap has a thickness between 0.5nm and lnm.

Example 6: The magnetic structure of example 1, wherein each of the one or more conductive nano-channels have a maximum width between lnm and lOnm.

Example 7: The magnetic structure of example 1 or 6, wherein at least one of the one or more conductive nano-channels extends to an uppermost surface of the magnetic layer.

Example 8: The magnetic structure of example 1, 6 or 7, wherein the one or more conductive nano-channels includes boron.

Example 9: The magnetic structure of example 1 further includes an etch stop layer on the second magnetic layer and wherein the etch stop layer has a thickness that is between 5-10 times the thickness of the metallic cap.

Example 10: The magnetic structure of example 1, wherein the second magnetic layer has a thickness between 0. lnm and 0.3nm.

Example 11 : A memory device includes a fixed magnet disposed above a bottom electrode. A tunnel barrier layer is disposed on the fixed magnet. A free magnet is disposed on the tunnel barrier. An oxide layer is disposed on the free magnet. A follower magnet is disposed on the oxide layer. A metallic cap is disposed on the follower magnet, wherein the metallic cap includes a metal selected from the group consisting of Hf, W and Ta. One or more conductive nano-channels extend from the metallic cap through the free magnet and into the oxide layer, wherein each of the one or more conductive nano-channels include the material of the metallic cap. The memory device further includes a top electrode on the etch stop layer.

Example 12: The memory device of example 11, wherein the metallic cap layer further includes a trace element selected from the group consisting of Kr and Xe.

Example 13 : The memory device of example 11 or 12, wherein the trace element in the metallic cap layer has a concentration between 2 x 10²⁰ atoms/cm³ to 4 x 10²⁰ atoms/cm³.

Example 14: The memory device of example 11, wherein each of the one or more conductive nano-channels has a maximum width between lnm and lOnm.

Example 15: The memory device of example 11 or 14, wherein each of the one or more conductive nano-channels includes boron.

Example 16: The memory device of example 11, 14 or 15, wherein each of the one or more conductive nano-channels further extends to an uppermost surface of the free magnet.

Example 17: The memory device of example 11, wherein the follower magnet is between O. lnm and 0.3nm.

Example 18: The memory device of example 11, wherein the oxide layer has a thickness between 0.5nm and 0.8nm.

Example 19: A method of fabricating a memory device includes forming a material layer stack for the memory device. Forming the material layer stack includes forming a bottom electrode layer above a substrate, forming a magnetic layer disposed above the bottom electrode layer, forming an oxide layer on the magnetic layer, forming a second magnetic layer on the oxide layer, forming a second oxide layer on the magnetic layer, forming a follower magnetic layer on the second oxide layer and forming a metallic cap layer on the follower magnetic layer by a deposition process. Forming the metallic cap layer creates one or more conductive nano- channels in the follower magnetic layer and in the underlying second oxide layer and fills the one or more conductive nano-channels with the material of the metallic cap layer. The method further includes forming a top electrode on the metallic cap layer, and patterning the material layer stack to form a memory device.

Example 20: The method of example 19, wherein the deposition process of forming the metallic cap layer further includes sputter depositing the metallic cap layer with an inert gas to optimize the creation of the nano-channel, and wherein the process of sputter depositing with an inert gas implants trace amounts of the inert gas into the metallic cap layer.

Example 21 : The method of example 19, wherein the material layer stack is annealed at temperatures between 300-400 degrees Celsius, and wherein the anneal enables boron to diffuse from the second magnetic layer into the nano-channel.

Example 22: The method of example 19 or 21, wherein the diffusion of boron enables an as deposited amorphous second magnetic layer to form a (001) crystal structure by templating off of a (001) crystal structure of the oxide layer.

Example 23 : The method of example 19, wherein forming the material layer stack for the memory device further includes forming an etch stop layer on the metallic cap.

Example 24: The method of example 19 further includes depositing a dielectric spacer layer on the memory device and then etching the dielectric spacer layer to form a dielectric spacer adjacent to sidewalls of the memory device.

Claims

What is claimed is: 1. A magnetic structure comprising:

a magnetic layer above a substrate;

an oxide layer on the magnetic layer;

a second magnetic layer on the oxide layer;

a metallic cap layer on the second magnetic layer; and

one or more conductive nano-channels extending from the metallic cap layer through the second magnetic layer into the oxide layer, wherein each of the one or more conductive nano-channels comprise the material of the metallic cap layer.

2. The magnetic structure of claim 1, wherein the metallic cap layer comprises a metal selected from the group consisting of HE, W and Ta.

3. The magnetic structure of claim 2, wherein the metallic cap layer further includes a trace element selected from the group consisting of Kr and Xe.

4. The magnetic structure of claim 3, wherein the trace element in the metallic cap layer has a concentration between 2 x 10²⁰ atoms/cm³ to 4 x 10²⁰ atoms/cm³.

5. The magnetic structure of claim 1, wherein the metallic cap has a thickness between 0.5nm and lnm.

6. The magnetic structure of claim 1, wherein each of the one or more conductive nano-channels have a maximum width between lnm and lOnm.

7. The magnetic structure of claim 1, wherein at least one of the one or more conductive nano- channels extends to an uppermost surface of the magnetic layer.

8. The magnetic structure of claim 1, wherein the one or more conductive nano-channels comprises boron.

9. The magnetic structure of claim 1 further includes an etch stop layer on the second magnetic layer and wherein the etch stop layer has a thickness that is between 5-10 times the thickness of the metallic cap.

10. The magnetic structure of claim 1, wherein the second magnetic layer has a thickness between 0. lnm and 0.3nm.

11. A memory device, comprising:

a bottom electrode;

a fixed magnet above the bottom electrode;

a tunnel barrier layer on the fixed magnet;

a free magnet on the tunnel barrier;

an oxide layer on the free magnet;

a follower magnet on the oxide layer;

a metallic cap on the follower magnet, wherein the metallic cap comprises a metal selected from the group consisting of Hf, W and Ta;

one or more conductive nano-channels extending from the metallic cap through the free magnet and into the oxide layer, wherein each of the one or more conductive nano-channels comprise the material of the metallic cap; and

a top electrode on the etch stop layer.

12. The memory device of claim 11, wherein the metallic cap layer further includes a trace element selected from the group consisting of Kr and Xe.

13. The memory device of claim 11, wherein the trace element in the metallic cap layer has a concentration between 2 x 10²⁰ atoms/cm³ to 4 x 10²⁰ atoms/cm³.

14. The memory device of claim 11, wherein each of the one or more conductive nano-channels has a maximum width between lnm and lOnm.

15. The memory device of claim 11, wherein each of the one or more conductive nano-channels comprises boron.

16. The memory device of claim 11, wherein each of the one or more conductive nano-channels further extends to an uppermost surface of the free magnet.

17. The memory device of claim 11, wherein the follower magnet is between 0. Inm and 0.3nm.

18. The memory device of claim 11, wherein the oxide layer has a thickness between 0.5nm and 0.8nm.

19. A method of fabricating a memory device, the method comprising:

forming a material layer stack for the memory device, the forming comprising:

forming a bottom electrode layer above a substrate;

forming a magnetic layer above the bottom electrode layer;

forming an oxide layer on the magnetic layer;

forming a second magnetic layer on the oxide layer;

forming a second oxide layer on the magnetic layer;

forming a follower magnetic layer on the second oxide layer;

forming a metallic cap layer on the follower magnetic layer by a deposition process, wherein the deposition process creates one or more conductive nano-channels in the follower magnetic layer and in the underlying second oxide layer and fills the one or more conductive nano-channels with the material of the metallic cap layer;

forming a top electrode on the metallic cap layer; and

patterning the material layer stack to form a memory device.

20. The method of claim 19, wherein the deposition process of forming the metallic cap layer further includes sputter depositing the metallic cap layer with an inert gas to optimize the creation of the nano-channel, and wherein the process of sputter depositing with an inert gas implants trace amounts of the inert gas into the metallic cap layer.

21. The method of claim 19, wherein the material layer stack is annealed at temperatures between 300-400 degrees Celsius, and wherein the anneal enables boron to diffuse from the second magnetic layer into the nano-channel.

22. The method of claim 21, wherein the diffusion of boron enables an as deposited amorphous second magnetic layer to form a (001) crystal structure by templating off of a (001) crystal structure of the oxide layer.

23. The method of claim 19, wherein forming the material layer stack for the memory device further includes forming an etch stop layer on the metallic cap.

24. The method of claim 19 further includes depositing a dielectric spacer layer on the memory device and then etching the dielectric spacer layer to form a dielectric spacer adjacent to sidewalls of the memory device.