WO2019005089A1

WO2019005089A1 - Ferroelectric charge pump

Info

Publication number: WO2019005089A1
Application number: PCT/US2017/040184
Authority: WO
Inventors: Huichu Liu; Sasikanth Manipatruni; Ian A. Young; Tanay Karnik; Daniel H. MORRIS; Kaushik VAIDYANATHAN; Uygar E. Avci; Dmitri E. Nikonov
Original assignee: Intel Corporation
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2019-01-03

Abstract

There is disclosed in one example a charge pump, including: a clock signal; an inverse clock signal; a first ferroelectric capacitor; a second capacitor; and a charge pump circuit electrically located between the first ferroelectric capacitor and the second capacitor.

Description

FERROELECTRIC CHARGE PUMP

Field of the specification

[0001] This disclosure relates in general to the field of microelectronics, and more particularly, though not exclusively to, a system and method for providing a ferroelectric charge pump.

Background

[0002] Multiprocessor systems are becoming more and more common. In the modern world, compute resources play an ever more integrated role with human lives. As computers become increasingly ubiquitous, controlling everything from power grids to large industrial machines to personal computers to light bulbs, the demand for ever more capable processors increases.

Brief Description of the Drawings

[0003] The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not necessarily drawn to scale, and are used for illustration purposes only. Where a scale is shown, explicitly or implicitly, it provides only one illustrative example. In other embodiments, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0004] FIGURE 1 is a top view of a wafer and dies that may include a ferroelectric charge pump, in accordance with any of the embodiments disclosed herein.

[0005] FIGURE 2 is a cross-sectional side view of an IC device that may include a ferroelectric charge pump, in accordance with any of the embodiments disclosed herein.

[0006] FIGURE 3 is a cross-sectional side view of an IC package that may include a ferroelectric charge pump, in accordance with various embodiments.

[0007] FIGURE 4 is a cross-sectional side view of an IC device assembly that may include a ferroelectric charge pump, in accordance with any of the embodiments disclosed herein. [0008] FIGURE 5 is a block diagram of an example electrical device that may include a ferroelectric charge pump, in accordance with any of the embodiments disclosed herein.

[0009] FIGURE 6 is a block diagram of a ferroelectric capacitor according to one or more examples of the present specification.

[0010] FIGURE 7 is a graph of the capacitance as a function of the input voltage according to one or more examples of the present specification.

[0011] FIGURE 8 is a schematic diagram of a test circuit for a ferroelectric capacitor according to one or more examples of the present specification.

[0012] FIGURE 9 is an illustration of a Dickson charge pump according to one or more examples of the present specification.

[0013] FIGURE 10 is an example of a cross coupled CMOS charge pump according to one or more examples of the present specification.

[0014] FIGURE 11 is a schematic diagram of a ferroelectric charge pump according to one or more examples of the present specification .

[0015] FIGURE 12 is a graph of a ferroelectric charge pump according to one or more examples of the present specification.

[0016] FIGURE 13 is a comparative graph illustrating a simulated output of a three-stage CMOS Dickson charge pump according to one or more examples of the present specification.

[0017] FIGURE 14 is a graph showing the effect of coercive voltage of the ferroelectric capacitor on the operation of the circuit according to one or more examples of the present specification.

Embodiments of the Disclosure

[0018] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0019] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0020] Ferroelectric capacitors are a species of capacitor that use a ferroelectric material in the place of a dielectric material that would appear in a traditional capacitor. The charge of a ferroelectric material can be changed by applying an electric field to the ferroelectric material between the two plates of the capacitor.

[0021] First-generation ferroelectric materials include PbZr03, PbTi03, and similar. Second-generation ferroelectric materials include BiFe03, BaTi03, and similar. This specification also includes novel third-generation ferroelectric materials, such as materials made of or comprising hafnium zirconium oxide (HfZrO).

[0022] One feature of interest for a ferroelectric capacitor is that there are certain regions in which it operates with a negative capacitance. This means that in the negative capacitance region, as the charge on the ferroelectric material increases, rather than increasing the voltage across the plates, the voltage actually decreases. Outside of the negative capacitance region, the ferroelectric capacitor behaves as an ordinary capacitor, with an increase of voltage corresponding to an increase of charge.

[0023] This negative capacitance property of ferroelectric capacitors can be used to design novel circuits. For example, a charge pump is a species of DC to DC converter, which can either step up or step down a supply voltage in a circuit. Charge pumps are particularly useful in integrated circuits, wherein a smaller input voltage may need to be stepped up to a larger voltage for certain portions of the circuit. For example, one portion of a circuit may work with a half-volt supply, while another portion of the circuit may operate with a 1.5 V supply. Thus, it may be necessary to use a charge pump to step up the 0.5 V supply to a 1.5 V supply. In general, existing charge pumps may require a larger number of stages to realize larger voltage increases. Some known charge pumps include the Dickson charge pump, and a cross-coupled CMOS charge pump. Both of these charge pumps may require multiple stages to realize the voltage gains necessary in an integrated circuit. However, in integrated circuits, element density is at a premium, and reducing the number of elements used in the circuit helps to reduce the size and power consumption of the circuit, and thus enable greater focus on the operational logic that end-users are interested in.

[0024] In certain embodiments of the present specification, a novel ferroelectric charge pump is provided, in which two ferroelectric capacitors are used to form the charge pump, and to enable the production of a higher supply voltage.

[0025] In existing charge pumps, such as a CMOS charge pump, greater increases in DC step-up voltage may require additional stages. However, an embodiment of the present specification provides a ferroelectric charge pump built with two ferroelectric capacitors, which can provide operational voltage step ups with only two stages.

[0026] Thus, by reducing the number of stages required to provide the step-up voltages, the novel ferroelectric charge pump reduces the area consumed by the charge pump, and the number of elements needed to build it. This realizes advantages in semiconductor design, and in chip density.

[0027] A ferroelectric charge pump will now be described with more particular reference to the Attached FIGURES.

[0028] It should be noted that throughout the FIGURES, certain reference numerals may be repeated to indicate that a particular device or block is wholly or substantially consistent across the FIGURES. This is not, however, intended to imply any particular relationship between the various embodiments disclosed. In certain examples, a genus of elements may be referred to by a particular reference numeral ("widget 10"), while individual species or examples of the genus may be referred to by a hyphenated numeral ("first specific widget 10-1" and "second specific widget 10-2").

[0029] FIGURE 1 is a top view of a wafer 100 and dies 102 that may include one or more ferroelectric charge pumps, or may be included in an IC package whose substrate includes one or more ferroelectric charge pumps (e.g., as discussed below with reference to FIG. 3) in accordance with any of the embodiments disclosed herein. The wafer 100 may be composed of semiconductor material and may include one or more dies 102 having IC structures formed on a surface of the wafer 100. Each of the dies 102 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 100 may undergo a singulation process in which each of the dies 102 is separated from one another to provide discrete "chips" of the semiconductor product. The die 102 may include one or more ferroelectric charge pumps (e.g., as discussed below with reference to FIG. 2), one or more transistors (e.g., some of the transistors 240 of FIG. 2, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. . In some embodiments, the wafer 100 or the die 102 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AN D, OR, NAN D, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 102. For example, a memory array formed by multiple memory devices may be formed on a same die 102 as a processing device (e.g., the processing device 502 of FIG. 5) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0030] FIGURE 2 is a cross-sectional side view of an IC device 200 that may include one or more ferroelectric charge pumps, or may be included in an IC package whose substrate includes one or more ferroelectric charge pumps (e.g., as discussed below with reference to FIG. 3), in accordance with any of the embodiments disclosed herein. One or more of the IC devices 200 may be included in one or more dies 102 (FIG. 1). The IC device 200 may be formed on a substrate 202 (e.g., the wafer 100 of FIG. 1) and may be included in a die (e.g., the die 102 of FIG. 1). The substrate 202 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems (or a combination of both). The substrate 202 may include, for example, a crystalline substrate formed using a bulk silicon or an SOI substructure. In some embodiments, the substrate 202 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate 202. Although a few examples of materials from which the substrate 202 may be formed are described here, any material that may serve as a foundation for an IC device 200 may be used. The substrate 202 may be part of a singulated die (e.g., the dies 102 of FIG. 1) or a wafer (e.g., the wafer 100 of FIG. 1).

[0031] The IC device 200 may include one or more device layers 204 located on the substrate 202. The device layer 204 may include features of one or more transistors 240 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 202. The device layer 204 may include, for example, one or more source and/or drain (S/D) regions 220, a gate 222 to control current flow in the transistors 240 between the S/D regions 220, and one or more S/D contacts 224 to route electrical signals to/from the S/D regions 220. The transistors 240 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 240 are not limited to the type and configuration depicted in FIG. 2 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

[0032] Each transistor 240 may include a gate 222 formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0033] The gate electrode layer may be formed on the gate dielectric layer and may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 240 is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an N MOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0034] In some embodiments, when viewed as a cross-section of the transistor 240 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U- shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0035] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0036] The S/D regions 220 may be formed within the substrate 202 adjacent to the gate 222 of each transistor 240. The S/D regions 220 may be formed using either an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 202 to form the S/D regions 220. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 202 may follow the ion- implantation process. In the latter process, the substrate 202 may first be etched to form recesses at the locations of the S/D regions 220. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 220. In some implementations, the S/D regions 220 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 220 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 220.

[0037] In some embodiments, the device layer 204 may include one or more ferroelectric charge pumps, in addition to or instead of transistors 240. FIG. 2 illustrates a single ferroelectric charge pump in the device layer 204 for illustration purposes, but any number and structure of ferroelectric charge pumps may be included in a device layer 204. A ferroelectric charge pump included in a device layer 204 may be referred to as a "front end" device. In some embodiments, the IC device 200 may not include any front end ferroelectric charge pumps. One or more ferroelectric charge pumps in the device layer 204 may be coupled to any suitable other ones of the devices in the device layer 204, to any devices in the metallization stack 219 (discussed below), and/or to one or more of the conductive contacts 236 (discussed below). [0038] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 240 and/or ferroelectric charge pumps) of the device layer 204 through one or more interconnect layers located on the device layer 204 (illustrated in FIG. 2 as interconnect layers 206-210). For example, electrically conductive features of the device layer 204 (e.g., the gate 222 and the S/D contacts 224) may be electrically coupled with the interconnect structures 228 of the interconnect layers 206-210. The one or more interconnect layers 206-210 may form a metallization stack (also referred to as an "ILD stack") 219 of the IC device 200. In some embodiments, one or more ferroelectric charge pumps may be located in one or more of the interconnect layers 206-210, in accordance with any of the techniques disclosed herein. FIG. 2 illustrates a single ferroelectric charge pump in the interconnect layer 208 for illustration purposes, but any number and structure of ferroelectric charge pumps may be included in any one or more of the layers in a metallization stack 219. A ferroelectric charge pump included in the metallization stack 219 may be referred to as a "back-end" device. In some embodiments, the IC device 200 may not include any back-end ferroelectric charge pumps; in some embodiments, the IC device 200 may include both front- and back-end ferroelectric charge pumps. One or more ferroelectric charge pumps in the metallization stack 219 may be coupled to any suitable ones of the devices in the device layer 204, and/or to one or more of the conductive contacts 236 (discussed below).

[0039] The interconnect structures 228 may be arranged within the interconnect layers 206-210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 228 depicted in FIG. 2). Although a particular number of interconnect layers 206-210 is depicted in FIG. 2, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0040] In some embodiments, the interconnect structures 228 may include lines 228a and/or vias 228b filled with an electrically conductive material such as a metal . The lines 228a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 202 upon which the device layer 204 is formed. For example, the lines 228a may route electrical signals in a direction in and out of the page from the perspective of FIG. 2. The vias 228b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 202 upon which the device layer 204 is formed. In some embodiments, the vias 228b may electrically couple lines 228a of different interconnect layers 206-210 together.

[0041] The interconnect layers 206-210 may include a dielectric material 226 located between the interconnect structures 228, as shown in FIG. 2. In some embodiments, the dielectric material 226 located between the interconnect structures 228 in different ones of the interconnect layers 206-210 may have different compositions; in other embodiments, the composition of the dielectric material 226 between different interconnect layers 206-210 may be the same.

[0042] A first interconnect layer 206 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 204. In some embodiments, the first interconnect layer 206 may include lines 228a and/or vias 228b, as shown. The lines 228a of the first interconnect layer 206 may be coupled with contacts (e.g., the S/D contacts 224) of the device layer 204.

[0043] A second interconnect layer 208 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 206. In some embodiments, the second interconnect layer 208 may include vias 228b to couple the lines 228a of the second interconnect layer 208 with the lines 228a of the first interconnect layer 206. Although the lines 228a and the vias 228b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 208) for the sake of clarity, the lines 228a and the vias 228b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0044] A third interconnect layer 210 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 208 according to similar techniques and configurations described in connection with the second interconnect layer 208 or the first interconnect layer 206. In some embodiments, the interconnect layers that are "higher up" in the metallization stack 219 in the IC device 200 (i .e., further away from the device layer 204) may be thicker. [0045] The IC device 200 may include a solder resist material 234 (e.g., polyimide or similar material) and one or more conductive contacts 236 formed on the interconnect layers 206-210. In FIG. 2, the conductive contacts 236 are illustrated as taking the form of bond pads. The conductive contacts 236 may be electrically coupled with the interconnect structures 228 and configured to route the electrical signals of the transistor(s) 240 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 236 to mechanically and/or electrically couple a chip including the IC device 200 with another component (e.g., a circuit board). The IC device 200 may include additional or alternate structures to route the electrical signals from the interconnect layers 206-210; for example, the conductive contacts 236 may include other analogous features (e.g., posts) that route the electrical signals to external components.

[0046] FIGURE 3 is a cross-sectional view of an example IC package 350 that may include one or more ferroelectric charge pumps. The package substrate 352 may be formed of a dielectric material, and may have conductive pathways extending through the dielectric material between the face 372 and the face 374, or between different locations on the 372, and/or between different locations on the face 374. These conductive pathways may take the form of any of the interconnects 228 discussed above with reference to FIG. 2. FIG. 3 illustrates a single ferroelectric charge pump in the package substrate 352, but this number and location of ferroelectric charge pumps in the IC package 350 is simply illustrative, and any number of ferroelectric charge pumps (with any suitable structure) may be included in a package substrate 352. In some embodiments, no ferroelectric charge pumps may be included in the package substrate 352.

[0047] The IC package 350 may include a die 356 coupled to the package substrate 352 via conductive contacts 354 of the die 356, first-level interconnects 358, and conductive contacts 360 of the package substrate 352. The conductive contacts 360 may be coupled to conductive pathways 362 through the package substrate 352, allowing circuitry within the die 356 to electrically couple to various conductive contacts 364 and/or to the ferroelectric charge pumps (or to other devices included in the package substrate 352, not shown). The first-level interconnects 358 illustrated in FIG. 3 are solder bumps, but any suitable first-level interconnects 358 may be used. As used herein, a "conductive contact" may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0048] In some embodiments, an underfill material 366 may be located between the die 356 and the package substrate 352 around the first-level interconnects 358, and a mold compound 368 may be located around the die 356 and in contact with the package substrate 352. In some embodiments, the underfill material 366 may be the same as the mold compound 368. Example materials that may be used for the underfill material 366 and the mold compound 368 are epoxy mold materials, as suitable. Second-level interconnects 370 may be coupled to the conductive contacts 364. The second- level interconnects 370 illustrated in FIG. 3 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 370 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 370 may be used to couple the IC package 350 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 4.

[0049] In FIG. 3, the IC package 350 is a flip chip package, and includes a ferroelectric charge pump in the package substrate 352. The number and location of ferroelectric charge pumps in the package substrate 352 of the IC package 350 is simply illustrative, and any number of ferroelectric charge pumps (with any suitable structure) may be included in a package substrate 352. In some embodiments, no ferroelectric charge pumps may be included in the package substrate 352. The die 356 may take the form of any of the embodiments of the die 102 discussed herein (e.g., may include any of the embodiments of the IC device 200). In some embodiments, the die 356 may include one or more ferroelectric charge pumps (e.g., as discussed above with reference to FIG. 1 and FIG. 2); in other embodiments, the die 356 may not include any ferroelectric charge pumps.

[0050] Although the IC package 350 illustrated in FIG. 3 is a flip chip package, other package architectures may be used. For example, the IC package 350 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 350 may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die 356 is illustrated in the IC package 350 of FIG. 3, an IC package 350 may include multiple dies 356 (e.g., with one or more of the multiple dies 356 coupled to ferroelectric charge pumps included in the package substrate 352). An IC package 350 may include additional passive components, such as surface-mount resistors, capacitors, and inductors located on the first face 372 or the second face 374 of the package substrate 352. More generally, an IC package 350 may include any other active or passive components known in the art.

[0051] FIGURE 4 is a cross-sectional side view of an IC device assembly 400 that may include one or more IC packages or other electronic components (e.g., a die) including one or more ferroelectric charge pumps, in accordance with any of the embodiments disclosed herein. The IC device assembly 400 includes a number of components located on a circuit board 402 (which may be, e.g., a motherboard). The IC device assembly 400 includes components located on a first face 440 of the circuit board 402 and an opposing second face 442 of the circuit board 402; generally, components may be located on one or both faces 440 and 442. Any of the IC packages discussed below with reference to the IC device assembly 400 may take the form of any of the embodiments of the IC package discussed above with reference to FIG. 3 (e.g., may include one or more ferroelectric charge pumps in a package substrate or in a die ).

[0052] In some embodiments, the circuit board 402 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 402. In other embodiments, the circuit board 402 may be a non-PCB substrate.

[0053] The IC device assembly 400 illustrated in FIG. 4 includes a package-on-interposer structure 436 coupled to the first face 440 of the circuit board 402 by coupling components 416. The coupling components 416 may electrically and mechanically couple the package-on-interposer structure 436 to the circuit board 402, and may include solder balls (as shown in FIG. 4), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0054] The package-on-interposer structure 436 may include an IC package 420 coupled to an interposer 404 by coupling components 418. The coupling components 418 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 416. Although a single IC package 420 is shown in FIG. 4, multiple IC packages may be coupled to the interposer 404; indeed, additional interposers may be coupled to the interposer 404. The interposer 404 may provide an intervening substrate used to bridge the circuit board 402 and the IC package 420. The IC package 420 may be or include, for example, a die (the die 102 of FIG. 1), an IC device (e.g., the IC device 200 of FIG. 2), or any other suitable component. Generally, the interposer 404 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 404 may couple the IC package 420 (e.g., a die) to a set of BGA conductive contacts of the coupling components 416 for coupling to the circuit board 402. In the embodiment illustrated in FIG. 4, the IC package 420 and the circuit board 402 are attached to opposing sides of the interposer 404; in other embodiments, the IC package 420 and the circuit board 402 may be attached to a same side of the interposer 404. In some embodiments, three or more components may be interconnected by way of the interposer 404.

[0055] The interposer 404 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 404 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 404 may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 406. The interposer 404 may further include embedded devices 414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 404. The package-on-interposer structure 436 may take the form of any of the package-on-interposer structures known in the art. In some embodiments, the interposer 404 may include one or more ferroelectric charge pumps.

[0056] The IC device assembly 400 may include an IC package 424 coupled to the first face 440 of the circuit board 402 by coupling components 422. The coupling components 422 may take the form of any of the embodiments discussed above with reference to the coupling components 416, and the IC package 424 may take the form of any of the embodiments discussed above with reference to the IC package 420.

[0057] The IC device assembly 400 illustrated in FIG. 4 includes a package-on-package structure 434 coupled to the second face 442 of the circuit board 402 by coupling components 428. The package-on-package structure 434 may include an IC package 426 and an IC package 432 coupled together by coupling components 430 such that the IC package 426 is located between the circuit board 402 and the IC package 432. The coupling components 428 and 430 may take the form of any of the embodiments of the coupling components 416 discussed above, and the IC packages 426 and 432 may take the form of any of the embodiments of the IC package 420 discussed above. The package- on-package structure 434 may be configured in accordance with any of the package-on-package structures known in the art.

[0058] FIGURE 5 is a block diagram of an example electrical device 500 that may include one or more ferroelectric pumps, in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device 500 may include one or more of IC packages, IC devices 200, or dies 102 disclosed herein . A number of components are illustrated in FIG. 5 as included in the electrical device 500, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device 500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. [0059] Additionally, in various embodiments, the electrical device 500 may not include one or more of the components illustrated in FIG. 5, but the electrical device 500 may include interface circuitry for coupling to the one or more components. For example, the electrical device 500 may not include a display device 506, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 506 may be coupled. In another set of examples, the electrical device 500 may not include an audio input device 524 or an audio output device 508, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 524 or audio output device 508 may be coupled.

[0060] The electrical device 500 may include a processing device 502 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 502 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 500 may include a memory 504, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 504 may include memory that shares a die with the processing device 502. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0061] In some embodiments, the electrical device 500 may include a communication chip 512 (e.g., one or more communication chips). For example, the communication chip 512 may be configured for managing wireless communications for the transfer of data to and from the electrical device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium . The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0062] The communication chip 512 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long- Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 512 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 512 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 512 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 512 may operate in accordance with other wireless protocols in other embodiments. The electrical device 500 may include an antenna 522 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0063] In some embodiments, the communication chip 512 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 512 may include multiple communication chips. For instance, a first communication chip 512 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 512 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 512 may be dedicated to wireless communications, and a second communication chip 512 may be dedicated to wired communications.

[0064] The electrical device 500 may include battery/power circuitry 514. The battery/power circuitry 514 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 500 to an energy source separate from the electrical device 500 (e.g., AC line power).

[0065] The electrical device 500 may include a display device 506 (or corresponding interface circuitry, as discussed above). The display device 506 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0066] The electrical device 500 may include an audio output device 508 (or corresponding interface circuitry, as discussed above). The audio output device 508 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0067] The electrical device 500 may include an audio input device 524 (or corresponding interface circuitry, as discussed above). The audio input device 524 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0068] The electrical device 500 may include a GPS device 518 (or corresponding interface circuitry, as discussed above). The GPS device 518 may be in communication with a satellite-based system and may receive a location of the electrical device 500, as known in the art.

[0069] The electrical device 500 may include another output device 510 (or corresponding interface circuitry, as discussed above). Examples of the other output device 510 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0070] The electrical device 500 may include another input device 520 (or corresponding interface circuitry, as discussed above). Examples of the other input device 520 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0071] The electrical device 500 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 500 may be any other electronic device that processes data.

[0072] FIGURE 6 is a block diagram of a ferroelectric capacitor according to one or more examples of the present specification. In this example, ferroelectric capacitor 600 includes two terminals, namely terminal 604-1 and terminal 604-2, separated by a ferroelectric oxide material 602. It is the use of ferroelectric oxide material 602 that gives ferroelectric capacitor 600 its ferroelectric properties.

[0073] Circuit model 608 is a Landau-Khalatnikov (LK) model of the ferroelectric capacitor. When a voltage source drives a ferroelectric capacitor 600 connected to a load capacitance, the operating region of the ferroelectric capacitor is biased by the load capacitance. When the ferroelectric capacitor is biased in the negative capacitance region, such that there is a positive charge on the ferroelectric capacitor, while the voltage across the ferroelectric capacitor is negative, the voltage across the load capacitance can be higher than the input voltage because of the polarity change induced by the ferroelectric capacitor. This can provide a voltage amplification effect.

[0074] Circuit model 608 shows that ferroelectric capacitor 600 can be modeled as a steady state capacitance C0 = A^*e0/d, in parallel with a leakage resistance pO and a varyi ng capacitance that is a function of the charge (C_F(Q_F)), controlled by the in put voltage.

[0075] FIGURE 7 is a graph of the capacitance as a function of the input voltage according to one or more exam ples of the present specification . As can be seen in this figure, as a voltage is applied to the ferroelectric capacitor, there is defined a negative capacitance region 702, i n which the coercive voltage actually varies inversely with charge instead of di rectly with charge. Thus, as additional charge is applied i n this region, the negative voltage is developed between the plates of the capacitor. By operating the ferroelectric capacitor i n this negative capacitance region i n appropriate circumstances, certain desirable effects can be achieved .

[0076] FIGU RE 8 is a schematic diagram of a test ci rcu it for a ferroelectric capacitor 600 according to one or more examples of the present specification . In this case, a ferroelectric capacitor 600 is placed in series with a regular dielectric capacitor 802. Normally, when an input voltage 804 is applied, the im pedance of the two capacitors would create a voltage divider effect at the output. However, when ferroelectric capacitor 600 is operating in its negative capacitance region, rather than formi ng a voltage divider at V_out, the two serious capacitors i nstead form a voltage ampl ifier, with V_out actual ly bei ng larger than V_in .

[0077] FIGURES 9 - 10 are exam ples of existing charge pumps that do not use ferroelectric capacitors. FIGU RE 9 is an example of a Dickson charge pum p 900, while FIGU RE 10 discloses an example of a cross coupled CMOS charge pump 1000. As discussed above, these charge pum ps may be used to convert a small RDC analog voltage power source to a higher DC voltage or power source . Charge pum p 1000 of FIGU RE 10 is particularly popular i n integrated ci rcuits, because it is com patible with the CMOS manufacturi ng technologies to manufacture those circuits. In contrast, Dickson charge pu mp 900 of FIGU RE 9 may be based on diodes, and may be more popular i n discrete circuits. I n each case, a clock and clock bar i nput are provided with an input voltage, and the result is a V_out, which is a step-up DC version of the DC i nput voltage applied to the load resistance and capacitance.

[0078] As described above, to provide greater step-up to desi red operational voltages, these charge pum ps, and i n particular the popu lar CMOS charge pum p, may require m ulti ple stages to achieve operational voltage. [0079] FIGURE 11 is a schematic diagram of a ferroelectric charge pump 1100 according to one or more examples of the present specification. Ferroelectric charge pump 1100 is in many respects similar to Dickson charge pump 900 of FIGURE 9, but the capacitors of Dickson charge pump 900 are replaced here with ferroelectric capacitors 600-1 and 600-2. The surface area, profile, and material properties of ferroelectric capacitors 600 may be selected according to the needs of the application. In an example, ferroelectric capacitor 600-1 may be selected to have a relatively high coercive voltage (i.e., relative to ferroelectric capacitor 600-2), while ferroelectric capacitor 600-2 may be selected to have a relatively low coercive voltage (i .e., relative to ferroelectric capacitor 600-1). In one example, the circuit is biased so that ferroelectric capacitor 600-1 operates within its negative capacitance region at the operational parameters of the circuit, while ferroelectric capacitor operates within its positive capacitance region. As discussed above, this provides a voltage amplification rather than a voltage dividing effect. Also note that in some embodiments, at least one capacitor, such as capacitor 600-2, may be replaced with an ordinary dielectric capacitance.

[0080] By way of nonlimiting example, the dimensions of the capacitors may be as follows:

[0081] Capacitor 600-1 : Plate-to-plate distance = 25 nm, lateral area = 0.5 μηι X 0.5 μηι.

[0082] Capacitor 600-2 : Plate-to-plate distance = 2.5 nm, lateral area is 0.5 μηι x 0.05 μηι.

[0083] More generally, capacitor 600-1 may have a plate-to-plate distance of approximately 25 - 40 nm and a lateral area of approximately 0.25 - 0.40 μιη². Capacitor 600-2 may have a plate-to-plate distance of approximately 2.5 - 4.0 nm, and a lateral area of approximately 0.025 - 0.040 μιη²

[0084] As before, a clock and clock bar signal are provided in addition to the input voltage at node N l . The voltage is then stepped up, and the voltage applied at node 3 to the load resistance and capacitance is a stepped-up version of the input voltage.

[0085] FIGURE 12 is a graph of a ferroelectric charge pump according to one or more examples of the present specification. Illustrated are voltages at node 1 and node 2 of ferroelectric charge pump 1100 of FIGURE 11. This graph shows the relationship between node N l and node N2.

[0086] Charge pump 1100 of FIGURE 11 is a polarization charge-induced voltage amplification effect. In charge pump 1100, ferroelectric capacitors 600 are operating in the negative capacitance region. The ferroelectric material for ferroelectric capacitors 600 may be any suitable ferroelectric capacitor material, and in one particular example, may be a third-generation ferroelectric material such as HfZrO or a composite thereof.

[0087] Comparing charge pump 1100 to Dickson charge pump 900 of FIGURE 9, because capacitors in Dickson charge pump 900 have been replaced with ferroelectric capacitors 600, the first stage DC input is eliminated.

[0088] Ferroelectric capacitor 600-1 has a high coercive voltage and may be designed to operate in its negative capacitance region. In contrast, ferroelectric capacitor 600-2 may have a low coercive voltage and may be designed to operate in its normal capacitance region. To achieve high DC output voltage, capacitance matching between ferroelectric capacitor 600-1 and ferroelectric capacitor 600-2 is beneficial. Control of the coercive voltage may be obtained by controlling, for example, the thickness of the ferroelectric material, the chemical composition and doping of the ferroelectric material with equivalent but nonpolarizable elements, and the lateral size of the ferroelectric capacitors. Note that clock and clock B are low-voltage two-phase clock signals connected to the input of the circuits, while the output node derives a resistive load RL. CL may be used to smooth ripples in the DC output voltage.

[0089] FIGURE 13 is a comparative graph illustrating a simulated output of a three-stage CMOS Dickson charge pump, as in FIGURE 9, and the ferroelectric charge pump 1100 of FIGURE 11. Note that Dickson charge pump 900 of FIGURE 9 is a three-stage charge pump, while ferroelectric charge pump 1100 of FIGURE 11 is a two-stage charge pump. It can be seen here that not only does ferroelectric charge pump 1100 provide greater voltage amplification, but also that it has a much steeper ramp up time.

[0090] FIGURE 14 is a graph showing the effect of coercive voltage on the ferroelectric capacitor on the operation of the circuit. A higher output DC voltage may be achieved in the ferroelectric charge pump by increasing the coercive voltage of ferroelectric capacitor 600-1. [0091] Computer simulation results are used to compare the two-stage ferroelectric charge pump design of FIGURE 11 to the three-stage Dickson charge pump design of FIGURE 9. In this case, the transistor sizing for both designs was identical, namely 25 fins per transistor at 14 nanometers. In the case of Dickson charge pump 900, CI = C2 = C3 = CL = 10 femtofarads.

[0092] The value of C04 ferroelectric capacitor 600-1 is 10 femtofarads, and for ferroelectric capacitor 600-2 it is 5 femtofarads. In the experiment, clock and clock B have values of V_DD = 0.5V, = 500MHz. The DC input V_in was the same as the clock, namely V_DD = 0.5V.

[0093] In computer simulation, ferroelectric charge pump 1100 showed higher internal voltages (N l and N2 as seen in FIGURE 12), than Dickson charge pump 900 despite the lack of initial DC input voltage).

[0094] In theory, the ideal DC output voltage of an end-stage CMOS Dickson charge pump is: V_0UtiDC = V_in - V_th + N(V_DD - V_th) .

[0095] Thus, for an ideal, lossless charge pump, V_{0Ut DC} = 1.2 V at V_th = 0.2V with a three-stage Dickson charge pump with V_in = 0.5 V. The graphs of FIGURE 13 show three-stage CMOS Dickson charge pump 900 in graph 1302, and a two- stage ferroelectric charge pump 1100 on graph 1304.

[0096] These results are with an R_load = 10 M Q . An output DC voltage of V_0Ut = 3.3 V is achieved by two-stage ferroelectric charge pump 1100, while a Vout = I V is achieved for the three-stage CMOS Dickson charge pump 900. The number of stages that would be required for a Dickson charge pump to reach 3.3 V is greater than nine stages according to the above equation. Thus, ferroelectric charge pump 1100 realizes a voltage increase that could be realized in a CMOS Dickson charge pump only with nine or more stages.

[0097] FIGURE 14 illustrates the voltage characteristics of ferroelectric capacitor 600-1 with varying physical characteristics. The high coercive voltage of ferroelectric capacitor 600-1 ensures a wide-range negative capacitance region, while ferroelectric capacitor 600-2 operates as a regular capacitor. As illustrated in FIGURE 14, additional voltage increase can be realized with a higher coercive voltage, even without the need to add additional stages.

[0098] In an example, the coercive voltage curves are achieved by varying the area and distance as follows

a. 1402 : Distance = 20 nm, area = 0.2 μιη² b. 1404 : Distance = 25 nm, lateral area = 0.25 μηι² c. 1406 : Distance = 30 nm, lateral area = 0.3 μηι²

d. 1408 : Distance = 37nm, lateral area = 0.375 μηι²

[0099] The foregoing outlines features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein . Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0100] All or part of any hardware element disclosed herein may readily be provided in a system-on-a-chip (SoC), including central processing unit (CPU) package. An SoC represents an integrated circuit (IC) that integrates components of a computer or other electronic system into a single chip. Thus, for example, client devices or server devices may be provided, in whole or in part, in an SoC. The SoC may contain digital, analog, mixed-signal, and radio frequency functions, all of which may be provided on a single chip substrate. Other embodiments may include a multichip module (MCM), with a plurality of chips located within a single electronic package and configured to interact closely with each other through the electronic package.

[0101] Note also that in certain embodiments, some of the components may be omitted or consolidated. In a general sense, the arrangements depicted in the figures may be more logical in their representations, whereas a physical architecture may include various permutations, combinations, and/or hybrids of these elements. It is imperative to note that countless possible design configurations can be used to achieve the operational objectives outlined herein . Accordingly, the associated infrastructure has a myriad of substitute arrangements, design choices, device possibilities, hardware configurations, software implementations, and equipment options.

[0102] In one example embodiment, any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. Any suitable processor and memory can be suitably coupled to the board based on particular configuration needs, processing demands, and computing designs. Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated or reconfigured in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are within the broad scope of this specification.

[0103] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims. In order to assist the United States Patent and Trademark Office (USPTO) and, additionally, any readers of any patent issued on this application in interpreting the claims appended hereto, Applicant wishes to note that the Applicant: (a) does not intend any of the appended claims to invoke paragraph six (6) of 35 U.S.C. section 112 (pre-AIA) or paragraph (f) of the same section (post-AIA), as it exists on the date of the filing hereof unless the words "means for" or "steps for" are specifically used in the particular claims; and (b) does not intend, by any statement in the specification, to limit this disclosure in any way that is not otherwise expressly reflected in the appended claims.

Example Implementations

[0104] There is disclosed, in one example, a charge pump, comprising : a clock signal ; an inverse clock signal ; a first ferroelectric capacitor; a second capacitor; and a charge pump circuit electrically located between the first ferroelectric capacitor and the second capacitor.

[0105] There is further disclosed an example, wherein the charge pump circuit is a two-stage charge pump circuit.

[0106] There is further disclosed an example, wherein the first ferroelectric capacitor has plate-to-plate distance of approximately 25 nm. [0107] There is further disclosed an example, wherein the first ferroelectric capacitor has a plate-to-plate distance in a range of approximately 25nm - 40nm.

[0108] There is further disclosed an example, wherein the first ferroelectric capacitor has a lateral area of approximately 0.25 μηι².

[0109] There is further disclosed an example, wherein the first ferroelectric capacitor has a lateral area in a range of approximately 0.25 - 0.40 μηι².

[0110] There is further disclosed an example, wherein the second capacitor is a ferroelectric capacitor.

[0111] There is further disclosed an example, wherein the second ferroelectric capacitor has a lateral area in a range of 0.025 - 0.040 μηι².

[0112] There is further disclosed an example, wherein the first ferroelectric capacitor has a relatively high coercive voltage, and the second ferroelectric capacitor has a relatively low coercive voltage.

[0113] There is further disclosed an example, wherein the charge pump comprises a ferroelectric material of HfZrO.

[0114] There is further disclosed an example of an integrated circuit, comprising : a first logic device having a first supply voltage; a second logic device having a second logic supply voltage; and a charge pump to scale the first supply voltage to the second supply voltage, comprising : a clock signal ; an inverse clock signal; a first ferroelectric capacitor; a second capacitor; and a charge pump circuit electrically located between the first ferroelectric capacitor and the second capacitor.

[0115] There is further disclosed an example of a charge pump on an integrated circuit, wherein the charge pump circuit is a two-stage charge pump circuit.

[0116] There is further disclosed an example of a charge pump on an integrated circuit, wherein the first ferroelectric capacitor has a plate-to-plate distance in a range of approximately 25nm - 40nm.

[0117] There is further disclosed an example of a charge pump on an integrated circuit, wherein the first ferroelectric capacitor has a lateral area in a range of approximately 0.25 - 0.40 μηι².

[0118] There is further disclosed an example of a charge pump on an integrated circuit, comprising a ferroelectric material comprising HfZrO. [0119] There is further disclosed a method of manufacturing a charge pump, comprising : providing a clock signal; providing an inverse clock signal; depositing a first ferroelectric capacitor; depositing a second capacitor; and depositing a charge pump circuit electrically located between the first ferroelectric capacitor and the second ferroelectric capacitor.

[0120] There is further disclosed an example, wherein the charge pump is a two-stage charge pump circuit.

[0121] There is further disclosed an example, wherein the first ferroelectric capacitor has a plate-to-plate distance in a range of approximately 25 nm - 40nm.

[0122] There is further disclosed an example, wherein the first ferroelectric capacitor has a lateral area in a range of approximately 0.25 - 0.40 μηι².

[0123] There is further disclosed an example, wherein the charge pump comprises a ferroelectric material of HfZrO.

Claims

Claims What is claimed is:

1. A charge pump, comprising : a clock signal; an inverse clock signal; a first ferroelectric capacitor; a second capacitor; and a charge pump circuit electrically located between the first ferroelectric capacitor and the second capacitor.

2. The charge pump of claim 1, wherein the charge pump circuit is a two- stage charge pump circuit.

3. The charge pump of claim 1, wherein the first ferroelectric capacitor has a plate-to-plate distance of approximately 25 nm.

4. The charge pump of claim 1, wherein the first ferroelectric capacitor has a plate-to-plate distance in a range of approximately 25 nm - 40nm.

5. The charge pump of claim 1, wherein the first ferroelectric capacitor has a lateral area of approximately 0.25 μηι².

6. The charge pump of claim 1, wherein the first ferroelectric capacitor has a lateral area in a range of approximately 0.25 - 0.40 μηι².

7. The charge pump of any of claims 1 - 6, wherein the second capacitor is a ferroelectric capacitor.

8. The charge pump of claim 7, wherein the second ferroelectric capacitor has a lateral area in a range of 0.025 - 0.040 μηι².

9. The charge pump of claim 8, wherein the first ferroelectric capacitor has a relatively high coercive voltage, and the second ferroelectric capacitor has a relatively low coercive voltage.

10. The charge pump of claim 1, comprising a ferroelectric material comprising HfZrO.

11. An integrated circuit, comprising : a first logic device having a first supply voltage; a second logic device having a second supply voltage; and a charge pump to scale the first supply voltage to the second supply voltage, comprising : a clock signal, an inverse clock signal, a first ferroelectric capacitor, a second capacitor, and a charge pump circuit electrically located between the first ferroelectric capacitor and the second capacitor.

12. The integrated circuit of claim 11, wherein the charge pump circuit is a two-stage charge pump circuit.

13. The integrated circuit of claim 11, wherein the first ferroelectric capacitor has plate-to-plate distance of 25 nm.

14. The integrated circuit of claim 11, wherein the first ferroelectric capacitor has a plate-to-plate distance in a range of 25 nm - 40nm .

15. The integrated circuit of claim 11, wherein the first ferroelectric capacitor has a lateral area of 0.25 μηι².

16. The integrated circuit of claim 11, wherein the first ferroelectric capacitor has a lateral area in a range of 0.25 - 0.40 μηι².

17. The integrated circuit of claim 11, wherein the first ferroelectric capacitor has a plate-to-plate distance of 20 nm.

18. The integrated circuit of claim 11, wherein the first ferroelectric capacitor has a plate-to-plate distance of 30 nm.

19. The integrated circuit of claim 11, wherein the first ferroelectric capacitor has a plate-to-plate distance of 37 nm.

20. The integrated circuit of claim 17, comprising a ferroelectric material comprising HfZrO.

21. A method of manufacturing a charge pump, comprising : providing a clock signal; providing an inverse clock signal; depositing a first ferroelectric capacitor; depositing a second ferroelectric capacitor; and depositing a charge pump circuit electrically located between the first ferroelectric capacitor and the second ferroelectric capacitor.

22. The method of claim 21, wherein the charge pump is a two-stage charge pump circuit.

23. The method of claim 21, wherein the first ferroelectric capacitor has a plate-to-plate distance in a range of approximately 25 nm - 40nm.

24. The method of claim 21, wherein the first ferroelectric capacitor has a lateral area in a range of approximately 0.25 - 0.40 μιη².

25. The method of claim 21, wherein the charge pump comprises a

ferroelectric material comprising HfZrO.