WO2019000218A1

WO2019000218A1 - Adaptive settling time notification in voltage regulator

Info

Publication number: WO2019000218A1
Application number: PCT/CN2017/090302
Authority: WO
Inventors: Xiaoguo Liang; Meng Wang; Zhiming Li; Behzad Vafakhah; Alexander B. Uan-Zo-Li
Original assignee: Intel Corporation
Priority date: 2017-06-27
Filing date: 2017-06-27
Publication date: 2019-01-03

Abstract

An apparatus is provided which comprises: a first circuitry to generate an output voltage, and to drive the output voltage from a first voltage level to a second voltage level; and a second circuitry to generate a notification, in response to the output voltage settling within a range of the second voltage level.

Description

[Title established by the ISA under Rule 37.2] ADAPTIVE SETTLING TIME NOTIFICATION IN VOLTAGE REGULATOR

BACKGROUND

A component of a computing device, e.g., a processing core, may operate at different voltage levels. Merely as an example, in a low frequency mode, the processing core may operate at a relatively low voltage； and in a high frequency mode, the processing core may operate at a relatively high voltage.

A voltage regulator (VR) may output and regulate a voltage for such a processing core. In an example, when a VR is to change the output voltage from a first level to a second level (e.g., from a relatively low voltage value to a relatively high voltage value) , the voltage may take some time to settle down (e.g., such that transient variations of the voltage subsides) .

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Figs. 1A-1C illustrate three timing diagrams, where in each of the timing diagrams, a component has to wait for at least a pre-defined time period to use an output voltage of a voltage regulator (VR) , after a change in a voltage level of the output voltage.

Fig. 2A illustrates a system comprising a VR configured to adaptively output a status signal, wherein the status signal to indicate a state of an output voltage of the VR, according to some embodiments.

Fig. 2B illustrates the status generation circuitry of Fig. 2A in further details, according to some embodiments.

Fig. 3 illustrates a flowchart depicting a method for adaptively indicating a settling time of an output voltage of a VR, according to some embodiments.

Figs. 4A-4C illustrate three timing diagrams, where in the timing diagrams, a VR transmits a status signal to a component to adaptively indicate a settling time of an output voltage of the VR, according to some embodiments.

Fig. 5 illustrates another flowchart depicting a method for adaptively indicating a settling time of an output voltage of a VR, according to some embodiments.

Fig. 6 illustrates a computing device, where a VR may adaptively indicate a settling time of an output voltage to a component of the computing device, according to some embodiments.

DETAILED DESCRIPTION

Figs. 1A-1C illustrate three timing diagrams 100p, 100q, and 100r, respectively, where in each of the timing diagrams 100p, 100q, and 100r, a component has to wait for at least a pre-defined time period (Δt) to use an output voltage of a VR, e.g., after a change in the voltage level of the output voltage. The component and the VR are not illustrated in Figs. 1A-1C.

Referring to Figs. 1A-1C, a voltage level of the output voltage of the VR may be changed from voltage Va to voltage Vb. In an example, the VR may take some time to change the output voltage. For example, the change in the voltage level may start from times tp0, tq0, and tr0 in the timing diagrams 100p, 100q, and 100r, respectively. In the timing diagrams 100p, 100q, and 100r, at times tp1, tq1, and tr1, respectively, the output voltage of the VR may reach an acceptable voltage range (e.g., within, for example, 1.5％of the voltage Vb) .

In the timing diagram 100p, the output voltage of the VR may settle and remain within the acceptable voltage range from time tp1, where the acceptable voltage range may be, merely as an example, within ±1.5％of the voltage Vb. For example, by time tp2, the output voltage of the VR may settle to the voltage Vb. In the timing diagram 100p, the output voltage of the VR may not exhibit substantial overshoot or undershoot (e.g., may not exhibit substantial oscillation) .

In the timing diagram 100q, the output voltage of the VR may reach within the acceptable voltage range at time tq1, by then may go beyond the acceptable voltage due to an overshoot. In an example, by time tq2, the output voltage of the VR may settle down within the acceptable voltage range. In the timing diagram 100q, the output voltage of the VR may exhibit a cycle of overshoot. As a result, the time difference between tq1 and tq2 in the timing diagram 100q may be larger than the time difference between tp1 and tp2 in the timing diagram 100p.

In the timing diagram 100r, the output voltage of the VR may reach within the acceptable voltage range at time tr1, but then go out of the range twice due to an overshoot and an undershoot of the voltage. In an example, by time tr2, the output voltage of the VR may settle to the acceptable voltage range. In the timing diagram 100r, the output voltage of the VR may exhibit a cycle of overshoot, followed by a cycle of undershoot. As a result, the time difference between tr1 and tr2 in the timing diagram 100r may be larger than those in the timing diagrams 100p and 100q.

In some embodiments, the component receiving the output voltage of the VR may not be aware as to exactly when the output voltage settles to the voltage Vb, or settles within the acceptable range of voltage (e.g., the acceptable range of voltage may be substantially centered about the voltage Vb) . Accordingly, in some examples, the component may wait for a pre-defined time period Δt after the output voltage has reached the acceptable voltage range for the first time. Merely as an example, the pre-defined time period Δt may be about 5 microseconds.

For example, in the timing diagram 100p, the component may start receiving the output voltage from time tp3 for a different operation mode of the component (e.g., high frequency or high performance mode) , where the time tp3 occurs Δt time period after the time tp1. In another example, in the timing diagram 100q, the component may start receiving the output voltage from time tq3, where the time tq3 occurs Δt time period after the time tq1. In another example, in the timing diagram 100r, the component may start receiving the output voltage from time tr3, where the time tr3 occurs Δt time period after the time tr1.

Thus, in each of the timing diagrams 100p, 100q, and 100r, the component may start receiving the output voltage Δt time period after the output voltage has reached the acceptable voltage range, irrespective of how quickly (or how slowly) the output voltage may reach and remain within the acceptable voltage range. The pre-defined Δt time period may be sufficiently long to ensure that the output voltage of the VR definitely settles down and remains within the acceptable voltage range (e.g., even in a worst-case scenario of one or more oscillation cycles in the output voltage) . Put differently, the pre- defined Δt time period may have to be long enough to include a safety margin to accommodate a worst-case scenario of settling down of the output voltage. This, for example, results in a wastage of wait time (e.g., while the component is supposedly waiting for the output voltage to settle down) , e.g., even if there is very small or no oscillation at all in the output voltage of the VR (e.g., as illustrated in Fig. 1A) .

In some embodiments discussed herein, a voltage regulator may output an output voltage to a component. The voltage regulator may continually monitor the output voltage, e.g., when the output voltage is to undergo a change in its voltage level. For example, the voltage regulator may signal the component receiving the output voltage, e.g., when the output voltage sufficiently settles down within an acceptable voltage range. Put differently, a wait-time for the component receiving the output voltage may be adaptive. For example, when the output voltage settles down relatively quickly, the component may start using the output voltage relatively quickly, e.g., with a relatively short wait time (e.g., based on receiving a confirmation from the voltage regulator that the output voltage is ready to be used) . On the other hand, for example, if the output voltage settles down relatively slowly, the component may start using the output voltage after a relatively long wait time, e.g., once the output voltage settles down. Thus, the wait-time for the component may be based on an actual settling time of the output voltage, rather than a long and pre-defined wait time Δt of Figs. 1A-1C.

Various technical effects will be evident from the various embodiments and figures.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a, ” “an, ” and “the” include plural references. The meaning of “in” includes “in” and “on. ” The terms “substantially, ” “close, ” “approximately, ” “near, ” and “about, ” generally refer to being within +/-10％of a target value.

Unless otherwise specified the use of the ordinal adjectives “first, ” “second, ” and “third, ” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases “Aand/or B” and “Aor B” mean (A) , (B) , or (Aand B) . For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A) , (B) , (C) , (Aand B) , (Aand C) , (B and C) , or (A, B and C) . The terms “left, ” “right, ” “front, ” “back, ” “top, ” “bottom, ” “over, ” “under, ” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

Fig. 2A illustrates a system 200 comprising a VR 204 configured to adaptively output a status signal to indicate a state of an output voltage Vout 224 of the VR 204, according to some embodiments. In some embodiments, the output voltage Vout 224 of the VR 204 may be received by a component 208.

The component 208 may be any appropriate type of component, e.g., a processing core, a cache, a memory, a graphics unit, an input/output controller, and/or any other appropriate type of component of a computing device. The system 200 may be included in any appropriate computing device.

In some embodiments, the component 208 may generate and transmit a voltage control signal 228 (henceforth also referred to as signal 228) to the VR 204. The signal 228 may indicate a desired voltage level of the output voltage 224 that is to be generated by the VR 204. For example, the signal 228 may comprise a voltage identification (VID) signal indicating a desired voltage level of the output voltage Vout 224. In some embodiments, the component 208 may also transmit a clock signal 232 to the VR 204.

In some embodiments, the VR 204 may comprise a voltage generation circuitry 212 that may generate the output voltage Vout 224, e.g., based on the signal 228. The voltage generation circuitry 212 may comprise appropriate components and circuit elements to generate and/or regulate an output voltage in a voltage regulator. Merely as an example, the voltage generation circuitry 212 may operate as a buck–boost converter, a switching regulator, a buck regulator, a boost regulator, a DC-to-DC converter, an automatic voltage regulator, and/or the like.

In some embodiments, the VR 204 may further comprise a voltage monitoring circuitry 216 to monitor the output voltage Vout 224. The voltage monitoring circuitry 216 may, for example, measure the output voltage Vout 224. In some embodiments, the voltage monitoring circuitry 216 may be integrated with, or included in the voltage generation circuitry 212.

In some embodiments, the VR 204 may further comprise a status generation circuitry 220 that may generate a status signal 236. The VR 204 may transmit the status signal 236 to the component 208. In some embodiments, the status signal 236 may be generated based on the voltage monitoring circuitry 216 monitoring the output voltage Vout 224, as discussed in further details herein. The status signal 236 may notify the component 208 about the status of the output voltage Vout 224. The status signal 236 may also be referred to as a notification signal.

Fig. 2B illustrates the status generation circuitry 220 of Fig. 2A in further details, according to some embodiments. In some embodiments, the status generation circuitry 220 may comprise a comparator 254, which may receive a measurement of the output voltage 224. The comparator 254 may also receive a reference 250, which will be discussed in further details herein later. The comparator 254 may output a comparison to a generator circuitry to generate the status signal 236, which may be transmitted to the component 208. Although Fig. 2B illustrates an example implementation of the status generation circuitry 220, other example implementation of the status generation circuitry 220 may also be possible.

Fig. 3 illustrates a flowchart depicting a method 300 for adaptively indicating a settling time of an output voltage of a voltage regulator (e.g., VR 204) , according to some embodiments. Although the blocks in the flowchart with reference to Fig. 3 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 3 may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

The method 300 is discussed with respect to example timing diagrams 400a, 400b, and 400c of Figs. 4A-4C, respectively. Figs. 4A-4C illustrate three timing diagrams 400a, 400b, and 400c, respectively, where in each of the timing diagrams 400a, 400b, and 400c, the voltage regulator 204 transmits the status signal 236 to the component 208 to adaptively indicate a settling time of the output voltage Vout 224 of the VR 204, according to some embodiments. A section of the timing diagram 400c is magnified in Fig. 4C.

The timing diagrams 400a, 400b, and 400c illustrate variation of output voltage Vout 224 of the VR 204 with respect to time for three different scenarios. In each of these timing diagrams, the output voltage Vout 224 is increased from a voltage level Va to a voltage level Vb. In the timing diagram 400a, the output voltage Vout 224 undergoes least amount of oscillation, undershoot or overshoot. In the timing diagram 400b, the output voltage Vout 224 undergoes a cycle of voltage overshoot. In the timing diagram 400c, the output voltage Vout 224 undergoes a cycle of voltage overshoot, followed by a cycle of voltage undershoot.

In some embodiments, the voltage Va may correspond to a low frequency mode operation of the component 208, and the voltage Vb may correspond to a high frequency mode operation of the component 208. For example, when the component 208 is to operate at a relatively low frequency, the component 208 may operate at a lower voltage level (e.g., voltage Va) . On the other hand, when the component 208 is to operate at a relatively high frequency, the component 208 may operate at a higher voltage level (e.g., voltage Vb) . Thus, the VR 204 may drive the output voltage Vout 224 from voltage Va to Vb, from voltage Vb to Va, or from any appropriate voltage level to another appropriate voltage level. Such transition between different voltage levels may have to be performed frequently by the VR 204 (e.g., few times each second, or even tens of times or more each second) , e.g., based on a mode of operation of the component 208.

Referring again to Fig. 3, at 304, the VR 204 may receive a voltage control signal (e.g., the voltage control signal 228) from a component (e.g., component 208) . The voltage control signal may request a change in a voltage level of an output voltage, e.g., output voltage Vout 224 of the VR 204. For example, the voltage control signal 228 may request that the VR 204 drive the output voltage Vout 224 from voltage Va to voltage Vb.

At 308, the VR 204 (e.g., the voltage generation circuitry 212) may start changing the output voltage Vout 224 to the desired voltage level Vb. For example, in the timing diagrams 400a, 400b, and 400c, the VR 204 may start changing the output voltage Vout 224 from times ta0, tb0, and tc0, respectively.

At 312, the VR may continue adjusting the output voltage Vout 224 to reach and settle within a range of the desired voltage level. The range of the desired voltage level may be, for example, within ±M percentage of the desired voltage level. M may have a pre-defined value, and merely as an example, M may be 1.5％, 2％, 3％, or the like. In some embodiments, the range of the desired voltage level may also be referred to as a regulation band of the desired output voltage. In some embodiments, the range of the desired voltage level may be based on a voltage tolerance range of the component 208 (e.g., a variation of the output voltage Vout 224 which may be acceptable to the component 208) . In some embodiments, whether the output voltage Vout 224 has reach and settled within the range of the desired voltage level may be decided by the comparator 254 of Fig. 2B. For example, the reference 250 may be the desired voltage, or the range of the desired voltage level. The comparator 254 may compare the measurement of the output voltage 224 to determine whether the output voltage Vout 224 has reached and settled within the range of the desired voltage level. In some embodiments, the comparator 254 may be integrated within the voltage generation circuitry 212. In such embodiments, the voltage generation circuitry 212 and the status generation circuitry 220 may be at least in part combined.

The operations at block 312 of the method 300 is also illustrated in Figs. 4A-4C, where the output voltage Vout 224 may be continually adjusted to reach the voltage level Vb. Figs. 4A and 4B illustrate only the desired voltage level Vb for purposes of illustrative clarity, whereas the magnified section of Fig. 4C illustrate the range of the desired voltage level, where the range may be between voltages Vb1 and Vb2. In some embodiments, the voltage range of Vb1-Vb2 may be nearly or substantially centered about the desired voltage level Vb, as illustrated in Fig. 4C.

Referring again to Fig. 3, at 316 it may be determined if the output voltage Vout 224 has been continuously within the range of the desired output voltage for at least a threshold period of time. Such determination may be made by, for example, the comparator 254, another component of the status generation circuitry 220, the voltage generation circuitry 212, and/or the like. The threshold period of time may be pre-defined and may be denoted by Δts herein. In some embodiments, the determination at 316 may be performed by the status generation circuitry 220, e.g., based on the voltage monitoring circuitry 216 monitoring the output voltage Vout 224.

For example, referring to Fig. 4A, the output voltage Vout 224 may reach the range of the desired output voltage at time ta1, and may remain within the range of the desired output voltage thereafter. At time ta2, which may be Δts after the time ta1, the VR 204 may determine that the output voltage Vout 224 has been continuously within the range of the desired output voltage for at least the threshold period of time Δts.

In another example, in Fig. 4B, at time tb2, the VR 204 may determine that the output voltage Vout 224 has been continuously within the range of the desired output voltage for at least the threshold period of time Δts.

In another example and referring to the magnified portion in Fig. 4C, at time tc1, the output voltage Vout 224 may enter the range Vb1-Vb2 of the desired output voltage Vb. However, due to an overshoot, the output voltage Vout 224 may soon be outside the range (e.g., be outside the range before the threshold period of time Δts from time tc1) . At time tc1’ , the output Vout 224 may re-enter the range Vb1-Vb2 of the desired output voltage Vb. However, due to the undershoot or voltage drop, the output voltage Vout 224 may soon be outside the range again (e.g., be outside the range before the threshold period of time Δts from time tc1’ ) .

At time tc1” , the output Vout 224 may again re-enter the range Vb1-Vb2. This time, the output voltage Vout 224 may remain within the range for at least the threshold period of time Δts from time tc1” . For example, time tc2 may occur at least after the threshold period of time Δts from time tc1” , and the output voltage Vout 224 may be within the range between an entirety of the time tc1” and tc2. Accordingly, at time tc2, the VR 204 may determine that the output voltage Vout 224 has been continuously within the range of the desired output voltage for at least the threshold period of time Δts.

Referring again to Fig. 3, if “no” at block 316 (e.g., if the output voltage Vout 224 has not been continuously within the range of the desired output voltage for at least the threshold period of time Δts) , the method 300 may loop back to 312, where the VR 204 may continue adjusting the output voltage to settle within the range of the desired voltage level.

On the other hand, if “yes” at bock 316, the method 300 may proceed to 320, where the VR 204 (e.g., the generator circuitry 258 of the status generation circuitry 220) may change the status signal 236. For example, as illustrated in Figs. 4A, 4B, and 4C, the status signal 236 is toggled at times ta2, tb2, and tc2, respectively. In an example, the VR 204 may notify, via the status signal 236, that the output voltage Vout 224 has sufficiently settled (e.g., the transients in the output voltage Vout 224 has sufficiently died down) . Although the status signal 236 in these figures is illustrated to transition from low to high, any other appropriate change in the status signal 236 (e.g., change from high to low, a pulse, etc. ) may also be used at 320.

In some embodiments, a change in the status signal 236 may provide an indication or notification to the component 208 that the output voltage Vout 224 has sufficiently settled down (e.g., settled within the range of the desired output voltage) . Accordingly, based on detecting the change in the status signal 236, the component 208 may start receiving the output voltage Vout 224 and/or may start utilizing the output voltage Vout 224 for operations of the component 208. For example, if the desired voltage Vb is intended for a high frequency mode of the component 208, the component 208 may start operating at the high frequency mode once the component 208 detects the change in the status signal at 320, or is otherwise notified.

Fig. 5 illustrates another flowchart depicting a method 500 for adaptively indicating a settling time of an output voltage of a voltage regulator (e.g., VR 204) , according to some embodiments. Although the blocks in the flowchart with reference to Fig. 5 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 5 may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Some of the features of Fig. 5 may be discussed with respect to one or more of the timing diagrams 400a, 400b, and 400c of Figs. 4A-4C, respectively.

Referring to Fig. 5, at 504, the VR 204 may receive a voltage control signal (e.g., the voltage control signal 228) from a component (e.g., component 208) . The voltage control signal may request a change in a voltage level of an output voltage, e.g., output voltage Vout 224 of the VR 204. For example, the voltage control signal may request the output voltage Vout 224 be changed from voltage Va to voltage Vb, as discussed with respect to Figs. 4A-4C.

At 508, the VR 204 (e.g., the voltage generation circuitry 212) may start changing the output voltage Vout 224 to the desired voltage level. In an example, the desired voltage level may be the reference 250 of Fig. 2B. For example, in the timing diagrams 400a, 400b, and 400c, the VR 204 may start changing the output voltage Vout 224 from times ta0, tb0, and tc0, respectively.

At 512, the VR 204 may detect if there is a first overshoot of the output voltage Vout 224. For example, the voltage monitoring circuitry 216 may perform such a detection. If “yes” at 512, the method 500 may proceed to block 516； and if “no” at 512, the method 500 may proceed to block 528. In some embodiments, the detection at 512 (and also at subsequent blocks 516 to 528) may be performed in real-time or near real-time (e.g., without any substantial delay) .

At 516, the VR 204 (e.g., the voltage monitoring circuitry 216) may detect if there has been a first undershoot of the output voltage Vout 224. If “yes” at 516, the method 500 may proceed to block 520； and if “no” at 516, the method 500 may proceed to block 528. For example, in the timing diagram of 400b, there is a first overshoot, but no undershoot； while in the timing diagram of 400c, there is a first overshoot and a first undershoot.

At 520, the VR 204 (e.g., the voltage monitoring circuitry 216) may detect if there is a second overshoot of the output voltage Vout 224. If “yes” at 520, the method 500 may proceed to block 524； and if “no” at 520, the method 500 may proceed to block 528. At 524, the VR 204 (e.g., the voltage monitoring circuitry 216) may detect if there is a second undershoot of the output voltage Vout 224. The method 500 may then proceed to block 528.

Thus, in blocks 512 to 524, oscillations of the output voltage Vout 224 (e.g., overshoots and/or undershoots) may be monitored (e.g., in real-time or near real-time) by the VR 204. In some embodiments, such monitoring may be performed by the comparator 254, another appropriate component of the status generation circuitry 220, the voltage generation circuitry 212, and/or the like.

Although the method 500 refers to monitoring two cycles of overshoot and undershoot, more than two cycles of overshoot and undershoot may also be monitored. For example, a number of cycles to be monitored may be based on how fast the VR 204 may be able to settle down within a range of the desired output voltage, and may be a user configurable parameter. Occurrence of overshoot and/or undershoot may indicate that the output voltage Vout 224 is potentially still be in transition and have not settled down sufficiently yet –accordingly, the VR 204 may wait for the transient oscillations to die down and the output voltage Vout 224 to sufficiently settle down.

At 528 (e.g., once the transient overshoots and/or undershoots in the output voltage Vout 224 has sufficiently died down) , the VR 204 may detect if the output voltage Vout 224 is within a regulation band of the desired output voltage Vb. The regulation band may be an acceptable range of the desired output voltage Vb for the component 208. If the output voltage Vout 224 has not yet settled down within the regulation band (e.g., if “no” at 528) , the method 500 may loop back at 528, and the VR 204 may continually perform the detection operation at 528.

Once the output voltage Vout 224 has settled down within the regulation band (e.g., if “yes” at 528) , the method 500 may proceed to 532, where the VR 204 (e.g., the status generation circuitry 220) may change the status signal 236. For example, as illustrated in Figs. 4A, 4B, and 4C, the status signal 236 may be toggled at times ta2, tb2, and tc2, respectively. Although the status signal 236 in these figures is illustrated to transition from low to high, any other appropriate change in the status signal 236 (e.g., change from high to low, a pulse, etc. ) may also be used at 520.

In some embodiments, a change in the status signal 236 may provide an indication or notification to the component 208 that the output voltage Vout 224 has sufficiently settled down (e.g., settled within the range of the desired output voltage) . Accordingly, based on receiving the change in the status signal 236, the component 208 may start receiving the output voltage Vout 224 and/or may start utilizing the output voltage Vout 224 for operations of the component 208. For example, if the desired voltage Vb is intended for a high frequency mode of the component 208, the component 208 may start operating at the high frequency mode once the component 208 receives the indication of the change in the status signal at 532.

In Figs. 1A-1C, the component has to wait for a pre-defined period of time Δt, irrespective of how quickly (or how slowly) the VR output voltage settles to the desired output voltage. In contrast, in Figs. 4A-4C (e.g., using the methods 300 and/or 500) , the VR 204 may substantially decrease the wait time for the component 208. For example, the VR 204 may adaptively generate a change in the status signal 236, e.g., to notify the component 208 that the output voltage Vout 224 has settled down sufficiently.

For example, in Fig. 4A, the output voltage Vout 224 may settle down relatively quickly (e.g., compared to Figs. 4B-4C) , and the component 208 may start using the output voltage Vout 224 from time ta2, thereby leading to a very short wait time for the component 208. In another example, in Fig. 4C, the output voltage Vout 224 may settle down relatively slowly (e.g., compared to Figs. 4A-4B) , and the component 208 may start using the output voltage Vout 224 from time tc2. Thus, in Figs. 4A-4C, the component 208 may start using the output voltage Vout 224 almost as soon as the output voltage Vout 224 settles down within an acceptable range. This may result in a shorter wait time for the component 208, e.g., compared to the scenarios of Figs. 1A-1C (e.g., where in Figs. 1A-1C, the component had to wait for a pre-defined time, where the pre-defined time had a safety margin to accommodate a worst-case scenario of settling down of the output voltage) .

Although Figs. 4A-4C (and some of the discussion herein above with respect to Figs. 3 and 5) are associated with a transition of the output voltage Vout 224 from a relatively low voltage level to a relatively high voltage level (e.g., from Va to Vb) , the teachings of this disclosure may also be applied to a transition of the output voltage Vout 224 from a relatively high voltage level to a relatively low voltage level (e.g., from Vb to Va) . For example, during a transition of the output voltage Vout 224 from a relatively high voltage level to a relatively low voltage level, the output voltage Vout 224 may take some time to settle down within an acceptable voltage range of the desired low voltage level (e.g., due to transient undershoots and/or overshoots) , and the VR 204 may adaptively and dynamically notify the component 208 (e.g., via the status signal 236) when the output voltage Vout 224 settles down within the acceptable voltage range, e.g., as discussed throughout this disclosure.

Fig. 6 illustrates a computing device 2100 (e.g., a smart device, a computing device or a computer system or a SoC (System-on-Chip) ) , where a VR (e.g. VR 204 of Fig. 2A) may adaptively indicate a settling time of an output voltage to a component of the computing device 2100, according to some embodiments. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, the computing device 2100 represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an IOT device, a server, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 2100.

In some embodiments, computing device 2100 includes processors 2110. The various embodiments of the present disclosure may also comprise a network interface within 2170 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, processors 2110 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 2110 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 2100 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device 2100 includes audio subsystem 2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 2100, or connected to the computing device 2100. In one embodiment, a user interacts with the computing device 2100 by providing audio commands that are received and processed by processor 2110.

Display subsystem 2130 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 2100. Display subsystem 2130 includes display interface 2132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 2132 includes logic separate from processor 2110 to perform at least some processing related to the display. In one embodiment, display subsystem 2130 includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller 2140 represents hardware devices and software components related to interaction with a user. I/O controller 2140 is operable to manage hardware that is part of audio subsystem 2120 and/or display subsystem 2130. Additionally, I/O controller 2140 illustrates a connection point for additional devices that connect to computing device 2100 through which a user might interact with the system. For example, devices that can be attached to the computing device 2100 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller 2140 can interact with audio subsystem 2120 and/or display subsystem 2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 2100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 2130 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 2140. There can also be additional buttons or switches on the computing device 2100 to provide I/O functions managed by I/O controller 2140.

In one embodiment, I/O controller 2140 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 2100. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features) .

In one embodiment, computing device 2100 includes power management 2150 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 2160 includes memory devices for storing information in computing device 2100. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 2160 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 2100.

Elements of embodiments are also provided as a machine-readable medium (e.g., memory 2160) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein) . The machine-readable medium (e.g., memory 2160) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM) , or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection) .

Connectivity 2170 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 2100 to communicate with external devices. The computing device 2100 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity 2170 can include multiple different types of connectivity. To generalize, the computing device 2100 is illustrated with cellular connectivity 2172 and wireless connectivity 2174. Cellular connectivity 2172 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 2174 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc. ) , local area networks (such as Wi-Fi) , and/or wide area networks (such as WiMax) , or other wireless communication.

Peripheral connections 2180 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 2100 could both be a peripheral device ( "to" 2182) to other computing devices, as well as have peripheral devices ( "from" 2 184) connected to it. The computing device 2100 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 2100. Additionally, a docking connector can allow computing device 2100 to connect to certain peripherals that allow the computing device 2100 to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 2100 can make peripheral connections 2180 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces) , DisplayPort including MiniDisplayPort (MDP) , High Definition Multimedia Interface (HDMI) , Firewire, or other types.

In some embodiments, the computing device 2100 may comprise the VR 204 of Fig. 2A. The component 208 of Fig. 2A may be any one or more appropriate components of the computing device 2100, e.g., the processor 2110, a memory of the memory subsystem 2160, the I/O controller 2140, and/or the like. In some embodiments, the VR 204 may output the output voltage Vout 224, and may also output the status signal 236 to indicate when the output voltage Vout 224 settles down within an acceptable range during a change in the voltage level of the output voltage Vout 224.

Reference in the specification to "an embodiment, " "one embodiment, " "some embodiments, " or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment, " "one embodiment, " or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may, " "might, " or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art) . Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The following clauses pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

Clause 1. An apparatus comprising: a first circuitry to generate an output voltage, and to drive the output voltage from a first voltage level to a second voltage level； and a second circuitry to generate a notification, in response to the output voltage settling within a range of the second voltage level.

Clause 2. The apparatus of clause 1, wherein the second circuitry is to generate the notification, in response to: the output voltage reaching the range of the second voltage level； and the output voltage continuously remaining within the range of the second voltage level for at least a threshold period of time.

Clause 3. The apparatus of clause 1, further comprising: a voltage monitoring circuitry to monitor the output voltage, wherein the second circuitry is to generate the notification, in response to the voltage monitoring circuitry indicating that the output voltage has settled within the range of the second voltage level.

Clause 4. The apparatus of any of clauses 1-3, further comprising: a component to receive the output voltage from the first circuitry, wherein the component is to receive the notification from the second circuitry.

Clause 5. The apparatus of clause 4, wherein the component is a processing core.

Clause 6. The apparatus of clause 4, wherein: the first voltage level is lower than the second voltage level； the component is to receive the output voltage at the first voltage level during a low frequency operation of the component； and the component is to operate in a high frequency state, in response to receiving the notification.

Clause 7. The apparatus of any of clauses 1-3, wherein the second circuitry is to provide the notification via a change in a status signal.

Clause 8. The apparatus of any of clauses 1-3, further comprising: a voltage regulator including the first circuitry and the second circuitry.

Clause 9. A system comprising: a memory to store instructions； a processor couple to the memory； a voltage regulator to supply an output voltage to the processor, wherein the voltage regulator is to: initiate a change in the output voltage from a first voltage level to a second voltage level, and transmit a notification to the processor to notify that the output voltage has settled within a threshold range of the second voltage level； and a wireless interface to allow the processor to communicate with another device.

Clause 10. The system of clause 9, wherein: the voltage regulator is to monitor for potential overshoots and undershoots in the output voltage, while the output voltage is to be changed from the first voltage level to the second voltage level.

Clause 11. The system of clause 9, wherein: the voltage regulator is to monitor the output voltage, while the output voltage is to be changed from the first voltage level to the second voltage level.

Clause 12. The system of any of clauses 9-11, wherein: the processor is to request the voltage regulator to change the output voltage from the first voltage level to the second voltage level.

Clause 13. The system of any of clauses 9-11, wherein the voltage regulator is to: monitor for potential overshoots and undershoots in the output voltage； fail to detect any overshoot and undershoot in the output voltage； detect that the output voltage is within the threshold range； and transmit the notification to the processor, in response to the failure to detect any overshoot and undershoot in the output voltage and in response to the detection that the output voltage is within the threshold range.

Clause 14. The system of any of clauses 9-11, wherein the voltage regulator is to: determine that the output voltage is within the threshold range for at least a threshold period of time, wherein the threshold range is substantially centered around the second voltage level, and transmit the notification, in response to the determination that the output voltage is within the threshold range for at least the threshold period of time.

Clause 15. The system of any of clauses 9-11, wherein: the first voltage level is lower than the second voltage level； the processor is to receive the output voltage at the first voltage level during a low frequency operation of the processor； and the processor is to receive the output voltage at the second voltage level subsequent to the notification and during a high frequency operation of the processor.

Clause 16. The system of any of clauses 9-11, wherein: the processor is to receive and utilize the output voltage from the voltage regulator, in response to receiving the notification.

Clause 17. A computer implemented method comprising: generating an output voltage； transitioning the output voltage from a low voltage level to a high voltage level； determining that the output voltage has reached within a band of the high voltage level and has remained within the band for at least a threshold period of time； and issuing a notification, in response to the determining.

Clause 18. The method of clause 17, further comprising: monitoring the output voltage while the output voltage is transitioning from the low voltage level to the high voltage level.

Clause 19. The method of clause 17, further comprising: operating, by a component receiving the output voltage, at a high frequency mode of operation, in response to receiving the notification.

Clause 20. The method of clause 17, further comprising: monitoring potential overshoots and potential undershoots in the output voltage, while the output voltage is transitioning from the low voltage level to the high voltage level.

Clause 21. The method of any of clauses 17-20, wherein issuing the notification comprises: issuing the notification by changing a status signal.

Clause 22. One or more non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to execute a method of any of the clauses 17-21.

Clause 23. An apparatus comprising: means for performing the method of any of the clauses 17-21.

Clause 24. One or more non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to perform operations comprising: generate an output voltage； transition the output voltage from a low voltage level to a high voltage level； determine that the output voltage has reached within a band of the high voltage level and has remained within the band for at least a threshold period of time； and issue a notification, in response to the determining.

Clause 25. The one or more non-transitory computer-readable storage media of clause 24, wherein the instructions cause the processor to perform operations comprising: monitor the output voltage while the output voltage is transitioning from the low voltage level to the high voltage level.

Clause 26. The one or more non-transitory computer-readable storage media of clause 24, wherein the instructions cause the processor to perform operations comprising: monitor potential overshoots and potential undershoots in the output voltage, while the output voltage is transitioning from the low voltage level to the high voltage level.

Clause 27. The one or more non-transitory computer-readable storage media of any of clauses 24-26, wherein the instructions cause the processor to perform operations comprising: operate a component receiving the output voltage at a high frequency mode of operation, in response to receiving the notification.

Clause 28. An apparatus comprising: means for generating an output voltage； means for transitioning the output voltage from a low voltage level to a high voltage level； means for determining that the output voltage has reached within a band of the high voltage level and has remained within the band for at least a threshold period of time； and means for issuing a notification, in response to the determining.

Clause 29. The apparatus of clause 28, further comprising: means for monitoring the output voltage while the output voltage is transitioning from the low voltage level to the high voltage level.

Clause 30. The apparatus of clause 28, further comprising: means for operating a component, which receives the output voltage, at a high frequency mode of operation, in response to receiving the notification.

Clause 31. The apparatus of clause 28, further comprising: means for monitoring potential overshoots and potential undershoots in the output voltage, while the output voltage is transitioning from the low voltage level to the high voltage level.

Clause 32. The apparatus of any of clauses 28-31, wherein the means for issuing the notification comprises: means for issuing the notification by changing a status signal.

An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

An apparatus comprising:

a first circuitry to generate an output voltage, and to drive the output voltage from a first voltage level to a second voltage level； and

a second circuitry to generate a notification, in response to the output voltage settling within a range of the second voltage level.
The apparatus of claim 1, wherein the second circuitry is to generate the notification, in response to:

the output voltage reaching the range of the second voltage level； and

the output voltage continuously remaining within the range of the second voltage level for at least a threshold period of time.
The apparatus of claim 1, further comprising:

a voltage monitoring circuitry to monitor the output voltage,

wherein the second circuitry is to generate the notification, in response to the voltage monitoring circuitry indicating that the output voltage has settled within the range of the second voltage level.
The apparatus of any of claims 1-3, further comprising:

a component to receive the output voltage from the first circuitry,

wherein the component is to receive the notification from the second circuitry.
The apparatus of claim 4, wherein the component is a processing core.
The apparatus of claim 4, wherein:

the first voltage level is lower than the second voltage level；

the component is to receive the output voltage at the first voltage level during a low frequency operation of the component； and

the component is to operate in a high frequency state, in response to receiving the notification.
The apparatus of any of claims 1-3, wherein the second circuitry is to provide the notification via a change in a status signal.
The apparatus of any of claims 1-3, further comprising:

a voltage regulator including the first circuitry and the second circuitry.
A system comprising:

a memory to store instructions；

a processor couple to the memory；

a voltage regulator to supply an output voltage to the processor,

wherein the voltage regulator is to:

initiate a change in the output voltage from a first voltage level to a second voltage level, and

transmit a notification to the processor to notify that the output voltage has settled within a threshold range of the second voltage level； and

a wireless interface to allow the processor to communicate with another device.
The system of claim 9, wherein:

the voltage regulator is to monitor for potential overshoots and undershoots in the output voltage, while the output voltage is to be changed from the first voltage level to the second voltage level.
The system of claim 9, wherein:

the voltage regulator is to monitor the output voltage, while the output voltage is to be changed from the first voltage level to the second voltage level.
The system of any of claims 9-11, wherein:

the processor is to request the voltage regulator to change the output voltage from the first voltage level to the second voltage level.
The system of any of claims 9-11, wherein the voltage regulator is to:

monitor for potential overshoots and undershoots in the output voltage；

fail to detect any overshoot and undershoot in the output voltage；

detect that the output voltage is within the threshold range； and

transmit the notification to the processor, in response to the failure to detect any overshoot and undershoot in the output voltage and in response to the detection that the output voltage is within the threshold range.
The system of any of claims 9-11, wherein the voltage regulator is to:

determine that the output voltage is within the threshold range for at least a threshold period of time, wherein the threshold range is substantially centered around the second voltage level, and

transmit the notification, in response to the determination that the output voltage is within the threshold range for at least the threshold period of time.
The system of any of claims 9-11, wherein:

the first voltage level is lower than the second voltage level；

the processor is to receive the output voltage at the first voltage level during a low frequency operation of the processor； and

the processor is to receive the output voltage at the second voltage level subsequent to the notification and during a high frequency operation of the processor.
The system of any of claims 9-11, wherein:

the processor is to receive and utilize the output voltage from the voltage regulator, in response to receiving the notification.
A computer implemented method comprising:

generating an output voltage；

transitioning the output voltage from a low voltage level to a high voltage level；

determining that the output voltage has reached within a band of the high voltage level and has remained within the band for at least a threshold period of time； and

issuing a notification, in response to the determining.
The method of claim 17, further comprising:

monitoring the output voltage while the output voltage is transitioning from the low voltage level to the high voltage level.
The method of claim 17, further comprising:

operating, by a component receiving the output voltage, at a high frequency mode of operation, in response to receiving the notification.
The method of claim 17, further comprising:

monitoring potential overshoots and potential undershoots in the output voltage, while the output voltage is transitioning from the low voltage level to the high voltage level.
The method of any of claims 17-20, wherein issuing the notification comprises:

issuing the notification by changing a status signal.
One or more non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to perform operations comprising:

generate an output voltage；

transition the output voltage from a low voltage level to a high voltage level；

determine that the output voltage has reached within a band of the high voltage level and has remained within the band for at least a threshold period of time； and

issue a notification, in response to the determining.
The one or more non-transitory computer-readable storage media of claim 22, wherein the instructions cause the processor to perform operations comprising:

monitor the output voltage while the output voltage is transitioning from the low voltage level to the high voltage level.
The one or more non-transitory computer-readable storage media of claim 22, wherein the instructions cause the processor to perform operations comprising:

monitor potential overshoots and potential undershoots in the output voltage, while the output voltage is transitioning from the low voltage level to the high voltage level.
The one or more non-transitory computer-readable storage media of any of claims 22-24, wherein the instructions cause the processor to perform operations comprising:

operate a component receiving the output voltage at a high frequency mode of operation, in response to receiving the notification.