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WO2019087809A1 - A/d converter - Google Patents

A/d converter Download PDF

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Publication number
WO2019087809A1
WO2019087809A1 PCT/JP2018/038902 JP2018038902W WO2019087809A1 WO 2019087809 A1 WO2019087809 A1 WO 2019087809A1 JP 2018038902 W JP2018038902 W JP 2018038902W WO 2019087809 A1 WO2019087809 A1 WO 2019087809A1
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Prior art keywords
filter
output
data
quantizer
converter
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PCT/JP2018/038902
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French (fr)
Japanese (ja)
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恭英 高▲瀬▼
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株式会社村田製作所
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Publication of WO2019087809A1 publication Critical patent/WO2019087809A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/02—Delta modulation, i.e. one-bit differential modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation

Definitions

  • the present invention relates to an A / D converter that quantizes a difference between an analog input signal and a predicted value output from a prediction filter with a quantizer to convert the analog input signal into a digital signal.
  • the A / D converter comprises a resistor, a continuous time filter, a summing circuit, a quantizer, a continuous time DAC, a delay element, a discrete time DAC, and a switch.
  • a continuous time filter receives the analog input signal and the feedback signal from the switch.
  • the feedback signal is a signal from one feedback path including a discrete time DAC and a delay element used when the clock signal has a relatively large jitter due to switch switching, and a high quality clock signal with a relatively small amount of jitter.
  • the signal from the other feedback path, including the continuous time DAC which requires
  • the continuous time filter is implemented as an Nth-order integrator and provides multiple feed forward path outputs to multiple inputs of the summing circuit.
  • Each of the plurality of inputs of the summing circuit includes a gain element.
  • the quantizer has an input terminal connected to the output terminal of the summing circuit and a plurality of output terminals, and generates a quantized discrete multi-bit output based on the input received from the summing circuit.
  • the decimation filter has a plurality of input terminals connected to a plurality of output terminals of the quantizer and a plurality of output terminals for providing a plurality of digital output bits. This decimation filter is coupled to the multi-bit output of the quantizer and is used to lower the data frequency, remove additional noise, and increase the resolution of the output.
  • the above-described conventional A / D converter has a multi-bit quantizer, as described above, it is necessary to process multi-bit data at a high oversampling frequency in the decimation filter. Therefore, the above-described conventional A / D converter has a problem that power consumption is increased.
  • An adder for calculating a difference between an analog input signal and a predicted value, a quantizer for quantizing a difference output from the adder, and a prediction filter for generating a predicted value from a signal output from the quantizer.
  • An A / D converter comprising: a decimation filter for limiting the frequency band of an A / D conversion output which is converted into a digital signal and output an analog input signal input to an adder and outputting the digital signal;
  • a decimation filter is connected to the output of the quantizer,
  • the present invention is characterized by comprising a compensation filter that compensates for frequency characteristics of output data at the output side of the decimation filter.
  • the short word length and high frequency data output from the quantizer are output to the decimation filter, and the decimation filter first performs frequency band limitation for the short word length and high frequency data and Data frequency reduction processing is performed. Then, at the output side of the decimation filter, the frequency characteristic of the output data is compensated by the compensation filter at the low-speed data frequency reduced by the decimation filter. For this reason, the power consumption of the A / D converter is reduced in the decimation filter as compared to the conventional processing of multi-bit data at a high oversampling frequency.
  • the prediction filter uses the predicted value of the digital value before analog conversion to be fed back to the adder by the prediction filter as the A / D converted output of the analog input signal inputted to the adder.
  • a decimation filter is connected to the output of the prediction filter to limit the frequency band of the A / D conversion output and to lower the data frequency. For this reason, in the decimation filter, data processing is performed on data having a word length longer than that of data output from the quantizer at the same high data frequency as that of the quantizer, and power consumption increases.
  • the decimation filter is connected to the output of the quantizer, and the decimation filter performs frequency band limitation and data frequency reduction on data having a word length shorter than that of the prediction filter. Then, at the output side of the decimation filter, the frequency characteristic of the output data is compensated by the compensation filter at the low-speed data frequency reduced by the decimation filter. Therefore, the data processed by the decimation filter is quantized with a word length shorter than that of the data output from the prediction filter, as compared with the case where the prediction value output from the prediction filter is subjected to the decimation filter as an A / D conversion output. Power consumption of the A / D converter.
  • the decimation filter is A first decimation filter connected to the output of the quantizer to reduce the data frequency to an intermediate data frequency lower than the data frequency of the quantizer and higher than the data frequency of the A / D conversion output; Characterized in that it is divided into a second decimation filter connected to the output of the compensation filter and further reducing the data frequency from the intermediate data frequency pulled down by the first decimation filter to the data frequency of the A / D conversion output. Do.
  • the compensation filter data processing is performed at an intermediate data frequency higher than the data frequency of the A / D conversion output. Therefore, the compensation of the frequency characteristic of the output data performed by the compensation filter is performed more accurately than in the case of the data frequency of the A / D conversion output. Therefore, the A / D conversion output obtained through the second decimation filter becomes an output that is more faithful to the analog input signal.
  • the present invention is characterized in that the decimation filter or the first decimation filter is constituted by a second-order or higher-order sinc filter.
  • the decimation filter or the first decimation filter configured by the sinc filter can keep aliasing noise at its output to a sufficient SNR (signal-to-noise ratio) even at the compensation filter output. , Can be suppressed. For this reason, the A / D conversion output becomes an output that is more faithful to the analog input signal.
  • the present invention is characterized in that an integrator is provided between the adder and the quantizer.
  • the quantization noise is noise-shaped such that the spectrum distribution becomes high in the high frequency region by the integrator provided between the adder and the quantizer. Therefore, the quantization noise is efficiently removed by the band limiting function of the decimation filter, the SNR is improved, and the A / D conversion output becomes an output faithful to the analog input signal.
  • the present invention is characterized in that the compensation filter is configured by an integrator.
  • the compensation filter can be formed with a simple circuit configuration, and the circuit scale of the A / D converter can be reduced. Therefore, a compact and low power consumption A / D converter can be provided.
  • decimation filter data processing of a signal with a high data frequency is performed with a short word length, and in the compensation filter, data with long word length data with a low data frequency reduced by the decimation filter The processing reduces the power consumed by the A / D converter.
  • FIG. 1 is a circuit block diagram showing a schematic configuration of an A / D converter according to a first embodiment of the present invention.
  • FIG. 6 is a circuit block diagram showing a schematic configuration of an A / D converter that uses an output of a prediction filter as an A / D conversion output.
  • FIG. 7 is a circuit block diagram showing a schematic configuration of an A / D converter according to a second embodiment of the present invention.
  • (A) is a circuit block diagram which shows schematic structure of the A / D converter by 3rd Embodiment of this invention
  • (b) is the A / D converter by 4th Embodiment of this invention.
  • FIG. 18A is a circuit block diagram showing a schematic configuration of an A / D converter according to an eighth embodiment of the present invention.
  • FIG. 1 is a circuit block diagram showing a schematic configuration of an A / D converter 1A according to a first embodiment of the present invention.
  • the A / D converter 1A is configured to include an adder 2, a quantizer 3, a prediction filter 4, a decimation filter 5 and a compensation filter 6.
  • the adder 2 calculates the difference between the analog input signal U and the predicted value P.
  • the quantizer 3 quantizes the difference output from the adder 2 each time the sampling clock clk of the data frequency fs is input, and converts the analog input signal U into a word data length WL0, for example, a digital data string of 1 bit. Do.
  • the prediction filter 4 operates based on the sampling clock clk having the same data frequency fs as the quantizer 3, and a predicted value of the word length WL1 (WL0 ⁇ WL1) from the digital data string of the word length WL0 output from the quantizer 3 Generate P.
  • the decimation filter 5 has a low-pass band-limiting filter function and a decimation function, and is connected to the output of the quantizer 3.
  • the band limiting filter function attenuates the high frequency noise included in the output of the quantizer 3 and converts the analog input signal U input to the adder 2 into a digital signal and outputs the digital signal.
  • the frequency band is limited. Further, the data frequency is lowered from the frequency fs to the frequency fo (fs> fo) by the thinning-out function, and the output of the quantizer 3 is resampled to low-speed, multi-bit data of word length WL2 (WL0 ⁇ WL2). It is converted.
  • the compensation filter 6 connected to the output of the decimation filter 5 integrates the output of the decimation filter 5 to compensate the frequency characteristic of the output data. Data processing in the compensation filter 6 is performed at the same data frequency fo as the decimation filter 5.
  • the decimation filter 5 data having a high frequency fs and a short word length WL0 output from the quantizer 3 is output to the decimation filter 5, and the decimation filter 5 initially has a short word length.
  • Frequency band limitation and data frequency reduction processing are performed on data having a high frequency fs at WL0.
  • the integration filter is performed by the compensation filter 6 at the low-speed data frequency fo lowered by the decimation filter 5, and the frequency characteristic of the output data is compensated. For this reason, the power consumption of the A / D converter 1A is reduced in the decimation filter of the conventional A / D converter disclosed in Patent Document 1 as compared with the case of processing multi-bit data at a high oversampling frequency. Be done.
  • the analog input to be input to the adder 22 is the predicted value P of the digital value before being analog converted and fed back to the adder 22 by the prediction filter 24. It is also conceivable to use an A / D conversion output Dout of the signal U.
  • the A / D converter 21 is configured to include an adder 22, a quantizer 23, a prediction filter 24, and a D / A converter 26.
  • the adder 22 calculates the difference between the analog input signal U and the predicted value P.
  • the quantizer 23 quantizes the difference output from the adder 22 each time the sampling clock clk is input, and converts the analog input signal U into a digital signal D.
  • the prediction filter 24 generates a prediction value P from the digital signal D output from the quantizer 23, and further delays the prediction value P by the delay unit 25 and outputs it.
  • the prediction filter 24 is composed of a second delay unit 27, a multiplier 28, a second adder 29, an attenuator 30, and a series circuit of an integrator 31, an incomplete differentiator 32, and a delay unit 25.
  • the D / A converter 26 converts the predicted value P from a digital signal to an analog signal and outputs the analog value to the adder 22.
  • the predicted value P before being converted into an analog signal by the D / A converter 26 is taken as the A / D conversion output Dout of the analog input signal U input to the adder 22. .
  • a decimation filter is connected to the output of the prediction filter 24 to limit the frequency band of the A / D conversion output Dout and to lower the data frequency. Since the prediction filter 24 is configured to include an integral element, the word length of data to be processed becomes long. Therefore, in the decimation filter, data processing is performed on data having a word length longer than the data of the word length WL0 output from the quantizer 23 at the same high data frequency fs as the quantizer 23. Power consumption increases.
  • the decimation filter 5 is connected to the output of the quantizer 3 by the A / D converter 1A according to the present embodiment, and the output of the quantizer 3 is converted to the A / D conversion output Dout.
  • the decimation filter 5 performs frequency band limitation and data frequency reduction on data having a word length WL0 shorter than the prediction filter 4 and the prediction filter 4. Then, at the output side of the decimation filter 5, the integration filter is performed by the compensation filter 6 at the low-speed data frequency fo lowered by the decimation filter 5, the frequency characteristic of the prediction filter 4 is compensated, and the frequency characteristic of the output data is Be compensated.
  • the data processed by the decimation filter 5 compared to the case where the prediction value P output from the prediction filter 24 is subjected to the decimation filter as the A / D conversion output Dout as in the A / D converter 21 shown in FIG. Is data output from the quantizer 3 having a word length WL0 shorter than the data of the word length WL1 output from the prediction filter 4, and the power consumption of the A / D converter 1A is reduced.
  • the decimation filter 5 data processing of the signal of high data frequency fs is performed with a short word length WL0, and in the compensation filter 6, it is reduced by the decimation filter 5.
  • the power consumed by the A / D converter 1A is reduced.
  • FIG. 3 is a circuit block diagram showing a schematic configuration of an A / D converter 1B according to a second embodiment of the present invention.
  • the same reference numerals as in FIG. 1 denote the same parts in FIG. 3, and a description thereof will be omitted.
  • the first decimation filter 5 a is connected to the output of the quantizer 3, and the second decimation is connected to the output of the compensation filter 6.
  • the point divided into the filter 5b is different from the A / D converter 1A according to the first embodiment.
  • the configuration other than this point is the same as that of the A / D converter 1A according to the first embodiment.
  • the first decimation filter 5a lowers the data frequency to an intermediate data frequency fd (fs> fd> fo) lower than the data frequency fs of the quantizer 3 and higher than the data frequency fo of the A / D conversion output Dout.
  • the compensation filter 6 performs integration processing on the data of the word length WL2 lowered to the intermediate data frequency fd to perform data processing to compensate the frequency characteristic of the output data, and the word length WL3 (WL2 ⁇ WL3). Output as data.
  • the second decimation filter 5b performs decimation processing on the data of word length WL3 input from the compensation filter 6, and the data of the A / D conversion output Dout from the intermediate data frequency fd reduced by the first decimation filter 5a.
  • the data frequency is further lowered to the frequency fo, and the data is output as data of the word length WLo (WL3 ⁇ WLo).
  • the compensation filter 6 data processing is performed at an intermediate data frequency fd higher than the data frequency fo of the A / D conversion output Dout. Therefore, the compensation of the frequency characteristic of the output data performed by the compensation filter 6 is performed more accurately than in the case of the data frequency fo with a low A / D conversion output Dout. Therefore, the A / D conversion output Dout obtained through the second decimation filter 5b becomes an output that is more faithful to the analog input signal U.
  • FIG. 4 (a) is an A / D converter 1C according to the third embodiment of the present invention
  • FIG. 4 (b) is a circuit block schematically showing the configuration of an A / D converter 1D according to the fourth embodiment.
  • FIG. 4 the same parts as in FIG. 1 and FIG. 3 are assigned the same reference numerals and explanation thereof is omitted.
  • the A / D converter 1C according to the third embodiment is characterized in that the decimation filter 5 in the A / D converter 1A according to the first embodiment is constituted by a second or higher-order sinc M filter (M ⁇ 2) 5c. Is different from the A / D converter 1A according to the first embodiment.
  • the configuration other than this point is similar to that of the A / D converter 1A according to the first embodiment.
  • the first decimation filter 5a in the A / D converter 1B according to the second embodiment is a second-order or higher sinc M filter (M ⁇ 2) 5d.
  • M ⁇ 2 sinc M filter
  • the sinc M filter 5c and the first decimation filter 5a constituting the decimation filter 5 can be used.
  • the sinc M filters 5d that are configured can suppress aliasing noise at their output to such an extent that a sufficient SNR (signal-to-noise ratio) can be maintained even at the output of the compensation filter 6. Therefore, each A / D conversion output Dout in the A / D converter 1C according to the third embodiment and the A / D converter 1D according to the fourth embodiment becomes an output faithful to the analog input signal U. .
  • FIG. 5 (a) is an A / D converter 1E according to a fifth embodiment of the present invention
  • FIG. 5 (b) is an A / D converter 1F according to the sixth embodiment of the present invention
  • FIG. 5D is a circuit block diagram showing a schematic configuration of an A / D converter 1H according to an eighth embodiment of the present invention.
  • the same reference numerals as in FIGS. 1, 3 and 4 denote the same parts in FIG. 5, and a description thereof will be omitted.
  • Each of the A / D converters 1E, 1F, 1G and 1H according to the fifth, sixth, seventh and eighth embodiments includes an integrator 7 between the adder 2 and the quantizer 3; This differs from the A / D converters 1A, 1B, 1C and 1D according to the first, second, third and fourth embodiments.
  • the configuration other than this point is the same as that of each of the A / D converters 1A, 1B, 1C and 1D according to the first, second, third and fourth embodiments.
  • the quantization noise is noise shaped in such a way that its spectral distribution becomes high in the high frequency domain. Therefore, the quantization noise is efficiently removed by the band limiting functions of the decimation filter 5, the first and second decimation filters 5a and 5b, and the sinc M filters 5c and 5d, and the SNR is improved, and the A / D is improved.
  • the converted output Dout further becomes an output faithful to the analog input signal U.
  • the A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G according to the first, second, third, fourth, fifth, sixth, seventh and eighth embodiments described above.
  • the compensation filter 6 may be configured by an integrator (1 / (1-z.sup.- 1 )). According to this configuration, compensation filter 6 can be formed with a simple circuit configuration, and the circuit scale of A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H can be reduced. . For this reason, it is possible to provide compact and low power consumption A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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Abstract

According to the present invention, the power consumption of an A/D converter including an adder, a quantizer, a prediction filter, and a decimation filter is reduced. An A/D converter 1A is provided with an adder 2, a quantizer 3, a prediction filter 4, a decimation filter 5, and a compensation filter 6. The adder 2 calculates the difference between an analog input signal U and a prediction value P. The quantizer 3 quantizes the above difference and converts the analog input signal U into a digital data string of a word length WL0. The prediction filter 4 generates the prediction value P of a word length WL1 from the above digital data string. The decimation filter 5 attenuates high frequency noise from an output of the quantizer 3, lowers a data frequency from fs to fo, and converts the output of the quantizer 3into multi-bit data at a low speed of a word length WL2. The compensation filter 6 compensates for frequency characteristics of output data and outputs data of the word length WL0 with the data frequency fo.

Description

Ａ／Ｄ変換器A / D converter
　本発明は、アナログ入力信号と予測フィルタから出力される予測値との差分を量子化器で量子化してアナログ入力信号をデジタル信号に変換するＡ／Ｄ変換器に関するものである。 The present invention relates to an A / D converter that quantizes a difference between an analog input signal and a predicted value output from a prediction filter with a quantizer to convert the analog input signal into a digital signal.
　従来、この種のＡ／Ｄ変換器としては、例えば、特許文献１に開示された構成変更可能な連続時間シグマデルタＡ／Ｄ変換器がある。 Conventionally, as this type of A / D converter, there is, for example, a changeable continuous time sigma delta A / D converter disclosed in Patent Document 1.
　このＡ／Ｄ変換器は、抵抗器、連続時間フィルタ、加算回路、量子化器、連続時間ＤＡＣ、遅延要素、離散時間型ＤＡＣ、およびスイッチを備える。連続時間フィルタは、アナログ入力信号と、スイッチからのフィードバック信号とを受信する。フィードバック信号は、スイッチの切り替えにより、クロック信号が比較的大きなジッタを有するときに用いられる離散時間型ＤＡＣおよび遅延要素を含む一方のフィードバック経路からの信号と、比較的ジッタの少ない高品質なクロック信号を必要とする連続時間ＤＡＣを含む他方のフィードバック経路からの信号とに切り替えられる。 The A / D converter comprises a resistor, a continuous time filter, a summing circuit, a quantizer, a continuous time DAC, a delay element, a discrete time DAC, and a switch. A continuous time filter receives the analog input signal and the feedback signal from the switch. The feedback signal is a signal from one feedback path including a discrete time DAC and a delay element used when the clock signal has a relatively large jitter due to switch switching, and a high quality clock signal with a relatively small amount of jitter. And the signal from the other feedback path, including the continuous time DAC, which requires
　連続時間フィルタは、Ｎ次の積分器として実装されており、複数のフィードフォワード経路出力を、加算回路の複数の入力に提供する。加算回路の複数の入力の各々は、利得要素を含む。量子化器は、加算回路の出力端子に接続された入力端子と、複数の出力端子とを有し、加算回路から受信された入力に基づき、量子化された離散マルチビット出力を発生させる。デシメーションフィルタは、量子化器の複数の出力端子に接続された複数の入力端子と、複数のデジタル出力ビットを提供するための複数の出力端子とを有する。このデシメーションフィルタは、量子化器のマルチビット出力に結合され、データ周波数を低下させ、追加のノイズを除去し、かつ出力の分解能を増大させるために用いられる。 The continuous time filter is implemented as an Nth-order integrator and provides multiple feed forward path outputs to multiple inputs of the summing circuit. Each of the plurality of inputs of the summing circuit includes a gain element. The quantizer has an input terminal connected to the output terminal of the summing circuit and a plurality of output terminals, and generates a quantized discrete multi-bit output based on the input received from the summing circuit. The decimation filter has a plurality of input terminals connected to a plurality of output terminals of the quantizer and a plurality of output terminals for providing a plurality of digital output bits. This decimation filter is coupled to the multi-bit output of the quantizer and is used to lower the data frequency, remove additional noise, and increase the resolution of the output.
特開２０１３－４２４８８号公報JP, 2013-42488, A
　しかしながら、上記従来のＡ／Ｄ変換器は、量子化器が多ビット出力のため、上述のように、デシメーションフィルタにおいて、多ビットデータを高いオーバーサンプリング周波数で処理する必要がある。このため、上記従来のＡ／Ｄ変換器は、消費電力が大きくなるという課題があった。 However, since the above-described conventional A / D converter has a multi-bit quantizer, as described above, it is necessary to process multi-bit data at a high oversampling frequency in the decimation filter. Therefore, the above-described conventional A / D converter has a problem that power consumption is increased.
　本発明はこのような課題を解決するためになされたもので、
アナログ入力信号と予測値との差分を演算する加算器と、加算器から出力される差分を量子化する量子化器と、量子化器から出力される信号から予測値を生成する予測フィルタと、加算器に入力されるアナログ入力信号がデジタル信号に変換されて出力されるＡ／Ｄ変換出力の周波数帯域を制限すると共にデータ周波数を引き下げるデシメーションフィルタとを備えるＡ／Ｄ変換器において、
デシメーションフィルタが量子化器の出力に接続され、
デシメーションフィルタの出力側において出力データの周波数特性を補償する補償フィルタを備えることを特徴とする。 The present invention has been made to solve such problems.
An adder for calculating a difference between an analog input signal and a predicted value, a quantizer for quantizing a difference output from the adder, and a prediction filter for generating a predicted value from a signal output from the quantizer. An A / D converter comprising: a decimation filter for limiting the frequency band of an A / D conversion output which is converted into a digital signal and output an analog input signal input to an adder and outputting the digital signal;
A decimation filter is connected to the output of the quantizer,
The present invention is characterized by comprising a compensation filter that compensates for frequency characteristics of output data at the output side of the decimation filter.
　本構成によれば、量子化器から出力される短い語長で周波数の高いデータがデシメーションフィルタに出力され、最初にデシメーションフィルタにおいて、短い語長で周波数の高いデータに対して周波数帯域の制限およびデータ周波数の引き下げ処理が行われる。そして、デシメーションフィルタの出力側において、デシメーションフィルタによって引き下げられた低速のデータ周波数で、補償フィルタにより出力データの周波数特性が補償される。このため、Ａ／Ｄ変換器の消費電力は、デシメーションフィルタにおいて、多ビットデータを高いオーバーサンプリング周波数で処理する従来に比べて、低減される。 According to this configuration, the short word length and high frequency data output from the quantizer are output to the decimation filter, and the decimation filter first performs frequency band limitation for the short word length and high frequency data and Data frequency reduction processing is performed. Then, at the output side of the decimation filter, the frequency characteristic of the output data is compensated by the compensation filter at the low-speed data frequency reduced by the decimation filter. For this reason, the power consumption of the A / D converter is reduced in the decimation filter as compared to the conventional processing of multi-bit data at a high oversampling frequency.
　また、予測フィルタによって加算器にフィードバックされるアナログ変換される前のデジタル値の予測値を、加算器に入力されるアナログ入力信号のＡ／Ｄ変換出力とすることも考えられる。しかし、この場合、予測フィルタの出力にデシメーションフィルタを接続して、Ａ／Ｄ変換出力の周波数帯域を制限すると共にデータ周波数を引き下げることになる。このため、デシメーションフィルタでは、量子化器と同じ高いデータ周波数で、量子化器から出力されるデータよりも長い語長のデータに対してデータ処理を行うことになり、消費電力が大きくなる。 Further, it is also conceivable to use the predicted value of the digital value before analog conversion to be fed back to the adder by the prediction filter as the A / D converted output of the analog input signal inputted to the adder. However, in this case, a decimation filter is connected to the output of the prediction filter to limit the frequency band of the A / D conversion output and to lower the data frequency. For this reason, in the decimation filter, data processing is performed on data having a word length longer than that of data output from the quantizer at the same high data frequency as that of the quantizer, and power consumption increases.
　しかし、本構成により、デシメーションフィルタが量子化器の出力に接続され、予測フィルタよりも短い語長のデータに対して、デシメーションフィルタにより、周波数帯域の制限およびデータ周波数の引き下げが行われる。そして、デシメーションフィルタの出力側において、デシメーションフィルタによって引き下げられた低速のデータ周波数で、補償フィルタによって出力データの周波数特性が補償される。このため、予測フィルタから出力される予測値がＡ／Ｄ変換出力としてデシメーションフィルタにかけられる場合に比べ、デシメーションフィルタの処理するデータが、予測フィルタから出力されるデータよりも短い語長の、量子化器から出力されるデータになり、Ａ／Ｄ変換器の消費電力は低減される。 However, according to this configuration, the decimation filter is connected to the output of the quantizer, and the decimation filter performs frequency band limitation and data frequency reduction on data having a word length shorter than that of the prediction filter. Then, at the output side of the decimation filter, the frequency characteristic of the output data is compensated by the compensation filter at the low-speed data frequency reduced by the decimation filter. Therefore, the data processed by the decimation filter is quantized with a word length shorter than that of the data output from the prediction filter, as compared with the case where the prediction value output from the prediction filter is subjected to the decimation filter as an A / D conversion output. Power consumption of the A / D converter.
　また、本発明は、デシメーションフィルタが、
量子化器の出力に接続されて、量子化器のデータ周波数より低くＡ／Ｄ変換出力のデータ周波数よりも高い中間データ周波数にデータ周波数を引き下げる第１のデシメーションフィルタと、
補償フィルタの出力に接続されて、第１のデシメーションフィルタによって引き下げられた中間データ周波数からＡ／Ｄ変換出力のデータ周波数にデータ周波数をさらに引き下げる第２のデシメーションフィルタとに分割されることを特徴とする。 In the present invention, the decimation filter is
A first decimation filter connected to the output of the quantizer to reduce the data frequency to an intermediate data frequency lower than the data frequency of the quantizer and higher than the data frequency of the A / D conversion output;
Characterized in that it is divided into a second decimation filter connected to the output of the compensation filter and further reducing the data frequency from the intermediate data frequency pulled down by the first decimation filter to the data frequency of the A / D conversion output. Do.
　本構成によれば、補償フィルタでは、Ａ／Ｄ変換出力のデータ周波数よりも高い中間データ周波数で、データ処理が行われる。したがって、補償フィルタで行われる出力データの周波数特性の補償は、Ａ／Ｄ変換出力のデータ周波数で行われる場合よりも、より精度高く行われる。このため、第２のデシメーションフィルタを介して得られるＡ／Ｄ変換出力は、よりアナログ入力信号に忠実な出力となる。 According to this configuration, in the compensation filter, data processing is performed at an intermediate data frequency higher than the data frequency of the A / D conversion output. Therefore, the compensation of the frequency characteristic of the output data performed by the compensation filter is performed more accurately than in the case of the data frequency of the A / D conversion output. Therefore, the A / D conversion output obtained through the second decimation filter becomes an output that is more faithful to the analog input signal.
　また、本発明は、デシメーションフィルタまたは第１のデシメーションフィルタが、２次以上のｓｉｎｃフィルタによって構成されることを特徴とする。 Furthermore, the present invention is characterized in that the decimation filter or the first decimation filter is constituted by a second-order or higher-order sinc filter.
　本構成によれば、ｓｉｎｃフィルタによって構成されるデシメーションフィルタまたは第１のデシメーションフィルタは、その出力における折り返し雑音を、補償フィルタ出力においても十分なＳＮＲ（信号対雑音比）を保つことができる程度に、抑圧することができる。このため、Ａ／Ｄ変換出力はさらにアナログ入力信号に忠実な出力となる。 According to this configuration, the decimation filter or the first decimation filter configured by the sinc filter can keep aliasing noise at its output to a sufficient SNR (signal-to-noise ratio) even at the compensation filter output. , Can be suppressed. For this reason, the A / D conversion output becomes an output that is more faithful to the analog input signal.
　また、本発明は、加算器と量子化器との間に積分器を備えることを特徴とする。 Also, the present invention is characterized in that an integrator is provided between the adder and the quantizer.
　本構成によれば、加算器と量子化器との間に備える積分器により、量子化雑音は、そのスペクトラム分布が高周波数領域で高くなる形にノイズシェーピングされる。このため、量子化雑音はデシメーションフィルタの帯域制限機能によって効率よく除去され、ＳＮＲが改善されて、Ａ／Ｄ変換出力はさらにアナログ入力信号に忠実な出力となる。 According to this configuration, the quantization noise is noise-shaped such that the spectrum distribution becomes high in the high frequency region by the integrator provided between the adder and the quantizer. Therefore, the quantization noise is efficiently removed by the band limiting function of the decimation filter, the SNR is improved, and the A / D conversion output becomes an output faithful to the analog input signal.
　また、本発明は、補償フィルタが積分器で構成されることを特徴とする。 Also, the present invention is characterized in that the compensation filter is configured by an integrator.
　本構成によれば、単純な回路構成で補償フィルタを形成することができ、Ａ／Ｄ変換器の回路規模を小さくすることができる。このため、小型で低消費電力のＡ／Ｄ変換器を提供することができる。 According to this configuration, the compensation filter can be formed with a simple circuit configuration, and the circuit scale of the A / D converter can be reduced. Therefore, a compact and low power consumption A / D converter can be provided.
　本発明によれば、デシメーションフィルタにおいて、データ周波数の高い信号のデータ処理が短い語長で行われ、補償フィルタにおいて、デシメーションフィルタによって引き下げられた低いデータ周波数で、語長の長いデータに対してデータ処理が行われることで、Ａ／Ｄ変換器で消費される電力は低減される。 According to the present invention, in the decimation filter, data processing of a signal with a high data frequency is performed with a short word length, and in the compensation filter, data with long word length data with a low data frequency reduced by the decimation filter The processing reduces the power consumed by the A / D converter.
本発明の第１の実施形態によるＡ／Ｄ変換器の概略構成を示す回路ブロック図である。FIG. 1 is a circuit block diagram showing a schematic configuration of an A / D converter according to a first embodiment of the present invention. 予測フィルタの出力をＡ／Ｄ変換出力とするＡ／Ｄ変換器の概略構成を示す回路ブロック図である。FIG. 6 is a circuit block diagram showing a schematic configuration of an A / D converter that uses an output of a prediction filter as an A / D conversion output. 本発明の第２の実施形態によるＡ／Ｄ変換器の概略構成を示す回路ブロック図である。FIG. 7 is a circuit block diagram showing a schematic configuration of an A / D converter according to a second embodiment of the present invention. （ａ）は本発明の第３の実施形態によるＡ／Ｄ変換器、（ｂ）は本発明の第４の実施形態によるＡ／Ｄ変換器の概略構成を示す回路ブロック図である。(A) is a circuit block diagram which shows schematic structure of the A / D converter by 3rd Embodiment of this invention, (b) is the A / D converter by 4th Embodiment of this invention. （ａ）は本発明の第５の実施形態によるＡ／Ｄ変換器、（ｂ）は本発明の第６の実施形態によるＡ／Ｄ変換器、（ｃ）は本発明の第７の実施形態によるＡ／Ｄ変換器、（ｄ）は本発明の第８の実施形態によるＡ／Ｄ変換器の概略構成を示す回路ブロック図である。(A) is an A / D converter according to a fifth embodiment of the present invention, (b) is an A / D converter according to the sixth embodiment of the present invention, (c) is a seventh embodiment of the present invention FIG. 18A is a circuit block diagram showing a schematic configuration of an A / D converter according to an eighth embodiment of the present invention, and FIG.
　次に、本発明のＡ／Ｄ変換器を実施するための形態について、説明する。 Next, an embodiment for implementing the A / D converter of the present invention will be described.
　図１は、本発明の第１の実施形態によるＡ／Ｄ変換器１Ａの概略構成を示す回路ブロック図である。 FIG. 1 is a circuit block diagram showing a schematic configuration of an A / D converter 1A according to a first embodiment of the present invention.
　Ａ／Ｄ変換器１Ａは、加算器２、量子化器３、予測フィルタ４、デシメーションフィルタ５および補償フィルタ６を備えて構成される。加算器２はアナログ入力信号Ｕと予測値Ｐとの差分を演算する。量子化器３は、加算器２から出力される差分を、データ周波数ｆｓのサンプリングクロックclkが入力される毎に量子化して、アナログ入力信号Ｕを語長ＷＬ０例えば１ビットのデジタルデータ列に変換する。予測フィルタ４は、量子化器３と同じデータ周波数ｆｓのサンプリングクロックclkに基づき動作し、量子化器３から出力される語長ＷＬ０のデジタルデータ列から語長ＷＬ１（ＷＬ０＜ＷＬ１）の予測値Ｐを生成する。 The A / D converter 1A is configured to include an adder 2, a quantizer 3, a prediction filter 4, a decimation filter 5 and a compensation filter 6. The adder 2 calculates the difference between the analog input signal U and the predicted value P. The quantizer 3 quantizes the difference output from the adder 2 each time the sampling clock clk of the data frequency fs is input, and converts the analog input signal U into a word data length WL0, for example, a digital data string of 1 bit. Do. The prediction filter 4 operates based on the sampling clock clk having the same data frequency fs as the quantizer 3, and a predicted value of the word length WL1 (WL0 <WL1) from the digital data string of the word length WL0 output from the quantizer 3 Generate P.
　デシメーションフィルタ５は、低域通過の帯域制限フィルタ機能と間引き（デシメーション）機能とを持ち、量子化器３の出力に接続される。帯域制限フィルタ機能により、量子化器３の出力に含まれる高周波ノイズが減衰させられ、加算器２に入力されるアナログ入力信号Ｕがデジタル信号に変換されて出力されるＡ／Ｄ変換出力Ｄoutの周波数帯域が制限される。また、間引き機能により、データ周波数が周波数ｆｓから周波数ｆｏ（ｆｓ＞ｆｏ）に引き下げられ、量子化器３の出力がリサンプリングされて語長ＷＬ２（ＷＬ０＜ＷＬ２）の低速で多ビットのデータに変換される。 The decimation filter 5 has a low-pass band-limiting filter function and a decimation function, and is connected to the output of the quantizer 3. The band limiting filter function attenuates the high frequency noise included in the output of the quantizer 3 and converts the analog input signal U input to the adder 2 into a digital signal and outputs the digital signal. The frequency band is limited. Further, the data frequency is lowered from the frequency fs to the frequency fo (fs> fo) by the thinning-out function, and the output of the quantizer 3 is resampled to low-speed, multi-bit data of word length WL2 (WL0 <WL2). It is converted.
　デシメーションフィルタ５の出力に接続される補償フィルタ６は、デシメーションフィルタ５の出力を積分処理して出力データの周波数特性を補償する。補償フィルタ６におけるデータ処理はデシメーションフィルタ５と同じデータ周波数ｆｏで行われる。 The compensation filter 6 connected to the output of the decimation filter 5 integrates the output of the decimation filter 5 to compensate the frequency characteristic of the output data. Data processing in the compensation filter 6 is performed at the same data frequency fo as the decimation filter 5.
　本実施形態によるＡ／Ｄ変換器１Ａによれば、量子化器３から出力される短い語長ＷＬ０で周波数ｆｓの高いデータがデシメーションフィルタ５に出力され、最初にデシメーションフィルタ５において、短い語長ＷＬ０で周波数ｆｓの高いデータに対して周波数帯域の制限およびデータ周波数の引き下げ処理が行われる。そして、デシメーションフィルタ５の出力側において、デシメーションフィルタ５によって引き下げられた低速のデータ周波数ｆｏで、補償フィルタ６により積分処理が行われて出力データの周波数特性が補償される。このため、Ａ／Ｄ変換器１Ａの消費電力は、特許文献１に開示される従来のＡ／Ｄ変換器のデシメーションフィルタにおいて、多ビットデータを高いオーバーサンプリング周波数で処理する場合に比べて、低減される。 According to the A / D converter 1A according to the present embodiment, data having a high frequency fs and a short word length WL0 output from the quantizer 3 is output to the decimation filter 5, and the decimation filter 5 initially has a short word length. Frequency band limitation and data frequency reduction processing are performed on data having a high frequency fs at WL0. Then, at the output side of the decimation filter 5, the integration filter is performed by the compensation filter 6 at the low-speed data frequency fo lowered by the decimation filter 5, and the frequency characteristic of the output data is compensated. For this reason, the power consumption of the A / D converter 1A is reduced in the decimation filter of the conventional A / D converter disclosed in Patent Document 1 as compared with the case of processing multi-bit data at a high oversampling frequency. Be done.
　また、図２に示すＡ／Ｄ変換器２１のように、予測フィルタ２４によって加算器２２にフィードバックされるアナログ変換される前のデジタル値の予測値Ｐを、加算器２２に入力されるアナログ入力信号ＵのＡ／Ｄ変換出力Ｄoutとすることも考えられる。 Further, as in the A / D converter 21 shown in FIG. 2, the analog input to be input to the adder 22 is the predicted value P of the digital value before being analog converted and fed back to the adder 22 by the prediction filter 24. It is also conceivable to use an A / D conversion output Dout of the signal U.
　Ａ／Ｄ変換器２１は、加算器２２、量子化器２３、予測フィルタ２４およびＤ／Ａ変換器２６を備えて構成される。加算器２２はアナログ入力信号Ｕと予測値Ｐとの差分を演算する。量子化器２３は、加算器２２から出力される差分をサンプリングクロックclkが入力される毎に量子化して、アナログ入力信号Ｕをデジタル信号Ｄに変換する。予測フィルタ２４は、量子化器２３から出力されるデジタル信号Ｄから予測値Ｐを生成し、さらに遅延器２５で予測値Ｐを遅延させて出力する。予測フィルタ２４は、第２の遅延器２７、乗算器２８、第２の加算器２９、減衰器３０、および、積分器３１と不完全微分器３２と遅延器２５の直列回路から構成される。Ｄ／Ａ変換器２６は、予測値Ｐをデジタル信号からアナログ信号に変換して、加算器２２へ出力する。このＡ／Ｄ変換器２１では、Ｄ／Ａ変換器２６によってアナログ信号に変換される前の予測値Ｐが、加算器２２に入力されるアナログ入力信号ＵのＡ／Ｄ変換出力Ｄoutとされる。 The A / D converter 21 is configured to include an adder 22, a quantizer 23, a prediction filter 24, and a D / A converter 26. The adder 22 calculates the difference between the analog input signal U and the predicted value P. The quantizer 23 quantizes the difference output from the adder 22 each time the sampling clock clk is input, and converts the analog input signal U into a digital signal D. The prediction filter 24 generates a prediction value P from the digital signal D output from the quantizer 23, and further delays the prediction value P by the delay unit 25 and outputs it. The prediction filter 24 is composed of a second delay unit 27, a multiplier 28, a second adder 29, an attenuator 30, and a series circuit of an integrator 31, an incomplete differentiator 32, and a delay unit 25. The D / A converter 26 converts the predicted value P from a digital signal to an analog signal and outputs the analog value to the adder 22. In this A / D converter 21, the predicted value P before being converted into an analog signal by the D / A converter 26 is taken as the A / D conversion output Dout of the analog input signal U input to the adder 22. .
　しかし、この場合、予測フィルタ２４の出力にデシメーションフィルタを接続して、Ａ／Ｄ変換出力Ｄoutの周波数帯域を制限すると共にデータ周波数を引き下げることになる。予測フィルタ２４は積分要素を含んで構成されるので、処理するデータの語長が長くなる。このため、デシメーションフィルタでは、量子化器２３と同じ高いデータ周波数ｆｓで、量子化器２３から出力される語長ＷＬ０のデータよりも長い語長のデータに対してデータ処理を行うことになり、消費電力が大きくなる。 However, in this case, a decimation filter is connected to the output of the prediction filter 24 to limit the frequency band of the A / D conversion output Dout and to lower the data frequency. Since the prediction filter 24 is configured to include an integral element, the word length of data to be processed becomes long. Therefore, in the decimation filter, data processing is performed on data having a word length longer than the data of the word length WL0 output from the quantizer 23 at the same high data frequency fs as the quantizer 23. Power consumption increases.
　しかし、本実施形態によるＡ／Ｄ変換器１Ａにより、デシメーションフィルタ５が量子化器３の出力に接続され、量子化器３の出力がＡ／Ｄ変換出力Ｄoutにされることで、予測フィルタ２４や予測フィルタ４よりも短い語長ＷＬ０のデータに対して、デシメーションフィルタ５により、周波数帯域の制限およびデータ周波数の引き下げが行われる。そして、デシメーションフィルタ５の出力側において、デシメーションフィルタ５によって引き下げられた低速のデータ周波数ｆｏで、補償フィルタ６によって積分処理が行われて予測フィルタ４の周波数特性が補償され、出力データの周波数特性が補償される。このため、図２に示すＡ／Ｄ変換器２１のように、予測フィルタ２４から出力される予測値ＰがＡ／Ｄ変換出力Ｄoutとしてデシメーションフィルタにかけられる場合に比べ、デシメーションフィルタ５の処理するデータが、予測フィルタ４から出力される語長ＷＬ１のデータよりも短い語長ＷＬ０の、量子化器３から出力されるデータになり、Ａ／Ｄ変換器１Ａの消費電力は低減される。 However, the decimation filter 5 is connected to the output of the quantizer 3 by the A / D converter 1A according to the present embodiment, and the output of the quantizer 3 is converted to the A / D conversion output Dout. The decimation filter 5 performs frequency band limitation and data frequency reduction on data having a word length WL0 shorter than the prediction filter 4 and the prediction filter 4. Then, at the output side of the decimation filter 5, the integration filter is performed by the compensation filter 6 at the low-speed data frequency fo lowered by the decimation filter 5, the frequency characteristic of the prediction filter 4 is compensated, and the frequency characteristic of the output data is Be compensated. Therefore, the data processed by the decimation filter 5 compared to the case where the prediction value P output from the prediction filter 24 is subjected to the decimation filter as the A / D conversion output Dout as in the A / D converter 21 shown in FIG. Is data output from the quantizer 3 having a word length WL0 shorter than the data of the word length WL1 output from the prediction filter 4, and the power consumption of the A / D converter 1A is reduced.
　すなわち、本実施形態によるＡ／Ｄ変換器１Ａによれば、デシメーションフィルタ５において、高いデータ周波数ｆｓの信号のデータ処理が短い語長ＷＬ０で行われ、補償フィルタ６において、デシメーションフィルタ５によって引き下げられた低いデータ周波数ｆｏで、長い語長ＷＬ２のデータに対してデータ処理が行われることで、Ａ／Ｄ変換器１Ａで消費される電力は低減される。 That is, according to the A / D converter 1A according to the present embodiment, in the decimation filter 5, data processing of the signal of high data frequency fs is performed with a short word length WL0, and in the compensation filter 6, it is reduced by the decimation filter 5. By performing data processing on data of a long word length WL2 at a low data frequency fo, the power consumed by the A / D converter 1A is reduced.
　図３は、本発明の第２の実施形態によるＡ／Ｄ変換器１Ｂの概略構成を示す回路ブロック図である。なお、図３において図１と同一部分には同一符号を付してその説明は省略する。 FIG. 3 is a circuit block diagram showing a schematic configuration of an A / D converter 1B according to a second embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same parts in FIG. 3, and a description thereof will be omitted.
　第２の実施形態によるＡ／Ｄ変換器１Ｂは、デシメーションフィルタ５が、量子化器３の出力に接続される第１のデシメーションフィルタ５ａと、補償フィルタ６の出力に接続される第２のデシメーションフィルタ５ｂとに分割される点が、第１の実施形態によるＡ／Ｄ変換器１Ａと相違する。この点以外の構成は第１の実施形態によるＡ／Ｄ変換器１Ａと同様である。 In the A / D converter 1 B according to the second embodiment, the first decimation filter 5 a is connected to the output of the quantizer 3, and the second decimation is connected to the output of the compensation filter 6. The point divided into the filter 5b is different from the A / D converter 1A according to the first embodiment. The configuration other than this point is the same as that of the A / D converter 1A according to the first embodiment.
　第１のデシメーションフィルタ５ａは、量子化器３のデータ周波数ｆｓより低く、Ａ／Ｄ変換出力Ｄoutのデータ周波数ｆｏよりも高い中間データ周波数ｆｄ（ｆｓ＞ｆｄ＞ｆｏ）に、データ周波数を引き下げる。補償フィルタ６は、この中間データ周波数ｆｄに引き下げられた語長ＷＬ２のデータに対して、積分処理を行って出力データの周波数特性を補償するデータ処理をし、語長ＷＬ３（ＷＬ２＜ＷＬ３）のデータにして出力する。第２のデシメーションフィルタ５ｂは、補償フィルタ６から入力した語長ＷＬ３のデータに対してデシメーション処理を行い、第１のデシメーションフィルタ５ａによって引き下げられた中間データ周波数ｆｄからＡ／Ｄ変換出力Ｄoutのデータ周波数ｆｏに、データ周波数をさらに引き下げ、語長ＷＬｏ（ＷＬ３＜ＷＬｏ）のデータとして出力する。 The first decimation filter 5a lowers the data frequency to an intermediate data frequency fd (fs> fd> fo) lower than the data frequency fs of the quantizer 3 and higher than the data frequency fo of the A / D conversion output Dout. The compensation filter 6 performs integration processing on the data of the word length WL2 lowered to the intermediate data frequency fd to perform data processing to compensate the frequency characteristic of the output data, and the word length WL3 (WL2 <WL3). Output as data. The second decimation filter 5b performs decimation processing on the data of word length WL3 input from the compensation filter 6, and the data of the A / D conversion output Dout from the intermediate data frequency fd reduced by the first decimation filter 5a. The data frequency is further lowered to the frequency fo, and the data is output as data of the word length WLo (WL3 <WLo).
　このような第２の実施形態によるＡ／Ｄ変換器１Ｂによれば、補償フィルタ６では、Ａ／Ｄ変換出力Ｄoutのデータ周波数ｆｏよりも高い中間データ周波数ｆｄで、データ処理が行われる。したがって、補償フィルタ６で行われる出力データの周波数特性の補償は、Ａ／Ｄ変換出力Ｄoutの低いデータ周波数ｆｏで行われる場合よりも、より精度高く行われる。このため、第２のデシメーションフィルタ５ｂを介して得られるＡ／Ｄ変換出力Ｄoutは、よりアナログ入力信号Ｕに忠実な出力となる。 According to the A / D converter 1B of the second embodiment, in the compensation filter 6, data processing is performed at an intermediate data frequency fd higher than the data frequency fo of the A / D conversion output Dout. Therefore, the compensation of the frequency characteristic of the output data performed by the compensation filter 6 is performed more accurately than in the case of the data frequency fo with a low A / D conversion output Dout. Therefore, the A / D conversion output Dout obtained through the second decimation filter 5b becomes an output that is more faithful to the analog input signal U.
　図４（ａ）は本発明の第３の実施形態によるＡ／Ｄ変換器１Ｃ、図４（ｂ）は本発明の第４の実施形態によるＡ／Ｄ変換器１Ｄの概略構成を示す回路ブロック図である。なお、図４において図１および図３と同一部分には同一符号を付してその説明は省略する。 FIG. 4 (a) is an A / D converter 1C according to the third embodiment of the present invention, and FIG. 4 (b) is a circuit block schematically showing the configuration of an A / D converter 1D according to the fourth embodiment. FIG. In FIG. 4, the same parts as in FIG. 1 and FIG. 3 are assigned the same reference numerals and explanation thereof is omitted.
　第３の実施形態によるＡ／Ｄ変換器１Ｃは、第１の実施形態によるＡ／Ｄ変換器１Ａにおけるデシメーションフィルタ５が、２次以上のｓｉｎｃＭフィルタ（Ｍ≧２）５ｃによって構成される点が、第１の実施形態によるＡ／Ｄ変換器１Ａと相違する。この点以外の構成は第１の実施形態によるＡ／Ｄ変換器１Ａと同様である。 The A / D converter 1C according to the third embodiment is characterized in that the decimation filter 5 in the A / D converter 1A according to the first embodiment is constituted by a second or higher-order sinc M filter (M ≧ 2) 5c. Is different from the A / D converter 1A according to the first embodiment. The configuration other than this point is similar to that of the A / D converter 1A according to the first embodiment.
　また、第４の実施形態によるＡ／Ｄ変換器１Ｄは、第２の実施形態によるＡ／Ｄ変換器１Ｂにおける第１のデシメーションフィルタ５ａが、２次以上のｓｉｎｃＭフィルタ（Ｍ≧２）５ｄによって構成される点が、第２の実施形態によるＡ／Ｄ変換器１Ｂと相違する。この点以外の構成は第２の実施形態によるＡ／Ｄ変換器１Ｂと同様である。 In the A / D converter 1D according to the fourth embodiment, the first decimation filter 5a in the A / D converter 1B according to the second embodiment is a second-order or higher sinc M filter (M ≧ 2) 5d. Are different from the A / D converter 1B according to the second embodiment. The configuration other than this point is the same as that of the A / D converter 1B according to the second embodiment.
　このような第３の実施形態によるＡ／Ｄ変換器１Ｃおよび第４の実施形態によるＡ／Ｄ変換器１Ｄによれば、デシメーションフィルタ５を構成するｓｉｎｃＭフィルタ５ｃおよび第１のデシメーションフィルタ５ａを構成するｓｉｎｃＭフィルタ５ｄは、それらの出力における折り返し雑音を、補償フィルタ６の出力においても十分なＳＮＲ（信号対雑音比）を保つことができる程度に、抑圧することができる。このため、これら第３の実施形態によるＡ／Ｄ変換器１Ｃおよび第４の実施形態によるＡ／Ｄ変換器１Ｄにおける各Ａ／Ｄ変換出力Ｄoutは、さらにアナログ入力信号Ｕに忠実な出力となる。 According to the A / D converter 1C according to the third embodiment and the A / D converter 1D according to the fourth embodiment, the sinc M filter 5c and the first decimation filter 5a constituting the decimation filter 5 can be used. The sinc M filters 5d that are configured can suppress aliasing noise at their output to such an extent that a sufficient SNR (signal-to-noise ratio) can be maintained even at the output of the compensation filter 6. Therefore, each A / D conversion output Dout in the A / D converter 1C according to the third embodiment and the A / D converter 1D according to the fourth embodiment becomes an output faithful to the analog input signal U. .
　図５（ａ）は本発明の第５の実施形態によるＡ／Ｄ変換器１Ｅ、図５（ｂ）は本発明の第６の実施形態によるＡ／Ｄ変換器１Ｆ、図５（ｃ）は本発明の第７の実施形態によるＡ／Ｄ変換器１Ｇ、図５（ｄ）は本発明の第８の実施形態によるＡ／Ｄ変換器１Ｈの概略構成を示す回路ブロック図である。なお、図５において図１、図３および図４と同一部分には同一符号を付してその説明は省略する。 5 (a) is an A / D converter 1E according to a fifth embodiment of the present invention, FIG. 5 (b) is an A / D converter 1F according to the sixth embodiment of the present invention, and FIG. An A / D converter 1G according to a seventh embodiment of the present invention, and FIG. 5D is a circuit block diagram showing a schematic configuration of an A / D converter 1H according to an eighth embodiment of the present invention. The same reference numerals as in FIGS. 1, 3 and 4 denote the same parts in FIG. 5, and a description thereof will be omitted.
　第５，第６，第７および第８の実施形態による各Ａ／Ｄ変換器１Ｅ，１Ｆ，１Ｇおよび１Ｈは、加算器２と量子化器３との間に積分器７を備える点が、第１，第２，第３および第４の実施形態による各Ａ／Ｄ変換器１Ａ，１Ｂ，１Ｃおよび１Ｄと相違する。この点以外の構成は第１，第２，第３および第４の実施形態による各Ａ／Ｄ変換器１Ａ，１Ｂ，１Ｃおよび１Ｄと同様である。 Each of the A / D converters 1E, 1F, 1G and 1H according to the fifth, sixth, seventh and eighth embodiments includes an integrator 7 between the adder 2 and the quantizer 3; This differs from the A / D converters 1A, 1B, 1C and 1D according to the first, second, third and fourth embodiments. The configuration other than this point is the same as that of each of the A / D converters 1A, 1B, 1C and 1D according to the first, second, third and fourth embodiments.
　このような第５，第６，第７および第８の実施形態による各Ａ／Ｄ変換器１Ｅ，１Ｆ，１Ｇおよび１Ｈによれば、加算器２と量子化器３との間に備える積分器７により、量子化雑音は、そのスペクトラム分布が高周波数領域で高くなる形にノイズシェーピングされる。このため、量子化雑音はデシメーションフィルタ５，第１および第２のデシメーションフィルタ５ａ，５ｂ、並びにｓｉｎｃＭフィルタ５ｃ，５ｄの各帯域制限機能によって効率よく除去され、ＳＮＲが改善されて、Ａ／Ｄ変換出力Ｄoutはさらにアナログ入力信号Ｕに忠実な出力となる。 According to the respective A / D converters 1E, 1F, 1G and 1H according to the fifth, sixth, seventh and eighth embodiments, an integrator provided between the adder 2 and the quantizer 3 At 7, the quantization noise is noise shaped in such a way that its spectral distribution becomes high in the high frequency domain. Therefore, the quantization noise is efficiently removed by the band limiting functions of the decimation filter 5, the first and second decimation filters 5a and 5b, and the sinc M filters 5c and 5d, and the SNR is improved, and the A / D is improved. The converted output Dout further becomes an output faithful to the analog input signal U.
　なお、上記の第１，第２，第３，第４，第５，第６，第７および第８の実施形態による各Ａ／Ｄ変換器１Ａ，１Ｂ，１Ｃ，１Ｄ，１Ｅ，１Ｆ，１Ｇおよび１Ｈにおいて、補償フィルタ６を積分器（１／（１－ｚ－１））で構成するようにしてもよい。本構成によれば、単純な回路構成で補償フィルタ６を形成することができ、Ａ／Ｄ変換器１Ａ，１Ｂ，１Ｃ，１Ｄ，１Ｅ，１Ｆ，１Ｇおよび１Ｈの回路規模を小さくすることができる。このため、小型で低消費電力のＡ／Ｄ変換器１Ａ，１Ｂ，１Ｃ，１Ｄ，１Ｅ，１Ｆ，１Ｇおよび１Ｈを提供することができる。 The A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G according to the first, second, third, fourth, fifth, sixth, seventh and eighth embodiments described above. And 1H, the compensation filter 6 may be configured by an integrator (1 / (1-z.sup.- 1 )). According to this configuration, compensation filter 6 can be formed with a simple circuit configuration, and the circuit scale of A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H can be reduced. . For this reason, it is possible to provide compact and low power consumption A / D converters 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H.
　１Ａ，１Ｂ，１Ｃ，１Ｄ，１Ｅ，１Ｆ，１Ｇ，１Ｈ…Ａ／Ｄ変換器
　２…加算器
　３…量子化器
　４…予測フィルタ
　５…デシメーションフィルタ
　５ａ…第１のデシメーションフィルタ
　５ｂ…第２のデシメーションフィルタ
　５ｃ，５ｄ…ｓｉｎｃＭフィルタ（Ｍ≧２）
　６…補償フィルタ
　７…積分器 1A, 1B, 1C, 1D, 1E, 1G, 1H ... A / D converter 2 ... adder 3 ... quantizer 4 ... prediction filter 5 ... decimation filter 5a ... first decimation filter 5b ... second Decimation filter 5c, 5d ... sinc M filter (M 2 2)
6 ... Compensation filter 7 ... Integrator

Claims (5)

  1. 　アナログ入力信号と予測値との差分を演算する加算器と、前記加算器から出力される前記差分を量子化する量子化器と、前記量子化器から出力される信号から前記予測値を生成する予測フィルタと、前記加算器に入力されるアナログ入力信号がデジタル信号に変換されて出力されるＡ／Ｄ変換出力の周波数帯域を制限すると共にデータ周波数を引き下げるデシメーションフィルタとを備えるＡ／Ｄ変換器において、
    　前記デシメーションフィルタは前記量子化器の出力に接続され、
    　前記デシメーションフィルタの出力側において出力データの周波数特性を補償する補償フィルタを備える
    　ことを特徴とするＡ／Ｄ変換器。     An adder for calculating a difference between an analog input signal and a predicted value, a quantizer for quantizing the difference output from the adder, and a predicted value generated from a signal output from the quantizer A / D converter comprising: a prediction filter; and a decimation filter for limiting the frequency band of the A / D conversion output and converting the analog input signal input to the adder into a digital signal and outputting the digital signal. In
    The decimation filter is connected to the output of the quantizer,
    An A / D converter comprising a compensation filter which compensates frequency characteristics of output data at an output side of the decimation filter.
  2. 　前記デシメーションフィルタは、
    　前記量子化器の出力に接続されて、前記量子化器のデータ周波数より低くＡ／Ｄ変換出力のデータ周波数よりも高い中間データ周波数にデータ周波数を引き下げる第１のデシメーションフィルタと、
    　前記補償フィルタの出力に接続されて、前記第１のデシメーションフィルタによって引き下げられた前記中間データ周波数からＡ／Ｄ変換出力のデータ周波数にデータ周波数をさらに引き下げる第２のデシメーションフィルタとに分割される
    　ことを特徴とする請求項１に記載のＡ／Ｄ変換器。     The decimation filter
    A first decimation filter connected to the output of the quantizer to lower the data frequency to an intermediate data frequency lower than the data frequency of the quantizer and higher than the data frequency of the A / D conversion output;
    Being connected to the output of the compensation filter and divided into a second decimation filter that further reduces the data frequency from the intermediate data frequency pulled down by the first decimation filter to the data frequency of the A / D conversion output. The A / D converter according to claim 1, characterized in that
  3. 　前記デシメーションフィルタまたは前記第１のデシメーションフィルタは、２次以上のｓｉｎｃフィルタによって構成されることを特徴とする請求項１または請求項２に記載のＡ／Ｄ変換器。 The A / D converter according to claim 1 or 2, wherein the decimation filter or the first decimation filter is configured by a second-order or higher-order sinc filter.
  4. 　前記加算器と前記量子化器との間に積分器を備えることを特徴とする請求項１から請求項３のいずれか１項に記載のＡ／Ｄ変換器。 The A / D converter according to any one of claims 1 to 3, further comprising an integrator between the adder and the quantizer.
  5. 　前記補償フィルタは積分器で構成されることを特徴とする請求項１から請求項４のいずれか１項に記載のＡ／Ｄ変換器。 The A / D converter according to any one of claims 1 to 4, wherein the compensation filter is configured by an integrator.
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JPH10509544A (en) * 1994-11-02 1998-09-14 アドバンスト・マイクロ・ディバイシス・インコーポレーテッド Monolithic PC audio circuit
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