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WO2019085266A1 - 一种栅极驱动电路 - Google Patents

一种栅极驱动电路 Download PDF

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Publication number
WO2019085266A1
WO2019085266A1 PCT/CN2018/071660 CN2018071660W WO2019085266A1 WO 2019085266 A1 WO2019085266 A1 WO 2019085266A1 CN 2018071660 W CN2018071660 W CN 2018071660W WO 2019085266 A1 WO2019085266 A1 WO 2019085266A1
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WO
WIPO (PCT)
Prior art keywords
thin film
signal
film transistor
pull
output
Prior art date
Application number
PCT/CN2018/071660
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English (en)
French (fr)
Inventor
肖军城
戴荣磊
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to KR1020207014488A priority Critical patent/KR102341620B1/ko
Priority to EP18872371.2A priority patent/EP3706111B1/en
Priority to PL18872371.2T priority patent/PL3706111T3/pl
Priority to JP2020522379A priority patent/JP6925524B2/ja
Priority to US15/969,129 priority patent/US10490151B2/en
Publication of WO2019085266A1 publication Critical patent/WO2019085266A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driving circuit.
  • Thin film transistor liquid crystal display has become the mainstream display on the market.
  • the basic principle is that the liquid crystal in the display is deflected by the voltage, changing the direction of light propagation and making the display display. different color.
  • the Gate Driver On Array (GOA) circuit is a technology for integrating a gate driving circuit on an array substrate of a liquid crystal display panel to realize progressive scanning of a gate line.
  • the liquid crystal panel may have a residual level due to pixel capacitance, resulting in image sticking.
  • the technical problem to be solved by the embodiments of the present invention is to provide a gate driving circuit capable of quickly clearing an image on a display when the liquid crystal panel is powered off.
  • the present invention provides a gate driving circuit, the gate driving circuit includes a multi-level gate driving unit, wherein the Nth-level gate driving unit includes:
  • a pull-up control module configured to generate a first control signal when the power is off
  • a pull-up output module configured to output a high level under the control of the first control signal
  • a pull-down control module for generating a second control signal when the power is off
  • a pull-down output module configured to output a low level under the control of the second control signal
  • the output end of the pull-up output module and the output end of the pull-down output module are connected to an output end of the Nth-stage gate driving unit, and when the power is off, the pull-up output module and the pull-down output The module outputs a high level to an output of the Nth stage gate driving unit.
  • the pull-up control module includes a first thin film transistor (NT1), a second thin film transistor (NT2), a fifth thin film transistor (NT5), and a seventh thin film transistor (NT7), wherein the first thin film transistor ( The gate of NT1) is connected to the output signal of the N-2th stage gate driving circuit, the source is connected to the forward scanning signal, and the drain is connected to the drain of the second thin film transistor (NT2); the second film The gate of the transistor (NT2) is connected to the output signal of the N+2 stage gate driving circuit, and the source is connected to the reverse scanning signal; the gate of the fifth thin film transistor (NT5) is connected to the pull-down control module.
  • the output terminal is connected to the drain of the first thin film transistor (NT1), the drain is connected to a low level signal, and the gate of the seventh thin film transistor (NT7) is connected to a high level signal.
  • a drain connected to a drain of the first thin film transistor (NT1), a drain connected to an output of the pull-up control module; wherein the pull-up control module is configured to output a first control of a high level when the power is off a signal, the first control signal being used to turn on the pull-up output module.
  • the pull-up output module includes: a ninth thin film transistor (NT9), a gate of the ninth thin film transistor (NT9) is connected to a drain of the seventh thin film transistor (NT7), and a source is connected to the first clock signal, Leaking the output of the Nth stage gate driving unit.
  • the pull-down control module includes a third thin film transistor (NT3), a fourth thin film transistor (NT4), a sixth thin film transistor (NT6), and an eighth thin film transistor (NT8), wherein the third thin film transistor (NT3)
  • the gate is connected to the forward scan signal, the source is connected to the N+1th clock signal, and the gate of the eighth thin film transistor (NT8) is connected to the drain;
  • the gate of the fourth thin film transistor (NT4) The pole is connected to the reverse scan signal, and the source is connected to the N-1th clock signal, and is connected to the gate of the eighth thin film transistor (NT8);
  • the gate of the sixth thin film transistor (NT6) Connecting a drain of the second thin film transistor (NT2), a source connected to a drain of the eighth thin film transistor (NT8), a drain connected to a low level signal, and a source of the eighth thin film transistor (NT8)
  • the first global control signal is connected, and the drain is connected to the output of the pull-down control module.
  • the pull-down output module includes a tenth thin film transistor (NT10), wherein a gate of the tenth thin film transistor (NT10) is connected to a drain of the eighth thin film transistor (NT8), and a source is connected to a low level. And a signal connected to the output end of the Nth stage gate driving unit, wherein the pull-down output module is turned off under the control of the second control signal, and no signal is output.
  • NT10 tenth thin film transistor
  • NT8 eighth thin film transistor
  • the Nth stage gate driving circuit further includes a reset circuit
  • the Nth stage gate driving unit further includes a reset circuit
  • the reset circuit includes an eleventh thin film transistor (NT11)
  • the tenth A thin film transistor (NT11) has a gate and a source connected to a reset signal, and a drain connected to a drain of the eighth thin film transistor (NT8).
  • the Nth stage gate driving unit further includes a global control module, where the control module includes a twelfth thin film transistor (NT12), the gate thereof is connected to the second global control signal, and the source is connected to a low A level signal is connected to the output of the Nth stage gate driving unit.
  • the control module includes a twelfth thin film transistor (NT12), the gate thereof is connected to the second global control signal, and the source is connected to a low A level signal is connected to the output of the Nth stage gate driving unit.
  • the Nth stage gate driving unit further includes a potential holding module, the potential holding module includes a first capacitor and a second capacitor, wherein the first capacitor is connected to the first thin film transistor (NT1) And the other end is connected to a low level signal; the second end of the second capacitor is connected to the gate of the fifth thin film transistor (NT5), and the other end is connected to a low level signal.
  • the potential holding module includes a first capacitor and a second capacitor, wherein the first capacitor is connected to the first thin film transistor (NT1) And the other end is connected to a low level signal; the second end of the second capacitor is connected to the gate of the fifth thin film transistor (NT5), and the other end is connected to a low level signal.
  • the forward scanning signal is always at a high level, and the reverse scanning signal is always a low level; when the reverse scanning is performed, the reverse The scan signal is always at a high level, and the forward scan signal is always at a low level.
  • a gate of the first thin film transistor (NT1) is connected to an enable signal; the gate In the penultimate stage gate driving unit and the last stage gate driving unit of the driving circuit, the gates of the second thin film transistors (NT2) are all connected to the enable signal.
  • the pull-up control module when the liquid crystal display is powered off, the pull-up control module generates a first control signal of a high level, and controls the pull-up output module to turn on a high level, and the pull-down control module Generating a low level second control signal, controlling the pull-down output module to turn off the non-output signal, thereby outputting the output of the Nth-level gate driving circuit connected to the pull-up output module and the pull-down output module Pull the high level signal output from the output module.
  • the gate line full-on (All Gate On) function can be performed when the power is suddenly turned off during the use of the liquid crystal screen, so that the liquid crystal screen is quickly cleared on the display in the event of power failure. Image, to avoid the afterimage of the display before the display appears.
  • FIG. 1 is a schematic diagram of functional modules of a gate driving unit according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram of a gate driving unit according to a second embodiment of the present invention.
  • Figure 3 is a signal timing diagram of a gate driving unit in a second embodiment of the present invention.
  • a first embodiment of the present invention provides a gate driving circuit.
  • the gate driving circuit includes multiple gate driving units of the same level, and N is set to a positive integer.
  • N is set to a positive integer.
  • the gate driving unit in the embodiment of the present invention includes the following modules: a pull-up control module 101 and a pull-up output module 102. , pull-down control module 103 and pull-down output module 104;
  • the pull-up control module 101 is configured to generate a first control signal when the gate driving circuit is powered off, wherein the first control signal is a high level signal, and is used to control the pull-up output module. 102 conduction;
  • the pull-up output module 102 is configured to output a high level to an output end of the Nth-stage gate driving unit under the action of the first control signal when the gate driving circuit is powered off;
  • the pull-down control module 103 is configured to generate a second control signal when the gate driving circuit is powered off, wherein the second control signal is a low level signal, and is used to control the pull-down output module 103 to be turned off. ;
  • the pull-down output module 104 is configured to output a low level to an output end of the Nth gate driving unit under the action of the second control signal when the gate driving circuit is powered off.
  • the pull-up control module 101 is connected to the pull-down control module 103 and the pull-up output module 102, and the pull-up output module 102 is connected to the pull-down output module 104, and the pull-down control module 103 and the The pull-down output module 104 is connected, and the pull-up output module and the output end of the pull-down output module are connected to the output end of the Nth-stage gate driving unit.
  • the input signal of the Nth stage pull-up control module 101 includes a forward scan signal U2D, a reverse scan signal D2U, an output signal G(n-2) of the N-2th gate drive circuit, and a Nth An output signal G(n+2) of the +2 stage gate driving circuit and a high level signal VGH;
  • the input signal of the pull-up output module 102 includes the first control signal and the Nth-level clock signal CK(n
  • the input signal of the pull-down control module 103 includes the forward scan signal U2D, the reverse scan signal D2U, the N+1th-level clock signal CK(n+1), and the N-1th-level clock signal CK. (n-1), a first global control signal GAS1 and a low level signal VGL;
  • the input signal of the pull-down output module 104 includes the second control signal of the output of the pull-down control module 103 and the low power Flat signal VGL.
  • the Nth stage gate driving circuit is in a forward scanning state, the forward scanning signal U2D is always a high level signal, and the reverse scanning signal D2U and the clock signal CK (including the Nth The clock signal CK(n), the N+1th clock signal CK(n+1) and the N-1th clock signal CK(n-1) are always low level signals, since the display is normally displayed.
  • the start signal (Start Vertical (STV) signal of the gate driving circuit is always a low level signal, so that each stage of the gate driving circuit outputs a low level signal, wherein the STV
  • the signal is used to convert the high level signal to the gate driving circuit when the gate driving circuit is powered off, and the STV signal is equivalent to the output signal of the 0th stage gate driving unit, and is input to the first a first pull-up control module of the stage gate drive unit and a first pull-up control module of the second stage gate drive unit.
  • the STV signal is converted from a low level signal to a high level signal to activate the gate drive circuit, and the forward scan signal U2D maintains a high level signal.
  • the reverse scan signal D2U and the clock signal CK are converted from a low level signal to a high level signal, and the first control signal GAS1 is converted from a high level signal to a low level signal.
  • the pull-up control module 101 causes the output signal G(n) of the forward-scanning signal U2D and the N-2th-level gate driving circuit by the change of the high-low level of the signal. -2), the first control signal of the high level is output by the output signal G(n+2) of the N+2th stage gate driving circuit and the high level signal VGH.
  • the pull-down control module 103 is in the forward scan signal U2D, the reverse scan signal D2U, the (N+1)th clock signal CK(n+1), and the N-1th clock signal CK ( N-1), the first global control signal GAS1 and the low level signal VGL output the second control signal of a low level.
  • the pull-up output module 102 is turned on by the first control signal, and outputs the Nth-level clock signal CK(n) of the high level to the output end of the Nth-stage gate driving circuit.
  • the pull-down output module 104 is turned off by the second control signal, so that the low-level signal VGL cannot be output to the output end of the Nth-stage gate driving circuit, so that the output of the Nth-stage gate driving circuit is made.
  • the terminal outputs a high level signal G(n).
  • the gate driving units of the gate driving circuit each output a high level signal, thereby realizing the gate all-on function, which avoids the image sticking phenomenon.
  • the pull-up control module when the liquid crystal display is powered off, the pull-up control module generates a first control signal of a high level, and controls the pull-up output module to turn on a high level, and at the same time
  • the pull-down control module generates a second control signal of a low level, and controls the pull-down output module to turn off the non-output signal, thereby outputting the Nth-level gate drive circuit connected to the pull-up output module and the pull-down output module
  • the terminal outputs a high level signal that is output through the pull-up output module.
  • a second embodiment of the present invention provides a gate driving circuit, the gate driving circuit includes multiple gate driving units of the same level, and N is a positive integer.
  • FIG. 2 is a gate provided by the second embodiment of the present invention.
  • the circuit diagram of the driving unit, as shown in FIG. 2, the Nth stage gate driving unit includes: a pull-up control module 201, a pull-up output module 202, a pull-down control module 203, a pull-down output module 204, a reset module 205, and global control.
  • Module 206 and potential holding module 207 includes: a pull-up control module 201, a pull-up output module 202, a pull-down control module 203, a pull-down output module 204, a reset module 205, and global control.
  • Module 206 and potential holding module 207 includes: a pull-up control module 201, a pull-up output module 202, a pull-down control module 203, a pull-down output module 204, a reset module 205
  • the pull-up control module 201 is configured to generate a first control signal when the gate driving circuit is powered off, wherein the first control signal is a high level signal, and is used to control the pull-up output module. 202 is turned on when the power is off;
  • the pull-up output module 202 is configured to output a high level to an output end of the Nth-stage gate driving unit under the action of the first control signal when the gate driving circuit is powered off;
  • the pull-down control module 203 is configured to generate a second control signal when the gate driving circuit is powered off, wherein the second control signal is a low level signal, and is used to control the pull-down output module 203 to be Turn off when power is off;
  • the pull-down output module 204 is configured to output a low level to an output end of the Nth gate driving unit under the action of the second control signal when the gate driving circuit is powered off;
  • the reset module 205 is configured to control the turn-on and turn-off of the pull-down output module 204 under the action of the reset signal Reset;
  • the global control module 206 is configured to control an output signal of the Nth stage gate driving circuit by the second global control signal GAS2;
  • the potential holding module 207 is configured to maintain potentials of the P point and the Q point of the Nth stage gate driving circuit.
  • the pull-up control module 201, the pull-up output module 202, the pull-down control module 203, and the potential holding module 207 are connected to the Q point, and the pull-up control module 201 and the pull-down control module 203.
  • the pull-down output module 204, the reset module 205, and the potential holding module 207 are connected to the P point, and the output terminals of the pull-up output module 202, the pull-down output module 203, and the global control module 206 are connected. And an output end of the Nth stage gate driving unit.
  • the input signals of the Nth stage pull-up control module 201 include a forward scan signal U2D, a reverse scan signal D2U, an output signal G(n-2) of the N-2th gate drive circuit, and an N+2 An output signal G(n+2) of the gate drive circuit and a high level signal VGH;
  • the input signal of the pull-up output module 202 includes the first control signal and the Nth-level clock signal CK(n);
  • the input signal of the pull-down control module 203 includes the forward scan signal U2D, the reverse scan signal D2U, the N+1th clock signal CK(n+1), and the N-1th clock signal CK(n -1) a first global control signal GAS1 and a low level signal VGL;
  • the input signal of the pull-down output module 204 includes the second control signal of the output of the pull-down control module 203 and the low level signal VGL;
  • the input signal of the reset control module 205 includes the reset signal Reset;
  • the forward scan signal U2D and the first global control signal GAS1 are always a high level signal when the display is normally displayed, and the Nth stage gate drive circuit is in a forward scan mode, the reverse scan signal D2U and clock signal CK (including Nth stage clock signal CK(n), N+1th stage clock signal CK(n+1) and N-1th stage clock signal CK(n-1)), said second
  • the global control signal GAS2 and the reset signal Reset are always low level signals
  • the start signal (Start Vertical (STV) signal of the gate driving circuit is always a low level signal when the display is normally displayed, so that the Each stage of the gate driving circuit outputs a low level signal, wherein the STV signal is used to convert to a high level signal when the gate driving circuit is powered off, and the gate is activated.
  • a driving circuit the STV signal is equivalent to an output signal of the 0th stage gate driving unit, and the first pull-up control is input to the first pull-up control module and the second-stage gate driving unit of the
  • the STV signal When the display is powered off during normal display, the STV signal is converted from a low level signal to a high level signal to activate the gate drive circuit, and the forward scan signal U2D maintains a high level signal.
  • the second global control signal GAS2 and the reset signal Reset are held at a low level, and the reverse scan signal D2U and the clock signal CK are converted from a low level signal to a high level signal, the first control The signal GAS1 is converted from a high level signal to a low level signal.
  • the pull-up control module 101 causes the output signal G(n) of the forward-scanning signal U2D and the N-2th-level gate driving circuit by the change of the high-low level of the signal. -2), the first control signal of the high level is output by the output signal G(n+2) of the N+2th stage gate driving circuit and the high level signal VGH.
  • the pull-down control module 103 is in the forward scan signal U2D, the reverse scan signal D2U, the (N+1)th clock signal CK(n+1), and the N-1th clock signal CK ( N-1), the first global control signal GAS1 and the low level signal VGL output the second control signal of a low level.
  • the pull-up output module 102 is turned on by the first control signal, and outputs the Nth-level clock signal CK(n) of the high level to the output end of the Nth-stage gate driving circuit.
  • the pull-down output module 104 is turned off by the second control signal, so that the low-level signal VGL cannot be output to the output end of the N-th stage gate driving circuit, so that the output of the N-th stage gate driving circuit is made.
  • the terminal outputs a high level signal G(n).
  • all the gate driving units of the gate driving circuit output a high level signal, thereby realizing the All Gate On function of the gate line, so that the liquid crystal screen quickly clears the display in the event of power failure.
  • the image on the screen prevents the image from appearing before the monitor appears.
  • the Nth stage gate driving unit and each module thereof will be specifically described below with reference to FIG. 2 .
  • the pull-up control module 201 includes a first thin film transistor NT1, a second thin film transistor NT2, a fifth thin film transistor NT5, and a seventh thin film transistor NT7, wherein a drain of the seventh thin film transistor NT7 is the upper The output of the control module 201 is pulled.
  • the gate of the first thin film transistor NT1 is connected to the output signal (G(n-2)) of the N-2th stage gate driving circuit, and the source is connected to the forward scanning signal (U2D), and the drain connection is connected.
  • a gate of the second thin film transistor NT2 is connected to an output signal (G(n+2)) of the N+2th gate driving circuit, and the source is reversed a scan signal (D2U);
  • a gate of the fifth thin film transistor NT5 is connected to an output end of the pull-down control module, a source is connected to a drain of the first thin film transistor NT1, and a drain is connected to the low-level signal (VGL);
  • the gate of the seventh thin film transistor NT7 is connected to a high level signal (VGH), the source is connected to the drain of the first thin film transistor NT1, and the drain is connected to the output of the pull-up control module. end.
  • the pull-up output module 202 includes a ninth thin film transistor NT9. a gate of the ninth thin film transistor NT9 is connected to an output end of the pull-up output module, a source is connected to the first clock signal CK(n), and a drain is connected to an output end of the Nth-stage gate driving circuit. .
  • the pull-down control module 203 includes a third thin film transistor NT3, a fourth thin film transistor NT4, a sixth thin film transistor NT6, and an eighth thin film transistor NT8, wherein the sixth thin film transistor NT6 and the eighth thin film transistor NT8 are drained. Connected as the output of the pull-down control module 203.
  • the gate of the third thin film transistor NT3 is connected to the forward scan signal (U2D), the source is connected to the N+1th clock signal (CK(n+1)), and the drain is connected to the eighth a gate of the thin film transistor NT8; a gate of the fourth thin film transistor NT4 is connected to the reverse scan signal (D2U), and a source is connected to a clock signal of the N-1th stage (CK(n-1)), a drain is connected to the gate of the eighth thin film transistor NT8; a gate of the sixth thin film transistor NT6 is connected to a drain of the second thin film transistor NT2, and a source is connected to a drain of the eighth thin film transistor NT8, and a drain Accessing a low level signal (VGL); a gate of the eighth thin film transistor NT8 is connected to drains of the third thin film transistor NT3 and the fourth thin film transistor NT4, and a source is connected to the first global control signal (GAS1), the drain is connected to the drain of the sixth thin film transistor
  • the pull-down output module includes a tenth thin film transistor NT10, wherein a gate of the tenth thin film transistor NT10 is connected to a drain of the sixth thin film transistor NT6 and the eighth thin film transistor NT8, and a source is connected to the source A low level signal (VGL) is connected to the output of the Nth stage gate driving circuit.
  • the reset module 205 includes an eleventh thin film transistor NT11, wherein a gate and a source of the eleventh thin film transistor NT11 are connected to the reset signal Reset, and a drain is connected to a gate of the tenth thin film transistor NT10. .
  • the global control module 206 includes a twelfth thin film transistor NT12, wherein a source of the twelfth thin film transistor NT12 is connected to the second global control signal GAS2, and a source is connected to the low level signal VGL.
  • the output terminal of the Nth stage gate driving circuit is connected to the drain.
  • the potential holding module 207 includes a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 is connected to the drain of the first thin film transistor NT1 and the other end is connected to the low level signal. VGL; one end of the second capacitor C2 is connected to the drain of the eighth thin film transistor NT8, and the other end is connected to the low level signal VGL.
  • the Nth stage gate driving is performed. The operation of the unit under the action of the signal timing control is described.
  • the display normally works display screen, the start signal (Start Vertical, STV) of the gate driving circuit, the reverse scan signal D2U, and the clock signal CK (including the Nth clock) Signal CK(n), N+1th clock signal CK(n+1) and N-1th clock signal CK(n-1), the second global control signal GAS2, and the reset signal Reset
  • the low level signal is always low, wherein the STV signal is connected to the gates of the first thin film transistors NT1 of the first stage gate driving unit and the second level gate driving unit.
  • the first stage gate driving unit and the second level gate unit Since the STV signal is at a low level, in the first stage gate driving unit and the second level gate unit, the first thin film transistor NT1 is in a closed state, then the first stage a corresponding pull-up control unit of the gate driving unit and the second-level gate unit has no level signal output, so that a corresponding one of the first-stage gate driving unit and the second-level gate unit The pull output unit is in an off state, and no signal is output to the output terminals of the first stage gate drive unit and the second stage gate unit.
  • the first stage gate driving unit and the second level gate unit are The eighth thin film transistor NT8 and the eleventh thin film transistor NT11 are in a closed state, and the corresponding pull-down control unit of the first-stage gate driving unit and the second-level gate unit has no level signal output, so that the a corresponding one of the first stage gate driving unit and the second stage gate unit is in a closed state, and no signal is output to the first stage gate driving unit and the second level gate unit Output.
  • the output terminals of the first-stage gate driving unit and the second-stage gate unit have no signal output, so that the N-th gate driving unit is deduced when the display is normally operated.
  • the gate input signal G(n-2) of the first thin film transistor NT1 is zero, and the Nth stage gate driving unit has no output signal.
  • the second timing phase shown in FIG. 3 indicates that the STV signal is converted from a low level signal to a high level signal, and the gate driving circuit is activated.
  • the forward scan signal U2D maintains a high level signal
  • the second global control signal GAS2 and the reset signal Reset are held at a low level
  • the reverse scan signal D2U and the clock signal CK are converted from a low level signal to A high level signal
  • the first control signal GAS1 is converted from a high level signal to a low level signal.
  • the first thin film transistor NT1 is in an on state
  • the seventh thin film transistor NT7 is also turned on under the VGH limit number.
  • the forward scan signal U2D of the high level flows into the gate of the ninth thin film transistor NT9 through the first thin film transistor NT1 and the seventh thin film transistor NT7, and the ninth thin film transistor NT9 is turned on. And causing the high-level timing signal CK signal to flow into the output ends of the first-stage gate driving unit and the second-stage gate unit through the ninth thin film transistor NT9.
  • the third thin film transistor NT3 and the fourth thin film transistor of the first stage gate driving unit and the second level gate unit are The NT4 is turned on, and the high-level timing signal CK flows into the gate of the eighth thin film transistor NT8 through the third thin film transistor NT3 and the fourth thin film transistor NT4, and the eighth thin film transistor NT8 is turned on, thereby
  • the first global control signal GAS1 of a low level flows into the gate of the tenth thin film transistor NT10, the tenth thin film transistor NT10 is turned off, and no signal is output to the first stage gate driving unit. And an output of the second stage gate unit.
  • the thin film transistor NT12 remains in the off state, and no signal is output to the output terminals of the first stage gate driving unit and the second level gate unit. . Therefore, in the first-stage gate driving unit and the second-level gate unit, only the high-level timing signal CK flows into the first-stage gate driving through the ninth thin film transistor NT9. And the output of the second stage gate unit causes the first stage gate driving unit and the second stage gate unit to output a high level signal.
  • the first thin film transistor in the Nth-stage gate driving circuit can be obtained by the timing change when the normal display screen of the display is powered off and the change of the output signal of the gate driving unit.
  • the gate input signal G(N-2) of NT1 is at a high level
  • the first thin film transistor NT1 is in an on state
  • the seventh thin film transistor NT7 is also in an on state under the VGH limit number, so as to be high.
  • the forward scan signal U2D of the level flows into the gate of the ninth thin film transistor NT9 through the first thin film transistor NT1 and the seventh thin film transistor NT7, and the ninth thin film transistor NT9 is turned on, thereby
  • the high-level timing signal CK signal flows into the output terminals of the first-stage gate driving unit and the second-stage gate unit through the ninth thin film transistor NT9.
  • the same analysis shows that the third thin film transistor NT3 and the fourth thin film transistor NT4 in the Nth stage gate driving unit are turned on because the reverse scan signal D2U is converted to a high level, the high level
  • the timing signal CK flows into the gate of the eighth thin film transistor NT8 through the third thin film transistor NT3 and the fourth thin film transistor NT4, and turns on the eighth thin film transistor NT8, thereby causing the first global control of the low level.
  • the signal GAS1 flows into the gate of the tenth thin film transistor NT10 such that the tenth thin film transistor NT10 is turned off, and no signal is output to the output terminal of the Nth stage gate driving unit.
  • the twelfth thin film transistor NT12 remains in the off state, and no signal is output to the output terminal of the Nth stage gate driving unit. Therefore, in the Nth-stage gate driving unit, only the high-level timing signal CK(n) flows into the output terminal of the N-th gate driving unit through the ninth thin film transistor NT9, so that The Nth stage gate driving unit outputs a high level signal.
  • each stage of the gate driving unit in the gate driving circuit outputs a high level signal, thereby realizing the All Gate On function at the time of power failure.
  • the pull-up control module when the liquid crystal display is powered off, the pull-up control module generates a first control signal of a high level, and controls the pull-up output module to turn on a high level, and the pull-down control module Generating a low level second control signal, controlling the pull-down output module to turn off the non-output signal, thereby outputting the output of the Nth-level gate driving circuit connected to the pull-up output module and the pull-down output module Pulling the high-level signal output from the output module to realize the All Gate On function during power-off, so that the LCD screen can quickly clear the image on the display in the event of power failure, and avoid the residual image of the display before the display appears.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

一种栅极驱动电路，包括：上拉控制模块（101、201），用于在断电时产生第一控制信号；上拉输出模块（102、202），用于在第一控制信号的控制下输出高电平；下拉控制模块（103、203），用于在断电时产生第二控制信号；下拉输出模块（104、204），用于在第二控制信号的控制下输出低电平。其中，上拉输出模块（102、202）的输出端和下拉输出模块（104、204）的输出端连接第N级栅极驱动单元的输出端，在断电时，上拉输出模块（102、202）和下拉输出模块（104、204）使第N级栅极驱动单元的输出端输出高电平。能够在使用液晶屏过程中突然发生断电的情况下，迅速清除屏幕上的影像，避免显示器出现之前显示画面的残影。

Description

一种栅极驱动电路 技术领域
本发明涉及显示技术领域，尤其涉及一种栅极驱动电路。
背景技术
薄膜晶体管液晶显示器(Thin film transistor liquid crystal display，TFT-LCD)现已成为市场上主流的显示器，其基本原理是显示器中的液晶在电压的驱动下发生偏转，改变光的传播方向从而使显示器显示不同的颜色。阵列基板栅极驱动(Gate Driver OnArray，GOA)电路，是将栅极驱动电路集成在液晶显示面板的阵列基板上，以实现对栅线逐行扫描的一项技术。在实际的使用中，在液晶显示断电后，液晶屏由于像素电容中可能会残留电平，从而导致残影现象。现有技术中，缺乏行之有效的机制来防止该现象的产生。
发明内容
本发明实施例所要解决的技术问题在于，提供一种栅极驱动电路，能够在液晶屏发生断电的情况下，迅速清除显示器上的影像。
本发明提供了一种栅极驱动电路，所述栅极驱动电路包括多级栅极驱动单元，其中，第N级栅极驱动单元包括：
上拉控制模块，用于在断电时产生第一控制信号；
上拉输出模块，用于在所述第一控制信号的控制下输出高电平；
下拉控制模块，用于在断电时产生第二控制信号；
下拉输出模块，用于在所述第二控制信号的控制下输出低电平；
其中，所述上拉输出模块的输出端和所述下拉输出模块的输出端连接所述第N级栅极驱动单元的输出端，在断电时，所述上拉输出模块和所述下拉输出模块使所述第N级栅极驱动单元的输出端输出高电平。
其中，所述上拉控制模块包括第一薄膜晶体管(NT1)、第二薄膜晶体管(NT2)、第五薄膜晶体管(NT5)和第七薄膜晶体管(NT7)，其中，所述第一薄膜晶体管(NT1)的栅极接入第N-2级栅极驱动电路的输出信号，源极接入正向扫描信 号，漏接连接所述第二薄膜晶体管(NT2)的漏极；所述第二薄膜晶体管(NT2)的栅极接入第N+2级栅极驱动电路的输出信号，源极接入反向扫描信号；所述第五薄膜晶体管(NT5)的栅极连接所诉下拉控制模块的输出端，源极连接所述第一薄膜晶体管(NT1)的漏级，漏极接入一低电平信号；所述第七薄膜晶体管(NT7)的栅极接入一高电平信号，源极连接所述第一薄膜晶体管(NT1)的漏级，漏极连接所述上拉控制模块的输出端；其中，所述上拉控制模块用于在断电时输出高电平的第一控制信号，所述第一控制信号用于使所述上拉输出模块导通。
所述上拉输出模块包括：第九薄膜晶体管(NT9)，所述第九薄膜晶体管(NT9)栅极连接所述第七薄膜晶体管(NT7)的漏极，源极接入第一时钟信号，漏接接所述第N级栅极驱动单元的输出端。
所述下拉控制模块包括第三薄膜晶体管(NT3)、第四薄膜晶体管(NT4)、第六薄膜晶体管(NT6)和第八薄膜晶体管(NT8)，其中，所述第三薄膜晶体管(NT3)的栅极接入所述正向扫描信号，源极接入第N+1级时钟信号，漏接连接所述第八薄膜晶体管(NT8)的栅极；所述第四薄膜晶体管(NT4)的栅极接入所述反向扫描信号，源极接入第N-1级时钟信号，漏接连接所述第八薄膜晶体管(NT8)的栅极；所述第六薄膜晶体管(NT6)的栅极连接所述第二薄膜晶体管(NT2)的漏极，源极连接第八薄膜晶体管(NT8)的漏级，漏极接入一低电平信号；所述第八薄膜晶体管(NT8)的源极接入第一全局控制信号，漏极连接所述下拉控制模块的输出端。其中，所述下拉控制模块用于在断电时输出低电平的第二控制信号，所述第二控制信号用于使所述下拉输出模块关闭。
所述下拉输出模块包括第十薄膜晶体管(NT10)，其中，所述第十薄膜晶体管(NT10)的栅极连接所述第八薄膜晶体管(NT8)的漏极，源极接入一低电平信号，漏极连接所述第N级栅极驱动单元的输出端，其中，所述下拉输出模块在所述第二控制信号的控制下关闭，无信号输出。
可选地，所述第N级栅极驱动电路还包括复位电路，所述第N级栅极驱动单元还包括复位电路，所述复位电路包括第十一薄膜晶体管(NT11)，所述第十一薄膜晶体管(NT11)的栅极与源极接入复位信号，漏极连接所述第八薄膜晶体管(NT8)的漏极。
可选地，所述第N级栅极驱动单元还包括全局控制模块，所述控制模块包括第十二薄膜晶体管(NT12)，其栅极接入第二全局控制信号，源极接入一低电 平信号，漏极连接所述第N级栅极驱动单元的输出端。
可选地，所述第N级栅极驱动单元还包括电位保持模块，所述电位保持模块包括第一电容和第二电容，其中，所述第一电容一端连接所述第一薄膜晶体管(NT1)的漏极，另一端接入一低电平信号；所述第二电容一端连接所述第五薄膜晶体管(NT5)的栅极，另一端接入一低电平信号。
可选地，所述栅极驱动单元正常工作正向扫描时，所述正向扫描信号恒为高电平，所述反向扫描信号恒为低电平；反向扫描时，所述反向扫描信号恒为高电平，所述正向扫描信号恒为低电平。
可选地，所述栅极驱动电路的第一级栅极驱动单元和第二级栅极驱动单元中，所述第一薄膜晶体管(NT1)的栅极均接入启动信号；所述栅极驱动电路的倒数第二级栅极驱动单元和最后一级栅极驱动单元中，所述第二薄膜晶体管(NT2)的栅极均接入所述启动信号。
通过实施本发明实施例，在液晶显示器断电时，所述上拉控制模块产生高电平的第一控制信号，控制所述上拉输出模块导通输出高电平，同时所述下拉控制模块产生低电平的第二控制信号，控制所述下拉输出模块关闭不输出信号，从而使与所述上拉输出模块和下拉输出模块相连的所述第N级栅极驱动电路输出端输出通过上拉输出模块输出的高电平信号。通过实施本发明实施例能够在使用液晶屏过程中突然发生断电的情况下断电时的栅线全开(All Gate On)功能，使液晶屏在发生断电的情况下，迅速清除显示器上的影像，避免显示器出现之前显示画面的残影。
背景技术
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例提供的栅极驱动单元的功能模块示意图；
图2是本发明第二实施例提供的栅极驱动单元的电路图；
图3是本发明第二实施例中的栅极驱动单元的信号时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本发明的说明书和权利要求书及上述附图中的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其他步骤或单元。
需要说明的是，下面详细描述本发明的实施例，以及在所述实施例的附图中，其中相同或类似的标号表示相同或类似的元件，或者相同或类似的信号，又或者表示具有相同或类似功能的元件或信号。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。
在本发明的描述中，需要说明的是，除非另有规定和限定，术语“安装”、“相连”、“连接”、“接”应做广义理解，例如，可以是机械连接或电连接，也可以是两个元件内部的连通，可以是直接相连，也可以通过中间媒介间接相连，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。
本发明第一实施例提供一种栅极驱动电路，所述栅极驱动电路包括多级相同的栅极驱动单元，设定N为正整数，第N级栅极驱动单元请参阅图1，图1 是本发明实施例提供的栅极驱动单元的功能模块示意图，如图1所示，本发明实施例中的所述栅极驱动单元包括以下模块：上拉控制模块101、上拉输出模块102、下拉控制模块103和下拉输出模块104；
其中，所述上拉控制模块101，用于在栅极驱动电路断电时，产生第一控制信号，其中，所述第一控制信号为高电平信号，用于控制所述上拉输出模块102导通；
所述上拉输出模块102，用于在所述栅极驱动电路断电时，在所述第一控制信号的作用下输出高电平至所述第N级栅极驱动单元的输出端；
所述下拉控制模块103，用于在所述栅极驱动电路断电时，产生第二控制信号，其中，所述第二控制信号为低电平信号，用于控制所述下拉输出模块103关闭；
所述下拉输出模块104，用于在所述栅极驱动电路断电时，在所述第二控制信号的作用下，输出低电平至所述第N栅极驱动单元的输出端。
其中，所述上拉控制模块101与所述下拉控制模块103、所述上拉输出模块102连接，所述上拉输出模块102与所述下拉输出模块104连接，所述下拉控制模块103与所述下拉输出模块104连接，所述上拉输出模块与所述下拉输出模块的输出端连接所述第N级栅极驱动单元的输出端。
其中，所述第N级的上拉控制模块101的输入信号包括正向扫描信号U2D、反向扫描信号D2U、第N-2级栅极驱动电路的输出信号G(n-2)、第N+2级栅极驱动电路的输出信号G(n+2)以及一高电平信号VGH；所述上拉输出模块102的输入信号包括所述第一控制信号以及第N级时钟信号CK(n)；所述下拉控制模块103的输入信号包括所述正向扫描信号U2D、所述反向扫描信号D2U、第N+1级时钟信号CK(n+1)、第N-1级时钟信号CK(n-1)、第一全局控制信号GAS1以及一低电平信号VGL；所述下拉输出模块104的输入信号包括所述下拉控制模块103的输出的所述第二控制信号以及所述低电平信号VGL。
若显示器正常显示画面，所述第N级栅极驱动电路在正向扫描时，所述正向扫描信号U2D恒为高电平信号，所述反向扫描信号D2U和时钟信号CK(包括第N级时钟信号CK(n)，第N+1级时钟信号CK(n+1)和第N-1级时钟信号CK(n-1))恒为低电平信号，由于在显示器正常显示时，所述栅极驱动电路的启动信号(Start Vertical，STV)信号恒为低电平信号，使得所述栅极驱动电路的每一 级栅极驱动单元都输出低电平信号，其中，所述STV信号用于在所述栅极驱动电路断电时，转换为高电平信号，启动所述栅极驱动电路，所述STV信号相当于第0级栅极驱动单元的输出信号，输入到第一级栅极驱动单元的第一上拉控制模块和第二级栅极驱动单元的第一上拉控制模块。
当所述显示器在正常显示时出现断电，此时所述STV信号由低电平信号转换为高电平信号，启动所述栅极驱动电路，所述正向扫描信号U2D保持高电平信号，所述反向扫描信号D2U和所述时钟信号CK由低电平信号转换为高电平信号，所述第一控制信号GAS1由高电平信号转换为低电平信号。
在上述断电情况下，由上述信号高低电平的变化，使所述上拉控制模块101在所述正向扫描信号U2D、所述第N-2级栅极驱动电路的输出信号G(n-2)、所述第N+2级栅极驱动电路的输出信号G(n+2)以及所述高电平信号VGH的作用下输出高电平的所述第一控制信号。所述下拉控制模块103在所述正向扫描信号U2D、所述反向扫描信号D2U、所述第N+1级时钟信号CK(n+1)、所述第N-1级时钟信号CK(n-1)、所述第一全局控制信号GAS1以及所述低电平信号VGL的作用下输出低电平的所述第二控制信号。所述上拉输出模块102在所述第一控制信号作用下导通，使高电平的所述第N级时钟信号CK(n)输出到所述第N级栅极驱动电路的输出端，所述下拉输出模块104在所述第二控制信号作用下关闭，使低电平信号VGL无法输出到所述第N级栅极驱动电路的输出端，从而使第N级栅极驱动电路的输出端输出高电平的信号G(n)。同理，所述栅极驱动电路的各级栅极驱动单元均输出高电平信号，从而实现栅线全开(All Gate On)功能，是所述显示器避免出现残影现象。
可以看出，通过实施本发明实施例，在液晶显示器断电时，所述上拉控制模块产生高电平的第一控制信号，控制所述上拉输出模块导通输出高电平，同时所述下拉控制模块产生低电平的第二控制信号，控制所述下拉输出模块关闭不输出信号，从而使与所述上拉输出模块和下拉输出模块相连的所述第N级栅极驱动电路输出端输出通过上拉输出模块输出的高电平信号。通过实施本发明实施例能够在使用液晶屏过程中突然发生断电的情况下实现All Gate On功能，迅速清除显示器上的影像，避免显示器出现之前显示画面的残影。
本发明第二实施例提供一种栅极驱动电路，所述栅极驱动电路包括多级相同的栅极驱动单元，设定N为正整数，图2是本发明第二实施例提供的栅极驱 动单元的电路图，如图2所示，所述第N级栅极驱动单元包括：上拉控制模块201、上拉输出模块202、下拉控制模块203、下拉输出模块204、复位模块205、全局控制模块206和电位保持模块207。
其中，所述上拉控制模块201，用于在栅极驱动电路断电时，产生第一控制信号，其中，所述第一控制信号为高电平信号，用于控制所述上拉输出模块202在断电时导通；
所述上拉输出模块202，用于在所述栅极驱动电路断电时，在所述第一控制信号的作用下输出高电平至所述第N级栅极驱动单元的输出端；
所述下拉控制模块203，用于在所述栅极驱动电路断电时，产生第二控制信号，其中，所述第二控制信号为低电平信号，用于控制所述下拉输出模块203在断电时关闭；
所述下拉输出模块204，用于在所述栅极驱动电路断电时，在所述第二控制信号的作用下，输出低电平至所述第N栅极驱动单元的输出端；
所述复位模块205，用于在所述复位信号Reset的作用下，控制所述下拉输出模块204的导通和关闭；
所述全局控制模块206，用于在所述第二全局控制信号GAS2的作用下，控制所述第N级栅极驱动电路的输出信号；
所述电位保持模块207，用于保持所述第N级栅极驱动电路的P点和Q点的电位。
其中，所述上拉控制模块201、所述上拉输出模块202、所述下拉控制模块203和所述电位保持模块207连接于Q点，所述上拉控制模块201、所述下拉控制模块203、所述下拉输出模块204、所述复位模块205和所述电位保持模块207连接于P点，所述上拉输出模块202、所述下拉输出模块203以及所述全局控制模块206的输出端连接于所述第N级栅极驱动单元的输出端。
所述第N级的上拉控制模块201的输入信号包括正向扫描信号U2D、反向扫描信号D2U、第N-2级栅极驱动电路的输出信号G(n-2)、第N+2级栅极驱动电路的输出信号G(n+2)以及一高电平信号VGH；所述上拉输出模块202的输入信号包括所述第一控制信号以及第N级时钟信号CK(n)；所述下拉控制模块203的输入信号包括所述正向扫描信号U2D、所述反向扫描信号D2U、第N+1级时钟信号CK(n+1)、第N-1级时钟信号CK(n-1)、第一全局控制信号GAS1以及一 低电平信号VGL；所述下拉输出模块204的输入信号包括所述下拉控制模块203的输出的所述第二控制信号以及所述低电平信号VGL；所述复位控制模块205的输入信号包括所述复位信号Reset；所述全局控制模块206的输入信号包括所述第二全局控制信号GAS2和所述低电平信号VGL；所述电位保持模块的输入限号包括所述低电平信号VGL。
若显示器正常显示画面，所述第N级栅极驱动电路在正向扫描时，所述正向扫描信号U2D和所述第一全局控制信号GAS1恒为高电平信号，所述反向扫描信号D2U和时钟信号CK(包括第N级时钟信号CK(n)，第N+1级时钟信号CK(n+1)和第N-1级时钟信号CK(n-1))、所述第二全局控制信号GAS2和所述复位信号Reset恒为低电平信号，由于在显示器正常显示时，所述栅极驱动电路的启动信号(Start Vertical，STV)信号恒为低电平信号，使得所述栅极驱动电路的每一级栅极驱动单元都输出低电平信号，其中，所述STV信号用于在所述栅极驱动电路断电时，转换为高电平信号，启动所述栅极驱动电路，所述STV信号相当于第0级栅极驱动单元的输出信号，输入到第一级栅极驱动单元的第一上拉控制模块和第二级栅极驱动单元的第一上拉控制模块。
当所述显示器在正常显示时出现断电，此时所述STV信号由低电平信号转换为高电平信号，启动所述栅极驱动电路，所述正向扫描信号U2D保持高电平信号，所述第二全局控制信号GAS2和所述复位信号Reset保持低电平，所述反向扫描信号D2U和所述时钟信号CK由低电平信号转换为高电平信号，所述第一控制信号GAS1由高电平信号转换为低电平信号。
在上述断电情况下，由上述信号高低电平的变化，使所述上拉控制模块101在所述正向扫描信号U2D、所述第N-2级栅极驱动电路的输出信号G(n-2)、所述第N+2级栅极驱动电路的输出信号G(n+2)以及所述高电平信号VGH的作用下输出高电平的所述第一控制信号。所述下拉控制模块103在所述正向扫描信号U2D、所述反向扫描信号D2U、所述第N+1级时钟信号CK(n+1)、所述第N-1级时钟信号CK(n-1)、所述第一全局控制信号GAS1以及所述低电平信号VGL的作用下输出低电平的所述第二控制信号。所述上拉输出模块102在所述第一控制信号作用下导通，使高电平的所述第N级时钟信号CK(n)输出到所述第N级栅极驱动电路的输出端，所述下拉输出模块104在所述第二控制信号作用下关闭，使低电平信号VGL无法输出到所述第N级栅极驱动电路的输出端， 从而使第N级栅极驱动电路的输出端输出高电平的信号G(n)。同理，所述栅极驱动电路的各级栅极驱动单元均输出高电平信号，从而实现栅线全开(All Gate On)功能，使液晶屏在发生断电的情况下，迅速清除显示器上的影像，避免显示器出现之前显示画面的残影。
下面结合图2对所述第N级栅极驱动单元及其各模块进行具体介绍。
具体的，所述上拉控制模块201包括第一薄膜晶体管NT1、第二薄膜晶体管NT2、第五薄膜晶体管NT5和第七薄膜晶体管NT7，其中，所述第七薄膜晶体管NT7的漏极为所述上拉控制模块201的输出端。
其中，所述第一薄膜晶体管NT1的栅极接入第N-2级栅极驱动电路的输出信号(G(n-2))，源极接入正向扫描信号(U2D)，漏接连接所述第二薄膜晶体管NT2的漏极；所述第二薄膜晶体管NT2的栅极接入第N+2级栅极驱动电路的输出信号(G(n+2))，源极接入反向扫描信号(D2U)；所述第五薄膜晶体管NT5的栅极连接所述下拉控制模块的输出端，源极连接所述第一薄膜晶体管NT1的漏级，漏极接入所述低电平信号(VGL)；所述第七薄膜晶体管NT7的栅极接入一高电平信号(VGH)，源极连接所述第一薄膜晶体管NT1的漏级，漏极连接所述上拉控制模块的输出端。
所述上拉输出模块202包括：第九薄膜晶体管NT9。所述第九薄膜晶体管NT9栅极连接所述上拉输出模块的输出端，源极接入所述第一时钟信号CK(n)，漏接接所述第N级栅极驱动电路的输出端。
所述下拉控制模块203包括第三薄膜晶体管NT3、第四薄膜晶体管NT4、第六薄膜晶体管NT6和第八薄膜晶体管NT8，其中，所述第六薄膜晶体管NT6和所述第八薄膜晶体管NT8的漏接相连作为所述下拉控制模块203的输出端。所述第三薄膜晶体管NT3的栅极接入所述正向扫描信号(U2D)，源极接入第N+1级的时钟信号(CK(n+1))，漏接连接所述第八薄膜晶体管NT8的栅极；所述第四薄膜晶体管NT4的栅极接入所述反向扫描信号(D2U)，源极接入第N-1级的时钟信号(CK(n-1))，漏接连接所述第八薄膜晶体管NT8的栅极；所述第六薄膜晶体管NT6的栅极连接所述第二薄膜晶体管NT2的漏极，源极连接第八薄膜晶体管NT8的漏级，漏极接入以低电平信号(VGL)；所述第八薄膜晶体管NT8的栅极连接所述第三薄膜晶体管NT3和所述第四薄膜晶体管NT4的漏极，源极接入第一全局控制信号(GAS1)，漏极连接所述第六薄膜晶体管NT6的漏极。
所述下拉输出模块包括第十薄膜晶体管NT10，其中，所述第十薄膜晶体管NT10的栅极连接所述第六薄膜晶体管NT6和所述第八薄膜晶体管NT8的漏接，源极接入所述低电平信号(VGL)，漏极连接所述第N级栅极驱动电路的输出端。
所述复位模块205包括第十一薄膜晶体管NT11，其中，所述第十一薄膜晶体管NT11的栅极和源极接入所述复位信号Reset，漏极接所述第十薄膜晶体管NT10的栅极。
所述全局控制模块206包括第十二薄膜晶体管NT12，其中，所述第十二薄膜晶体管NT12的源极接入所述第二全局控制信号GAS2，源极接入所述低电平信号VGL，漏接连接所述第N级栅极驱动电路的输出端。
所述电位保持模块207包括第一电容C1和所述第二电容C2，其中，所述第一电容C1一端接所述第一薄膜晶体管NT1的漏极，另一端接入所述低电平信号VGL；所述第二电容C2一端接所述第八薄膜晶体管NT8的漏极，另一端接所述低电平信号VGL。
结合图2所示的第N级栅极驱动单元的具体接线图，以及图3所示的本发明第二实施例中的栅极驱动单元的信号时序图，对所述第N级栅极驱动单元在所述信号时序控制作用下的运行过程进行介绍。
在图3所示的第一时序阶段，显示器正常工作显示画面，所述栅极驱动电路的启动信号(Start Vertical，STV)、所述反向扫描信号D2U、时钟信号CK(包括第N级时钟信号CK(n)，第N+1级时钟信号CK(n+1)和第N-1级时钟信号CK(n-1))、所述第二全局控制信号GAS2和所述复位信号Reset恒为低电平信号恒为低电平，其中，所述STV信号接入第一级栅极驱动单元和第二级栅极驱动单元中第一薄膜晶体管NT1的栅极。由于所述STV信号为低电平，则在所述第一级栅极驱动单元和所述第二级栅极单元的中，所述第一薄膜晶体管NT1为关闭状态，则所述第一级栅极驱动单元和所述第二级栅极单元中对应的上拉控制单元无电平信号输出，使所述第一级栅极驱动单元和所述第二级栅极单元的中对应的上拉输出单元为关闭状态，无信号输出到所述第一级栅极驱动单元和所述第二级栅极单元的输出端。
可以理解的是，显示器正常工作显示画面时，由于所述时钟信号CK和所述复位信号Reset为低电平，则所述第一级栅极驱动单元和所述第二级栅极单元中第八薄膜晶体管NT8和第十一薄膜晶体管NT11为关闭状态，则所述第一级栅 极驱动单元和所述第二级栅极单元中对应的下拉拉控制单元无电平信号输出，使所述第一级栅极驱动单元和所述第二级栅极单元的中对应的下拉输出单元为关闭状态，无信号输出到所述第一级栅极驱动单元和所述第二级栅极单元的输出端。从而所述第一级栅极驱动单元和所述第二级栅极单元的输出端无信号输出，因此推导在所述显示器正常工作显示画面时，所述第N级栅极驱动单元中的所述第一薄膜晶体管NT1的栅极输入信号G(n-2)为零，则所述第N级栅极驱动单元无输出信号。
在所述显示器正常显示画面时发生断电，由图3所示的第二时序阶段可知，所述STV信号由低电平信号转换为高电平信号，启动所述栅极驱动电路，所述正向扫描信号U2D保持高电平信号，所述第二全局控制信号GAS2和所述复位信号Reset保持低电平，所述反向扫描信号D2U和所述时钟信号CK由低电平信号转换为高电平信号，所述第一控制信号GAS1由高电平信号转换为低电平信号。则在所述第一级栅极驱动单元和所述第二级栅极单元中，所述第一薄膜晶体管NT1为导通状态，第七薄膜晶体管NT7在所述VGH限号下也处于导通状态，则高电平的所述正向扫描信号U2D通过所述第一薄膜晶体管NT1和所述第七薄膜晶体管NT7流入第九薄膜晶体管NT9的栅极，使所述第九薄膜晶体管NT9导通，进而使所述高电平的时序信号CK信号通过所述第九薄膜晶体管NT9流入所述第一级栅极驱动单元和所述第二级栅极单元的输出端。
可以理解的是，由于所述反向扫描信号D2U转换为高电平，则所述第一级栅极驱动单元和所述第二级栅极单元中的第三薄膜晶体管NT3和第四薄膜晶体管NT4导通，所述高电平的时序信号CK通过所述第三薄膜晶体管NT3和第四薄膜晶体管NT4流入第八薄膜晶体管NT8的栅极，使所述第八薄膜晶体管NT8导通，进而使低电平的所述第一全局控制信号GAS1流入所述第十薄膜晶体管NT10的栅极，使所述第十薄膜晶体管NT10的处于关闭状态，无信号输出到所述第一级栅极驱动单元和所述第二级栅极单元的输出端。又由于所述第二全局控制信号GAS2保持低电平信号，所述薄膜晶体管NT12保持关闭状态，无信号输出到所述第一级栅极驱动单元和所述第二级栅极单元的输出端。因此，在所述第一级栅极驱动单元和所述第二级栅极单元中，只有所述高电平的时序信号CK通过所述第九薄膜晶体管NT9流入所述第一级栅极驱动单元和所述第二级栅极单元的输出端，使所述第一级栅极驱动单元和所述第二级栅极单元输出高 电平信号。
可以理解的是，通过上述在所述显示器正常显示画面发生断电时的时序变化和栅极驱动单元输出信号的变化，可以得到所述第N级栅极驱动电路中的所述第一薄膜晶体管NT1的栅极输入信号G(N-2)为高电平，则所述第一薄膜晶体管NT1为导通状态，第七薄膜晶体管NT7在所述VGH限号下也处于导通状态，使高电平的所述正向扫描信号U2D通过所述第一薄膜晶体管NT1和所述第七薄膜晶体管NT7流入第九薄膜晶体管NT9的栅极，使所述第九薄膜晶体管NT9导通，进而使所述高电平的时序信号CK信号通过所述第九薄膜晶体管NT9流入所述第一级栅极驱动单元和所述第二级栅极单元的输出端。同样分析可知，由于所述反向扫描信号D2U转换为高电平，则所述第N级栅极驱动单元中的第三薄膜晶体管NT3和第四薄膜晶体管NT4导通，所述高电平的时序信号CK通过所述第三薄膜晶体管NT3和第四薄膜晶体管NT4流入第八薄膜晶体管NT8的栅极，使所述第八薄膜晶体管NT8导通，进而使低电平的所述第一全局控制信号GAS1流入所述第十薄膜晶体管NT10的栅极，使所述第十薄膜晶体管NT10的处于关闭状态，无信号输出到所述第N级栅极驱动单元的输出端。又由于所述第二全局控制信号GAS2保持低电平信号，所述第十二薄膜晶体管NT12保持关闭状态，无信号输出到所述第N级栅极驱动单元的输出端。因此，在所述第N级栅极驱动单元中，只有所述高电平的时序信号CK(n)通过所述第九薄膜晶体管NT9流入所述第N级栅极驱动单元的输出端，使所述第N级栅极驱动单元输出高电平信号。
由上述的推导过程可知，在断电时，所述栅极驱动电路中的每一级栅极驱动单元均输出高电平信号，从而实现断电时的All Gate On功能。
通过实施本发明实施例，在液晶显示器断电时，所述上拉控制模块产生高电平的第一控制信号，控制所述上拉输出模块导通输出高电平，同时所述下拉控制模块产生低电平的第二控制信号，控制所述下拉输出模块关闭不输出信号，从而使与所述上拉输出模块和下拉输出模块相连的所述第N级栅极驱动电路输出端输出通过上拉输出模块输出的高电平信号，从而实现断电时的All Gate On功能，使液晶屏在发生断电的情况下，迅速清除显示器上的影像，避免显示器出现之前显示画面的残影。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程， 是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种栅极驱动电路，其特征在于，所述栅极驱动电路包括多级栅极驱动单元，其中，第N级栅极驱动单元包括：
    上拉控制模块，用于在断电时产生第一控制信号；
    上拉输出模块，用于在所述第一控制信号的控制下输出高电平；
    下拉控制模块，用于在断电时产生第二控制信号；
    下拉输出模块，用于在所述第二控制信号的控制下输出低电平；
    其中，所述上拉输出模块的输出端和所述下拉输出模块的输出端连接所述第N级栅极驱动单元的输出端，在断电时，所述上拉输出模块和所述下拉输出模块使所述第N级栅极驱动单元的输出端输出高电平。
  2. 根据权利要求1所述的栅极驱动电路，其特征在于，所述上拉控制模块包括第一薄膜晶体管(NT1)、第二薄膜晶体管(NT2)、第五薄膜晶体管(NT5)和第七薄膜晶体管(NT7)，其中，
    所述第一薄膜晶体管(NT1)的栅极接入第N-2级栅极驱动单元的输出信号，源极接入正向扫描信号，漏接连接所述第二薄膜晶体管(NT2)的漏极；
    所述第二薄膜晶体管(NT2)的栅极接入第N+2级栅极驱动单元的输出信号，源极接入反向扫描信号；
    所述第五薄膜晶体管(NT5)的栅极连接所述下拉控制模块的输出端，源极连接所述第一薄膜晶体管(NT1)的漏级，漏极接入一低电平信号；
    所述第七薄膜晶体管(NT7)的栅极接入一高电平信号，源极连接所述第一薄膜晶体管(NT1)的漏级，漏极连接所述上拉控制模块的输出端；
    其中，所述上拉控制模块用于在断电时输出高电平的第一控制信号，所述第一控制信号用于使所述上拉输出模块导通。
  3. 根据权利要求1所述的栅极驱动电路，其特征在于，所述上拉输出模块包括：第九薄膜晶体管(NT9)，所述第九薄膜晶体管(NT9)的栅极连接所述上拉输出模块的输出端，源极接入第一时钟信号，漏接接所述第N级栅极驱动单元的输出端。
  4. 根据权利要求1所述的栅极驱动电路，其特征在于，所述下拉控制模块 包括第三薄膜晶体管(NT3)、第四薄膜晶体管(NT4)、第六薄膜晶体管(NT6)和第八薄膜晶体管(NT8)，其中，
    所述第三薄膜晶体管(NT3)的栅极接入所述正向扫描信号，源极接入第N+1级时钟信号，漏接连接所述第八薄膜晶体管(NT8)的栅极；
    所述第四薄膜晶体管(NT4)的栅极接入所述反向扫描信号，源极接入第N-1级时钟信号，漏接连接所述第八薄膜晶体管(NT8)的栅极；
    所述第六薄膜晶体管(NT6)的栅极连接所述第二薄膜晶体管(NT2)的漏极，源极连接第八薄膜晶体管(NT8)的漏级，漏极接入一低电平信号；
    所述第八薄膜晶体管(NT8)的源极接入第一全局控制信号，漏极连接所述下拉控制模块的输出端；
    其中，所述下拉控制模块用于在断电时输出低电平的第二控制信号，所述第二控制信号用于使所述下拉输出模块关闭。
  5. 根据权利要求1所述的栅极驱动电路，其特征在于，所述下拉输出模块包括第十薄膜晶体管(NT10)，其中，所述第十薄膜晶体管(NT10)的栅极连接所述第八薄膜晶体管(NT8)的漏极，源极接入一低电平信号，漏极连接所述第N级栅极驱动单元的输出端。
  6. 根据权利要求5所述的栅极驱动电路，其特征在于，所述第N级栅极驱动单元还包括复位模块，所述复位模块包括第十一薄膜晶体管(NT11)，所述第十一薄膜晶体管(NT11)的栅极与源极接入复位信号，漏极连接所述第八薄膜晶体管(NT8)的漏极。
  7. 根据权利要求6所述的栅极驱动电路，其特征在于，所述第N级栅极驱动单元还包括全局控制模块，所述控制模块包括第十二薄膜晶体管(NT12)，其栅极接入第二全局控制信号，源极接入一低电平信号，漏极连接所述第N级栅极驱动单元的输出端。
  8. 根据权利要求7所述的栅极驱动电路，其特征在于，所述第N级栅极驱动单元还包括电位保持模块，所述电位保持模块包括第一电容和第二电容，其中，所述第一电容一端连接所述第一薄膜晶体管(NT1)的漏极，另一端接入一低电平信号；所述第二电容一端连接所述第五薄膜晶体管(NT5)的栅极，另一端接入一低电平信号。
  9. 根据权利要求8所述的栅极驱动电路，其特征在于，所述栅极驱动单元 正常工作正向扫描时，所述正向扫描信号恒为高电平，所述反向扫描信号恒为低电平；反向扫描时，所述反向扫描信号恒为高电平，所述正向扫描信号恒为低电平。
  10. 根据权利要求1所述的栅极驱动电路，其特征在于，所述栅极驱动电路的第一级栅极驱动单元和第二级栅极驱动单元中，所述第一薄膜晶体管(NT1)的栅极均接入启动信号；所述栅极驱动电路的倒数第二级栅极驱动单元和最后一级栅极驱动单元中，所述第二薄膜晶体管(NT2)的栅极均接入所述启动信号。
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