WO2019066820A1

WO2019066820A1 - Cascaded magnetoelectric spin orbit logic

Info

Publication number: WO2019066820A1
Application number: PCT/US2017/053829
Authority: WO
Inventors: Huichu Liu; Sasikanth Manipatruni; Dmitri E. Nikonov; Tanay Karnik; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2019-04-04

Abstract

An apparatus is provided which comprises: a first logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using first a clock signal; a second logic device coupled to the first logic device, the second logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a second clock signal; and a third logic device coupled to the second logic device, the third logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a third clock signal, wherein the first, second, and third clocks have overlapping phases.

Description

CASCADED MAGNETOELECTRIC SPIN ORBIT LOGIC

BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than 100 μΑ/bit) and voltage

(e.g., greater than 0.7 V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the spin filtering tunneling dielectric of the MTJs e.g., magnesium oxide (MgO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates a magnetization response to an applied magnetic field for a ferromagnet.

[0005] Fig. IB illustrates a magnetization response to an applied magnetic field for a paramagnet.

[0006] Fig. 1C illustrates a magnetization response to an applied voltage field for a paramagnet connected to a magnetoelectric layer.

[0007] Fig. 2Α illustrates a unidirectional magnetoelectric spin orbit (MESO) logic, according to some embodiments of the disclosure.

[0008] Fig. 2B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure. [0009] Fig. 2C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure.

[0010] Fig. 3A illustrates an equivalent circuit model for a first section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments.

[0011] Fig. 3B illustrates an equivalent circuit model for a second section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments.

[0012] Figs. 4A-B illustrate a ferroelectric Landau Khalatnikov (LK) model and corresponding plot showing two ferroelectric states.

[0013] Fig. 5 illustrates a unidirectional cascaded MESO logic, according to some embodiments of the disclosure.

[0014] Fig. 6 illustrates a plot showing transient simulation of the unidirectional cascaded MESO logic of Fig. 5, according to some embodiments of the disclosure.

[0015] Fig. 7 illustrates a counter (or ring-oscillator) comprising a unidirectional cascaded MESO logic, according to some embodiments of the disclosure.

[0016] Figs. 8A-C illustrate plots showing simulation results of the counter of Fig. 7, according to some embodiments of the disclosure.

[0017] Fig. 9 illustrates an apparatus showing a series of cascaded unidirectional

MESO logic devices, according to some embodiments of the disclosure.

[0018] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with unidirectional MESO logic, according to some embodiments.

DETAILED DESCRIPTION

[0019] The Magnetoelectric (ME) effect has the ability to manipulate the

magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the ME effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, ME materials have the capability for next-generation memory and logic applications.

[0020] Magnetoelectric Spin Orbit (MESO) Logic devices/gates when cascaded with one another may suffer from back propagation of signals that may switch magnets unintentionally. Various embodiments describe a MESO Logic which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion, where the MESO logic comprises an input magnet and stack of layers for spin-to-charge conversion. Spin-to-charge conversion is achieved via one or more layers with the inverse Rashba- Edelstein effect (or spin Hall effect) wherein a spin current injected from the input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus of magnetization. In some embodiments, charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output magnet. In some embodiments, magnetic response of a magnet is according to an applied exchange bias from the magnetoelectric effect.

[0021] There are many technical effects of various embodiments. For example, high speed operation of the logic (e.g., 100 picoseconds (ps)) is achieved via the use of magnetoelectric switching operating on semi-insulating nanomagnets. In some examples, switching energy is reduced (e.g., 1-10 attojoules (aJ)) because the current needs to be "on" for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor. In some examples, in contrast to the spin current, here charge current does not attenuate when it flows through an interconnect. Other technical effects will be evident from various embodiments and figures.

[0022] In some embodiments, a multi-phase clock is used with transistors to cascade multiple MESO logic devices. For example, a 3-phase clock is used to prevent back propagation of current from the output magnet to towards the input magnet. In some embodiments, the clocks control the power supply of each MESO logic/device. For example, when clock phase is low, power supply is coupled to the magnet of the MESO logic/device. In some embodiments, merely two series connected MESO devices conduct while other MESO devices in the cascaded logic are prevented from conducting. As such,

unidirectionality for signal propagation is achieved in the cascaded MESO logic. Further, backward propagation of current and leakage current is prevented by the transistors controlled by the multi-phase clock. The techniques of various embodiments are applicable to a variety of MESO devices using a single power supply, in accordance with some embodiments.

[0023] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0024] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0025] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0026] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0027] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0028] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0029] Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet 101.

The plot shows magnetization response to applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field 'H' while the y-axis is magnetization 'm' . For ferromagnet (FM) 101 , the relationship between 'FT and 'm' is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields. For example, the magnetization of FM 101 in configuration 105 can be either in the +x direction or the -x direction for an in-plane FM. As such, changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103. Semi-insulating or insulating magnets also have a hysteresis curve, and can be used as magnets in various embodiments.

[0030] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to applied magnetic field for paramagnet 121. The x-axis of plot 120 is magnetic field 'FT while the y-axis is magnetization 'm' . A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0031] Fig. 1C illustrates plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132. Here, the x-axis is voltage 'V applied across ME layer 132 and y-axis is magnetization 'm'. Ferroelectric polarization 'PFE' is in ME layer 132 is indicated by an arrow. In this example,

magnetization is driven by exchange bias exerted by a ME effect from ME layer 132. When positive voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the +x direction by voltage +V_C) as shown by configuration 136. When negative voltage is applied by ME layer 132, paramagnet 131 establishes a

deterministic magnetization (e.g., in the -x direction by voltage -V_c) as shown by

configuration 134. Plot 130 shows that magnetization functions 133a and 133b have hysteresis. In some embodiments, by combining ME layer 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved. In some embodiments, the hysteresis behavior of FM 131, as shown in Fig. 1C, is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching.

[0032] Fig. 2A illustrates a unidirectional magnetoelectric spin orbit (MESO) logic, according to some embodiments of the disclosure. Fig. 2B illustrates a material stack at the input of an interconnect, according to some embodiments of the disclosure. Fig. 2C

illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 2A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0033] In some embodiments, MESO logic 200 comprises a first magnet 201, a stack of layers (e.g., layers 202, 203, and 204, also labeled as 202a/b, 203a/b, and 204a/b), interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) layer 206 (206a/b), second magnet 207, first contact 209a, and second contact 209b.

[0034] In some embodiments, the first and second magnets 201 and 207, respectively, have in-plane magnetic anisotropy. In some embodiments, first magnet 201 comprises first and second portions, wherein the first portion of first magnet 201 is adjacent to the stack of layers (e.g., layers 202a, 203a, and 204a), and wherein the second portion of first magnet 201 is adjacent to a magnetoelectric material stack or layer 206b. In some embodiments, second magnet 207 comprises first and second portions, wherein the first portion of second magnet 207 is adjacent to the magnetoelectric material stack or layer 206a, and wherein the second portion of second magnet 207 is adjacent to stack of layers (e.g., layers 202b, 203b, and 204b). [0035] In some embodiments, conductor 205 (or charge interconnect) is coupled to at least a portion of the stack of layers (e.g., one of layers 202a, 203a, or 204a) and ME layer 206a. For example, conductor 205 is coupled to layer 204a of the stack.

[0036] In some embodiments, the stack of layers (e.g., layers 202a/b, 203a/b, or

204a/b) is to provide an inverse Rashba-Edelstein effect (or inverse spin Hall effect). In some embodiments, the stack of layers provide spin-to-charge conversion where a spin current Is (or spin energy J_s) is injected from first magnet 201 and charge current I_c is generated by the stack of layers. This charge current I_c is provided to conductor 205 (e.g., charge interconnect). In contrast to spin current, charge current does not attenuate in conductor 205. The direction of the charge current I_c depends on the direction of

magnetization of first magnet 201.

[0037] In some embodiments, the charge current I_c charges the capacitor around ME layer 206a and switches its polarization. ME layer 206a exerts exchange bias on second magnet layer 207, and the direction of the exchange bias determines the magnetization of second magnet 207. The same dynamics occurs by ME layer 206b which exerts exchange bias on first magnet 201 according to input charge current on conductor 211a.

[0038] In this example, the length of first magnet 201 is L_m, the width of conductor

205 is Wc, the length of conductor 205 from the interface of layer 204a to ME layer 206a is Lc, t_c is the thickness of the magnets 201 and 207, and ΪΜΕ is the thickness of ME layer 206a. In some embodiments, conductor 205 comprises a material including one of: Cu, Ag, Al, or Au.

[0039] In some embodiments, the input and output charge conductors (21 la and

211b, respectively) and associated spin-to-charge and charge-to-spin converters are provided. In some embodiments, input charge current Icharge(iN) (or IIN) is provided on interconnect 21 la (e.g., charge interconnect made of same material as interconnect 205). In some

embodiments, interconnect 21 la is coupled to first magnet 201 via ME layer 206b. In some embodiments, interconnect 21 la is orthogonal to first magnet 201. For example, interconnect 211a extends in the +x direction while first magnet 201 extends in the -y direction. In some embodiments, Icharge(iN) is converted to corresponding magnetic polarization of 201 by ME layer 206b. The materials for ME layers 206a/b are the same as the materials of ME layer 206.

[0040] In some embodiments, an output interconnect 21 lb is provided to transfer output charge current Icharge(OUT) to another logic or stage. In some embodiments, output interconnect 21 lb is coupled to second magnet 207 via a stack of layers that exhibit spin Hall effect and/or Rashba Edelstein effect. For example, layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 21 1b with second magnet 207. Material wise, layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively.

[0041] In some embodiments, ME layer 206a/b forms the magnetoelectric capacitor to switch the magnets 201/207. For example, conductor 205 forms one plate of the capacitor, magnet 207 forms the other plate of the capacitor, and layer 206a is the magnetic-electric oxide that provides out-of-plane exchange bias to second magnet 207. In some embodiments, the magnetoelectric oxide comprises perpendicular exchange bias due to partially

compensated anti-ferromagnetism.

[0042] In some embodiments, first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a). The spin polarization is determined by the magnetization of first magnet.

[0043] In some embodiments, the stack comprises i) an interface 203a/b with a high density 2D (two dimensional) electron gas and with high SOC formed between 202a/b and 204a/b materials such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt. In some embodiments, a spacer (or template layer) is formed between first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201. In some embodiments, the metal of the spacer which is directly coupled to first magnet 201 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table. In some embodiments, first magnet 201 (and by extension first semi- insulating magnet 209a) are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).

[0044] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (i.e., matching gets closer to perfect matching), spin injection efficiency from spin transfer from first magnet 201 to first ISHE/ISOC stacked layer increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device. [0045] Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion

[0046] In some embodiments, a transistor (e.g., n-type transistor MN1) is coupled to first contact 209a. In this example, the drain terminal of transistor MN1 is coupled to a supply Vdd, the gate terminal of transistor MN1 is coupled to a control voltage Vciki (e.g., a switching clock signal, which switches between Vdd and ground), and the source terminal of transistor MN1 is coupled to first contact 209a. In some embodiments, first contact 209a is made of any suitable conducting material used to connect the transistor to the first magnet 201. In some embodiments, the current Idrfve (or ISUPPLY) from transistor MN1 generates spin current into the stack of layers (e.g., layers 202a, 203a, and 204a).

[0047] In some embodiments, along with the n-type transistor MN1 connected to Vdd, an n-type transistor MN2 is provided which couples layer 203a of the stack of layers (202a, 203a, and 204a) to ground. In this example, the drain terminal of transistor MN2 is coupled to layer 204a, the gate terminal of transistor MN2 is coupled to a control voltage Vdki (e.g., a switching clock signal, which switches between Vdd and ground), and the source terminal of transistor MN2 is coupled to ground.

[0048] In some embodiments, n-type transistor MN3 is provided which is operable to couple power supply Vdd to second contact 209b. In this example, the drain terminal of transistor MN3 is coupled to a supply Vdd, the gate terminal of transistor MN3 is coupled to a control voltage Vdk2 (e.g., a switching clock signal, which switches between Vdd and ground and is of different phase than Vdki), and the source terminal of transistor MN3 is coupled to second contact 209b. In some embodiments, second contact 209b is made of any suitable conducting material used to connect the transistor to the second magnet 207. In some embodiments, the current Idrive from transistor MN3 generates spin current into the stack of layers (e.g., layers 202b, 203b, and 204b).

[0049] In some embodiments, along with the n-type transistor MN4 connected to Vdd, an n-type transistor MN4 is provided which couples layer 204b of the stack of layers (202b, 203b, and 204b) to ground. In this example, the drain terminal of transistor MN4 is coupled to layer 203b, the gate terminal of transistor MN4 is coupled to a control voltage V_cik2, and the source terminal of transistor MN4 is coupled to ground.

[0050] For purposes of explaining MESO logic device 200, MESO logic device can be considered to have two portions or sections. The first portion/section comprises components/layers from 21 l a to the left of conductor 205, and the second portion/section comprises conductor 205 to layer 21 lb to the right. An ideal unidirectional signal propagation scenario is as follows: an input charge current drives magnet 201 while a supply charge current is inj ected to the spin-orbit coupling (SOC) stack (202a, 203a, 204a). The magnet 201 switches and its directionality determines the output charge current (Ιουτι) direction in conductor 205. The output current Ιουτι of the first MESO section drives the second MESO section, which continues to switch the MESO of that section. In the absence of transistors MN2 and MN4, simply connecting the two MESO sections in series can cause the ferroelectric capacitor in the second section of the MESO to switch input magnet 201 of the first section, which disturbs the logic operation.

[0051] In some embodiments, transistors MN1 and MN2 of the first section are in series with the nanomagnet 201 and SOC stack (202a, 203a, and 204a). In some

embodiments, transistors MN3 and MN4 of the second section are in series with the nanomagnet 207 and SOC stack (202b, 203b, and 204b). In some embodiments, different clock signals (Vdki and V_cik2) are applied to the gate terminals of the transistors, where transistors connected to the same MESO section share the same clock. The polarization direction of the ferroelectric charge in the magnet stack determines the magnetic directions of the nano-magnets 201 and 207, which determines the output current direction.

[0052] In this example, in the first MESO section, IIN (or Icharge(iN)) from input conductor 21 1a induces positive polarization charge on the bottom plate of the ferroelectric capacitor 206b and results in polarization of magnet 201. With a charge current ISUPPLY (or Idrive) from layer 209a to 204a, output current Ιουτι is generated on conductor 205 which is inversed from the input. Current Ιουτι then provides input current to the next MESO section. This current induces a negative polarization charge on the bottom plate of the ferroelectric capacitor 206a of the next MESO section. This polarization charge causes magnet 207 of the second MESO section to switch which results in the output current Ioim to be in the same direction as IIN (with the same ISUPPLY current direction).

[0053] The following section describes the spin to charge and charge to spin dynamics. In some embodiments, the spin-orbit mechanism responsible for spin-to-charge conversion is described by the inverse Rashba-Edelstein effect in 2D electron gases. The Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:

H_R = a_R (k x z) . σ

where i¾is the Rashba-Edelstein coefficient, 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0054] The spin polarized electrons with direction of polarization in-plane (e.g., in the xy -plane) experience an effective magnetic field dependent on the spin direction:

B(k)= —(k x z)

½

where i_Bis the Bohr magneton

[0055] This results in the generation of a charge current I_c in interconnect 205 proportional to the spin current L (or Js). The spin-orbit interaction by Ag and Bi interface layers 202 and 204 (e.g., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current I_c in the horizontal direction given as:

. _ ^_IREEI_S

W_m

where w_m is width of the input magnet 201, and _IREE is the IREE constant (with units of length) proportional to a_R.

[0056] Alternatively, the Inverse Spin Hall Effect in Ta, W, or Pt layer 203a/b produces the horizontal charge current I_c given as:

2w_m

[0057] Both IREE and ISHE effects produce spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width. For scaled nanomagnets (e.g., 5 nm wide magnets) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5. The net conversion of the drive charge current Idnve to magnetization dependent charge current is given as:

j _± REEP _{for IREE md I} + OsHEtsHEPIs _foj. _jg_jjg m 2 _m

where 'P' is the dimensionless spin polarization. For this estimate, the drive current Idnve and the charge current I_c = I_d = 100 μΑ is set. As such, when estimating the resistance of the ISHE interface to be equal to R = 100 Ω, then the induced voltage is equal to V_ISHE = 10 mV. [0058] The charge current I_c, carried by interconnect 205, produces a voltage on the capacitor of ME layer 206a comprising magnetoelectric material dielectric (such as BiFeCb (BFO) or CnC ) in contact with second magnet 207 (which serves as one of the plates of the capacitor) and interconnect 205 (which series as the other of the plates of the capacitor). In some embodiments, magnetoelectric materials are either intrinsic multiferroic or composite multiferroic structures. As the charge accumulates on the magnetoelectric capacitor of ME layer 206a, a strong magnetoelectric interaction causes the switching of magnetization in second magnet 207 (and by extension second semi-insulating magnet 209b).

[0059] For the following parameters of the magnetoelectric capacitor: thickness

^ME ⁼ 5 nm, dielectric constant ε = 500, area A = 60 nm x 20 nm. Then the capacitance is given as:

εε_ηΑ

C =—2- « IfF

^ME

[0060] Demonstrated values of the magnetoelectric coefficient is a_ME~ 10/c , where the speed of light is c. This translates to the effective magnetic field exerted on second semi- insulating magnet 207, which is expressed as:

C ME ^ISHE

BME = ME^ =— 0-06Γ

^ΤΜΕ

This is a strong field sufficient to switch magnetization.

[0061] The charge on the capacitor of ME layer 206a is Q =— x 10 mV = 10 aC, and the time to fully charge it to the induced voltage is td = 10— ~ 1 ps (with the account of decreased voltage difference as the capacitor charges). If the driving voltage is V_d =

100 mV, then the energy E_sw to switch is expressed as:

E_sw~ 100mV x ΙΟΟμΑ x lps~ 10a/

which is comparable to the switching energy of CMOS transistors. Note that the time to switch t_sw magnetization remains much longer than the charging time and is determined by the magnetization precession rate. The micro-magnetic simulations predict this time to be t_sw~ 100ps, for example.

[0062] In some embodiments, materials for first and second magnets 201 and 207 have saturated magnetization M_s and effective anisotropy field Hk. Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Anisotropy Hk generally refers material properties that are highly directionally dependent. [0063] In some embodiments, materials for first and second magnets 201 and 207, respectively, are non-ferromagnetic elements with strong paramagnetism which have a high number of unpaired spins but are not room temperature ferromagnets. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. In some embodiments, magnets 209a/b and 210a/b comprise a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), Cr₂Cb (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy20 (dysprosium oxide), Erbium (Er), EnCb (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd203), FeO and Fe203 (Iron oxide), Neodymium (Nd), Nd2C (Neodymium oxide), KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), SrmC (samarium oxide), Terbium (Tb), Tb2Cb (Terbium oxide), Thulium (Tm), TrmCb (Thulium oxide), or V2O3 (Vanadium oxide). In some embodiments, the first and second paramagnets 201 and 207 comprise dopants selected from a group which includes one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[0064] In some embodiments, first and second magnets 201 and 207, respectively, are ferromagnets. In some embodiments, first and second magnets 201 and 207, respectively, comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or MmX, where 'X' is one of Ga or Ge.

[0065] In some embodiments, the stack of layers providing spin orbit coupling comprises: a first layer 202a/b comprising Ag, wherein the first layer is adjacent to first magnet 209a/b; and a second layer 204a/b comprising Bi or W, wherein second layer 204a/b is adjacent to first layer 202a/b and to a conductor (e.g., 205, 21 lb). In some embodiments, a third layer 203a/b (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202a/b and second layer 204a/b as shown. In some embodiments, the stack of layers comprises a material which includes one of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. [0066] In some embodiments, ME layer 206a/b is formed of a material which includes one of: CnCb and multiferroic material. In some embodiments, ME layer 206 comprises Cr and O. In some embodiments, the multiferroic material comprises BFO (e.g., BiFeC ), LFO (LuFeC , LuFe204), or La doped BiFeC . In some embodiments, the multiferroic material includes one of: Bi, Fe, O, Lu, or La. In some embodiments, ME layer 206a/b comprises one of: dielectric, para-electric, or ferro-electric material.

[0067] In some embodiments, first contact 209a is replaced with a first semi- insulating magnet 209a, and second contact 209b is replaced with a second semi-insulating magnet 209b. In some embodiments, first semi-insulating magnet 209a is adjacent to first magnet 201 and is also coupled to a transistor (e.g., n-type transistor MNl). As such, first semi-insulating magnet 209a functions as a displacement capacitor between the transistor MNl and the first magnet 201. Here the term "semi-insulating magnet" generally refers to a material that has magnetic properties but has higher resistivity compared to normal ferromagnets. For example, semi-insulating or insulating magnets may not be conductive for charge current, but exhibit magnetic properties. The semi-insulating magnet or insulating magnet may have a Spinel crystal structure, can be hexagonal (e.g., Fe2Cb), or they can belong to any of the crystal classes. In some embodiments, materials for semi-insulating or insulating magnets include one of: Fe203, C02O3, Co2Fe04, or Ni2Fe04. In some embodiments, elements for semi-insulating or insulating magnets include one or more of: Fe, O, Co or Ni. The direction of the charge current I_c also depends on the direction of magnetization of first semi-insulating magnet 209a.

[0068] In some embodiments, first semi-insulating magnet 209a and second semi- insulating magnet 209b form displacement capacitors. The nature of the displacement capacitor may be set by the leakage and the dielectric constants of the semi-insulating magnets 209a/b. In some embodiments, first semi-insulating magnet 209a and second semi- insulating magnet 209b form dielectric capacitors, where a bound charge is generated at the plates.

[0069] In some embodiments, first and second semi-insulating magnets 209a and

209b, respectively, comprise a material which includes one or more of: Co, Fe, No, or O. In some embodiments, the first and second semi-insulating magnets 209a and 209b, respectively, comprise a material which includes one or more of: C02O3, Fe2Cb, Co2Fe04,or Ni2Fe04. In some embodiments, first and second semi-insulating magnets 209a and 209b have Spinel crystal structure. In some embodiments, magnets 209a and 209b have non- insulating properties. For example, magnets 209a and 209b can be paramagnets or ferromagnets.

[0070] In some embodiments, the magnetization of first semi-insulating magnet 209a is determined by the magnetization of first magnet 201. For example, when first magnet 201 has magnetizations pointing in -y direction, then first semi-insulating magnet 209a has magnetization pointing in the -y direction. In some embodiments, the magnetization of second semi-insulating magnet 209b is determined by the magnetization of second magnet 207. For example, when second magnet 207 has magnetizations pointing in -y direction, then second semi-insulating magnet 209b has magnetization pointing in the -y direction. In some embodiments, second semi-insulating magnet 209b is adjacent to second magnet 207 such that second magnet 207 is between second semi-insulating magnet 209b and the stack of layers providing spin orbit coupling.

[0071] While various embodiments are illustrated with n-type transistors MN1, MN2,

MN3, and MN3, p-type transistors can be used instead and the switching gate signals can be logically inversed. In some embodiments, a combination of n-type and p-type transistors are used. For example, the transistors coupled to power supply Vdd are p-type transistors while the transistors coupled to ground are n-type transistors. Appropriate logic change can be made to the driving gate signals to achieve the same technical effect (e.g., unidirectionality) as achieved by the n-type transistors MN1, MN2, MN3, and MN3. In some embodiments, a combination of n-type and p-type devices (e.g., transmission gates) can be used instead of n- type transistors MN1, MN2, MN3, and MN3.

[0072] Fig. 3A illustrates an equivalent circuit model 300 for the first section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments. It is pointed out that those elements of Fig. 3A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0073] Here Rmagnet, Rsi, Rsi, RIREE and Ric are the modeled resistances for magnet

201, SOC stack (202a, 203a, 204a) shunt resistance, the Inverse Rashba-Edelstein Effect (IREE) resistance, and interconnect resistance of conductor 205, respectively. In some embodiments, the IREE effect from the current in the SOC stack is modeled as a current controlled current source, of which the current direction is determined by the magnet "state" (e.g., the nano-magnet direction, which is inconsistent with the polarization charge in the ferroelectric). In some embodiments, the ferroelectric 206b is modeled as a non-linear capacitor using Landau Khalatnikov (LK) equations. [0074] Fig. 3B illustrates an equivalent circuit model 320 for the second section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments. It is pointed out that those elements of Fig. 3B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0075] Here Rmagnet, Rsi, Rsi, RIREE and Ric are the modeled resistances for magnet

207, SOC stack (202b, 203b, 204b) shunt resistance, the Inverse Rashba-Edelstein Effect (IREE) resistance, and interconnect resistance of conductor 211b, respectively. In some embodiments, the IREE effect from the current in the SOC stack is modeled as a current controlled current source, of which the current direction is determined by the magnet "state" (e.g., the nano-magnet direction, which is inconsistent with the polarization charge in the ferroelectric). In some embodiments, the ferroelectric 206a is modeled as a non-linear capacitor using LK equations. In some embodiments, to enable the unidirectional signal propagation, Vciki and V_cik2 are out-of-phase and with overlap. In some embodiments, VCM and V_cik2 are out-of-phase and non-overlapping. For example, Vciki and V_cik2 are out-of-phase by 180°.

[0076] Figs. 4A-B illustrate a ferroelectric Landau Khalatnikov (LK) model 400 and corresponding plot 420 showing two ferroelectric states. In some embodiments, positive polarization charge +QF corresponds to state Ί ' of the magnet, while negative polarization charge -QF corresponds to state '0' of the magnet. Here, normalized +QF(1) and -QF(-l) are used in circuit simulation to indicate the ferroelectric states.

[0077] LK model 400 illustrates a circuit that provides ferroelectric voltage VFE and comprises capacitor CO in parallel with a series coupled resistance p and internal capacitance CF(QFE) that provides internal voltage Vim. Here, 'A' is the area of capacitor CO, 'd' is the distance between the plates of capacitor CO, and E0 is the dielectric constant. Plot 420 shows the capacitance behavior of a ferroelectric capacitor (FE-Cap) when connected with a load capacitor. Here, x-axis is the internal voltage Vint in volts, while the y-axis is charge from the ferroelectric capacitor when connected with a load capacitor. The dotted region in plot 420 represents the negative capacitance region between the coercive voltage bounds.

[0078] When a voltage source drives the FE-Cap connected with a load capacitor, the operating region of a FE-cap is biased by the load capacitance. When the FE-Cap is biased at the negative capacitance region (e.g., charge on FE-cap is positive while the voltage across the FE-cap is negative, and vice versa), the voltage across the load capacitance can be higher than the input voltage, owning to the ferroelectric polarity charge induced voltage amplification effect. On the other hand, when the FE-Cap is biased at the positive capacitance region, it operates as a regular capacitor. The negative capacitance effect has been mainly utilized for transistor gate stack enhancement (e.g., negative capacitance FETs) for low-voltage transistors. Some embodiments use the concept of negative capacitance to a MESO logic to enhance the switching of magnets via the magnetoelectric layer.

[0079] Fig. 5 illustrates a unidirectional cascaded MESO logic 500, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0080] In this example, MESO logic 500 comprises two MESO stages 501 and 502 that are cascaded with one another. To drive the MESO logic 500, three different clocks are used to drive the transistor pairs— MN1, MN2; ΜΝ ,ΜΝ2'; and MN1 ", MN2"— to ensure unidirectional flow of current and integrity of logic operation.

[0081] In some embodiments, Vdk3 is applied to control the input drivers (gates of transistors MN1 and MN2) of MESO stage 501. In some embodiments, the input driver provides a positive current IIN to the first ferroelectric capacitor 206b. In this example, VDD of 100 mV and Vciki, V_cik2, V_cik3 of 1 V with 12 ns (nanoseconds) clock period are used. In some embodiments, two out of the three clocks (Vciki, V_cik2, V_cik3) have an overlap of l/3^rd clock high duration (e.g., t=2 ns). However, the overlap can by l/4^th of clock high duration or other fractions that allow unidirectional flow of current and integrity of logic operation. In the initial condition, ferroelectric capacitor 206b of MESO stage 501 has negative charge - QF (MES01.QFE=-1) and ferroelectric capacitor 206b of MESO stage 502 has positive charge +QF (MES02.QFE=+1), which indicate their magnet states of '0' and Ί ', respectively.

[0082] Fig. 6 illustrates plot 600 (which includes sub-plots 601, 602, and 603) showing transient simulation of the unidirectional cascaded MESO logic of Fig. 5, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0083] Sub-plot 601 illustrates Vciki, V_cik2, and V_cik3 which are control voltages to the drive transistors. Here, y-axis is voltage and x-axis is time. From time 0 ns to 1 ns,

Vdk2 = Vdk3 = 0. As such, all the drive transistors are off and no current flows, and the states of the magnets are unchanged. From time 1 ns to 5 ns,

As such the first input driver has a DC current path to its ground via transistors MN1 and MN2, while other transistors ΜΝ , MN2', MN1 ", and MN2" are off. Because ISUPPLY is off for MESO devices, no transient current flows (e.g., IIN =0).

[0084] During time tO (e.g., 5 ns to 7 ns), Vciki= Vdk3= 1, Vdk2 = 0, ISUPPLY of MESO stage 501 is on while ISUPPLY of MESO stage 502 is off. The ferroelectric 206b in MESO stage 501 (MESOl .Fe) has a transient current path from the input driver VDD to the ground of MESO stage 501, while the transient conduction path from MESO stage 501 to MESO stage 502 through Ιουτι is off. In this example, ferroelectric 206b of MESO stage 501 switches from -QF to +QF due to positive current IIN, while the ferroelectric 206b of MESO stage 502 is unchanged.

[0085] During time tl (e.g., 7 ns to 9 ns), Vdk3 = Vdk2 = 0, Vdki = 1, ferroelectrics

206b of MESO stages 501 and 502 are isolated since no conducting path exists. During time t2, Vdki = Vdk2 =1, V_cik3 = 0, a transient current path exists from Vdd of MESO stage 501 to ground of MESO stage 502. Since +QF is deposited on ferroelectric 206b of MESO stage 501 (MESOl .QFe) during time tO, a negative transient current Ιουτι is generated due to IREE and discharges ferroelectric 206b of MESO stage 501 (MES02.QFe). As such, magnet 201 of MESO stage 502 switches from state T to state '0' with negative polarization charge. Note that magnet 201 of MESO stage 501 switches when Vdk3 and Vdki overlap (e.g., at tO), and magnet 201 of MESO stage 502 switches when Vdki and Vdk2 overlap (e.g., t2). In some embodiments, each magnet 201 of a MESO stage switches once during one clock period. As such, choosing proper clock signals can enable cascaded MESO circuits in accordance with various embodiments. In some embodiments, as more MESO stages are cascaded, more clocks may be used to ensure unidirectional flow of current. In some embodiments, when propagated voltage through a MESO stage is less than a threshold of the ferroelectric capacitor, then no more clocks are used because uni directionality is preserved.

[0086] Fig. 7 illustrates a counter (or ring oscillator) 700 comprising a unidirectional cascaded MESO logic, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0087] In some embodiments, by cascading multiple MESO devices with 3-phase clocks, a counter can be realized. The size of the counter depends on the number of cascaded MESO devices, in accordance with some embodiments. Fig. 7 illustrates a 3-bit counter which is realized using three stages of cascaded MESO devices 701, 702, and 703 with three phase clocks (Vdki, Vdk2 and Vdk3), in accordance with some embodiments. [0088] In some embodiments, the output o3 of the MESO device 703 is connected to the input of MESO device 701. Here, the initial state of magnet 201 for MESO stage 710 is Ό', magnet 201 for MESO stage 702 is Ό', and magnet 201 for MESO stage 703 is Ί'. (e.g., MES01.QFE=-1 (state "0"), MES02.QFE=1 (state "1"), and MES03.QFE=-1 (state 0)). In some embodiments, the clocks are non-overlapping clocks that allow each MESO stage to behave life a traditional flip-flop in a counter.

[0089] In some embodiments, each MESO device/stage operates as an "inverter" for current. As such this 3-stage MESO also operates as a ring-oscillator, in which the state of each MESO device changes when its own clock and previous stage's clock overlaps. For example, when

magnet 201 of MESO stage 702 switches from state '0' to T when the state of magnet 201 of MESO stage 701 is 'Ο'). In another example, when

Vdk3=Vcik2=l, magnet 201 of MESO stage 702 switches from state T to '0' when the state of magnet 201 of MESO stage 701 is T. The 3-phase clocks effectively prevent back propagation of adjacent series connected MESO devices, and provide unidirectional signal propagation.

[0090] Figs. 8A-C illustrate plots 800, 820, and 830, respectively, showing simulation results of the counter (or ring oscillator) of Fig. 7, according to some

embodiments of the disclosure. It is pointed out that those elements of Figs. 8A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Plot 800 illustrates overlapping clocks Vciki, V_cik2, and V_cik3 signals. Plot 820 illustrates output currents Ιουτι, Ioim, Ioiro from three MESO devices 701, 702, and 703. Plot 830 illustrates normalized ferroelectric charges on the three MESO devices 701, 702, and 703 illustrating magnet state transition. Here, the vertical shades illustrate the overlapped duration of Vcik2/Vcik3, Vciki/Vdk2 and V_ciki/V_cik3, respectively.

[0091] Fig. 9 illustrates apparatus 900 showing a series of cascaded unidirectional

MESO logic devices, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Apparatus 900 shows 'N' MESO logic devices that are coupled in series or a chain using the 3-phase clock solution of various embodiments. As such, uni directionality of magnet state propagation is achieved which effectively prevents back signal propagation.

[0092] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with unidirectional MESO logic, according to some embodiments. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0093] Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0094] In some embodiments, computing device 1600 includes first processor 1610 with unidirectional MESO logic, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a unidirectional MESO logic, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0095] In some embodiments, processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0096] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0097] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0098] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0099] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[00100] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[00101] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[00102] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[00103] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00104] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00105] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00106] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00107] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00108] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00109] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims. [00110] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00111] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00112] Example 1. An apparatus comprising: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising a magnetoelectric material; a conductor adjacent to the layer; a first device coupled to a first supply node and to the magnet; and a second device coupled to a second supply node and to a layer of the stack of layers.

[00113] Example 2. The apparatus of example 1 comprises: a second magnet having a first portion and a second portion; a second stack of layers, a portion of which is adjacent to the first portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect; a second layer adjacent to the second portion of the second magnet, the second layer comprising a magnetoelectric material; a second conductor adjacent to the second layer; a third conductor adjacent to a portion of the stack of layers and the second layer; a third device coupled to the first supply node and to the second magnet; and a fourth device coupled to the second supply node and to a layer of the second stack of layers.

[00114] Example 3. The apparatus of example 2, wherein the first and second devices are controllable by a first switching signal, and wherein the third and fourth devices are controllable by a second switching signal.

[00115] Example 4. The apparatus of example 3, wherein the first switching signal has a first phase, wherein the second switching signal has a second phase, and wherein the first phase is different from the second phase. [00116] Example 5. The apparatus of example 2, wherein the first, second, third, and fourth devices have the same conductivity type.

[00117] Example 6. The apparatus of example 2, wherein the first and third devices have a first conductivity type, and wherein the second and fourth devices have a second conductivity type.

[00118] Example 7. The apparatus according to any of examples 2 to 6, wherein the layer and second layer include one or more of: Cr₂0₃ or multiferroic material, or wherein the layer and second layer comprise a material which includes one of: Cr, O, Cr₂0₃, or multiferroic material.

[00119] Example 8. The apparatus of example 7, wherein the multiferroic material includes one of: BiFeC , LuFeC , LuFe204, or La doped BiFeCb, or wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00120] Example 9. The apparatus according to any of examples 2 to 8, wherein the stack of layers and the second stack of layers comprises a material which includes one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00121] Example 10. The apparatus to any of examples 2 to 9, wherein the first and second magnets are a paramagnet or a ferromagnet, or wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er, Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, FeO, Fe₂0₃, Nd, Nd₂0₃, K0₂, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

[00122] Example 11. The apparatus to any of examples 2 to 9, wherein the first and second magnets comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, NiJVInAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, PdJVInSn, PdJVInSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or Mn₃X, where 'X' is one of Ga or Ge.

[00123] Example 12. An apparatus comprising: a first logic device according to any one of examples 4 to 11 ; a second logic device according to any one of examples 4 to 11, wherein the second conductor of the first logic device is coupled to the conductor of the second logic device; and a third logic device according to any one of examples 4 to 11, wherein the second conductor of the second logic device is coupled to the conductor of the third logic device.

[00124] Example 13. The apparatus of example 12, wherein: the second switching signal to the third and fourth devices of the first logic device has a first phase which is different than a second phase of the first switching signal to the first and second devices of the second logic device, and the second switching signal to the third and fourth devices of the second logic device has a third phase which is different than a first phase of the first switching signal to the first and second devices of the third logic device.

[00125] Example 14. An apparatus comprising: a first logic device including: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising magnetoelectric material; a first conductor adjacent to the layer; a second conductor adjacent to a layer of the stack of layers, a first transistor coupled to a first supply node and to the magnet; and a second transistor coupled to a second supply node and to a layer of the stack of layers; a second logic device coupled to the first logic device, wherein the second logic device includes: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising magnetoelectric material; a first conductor adj acent to the layer; a second conductor adjacent to a layer of the stack of layers, a first transistor coupled to a first supply node and to the magnet; and a second transistor coupled to a second supply node and to a layer of the stack of layers; and a third logic device coupled to the second logic device, wherein the third logic device includes: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising magnetoelectric material; a first conductor adjacent to the layer; a second conductor adjacent to a layer of the stack of layers, a first transistor coupled to a first supply node and to the magnet; and a second transistor coupled to a second supply node and to a layer of the stack of layers, wherein the second conductor of the third logic device is coupled to the first conductor of the first logic device, wherein the second conductor of the second logic device is coupled to the first conductor of the third logic device, and wherein second conductor of the first logic device is coupled to the first conductor of the second logic device. [00126] Example 15. The apparatus of example 14, wherein: the first and second transistors of the first logic device are controllable by a first switching signal, the first and second transistors of the second logic device are controllable by a second switching signal; and the first and second transistors of the third logic device are controllable by a third switching signal.

[00127] Example 16. The apparatus of example 15, wherein: the first switching signal has a first phase, the second switching signal has a second phase, the third switching signal has a third phase, wherein the first, second, and third phases are different from one another.

[00128] Example 17. The apparatus of example 16, wherein the first, second, and third phases are overlapping phases.

[00129] Example 18. An apparatus comprising: a first logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using first a clock signal; a second logic device coupled to the first logic device, the second logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a second clock signal; and a third logic device coupled to the second logic device, the third logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a third clock signal, wherein the first, second, and third clocks have overlapping phases.

[00130] Example 19. The apparatus of example 18, wherein the first logic device is according to any one of examples 1 to 11 , wherein the second logic device is according to any one of examples 1 to 1 1, wherein the third device is according to any one of examples 1 to 11.

[00131] Example 20. The apparatus of example 18, wherein the third logic device is coupled to the first logic device such that the first, second, and third logic devices together form a counter or a ring oscillator.

[00132] Example 21. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 11 , apparatus examples 12 to 13, apparatus examples 14 to 17; or apparatus examples 18 to 20; and a wireless interface to allow the processor to communicate with another device.

[00133] Example 22. A method comprising: forming a magnet having a first portion and a second portion; forming a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; forming a layer adjacent to the second portion, the layer comprising magnetoelectric material; forming a conductor adjacent to the layer; forming a first transistor coupled to a first supply node and to the magnet; and forming a second transistor coupled to a second supply node and to a layer of the stack of layers.

[00134] Example 23. The method of example 22 comprises: forming a second magnet having a first portion and a second portion; forming a second stack of layers, a portion of which is adjacent to the first portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect; forming a second layer adjacent to the second portion of the second magnet, the second layer comprising magnetoelectric material; forming a second conductor adjacent to the second layer; forming a third conductor adjacent to a portion of the stack of layers and the second layer; forming a third transistor coupled to the first supply node and to the second magnet; and forming a fourth transistor coupled to the second supply node and to a layer of the second stack of layers.

[00135] Example 24. The method of example 23 comprises: controlling the first and second transistors by a first switching signal; and controlling the third and fourth transistors by a second switching signal.

[00136] Example 25. The method of example 24, wherein the first switching signal has a first phase, wherein the second switching signal has a second phase, and wherein the first phase is different from the second phase.

[00137] Example 26. The method of example 24, wherein the first, second, third, and fourth transistors have the same conductivity type.

[00138] Example 27. The method of example 24, wherein the first and third transistors have a first conductivity type, and wherein the second and fourth transistors have a second conductivity type.

[00139] Example 28. The method according to any of examples 22 to 27, wherein the layer and second layer include one or more of: CnCb or multiferroic material, or wherein the layer and second layer comprise a material which includes one of: Cr, O, CnCb or multiferroic material.

[00140] Example 29. The method of example 28 wherein the multiferroic material comprises BiFeCb, LuFeC , LuFe204, or La doped BiFeC , or wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

[00141] Example 30. The method according to any of examples 22 to 29, wherein the stack of layers and the second stack of layers comprises a material which includes one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. [00142] Example 31. The method to any of examples 22 to 30, wherein the first and second magnets are a paramagnet or a ferromagnet, or wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er, Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, FeO, Fe₂0₃, Nd, Nd₂0₃, K0₂, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

[00143] Example 33. The method to any of examples 22 to 30, wherein the first and second magnet comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or Mn₃X, where 'X' is one of Ga or Ge.

[00144] Example 34. A method comprising: forming a first logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using first a clock signal; forming a second logic device coupled to the first logic device, the second logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a second clock signal; and forming a third logic device coupled to the second logic device, the third logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a third clock signal, wherein the first, second, and third clocks have overlapping phases.

[00145] Example 35. The method of example 33 comprises coupling the third logic device to the first logic device such that the first, second, and third logic devices together form a counter or a ring oscillator.

[00146] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a magnet having a first portion and a second portion;

a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect;

a layer adjacent to the second portion, the layer comprising a magnetoelectric material;

a conductor adjacent to the layer;

a first device coupled to a first supply node and to the magnet; and

a second device coupled to a second supply node and to a layer of the stack of layers.

2. The apparatus of claim 1 comprises:

a second magnet having a first portion and a second portion;

a second stack of layers, a portion of which is adjacent to the first portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect;

a second layer adjacent to the second portion of the second magnet, the second layer comprising a magnetoelectric material;

a second conductor adjacent to the second layer;

a third conductor adjacent to a portion of the stack of layers and the second layer; a third device coupled to the first supply node and to the second magnet; and a fourth device coupled to the second supply node and to a layer of the second stack of layers.

3. The apparatus of claim 2, wherein the first and second devices are controllable by a first switching signal, and wherein the third and fourth devices are controllable by a second switching signal.

4. The apparatus of claim 3, wherein the first switching signal has a first phase, wherein the second switching signal has a second phase, and wherein the first phase is different from the second phase.

5. The apparatus of claim 2, wherein the first, second, third, and fourth devices have the same conductivity type.

6. The apparatus of claim 2, wherein the first and third devices have a first conductivity type, and wherein the second and fourth devices have a second conductivity type.

7. The apparatus according to any of claims 2 to 6, wherein the layer and second layer

include one or more of: Cr₂0₃ or multiferroic material, or wherein the layer and second layer comprise a material which includes one of: Cr, O, Cr₂0₃, or multiferroic material.

8. The apparatus of claim 7, wherein the multiferroic material includes one of: BiFeC , LuFeC , LuFe204, or La doped BiFeC , or wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.

9. The apparatus according to any of claims 2 to 8, wherein the stack of layers and the

second stack of layers comprises a material which includes one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

10. The apparatus to any of claims 2 to 9, wherein the first and second magnets are a

paramagnet or a ferromagnet, or wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr₂0₃, CoO, Dy, Dy₂0, Er, Er₂0₃, Eu, Eu₂0₃, Gd, Gd₂0₃, FeO, Fe₂0₃, Nd, Nd₂0₃, K0₂, Pr, Sm, Sm₂0₃, Tb, Tb₂0₃, Tm, Tm₂0₃, V, or V₂0₃.

11. The apparatus to any of claims 2 to 9, wherein the first and second magnets comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, CiteMnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, MnGaRu, or Mn₃X, where 'X' is one of Ga or Ge.

12. An apparatus comprising:

a first logic device according to any one of claims 4 to 11 ;

a second logic device according to any one of claims 4 to 11 , wherein the second conductor of the first logic device is coupled to the conductor of the second logic device; and

a third logic device according to any one of claims 4 to 11 , wherein the second conductor of the second logic device is coupled to the conductor of the third logic device.

13. The apparatus of claim 12, wherein:

the second switching signal to the third and fourth devices of the first logic device has a first phase which is different than a second phase of the first switching signal to the first and second devices of the second logic device, and

the second switching signal to the third and fourth devices of the second logic device has a third phase which is different than a first phase of the first switching signal to the first and second devices of the third logic device.

14. An apparatus comprising:

a first logic device including: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adj acent to the second portion, the layer comprising magnetoelectric material; a first conductor adjacent to the layer; a second conductor adjacent to a layer of the stack of layers, a first transistor coupled to a first supply node and to the magnet; and a second transistor coupled to a second supply node and to a layer of the stack of layers;

a second logic device coupled to the first logic device, wherein the second logic device includes: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising magnetoelectric material; a first conductor adjacent to the layer; a second conductor adjacent to a layer of the stack of layers, a first transistor coupled to a first supply node and to the magnet; and a second transistor coupled to a second supply node and to a layer of the stack of layers; and

a third logic device coupled to the second logic device, wherein the third logic device includes: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adj acent to the second portion, the layer comprising magnetoelectric material; a first conductor adjacent to the layer; a second conductor adjacent to a layer of the stack of layers, a first transistor coupled to a first supply node and to the magnet; and a second transistor coupled to a second supply node and to a layer of the stack of layers,

wherein the second conductor of the third logic device is coupled to the first conductor of the first logic device, wherein the second conductor of the second logic device is coupled to the first conductor of the third logic device, and wherein second conductor of the first logic device is coupled to the first conductor of the second logic device.

15. The apparatus of claim 14, wherein:

the first and second transistors of the first logic device are controllable by a first switching signal,

the first and second transistors of the second logic device are controllable by a second switching signal; and

the first and second transistors of the third logic device are controllable by a third switching signal.

16. The apparatus of claim 15, wherein:

the first switching signal has a first phase,

the second switching signal has a second phase,

the third switching signal has a third phase, wherein the first, second, and third phases are different from one another.

17. The apparatus of claim 16, wherein the first, second, and third phases are overlapping phases.

18. An apparatus comprising:

a first logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using first a clock signal; a second logic device coupled to the first logic device, the second logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a second clock signal; and

a third logic device coupled to the second logic device, the third logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a third clock signal, wherein the first, second, and third clocks have overlapping phases.

19. The apparatus of claim 18, wherein the first logic device is according to any one of claims 1 to 11 , wherein the second logic device is according to any one of claims 1 to 11 , wherein the third device is according to any one of claims 1 to 11.

20. The apparatus of claim 18, wherein the third logic device is coupled to the first logic device such that the first, second, and third logic devices together form a counter or a ring oscillator.

21. A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus claims 1 to 1 1, apparatus claims 12 to 13, apparatus claims 14 to 17; or apparatus claims 18 to 20; and a wireless interface to allow the processor to communicate with another device.

22. A method comprising:

forming a magnet having a first portion and a second portion;

forming a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; forming a layer adjacent to the second portion, the layer comprising

magnetoelectric material;

forming a conductor adjacent to the layer;

forming a first transistor coupled to a first supply node and to the magnet; and forming a second transistor coupled to a second supply node and to a layer of the stack of layers.

23. The method of claim 22 comprises:

forming a second magnet having a first portion and a second portion; forming a second stack of layers, a portion of which is adjacent to the first portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect;

forming a second layer adjacent to the second portion of the second magnet, the second layer comprising magnetoelectric material;

forming a second conductor adjacent to the second layer;

forming a third conductor adjacent to a portion of the stack of layers and the second layer;

forming a third transistor coupled to the first supply node and to the second magnet; and

forming a fourth transistor coupled to the second supply node and to a layer of the second stack of layers.

24. The method of claim 23 comprises:

controlling the first and second transistors by a first switching signal; and controlling the third and fourth transistors by a second switching signal.

25. The method of claim 24, wherein the first switching signal has a first phase, wherein the second switching signal has a second phase, and wherein the first phase is different from the second phase.