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WO2019062320A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2019062320A1
WO2019062320A1 PCT/CN2018/098089 CN2018098089W WO2019062320A1 WO 2019062320 A1 WO2019062320 A1 WO 2019062320A1 CN 2018098089 W CN2018098089 W CN 2018098089W WO 2019062320 A1 WO2019062320 A1 WO 2019062320A1
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WIPO (PCT)
Prior art keywords
electrode
array substrate
substrate
strip
passivation
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Application number
PCT/CN2018/098089
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English (en)
French (fr)
Inventor
董霆
曲莹莹
陈轶夫
刘德强
周健
杨建�
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/329,878 priority Critical patent/US20210327917A1/en
Priority to EP18849418.1A priority patent/EP3690537A4/en
Publication of WO2019062320A1 publication Critical patent/WO2019062320A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, and a display device.
  • the Advanced Super Dimensional Switching (ADS) technology is a technology in which the first electrode and the second electrode are disposed on the array substrate; at present, the display product using the ADS technology is improved from a color film, a polarizer, a liquid crystal, Pixel design or electrode structure to improve transmittance.
  • the embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display device.
  • the embodiment of the present disclosure can improve the transmittance of the display product.
  • At least one embodiment of the present disclosure provides an array substrate including a substrate, first and second electrodes disposed over the substrate, and an insulating layer between the first and second electrodes;
  • One of the first electrode and the second electrode is a pixel electrode and the other of the first electrode and the second electrode is a common electrode;
  • the second electrode includes a plurality of electrode groups, the electrode group
  • the electrode strip includes a passivation wall sandwiched between the electrode strips, and the passivation wall is made of an insulating material.
  • the first electrode is located between the substrate and the second electrode in a direction perpendicular to a surface of the substrate facing the insulating layer; in the same electrode group, the electrode
  • the direction in which the strip and the passivation wall are aligned is parallel to the surface of the substrate and there is an overlap between the electrode strip and the orthographic projection of the passivation wall on the substrate.
  • the contact surface between the electrode strip of each of the electrode groups and the passivation wall has an angle with the surface of the substrate, and the included angle is an acute angle.
  • the passivation wall includes inclined sides covered by the electrode strips, and the inclined sides of the same passivation wall have different inclination directions.
  • the electrode strips included in the same electrode group are disconnected from each other at the position of the top end of the passivation wall, and the top end of the passivation wall is an end of the passivation wall remote from the substrate.
  • the electrode strips included in the same electrode group are directly electrically connected.
  • the electrode strips included in the same electrode group are electrically connected by a conductive structure.
  • adjacent passivation walls of adjacent electrode groups have a recessed space between them.
  • adjacent electrode strips of adjacent electrode groups are disconnected from each other in the recessed space.
  • the face of the second electrode near the substrate is the same width as the face away from the substrate.
  • the electrode strip has a parallelogram in a direction perpendicular to the direction of the substrate and perpendicular to the electrode strip.
  • the passivation wall of each of the electrode groups is the same size as the electrode strip in a direction perpendicular to the substrate.
  • the electrode strip width is 0.5 to 1.2 ⁇ m in a direction parallel to the surface of the substrate facing the insulating layer.
  • the distance between two electrode strips in the same electrode group is 1.8-3.4 ⁇ m.
  • the distance between adjacent electrode groups is 5.2-5.6 ⁇ m.
  • the insulating layer and the passivation wall are integrally formed.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, comprising: forming a first electrode over a substrate; forming an insulating layer over the first electrode; forming a second electrode over the insulating layer, One of the electrode and the second electrode is a pixel electrode, the other of the first electrode and the second electrode is a common electrode, the second electrode includes a plurality of electrode groups, and the electrode group includes an electrode a strip and a passivation wall sandwiched between the electrode strips.
  • At least one embodiment of the present disclosure further provides a display device including an opposite substrate and the array substrate provided by any of the above embodiments, and a liquid crystal sandwiched between the opposite substrate and the array substrate.
  • the first electrode is located between the substrate and the second electrode in a direction perpendicular to a surface of the substrate facing the insulating layer; in the same electrode group, the electrode
  • the direction in which the strip and the passivation wall are aligned is parallel to the surface of the substrate and there is an overlap between the electrode strip and the orthographic projection of the passivation wall on the substrate.
  • 1 is a schematic structural view of an array substrate
  • FIG. 2 is a cross-sectional structural view showing a portion of a structure in an array substrate according to at least one embodiment of the present disclosure
  • 3a is a cross-sectional structural view of an array substrate according to at least one embodiment of the present disclosure
  • 3b and 3c are top plan views showing a part of the structure of the array substrate shown in FIG. 3a;
  • FIG. 4 is a schematic diagram of dimensioning an array substrate of at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic view showing dimensioning of an array substrate of a comparative example
  • FIG. 6 is a schematic diagram of electric field distribution of an array substrate of a comparative example
  • FIG. 8 is a liquid crystal deflection simulation diagram of an array substrate according to at least one embodiment of the present disclosure.
  • VT voltage vs. transmittance
  • FIG. 10 is a flow chart of a method for fabricating an array substrate according to at least one embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 1 is a schematic structural view of an array substrate.
  • the array substrate includes a common electrode 1', an insulating layer covering the common electrode 1', and a pixel electrode 2' on the insulating layer.
  • the pixel electrode 2' includes a plurality of pixels tiled on the insulating layer. Electrode strip.
  • an ADS display product which includes, for example, an array substrate as shown in FIG. 1
  • a horizontal electric field is formed by a pixel electrode and a common electrode, and liquid crystal molecules are deflected by the horizontal electric field to form a display screen
  • the ADS electric field generated by the structure shown in FIG. 1 includes a horizontal component Ey effective for deflecting liquid crystal molecules and a vertical component Ez which is ineffective for deflection of liquid crystal molecules, and Ey is strong at the edge of the pixel electrode strip and is in the pixel.
  • the middle position of the middle of the electrode strip and the adjacent pixel electrode strip is weak, and Ez is stronger in the middle of the middle of the pixel strip and the adjacent pixel strip and weaker at the edge of the pixel strip; therefore, as shown in FIG.
  • the ADS shows that the transmittance (ie, light transmittance) of the product varies with the position of the pixel strip. Generally, the transmittance is the largest at the edge of the pixel strip, in the middle of the middle of the pixel strip and the adjacent two pixel strips. The position transmission rate is extremely small.
  • the array substrate includes a substrate 01, first and second electrodes 2 and 2 disposed above the substrate 01 and located in different layers, and The insulating layer 4 between the first electrode 1 and the second electrode 2, the first electrode 1 is located between the substrate 01 and the second electrode 2 in a direction perpendicular to the surface 01A of the substrate 01 facing the insulating layer 4,
  • the two electrodes 2 comprise a plurality of electrode groups 22, each electrode group 22 comprising an electrode strip 21 and an insulating passivation wall 3 interposed between the electrode strips 21 (for example, the passivation wall 3 is made of an insulating material)
  • the arrangement direction of the walls 3 is parallel to the surface 01A of the substrate 01 facing the insulating layer 4.
  • the first electrode 1 is a continuously formed block electrode, and the orthographic projection of the plurality of
  • one of the first electrode 1 and the second electrode 2 is a pixel electrode and the other is a common electrode.
  • the first electrode 1 is a common electrode and the second electrode 2 is a pixel electrode; or, the first electrode 1 is a pixel electrode and the second electrode 2 is a common electrode, in this case, the data on the common electrode and the array substrate
  • the larger distance between the lines is beneficial to increase the transmittance at the edge of the common electrode.
  • the second electrode 2 and the first electrode 1 are both disposed on the array substrate, and the second electrode 2 includes a plurality of electrode strips 21 (ie, strip electrodes), and one side of the electrode strip 21 is provided with
  • the electrode strip 21 is adjacent to the passivation wall 3, so the structure of the second electrode 2 of the present embodiment can be regarded as follows: the second electrode 2 includes a plurality of electrode groups 22, and each electrode group 22 includes a plurality of electrode strips 21 (for example, two electrode strips 21), and a passivation wall 3 is interposed between adjacent electrode strips 21 of the same electrode group 22.
  • the vertical component Ez of the electric field at the position of the passivation wall 3 is weak, and the vertical component Ez of the electric field between the adjacent electrode groups 22 is also weak.
  • a new electric field line is formed between the electrode strip 21 on the inclined surface of the passivation wall 3 and the first electrode 1.
  • the additional horizontal component provided by the small electric field enhances the position of the electrode strip 21 (ie, the electrode group).
  • the horizontal component Ey of the electric field of the edge of 22, therefore, the electric field formed in the array substrate of the embodiment of the present disclosure includes each electrode group 22 in addition to the horizontal electric field formed between each electrode group 22 and the first electrode 1.
  • a plurality of (for example, two) new horizontal electric fields formed between the plurality of (for example, two) electrode strips 21 and the first electrode 1 form a new horizontal electric field to increase the liquid crystal deflection angle, thereby improving transmission. rate.
  • the contact surface of the electrode strip 21 of each electrode group 22 with the passivation wall 3 and the surface of the substrate 01 have an angle which is an acute angle.
  • the passivation wall 3 includes inclined side faces 3A and 3B covered by the electrode strip 21, and the surfaces of the inclined side faces 3A and 3B with respect to the substrate 01 01A is inclined, and the inclined sides 3A and 3B of the same passivation wall 3 have different inclination directions, for example, the inclination directions are opposite.
  • the electrode strips 21 included in the same electrode group 22 are disconnected from each other at the position of the top end 3C of the passivation wall 3, and the top end 3C of the passivation wall 3 is the passivation wall 3 One end away from the substrate 01. Since the adjacent electrode strips 21 included in the same electrode group 22 (that is, the other electrode strips 21 are not disposed between the adjacent electrode strips 21) are disconnected from each other, the electrode strips 21 included in the electrode group 22 and the first electrode 1 are The overlap area between the orthographic projections on the substrate 01 is small, thereby facilitating reduction of the storage capacitance.
  • the adjacent passivation walls 3 of adjacent electrode groups 22 have recessed spaces 9 therebetween.
  • FIG. 2 shows three electrode groups 22 and each electrode group includes a passivation wall 3, the electrode group 22 on the left side is adjacent to the middle electrode group 22, and the passivation wall in the electrode group 22 on the left side. 3 is adjacent to the passivation wall 3 of the middle electrode group 22 (ie, no other passivation walls 3 are provided between the two passivation walls 3), and there is a recessed space 9 between the two passivation walls 3.
  • adjacent electrode strips 21 of adjacent electrode groups 22 are disconnected from each other in the recessed space 9.
  • the right electrode strip 21 in the electrode group 22 on the left side is adjacent to the left electrode strip 21 in the middle electrode group 22, and the two adjacent electrode strips 21 are disconnected from each other. .
  • FIG. 3a A partial structure of the array substrate is shown in Figure 3a corresponding to at least one embodiment of the present disclosure.
  • the substrate 01 is sequentially arranged from bottom to top: a first electrode 1, an insulating layer 4, a second electrode 2, and an insulating layer 4 is disposed between the first electrode 1 and the second electrode 2 such that the first electrode 1 and the second electrode 2 are insulated from each other.
  • the second electrode 2 includes a plurality of electrode groups 22, for example, each electrode group 22 includes two adjacent electrode strips 21; in the direction parallel to the plane of the substrate 01, the two electrodes
  • a passivation wall 3 is sandwiched between the strips 21.
  • the passivation wall 3 and the insulating layer 4 are formed of a transparent insulating material so as not to affect the transmittance of the array substrate.
  • the manner in which the second electrode 2 is connected to the thin film transistor is also shown in FIG. 3a corresponding to at least one embodiment of the present disclosure.
  • the thin film transistor includes a gate electrode 51, a gate insulating layer 52, an active layer 53, a source 54 and a drain 55, and the second electrode 2 is electrically connected to the drain 55 through a via.
  • the second electrode 2 as a pixel electrode may also be directly electrically connected to the drain 55 or electrically connected to the drain 55 through a conductive member.
  • the electrode strips 21 included in the same electrode group 22 are directly electrically connected; or, the electrode strips 21 included in the same electrode group 22 are electrically connected through a conductive structure.
  • 3b and 3c each show the manner in which two adjacent electrode strips 21 (i.e., electrode strips 21 on both sides of the same passivation wall 3) in the same electrode group are connected to the drain 55 of the thin film transistor.
  • two adjacent electrode strips 21 in each electrode group are electrically connected to the drain electrode 55, respectively, so that the two electrode strips 21 are electrically connected through the drain electrode 55 (an example of the above-described conductive structure). Connecting; or, for example, as shown in FIG.
  • one of the electrode strips 21 of the same electrode group is connected to the other electrode strip 21 of the electrode group at a position close to the drain electrode 55, and is electrically connected to the drain electrode 55, thereby The electrode strips 21 included in the same electrode group are directly electrically connected.
  • the second electrodes 2 located in different sub-pixels in an array substrate may be in the above-mentioned electrode group 22 mode, or only a part of the electrodes may be Group 22 is in the form and the other part is in other forms, which can be selected according to actual needs.
  • the insulating layer 4 and the passivation wall 3 are integrally formed. That is to say, the insulating layer 4 and the passivation wall 3 can be formed by the same material using the same mask.
  • the insulating layer 4 and the passivation layer 3 in the embodiment of the present disclosure can be formed by a halftone mask process. This saves process steps and does not increase product costs.
  • the face 21A of the second electrode 2 near the substrate 01 is the same width as the face 21B of the substrate 01 in a direction parallel to the surface 01A of the substrate 01.
  • the cross section of the passivation wall 3 is a trapezoidal shape, so that the design of the electrode strip 21 can be formed by the contact surface of the passivation wall 3, and the electrode strip 21 thus formed is more precise in size.
  • the cross-section of the passivation wall 3 may also be triangular or other similar shape having sloping sides.
  • the electrode strip 21 has a parallelogram in a direction perpendicular to the direction of the substrate 01 and perpendicular to the electrode strip 21. That is, the face 21B of the electrode strip 21 remote from the substrate 01 and the face 21A close to the substrate 01 are parallel to each other, and the side of the electrode strip 21 away from the passivation wall 3 where it is located and the side close to the passivation wall 3 are mutually parallel.
  • the cross section of the passivation wall 3 is trapezoidal, the cross section of the electrode strip 21 formed by the passivation wall 3 in this embodiment is no longer a rectangle, but a parallelogram having the same inclination angle as the trapezoidal bottom angle.
  • the size of the passivation wall 3 of each electrode group 22 is the same as that of the second electrode 2. That is, the thickness of the passivation wall 3 (which may also be referred to as height in FIG. 3) is the same as the thickness of the second electrode 2. If the thickness of the passivation wall 3 is smaller than the thickness of the second electrode 2, it is not easy to form the electrode strip 21 having a precise size; if the thickness of the passivation wall 3 is larger than the thickness of the second electrode 2, the passivation wall 3 is wasted. material.
  • the electrode strip 21 has a width of 0.5 to 1.2 ⁇ m.
  • the distance between the two electrode strips 21 in the electrode group is 1.8 to 3.4 ⁇ m.
  • the distance between adjacent electrode groups is 5.2 - 5.6 ⁇ m.
  • the distance between the two electrode strips 21 in the electrode group described in the embodiment of the present disclosure is also the width of the passivation wall 3.
  • the distance between adjacent electrode groups is the interval between adjacent electrode groups.
  • the first electrode group is adjacent to the second electrode group, and the interval is: parallel to the surface of the second electrode, and A dimension between the electrode strips of the first electrode group adjacent to the second electrode group and the electrode strips of the second electrode group adjacent to the first electrode group in a direction perpendicular to the electrode strip 21.
  • each structural layer shown in the drawings are merely illustrative.
  • the projected area of each structural layer on the substrate may be the same or different.
  • the required projection area of each structural layer can be realized by an etching process; at the same time, the structure shown in the drawing does not limit the geometric shape of each structural layer, and may be, for example, a trapezoid as shown in the drawing, or may be Other shapes can also be achieved by etching.
  • an embodiment of the present disclosure provides an array substrate of an exemplary size: Referring to FIG. 4, in each electrode group 22, the width h1 of each electrode strip is 0.5 ⁇ m, and the passivation wall 3 is in contact with the insulating layer 4 below.
  • the width of the face h2 2 ⁇ m, and the interval between the adjacent two sets of electrode groups 22, that is, the width h3 of the slit is 5 ⁇ m.
  • the comparative example is an ADS array substrate as shown in FIG. 1. After the ADS array substrate shown in FIG. 1 is labeled, as shown in FIG. 5, the pixel electrode 2' and the common electrode 1' form a horizontal electric field, and the liquid crystal is driven by the electric field. The molecules are deflected to form a display.
  • the width h4 of the pixel electrode strip of the pixel electrode 2' is 2.6 ⁇ m, and the pitch h5 of the two pixel electrode strips is 5.4 ⁇ m.
  • the pixel electrode 2' of the comparative example includes the edge electric field distribution of the pixel electrode strip as shown in FIG. 6.
  • the horizontal component Ey of the electric field is extremely strong at the edge of the pixel electrode strip, and is in the middle and phase of the pixel electrode strip.
  • the position between the two adjacent pixel electrodes 2 is extremely weak; the vertical component Ez of the electric field exists at the same time, the extremely strong point of Ez is at the middle of the pixel electrode strip, and the Ez is weak at the edge of the pixel electrode.
  • the array substrate of the embodiment of the present disclosure and the array substrate of the comparative example are simulated by TechWiz 2D software, and the simulation data is simulated.
  • the simulation results are shown in FIG. 7 and FIG. 8.
  • FIG. 7 is a simulation result of the comparative example
  • FIG. 8 is a simulation result of the embodiment of the present disclosure
  • the maximum value of the twist angle is near the bottom surface of the edge of the pixel electrode strip, and the transmittance varies with the position of the pixel strip: the transmittance is the largest at the edge of the pixel strip, and the middle of the pixel strip and the adjacent two
  • the light transmittance in the middle of the pixel electrode strip is extremely small. That is, the position between the single pixel electrode strip and the electric field between the adjacent pixel electrode strips affect the deflection range of the liquid crystal molecules and the deflection angle of the liquid crystal molecules, and the transmittance is low in the above position, and the adjacent pixel electrode strips are in the middle.
  • the liquid crystal torsion angle of the position is only 20 to 30 degrees.
  • the electrode group 22 is divided into two small wall-shaped electrode strips 21, and the presence of the passivation wall 3 eliminates the vertical component Ez of the electric field in the middle of the pixel electrode strip as shown in FIG. 1, in the same electrode group 22.
  • Two new electric fields with dense electric field lines are formed between the two electrode strips 21 and the first electrode of the lower layer, and the two small electric fields provide an additional horizontal electric field, so that the overall electric field is enhanced, and the intermediate position of the passivation wall 3 is made.
  • the liquid crystal is rotated by the newly added horizontal electric field, and the range of the liquid crystal molecules that rotate is increased to increase the transmittance; on the other hand, due to the change of the pattern of the second electrode 2, the adjacent two electrode groups 22 are The Ez becomes weaker, and the adverse effect of the more serious liquid crystal molecules affected by this Ez becomes smaller, thereby further increasing the transmittance.
  • FIG. 9 is a comparison diagram of a VT (voltage transmittance curve) curve of an embodiment of the present disclosure and a comparative example, wherein a is a comparative example Tr (Transmittance), and b is a Tr of the disclosed embodiment, and a curve in the figure
  • Tr Transmission transmittance
  • At least one embodiment of the present disclosure provides a method for fabricating an array substrate as shown in FIG. 2. As shown in FIG. 10, the preparation method includes the following steps S01 to S04.
  • Step S01 forming a first electrode 1 over the substrate, wherein the first electrode 1 may be a full-surface plate electrode.
  • the material of the first electrode 1 may be ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) or a similar transparent conductive material.
  • step S2' an insulating layer 4 is formed on the first electrode 1.
  • a pattern including an insulating layer and its electrode contact vias may be formed using a patterning process.
  • the patterning process includes: depositing a passivation film layer (for example, the material of the passivation film layer includes Si x N y or Si x O y , that is, silicon nitride or silicon oxide, or other inorganic insulating material or organic Insulating material); coating a photoresist on the passivation film layer; exposing the photoresist in a region corresponding to the pattern in which the electrode contacts the via hole, and developing and post-baking the exposed photoresist; Etching to form electrode contact vias; finally, the photoresist is stripped.
  • a passivation film layer for example, the material of the passivation film layer includes Si x N y or Si x O y , that is, silicon nitride or silicon oxide, or other inorganic insulating material or organic Insulating material.
  • step S03 a passivation wall 3 is formed over the insulating layer 4.
  • Steps S03 are similar to the steps of S2'. I won't go into details here.
  • the material of the passivation wall 3 may be the same as or different from the material of the insulating layer 4.
  • step S2' and step S03 may be formed using the same mask, for example, the insulating layer 4 and the passivation wall 3 are formed using a halftone mask process.
  • the materials of the insulating layer 4 and the passivation wall 3 may be selected from Si x N y or Si x O y or the like.
  • step S04 the second electrode 2 including the plurality of electrode strips 21 is formed on the basis of the passivation wall 3.
  • a pattern including the second electrode can be formed using a patterning process.
  • step S04 includes: depositing a second electrode film layer (for example, the material thereof comprises ITO or IZO or a similar transparent conductive material); coating a photoresist on the second electrode film layer; and light on the second electrode film layer The adhesive is exposed and the exposed photoresist is developed and post-baked; the second electrode film layer is etched to form a second electrode 2 including a plurality of electrode strips 21; then photoresist stripping is performed; then annealing is performed deal with.
  • a second electrode film layer for example, the material thereof comprises ITO or IZO or a similar transparent conductive material
  • one of the first electrode 1 and the second electrode 2 is a pixel electrode and the other of the first electrode 1 and the second electrode 2 is a common electrode.
  • the first electrode 1 is located between the substrate 01 and the second electrode 2 in a direction perpendicular to the surface 01A of the substrate 01 facing the insulating layer 4;
  • the arrangement direction of the electrode strip 21 and the passivation wall 3 is parallel to the surface 01A of the substrate 01 and there is an overlap between the electrode strip 21 and the orthographic projection of the passivation wall 3 on the substrate 01.
  • At least one embodiment of the present disclosure provides a display device including a display panel, as shown in FIG. 11 , the display panel includes an opposite substrate 300 and the array substrate 200 provided by any of the above embodiments, and the opposite substrate
  • the liquid crystal 400 between the array substrate 200 and the array substrate 200 is connected to the counter substrate 300 by a sealant 350.
  • the counter substrate 300 is a color filter substrate including a color filter layer.
  • the display device further includes a backlight 50 that provides backlighting for the array substrate 200.
  • the display device may be any product or component having a display function such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the array substrate includes a first electrode, a second electrode, and an insulating layer between the first electrode and the second electrode, the second electrode includes a plurality of electrode groups, and the electrode group includes the electrode strip and the electrode strip.
  • the upper electrode strip enhances the horizontal electric field at the position of the electrode strip, so that the liquid crystal deflection angle can be increased, thereby increasing the transmittance.
  • the array substrate of the present disclosure is suitable for use in various display devices, and is particularly suitable for ADS display products.

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Abstract

一种阵列基板及其制备方法、显示装置，该阵列基板包括第一电极(1)、第二电极(2)以及位于第一电极(1)和第二电极(2)之间的绝缘层(4)，第二电极(2)包括多个电极组(22)，电极组(22)包括电极条(21)与夹设于所述电极条(21)之间的绝缘的钝化墙(3)。该阵列基板具有较高的透过率。

Description

阵列基板及其制备方法、显示装置
对相关申请的交叉参考
本申请要求于2017年9月29日递交的中国专利申请第201710909996.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种阵列基板及其制备方法、显示装置。
背景技术
目前，用户对超高清显示产品的能耗等级的要求越来越严格，这就对显示面板的透过率的要求越来越高。高级超维场开关(Advanced Super Dimensional Switching；ADS)技术是将第一电极和第二电极都设置于阵列基板上的技术；目前，采用ADS技术的显示产品从改进彩膜、偏光片、液晶、像素设计或电极结构等方面来提高透过率。
发明内容
本公开实施例提供一种阵列基板及其制备方法、显示装置，本公开实施例可以提高显示产品的透过率。
本公开的至少一个实施例提供一种阵列基板，其包括衬底、设于衬底上方的第一电极和第二电极、以及位于所述第一电极与第二电极之间的绝缘层；所述第一电极和所述第二电极之一为像素电极且所述第一电极和所述第二电极中的另一个为公共电极；所述第二电极包括多个电极组，所述电极组包括电极条与夹设于所述电极条之间的钝化墙，所述钝化墙由绝缘材料构成。
例如，在与所述衬底的面向所述绝缘层的表面相垂直的方向上，所述第一电极位于所述衬底和所述第二电极之间；在同一电极组中，所述电极条和所述钝化墙的排列方向平行于所述衬底的所述表面并且所述电极条与所述钝化墙在所述衬底上的正投影之间有交叠部分。
例如，每个所述电极组的所述电极条与所述钝化墙之间的接触面与衬底所在面具有夹角，所述夹角为锐角。
例如，在同一电极组中，所述钝化墙包括被所述电极条覆盖的倾斜侧面，并且同一钝化墙的所述倾斜侧面的倾斜方向不同。
例如，同一电极组包括的电极条在所述钝化墙的顶端的位置处彼此断开，所述钝化墙的顶端为所述钝化墙的远离所述衬底的一端。
例如，同一电极组包括的电极条直接电连接。
例如，同一电极组包括的电极条通过导电结构电连接。
例如，相邻电极组的相邻的钝化墙之间具有凹陷空间。
例如，相邻电极组的相邻电极条在所述凹陷空间中彼此断开。
例如，所述第二电极靠近衬底的面与远离衬底的面的宽度相同。
例如，在垂直于所述衬底的方向且垂直于所述电极条延伸的方向上，所述电极条的截面为平行四边形。
例如，在垂直于所述衬底的方向上，每个所述电极组的钝化墙的尺寸与电极条的尺寸相同。
例如，在平行于所述衬底的面向所述绝缘层的表面的方向上，电极条宽度为0.5-1.2μm。
例如，同一电极组中的两根电极条之间的距离为1.8-3.4μm。
例如，相邻的电极组之间的距离为5.2-5.6μm。
例如，所述绝缘层与所述钝化墙为一体成型结构。
本公开至少一个实施例还提供一种阵列基板的制备方法，其包括：在衬底上方形成第一电极；在第一电极上方形成绝缘层；在绝缘层上方形成第二电极，使所述第一电极和所述第二电极之一为像素电极，所述第一电极和所述第二电极中的另一个为公共电极，所述第二电极包括多个电极组，所述电极组包括电极条与夹设于所述电极条之间的钝化墙。
本公开至少一个实施例还提供一种显示装置，其包括对置基板和上述任一实施例提供的阵列基板，以及夹在所述对置基板与阵列基板之间的液晶。
例如，在与所述衬底的面向所述绝缘层的表面相垂直的方向上，所述第一电极位于所述衬底和所述第二电极之间；在同一电极组中，所述电极条和所述钝化墙的排列方向平行于所述衬底的所述表面并且所述电极条与所述钝 化墙在所述衬底上的正投影之间有交叠部分。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的结构示意图；
图2为本公开的至少一个实施例的阵列基板中部分结构的剖视结构示意图；
图3a为本公开的至少一个实施例的阵列基板的剖视结构示意图；
图3b和图3c为图3a所示阵列基板中部分结构的俯视示意图；
图4为对本公开的至少一个实施例的阵列基板进行尺寸标注的示意图；
图5为对对比例的阵列基板进行尺寸标注的示意图；
图6为对比例的阵列基板的电场分布示意图；
图7为对比例的阵列基板的液晶偏转模拟图；
图8为本公开的至少一个实施例的阵列基板的液晶偏转模拟图；
图9为本公开的至少一个实施例的阵列基板以及对比例的阵列基板的VT(电压与透过率)曲线对比图；
图10为本公开的至少一个实施例提供的阵列基板的制备方法流程图；
图11为本公开的至少一个实施例提供的显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来 区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种阵列基板的结构示意图。如图1所示，该阵列基板包括公共电极1’，覆盖公共电极1’的绝缘层以及位于该绝缘层上的像素电极2’，像素电极2’包括多个平铺在绝缘层上的像素电极条。
本申请的发明人发现，在ADS显示产品(其例如包括如图1所示的阵列基板)中，通过像素电极和公共电极形成水平电场，通过该水平电场驱动液晶分子偏转，从而形成显示画面；如图6所示，如图1所示的结构产生的ADS电场包括对液晶分子偏转有效的水平分量Ey和对液晶分子偏转无效的垂直分量Ez，Ey在像素电极条边缘位置较强且在像素电极条中部和相邻像素电极条的中间位置较弱，且Ez在像素电极条中部和相邻像素电极条的中间位置较强并且在像素电极条的边缘位置较弱；因此，如图1所示ADS显示产品的透过率(即光透过率)随像素电极条位置变化，一般其透过率在像素电极条边缘处最大，在像素电极条中部和相邻的两像素电极条的中间位置透过率极小。
本公开至少一个实施例提供一种阵列基板，如图2所示，该阵列基板包括衬底01、设于衬底01上方且位于不同层中的第一电极1和第二电极2、以及位于第一电极1和第二电极2之间的绝缘层4，第一电极1在垂直于衬底01的面向绝缘层4的表面01A的方向上位于衬底01与第二电极2之间，第二电极2包括多个电极组22，每个电极组22包括电极条21与夹设于所述电极条21之间的绝缘的钝化墙3(例如，所述钝化墙3由绝缘材料构成)，该相邻的电极条21与位于该相邻的电极条21之间的钝化墙3在衬底01上的正投影之间有交叠部分，并且该相邻的电极条21和钝化墙3的排列方向平行于衬底01的面向绝缘层4的表面01A。例如，第一电极1为连续形成的块状电极，第二电极2包括的多个电极组22在第一电极1所在面上的正投影位于第一电极1所在区域内。
在本公开实施例中，第一电极1和第二电极2中的一个为像素电极且另一个为公共电极。例如，第一电极1为公共电极并且第二电极2为像素电极；或者，第一电极1为像素电极并且第二电极2为公共电极，在这种情况下，公共电极与阵列基板上的数据线之间的距离较大，有利于提高公共电极边缘处的透过率。
本公开至少一个实施例中将第二电极2和第一电极1均设置在阵列基板上，第二电极2包括多根电极条21(即条状电极)，电极条21的一侧设有与电极条21相邻的钝化墙3，因此本实施例的第二电极2的结构可以看做是：第二电极2包括多个电极组22，每一电极组22中包括多个电极条21(例如两个电极条21)，并且同一电极组22中相邻的电极条21之间夹设有钝化墙3。
在本公开实施例中，钝化墙3所在位置处(即电极组22的中部)的电场的垂直分量Ez较弱，相邻电极组22之间的电场的垂直分量Ez也较弱，形成在钝化墙3的倾斜表面上的电极条21与第一电极1之间形成新的电场线较密的小电场，该小电场提供的额外的水平分量增强了电极条21所在位置(即电极组22的边缘)的电场的水平分量Ey，因此本公开实施例的阵列基板中形成的电场除了包括每一电极组22与第一电极1之间形成的水平电场外，还包括每一电极组22中的多个(例如两个)电极条21与第一电极1之间形成的多个(例如两个)新的水平电场，所形成的新的水平电场可以提高液晶偏转角度，从而提高透过率。
作为本公开实施例中的一种可选实施方案，每个电极组22的电极条21与钝化墙3的接触面与衬底01所在面之间具有夹角，所述夹角为锐角。
作为本公开实施例中的一种可选实施方案，在同一电极组22中，钝化墙3包括被电极条21覆盖的倾斜侧面3A和3B，倾斜侧面3A和3B相对于衬底01的表面01A倾斜，并且同一钝化墙3的倾斜侧面3A和3B的倾斜方向不同，例如倾斜方向相反。
作为本公开实施例中的一种可选实施方案，同一电极组22包括的电极条21在钝化墙3的顶端3C的位置处彼此断开，钝化墙3的顶端3C为钝化墙3的远离衬底01的一端。由于同一电极组22包括的相邻电极条21(即该相邻的电极条21之间未设置其它电极条21)彼此断开，因此该电极组22包括的 电极条21与第一电极1在衬底01上的正投影之间的交叠面积较小，从而有利于减小存储电容。
作为本公开实施例中的一种可选实施方案，相邻电极组22的相邻的钝化墙3之间具有凹陷空间9。例如，图2示出了三个电极组22且每个电极组包括一个钝化墙3，左侧的电极组22与中间的电极组22相邻，左侧的电极组22中的钝化墙3与中间的电极组22的钝化墙3相邻(即这两个钝化墙3之间未设置其它钝化墙3)，并且这两个钝化墙3之间具有凹陷空间9。
作为本公开实施例中的一种可选实施方案，相邻电极组22的相邻电极条21在凹陷空间9中彼此断开。例如，如图2所示，左侧的电极组22中的右侧电极条21与中间的电极组22中的左侧电极条21相邻，并且这两个相邻的电极条21彼此断开。
本公开至少一个实施例对应的附图3a中显示了阵列基板的部分结构。如图3a所示，衬底01上由下至上依次是：第一电极1、绝缘层4，第二电极2，绝缘层4设于第一电极1与第二电极2之间使得第一电极1和第二电极2相互绝缘。如图2所示，第二电极2包括多个电极组22，例如，每一电极组22包括相邻的两个电极条21；在与衬底01所在面相平行的方向上，这两个电极条21之间夹设有钝化墙3。需要说明的是，钝化墙3和绝缘层4是由透明的绝缘材料形成，这样不会影响阵列基板的透过率。
在第二电极2为像素电极的情况下，本公开至少一个实施例对应的附图3a中还显示了第二电极2与薄膜晶体管的连接方式。例如，如图3所示，薄膜晶体管包括栅极51、栅绝缘层52、有源层53、源极54和漏极55，第二电极2通过过孔与漏极55电连接。在其它实施例中，作为像素电极的第二电极2也可以与漏极55直接电连接，或者通过导电部件与漏极55电连接。
例如，同一电极组22包括的电极条21直接电连接；或者，同一电极组22包括的电极条21通过导电结构电连接。
图3b和图3c都示出了同一电极组中相邻的两个电极条21(即位于同一钝化墙3两侧的电极条21)与薄膜晶体管的漏极55的连接方式。例如，如图3b所示，每一个电极组中相邻的两个电极条21分别电连接至漏极55，从而这两个电极条21通过漏极55(上述导电结构的一个示例)实现电连接；或者，例如，如图3c所示，同一电极组中的一个电极条21在靠近漏极55 的位置处连接至该电极组中的另一个电极条21后电连接至漏极55，从而同一电极组包括的电极条21直接电连接。
需要说明的是，一个阵列基板中的位于不同子像素中的第二电极2(例如与不同薄膜晶体管电连接的第二电极2)可以均为上述电极组22模式，或者可以只有一部分为上述电极组22形式且另一部分为其它形式，这可以根据实际需要进行选择。
作为本公开实施例的一种可选实施方案，绝缘层4与钝化墙3为一体成型结构。也就是说，绝缘层4与钝化墙3可以采用同一种材料利用同一掩膜板形成，例如可以采用半色调掩膜工艺形成本公开实施例中的绝缘层4和钝化层3。这样节省工艺步骤，不会增加产品成本。
在一个实施例中，在平行于衬底01的表面01A的方向上，所述第二电极2靠近衬底01的面21A与远离衬底01的面21B的宽度相同。
参见图3的截面图，可以看出：钝化墙3远离入光侧(即背光源发出的光的入射侧)一面的正投影面积落入且小于靠近入光侧的一面的正投影面积，即钝化墙3的截面是一个梯形，这样设计的作用是：在后续形成电极条21时，电极条21可以依附钝化墙3的接触面形成，这样形成的电极条21尺寸更精准。在其它实施例中，钝化墙3的截面也可以是三角形或者其它类似的具有倾斜侧面的形状。
在一个实施例中，在垂直于衬底01的方向且垂直于所述电极条21延伸的方向上，电极条21的截面为平行四边形。也就是说，电极条21的远离衬底01的面21B和靠近衬底01的面21A相互平行，且电极条21的远离其所在的钝化墙3的侧面与靠近钝化墙3的侧面彼此平行。
参见图3，由于上述钝化墙3的截面是梯形，因此本实施例中依附钝化墙3形成的电极条21的截面不再是矩形，而是倾斜角度与梯形底角相同的平行四边形。
例如，在垂直于衬底01的表面01A的方向上，每个电极组22的钝化墙3的尺寸与第二电极2的尺寸相同。也就是说，钝化墙3的厚度(图3中也可称为高度)与第二电极2的厚度相同。若钝化墙3的厚度小于第二电极2的厚度，那么不容易形成尺寸精准的电极条21；若钝化墙3的厚度大于所述第二电极2的厚度，则浪费钝化墙3的材料。
例如，在平行于衬底01的表面01A的方向上，电极条21宽度为0.5-1.2μm。例如，在平行于衬底01的表面01A的方向上，电极组中的两根电极条21之间的距离为1.8-3.4μm。例如，在平行于衬底01的表面01A的方向上，相邻的电极组之间的距离为5.2-5.6μm。
本公开实施例中所述的电极组中的两根电极条21之间的距离也就是钝化墙3的宽度。相邻的电极组之间的距离也就是相邻的电极组之间的间隔，例如，第一电极组与第二电极组相邻，上述间隔是指：在平行于第二电极所在面，且垂直于电极条21的方向上，第一电极组中的靠近第二电极组的电极条与第二电极组中的靠近第一电极组的电极条之间的尺寸。
需要说明的是，附图所示各结构层的大小、厚度等仅为示意。在工艺实现中，各结构层在衬底上的投影面积可以相同，也可以不同。例如，可以通过刻蚀工艺实现所需的各结构层投影面积；同时，附图所示结构也不限定各结构层的几何形状，例如可以是附图所示的还可以是梯形，还可以是其它的形状，同样可通过刻蚀实现。
在此本公开实施例给出一种示例性尺寸的阵列基板：参见图4，每一电极组22中，每根电极条的宽度h1是0.5μm，钝化墙3与下方的绝缘层4接触的面的宽度h2＝2μm，相邻的两组电极组22的间隔即缝隙的宽度h3是5微米。
对比例：对比例为如图1所示的ADS阵列基板，对图1所示ADS阵列基板进行标注后如图5所示，像素电极2’和公共电极1’形成水平电场，通过电场驱动液晶分子偏转，从而形成显示画面。像素电极2’的像素电极条的宽度h4为2.6μm，两像素电极条的间距h5为5.4μm。
对比例的像素电极2’包括像素电极条的边缘电场分布如图6所示，从图6中可以看出：电场的水平分量Ey在像素电极条边缘位置极强，在像素电极条中部和相邻的两像素电极2中间的位置极弱；电场的垂直分量Ez同时存在，Ez的极强点在像素电极条中部位置，Ez极弱点在像素电极边缘。
在本公开实施例的阵列基板的第一电极1为公共电极且第二电极2为像素电极的情况下，将本公开实施例的阵列基板与对比例的阵列基板通过TechWiz 2D软件模拟，模拟数据为：LC MAT-09-1284，模拟结果参见图7、图8，其中，图7为对比例的模拟结果，图8为本公开实施例的模拟结果， 图7、图8中的横坐标代表实际模拟区域，纵坐标代表透过率。
从图7、图8中可以看出如下模拟结果。
对比例的图7中扭转角最大值在像素电极条边缘底表面附近，透过率随像素电极条位置变化：透过率在像素电极条边缘处最大，在像素电极条中部和相邻的两像素电极条中间位置光透过率极小。即单根像素电极条中间的位置以及相邻像素电极条之间的电场会影响液晶分子的偏转范围及液晶分子偏转角度，透过率在上述位置是偏低的，相邻的像素电极条中间位置的液晶扭转角只有20～30°。
本公开实施例中：电极组22被分成两个小的墙型电极条21，钝化墙3的存在消除了如图1所示像素电极条中部的电场的垂直分量Ez，同一电极组22中两个电极条21与下层的第一电极之间形成两个新的、且电场线较密的小电场，两小电场提供了额外的水平电场，使得整体电场增强，使钝化墙3中间位置的液晶受新额外增加的水平电场发生旋转，发生旋转的液晶分子范围增大，从而增大透过率；另一方面，由于第二电极2图案的变化，使得相邻两电极组22之间的Ez变弱了，受使此Ez影响的较为严重的液晶分子的不利影响变小了，从而进一步提升透过率。
上述不同结果的产生是由于电极结构的改变，对比例中的Cst(存储电容)＝正向Cst(70％)+侧向Cst(30％)，本公开实施例中正向Cst大大减少，所以Cst＝正向Cst(40％)+侧向Cst(30％)；Cst约降低30％，阵列基板充电时间及充电率都大大提升，透过率提升4％以上，从而提升了显示品质。
图9为本公开实施例以及对比例的VT(电压透过率曲线)曲线对比图，其中，a为对比例Tr(Transmittance，透过率)，b为本公开实施例Tr，图中a曲线的最大值为0.285745，b曲线的最大值为0.297947，Tr提升4.27％。
本公开至少一个实施例提供一种如图2所示的阵列基板的制备方法，如图10所示，该制备方法包括以下步骤S01至步骤S04。
步骤S01、在衬底上方形成第一电极1，其中，第一电极1可以是整面的板状电极。
例如，第一电极1的材料可以是ITO(氧化铟锡)或IZO(氧化铟锌)或类似的透明导电材料。
步骤S2’、在第一电极1上形成绝缘层4。
例如，可以采用一次构图工艺形成包括绝缘层及其电极接触过孔的图形。
例如，在该步骤中，构图工艺包括：沉积钝化膜层(例如钝化膜层的材料包括Si xN y或Si xO y，即氮化硅或氧化硅，或者其它无机绝缘材料或有机绝缘材料)；在钝化膜层上涂覆光刻胶；在对应形成电极接触过孔图形的区域对光刻胶进行曝光，并对曝光后的光刻胶进行显影和后烘处理；之后进行刻蚀以形成电极接触过孔；最后，将光刻胶剥离。
步骤S03、在绝缘层4上方形成钝化墙3。
步骤S03与S2’的步骤类似。这里不再赘述。例如，钝化墙3的材料可以与绝缘层4的材料相同，也可以不同。
例如，步骤S2’与步骤S03可以利用同一个掩膜板形成，例如，绝缘层4与钝化墙3采用半色调掩膜工艺形成。在这种情况下，例如，绝缘层4及钝化墙3的材料都可以选择Si xN y或Si xO y或类似绝缘材料。
步骤S04、以钝化墙3为依托，形成包括多个电极条21的第二电极2。
例如，可以采用一次构图工艺形成包括第二电极的图形。例如，步骤S04包括：沉积第二电极膜层(例如，其材料包括ITO或IZO或类似透明导电材料)；在第二电极膜层上涂覆光刻胶；对第二电极膜层上的光刻胶进行曝光并对曝光后的光刻胶进行显影和后烘处理；刻蚀第二电极膜层以形成包括多个电极条21的第二电极2；然后进行光刻胶剥离；之后进行退火处理。
在本公开实施例提供的制备方法中，第一电极1和第二电极2之一为像素电极且第一电极1和第二电极2中的另一个为公共电极。
例如，在本公开实施例提供的制备方法中，在与衬底01的面向绝缘层4的表面01A相垂直的方向上，第一电极1位于衬底01和第二电极2之间；在同一电极组22中，电极条21和钝化墙3的排列方向平行于衬底01的表面01A并且电极条21与钝化墙3在衬底01上的正投影之间有交叠部分。
本公开至少一个实施例提供一种显示装置，其包括显示面板，如图11所示，显示面板包括对置基板300和上述任一实施例提供的阵列基板200，以及夹在所述对置基板300与阵列基板200之间的液晶400，阵列基板200与对置基板300通过封框胶350连接。
例如，对置基板300为包括彩色滤光层的彩膜基板。
在一些实施例中，该显示装置还包括为阵列基板200提供背光的背光源50。
例如，所述显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例中，阵列基板包括第一电极、第二电极以及位于第一电极和第二电极之间的绝缘层，第二电极包括多个电极组，电极组包括电极条与夹设于所述电极条之间的钝化墙，钝化墙所在位置处的电场的垂直分量Ez较弱，相邻电极组之间的电场的垂直分量Ez也较弱，形成在钝化墙的倾斜表面上的电极条增强了电极条位置处的水平电场，因此可以提高液晶偏转角度，从而提高透过率。本公开的阵列基板适用于各种显示装置，尤其适用于ADS显示产品。
以上关于阵列基板及其制作方法和显示装置的实施例可以互相参照，重复之处不再赘述。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (19)

  1. 一种阵列基板，包括：
    衬底；
    设于所述衬底上方的第一电极和第二电极，其中，所述第一电极和所述第二电极之一为像素电极且所述第一电极和所述第二电极中的另一个为公共电极；以及
    位于所述第一电极与所述第二电极之间的绝缘层；
    其中，所述第二电极包括多个电极组，所述电极组包括电极条与夹设于所述电极条之间的绝缘的钝化墙。
  2. 根据权利要求1所述的阵列基板，其中，
    在垂直于所述衬底的面向所述绝缘层的表面的方向上，所述第一电极位于所述衬底和所述第二电极之间；
    在同一电极组中，所述电极条和所述钝化墙的排列方向平行于所述衬底的所述表面并且所述电极条与所述钝化墙在所述衬底上的正投影之间有交叠部分。
  3. 根据权利要求1或2所述的阵列基板，其中，每个所述电极组的所述电极条与所述钝化墙之间的接触面与所述衬底所在面之间具有夹角，所述夹角为锐角。
  4. 根据权利要求1-3中任一项所述的阵列基板，其中，在同一电极组中，所述钝化墙包括被所述电极条覆盖的倾斜侧面，并且同一钝化墙的所述倾斜侧面的倾斜方向不同。
  5. 根据权利要求1-4中任一项所述的阵列基板，其中，同一电极组包括的电极条在所述钝化墙的顶端的位置处彼此断开，所述钝化墙的顶端为所述钝化墙的远离所述衬底的一端。
  6. 根据权利要求5所述的阵列基板，其中，同一电极组包括的电极条直接电连接。
  7. 根据权利要求5所述的阵列基板，其中，同一电极组包括的电极条通过导电结构电连接。
  8. 根据权利要求1-7中任一项所述的阵列基板，其中，相邻电极组的相 邻的钝化墙之间具有凹陷空间。
  9. 根据权利要求8所述的阵列基板，其中，相邻电极组的相邻电极条在所述凹陷空间中彼此断开。
  10. 根据权利要求1-9中任一项所述的阵列基板，其中，所述第二电极的靠近衬底的面与远离衬底的面的宽度相同。
  11. 根据权利要求1-10中任一项所述的阵列基板，其中，在垂直于所述衬底的方向且垂直于所述条状第二电极延伸的方向上，所述电极条的截面为平行四边形。
  12. 根据权利要求1-11中任一项所述的阵列基板，其中，在垂直于所述衬底的方向上，每个所述电极组的钝化墙的尺寸与电极条的尺寸相同。
  13. 根据权利要求1-12中任一项所述的阵列基板，其中，在平行于所述衬底的面向所述绝缘层的表面的方向上，电极条宽度为0.5-1.2μm。
  14. 根据权利要求1-13中任一项所述的阵列基板，其中，同一电极组中的相邻电极条之间的距离为1.8-3.4μm。
  15. 根据权利要求1-14中任一项所述的阵列基板，其中，相邻的电极组之间的距离为5.2-5.6μm。
  16. 根据权利要求1-15中任一项所述的阵列基板，其中，所述绝缘层与所述钝化墙为一体成型结构。
  17. 一种显示装置，包括对置基板和权利要求1-16中任一项所述的阵列基板、以及夹在所述对置基板与所述阵列基板之间的液晶。
  18. 一种阵列基板的制备方法，包括：
    在衬底上方形成第一电极；
    在所述第一电极上方形成绝缘层；
    在所述绝缘层上方形成第二电极，其中，所述第一电极和所述第二电极之一为像素电极且所述第一电极和所述第二电极中的另一个为公共电极；所述第二电极包括多个电极组，所述电极组包括电极条与夹设于所述电极条之间的钝化墙。
  19. 根据权利要求18所述的制备方法，其中，
    在与所述衬底的面向所述绝缘层的表面相垂直的方向上，所述第一电极位于所述衬底和所述第二电极之间；
    在同一电极组中，所述电极条和所述钝化墙的排列方向平行于所述衬底的所述表面并且所述电极条与所述钝化墙在所述衬底上的正投影之间有交叠部分。
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