WO2019050255A1

WO2019050255A1 - Printed circuit board assembly

Info

Publication number: WO2019050255A1
Application number: PCT/KR2018/010300
Authority: WO
Inventors: 황보훈
Original assignee: 삼성전자주식회사
Priority date: 2017-09-06
Filing date: 2018-09-04
Publication date: 2019-03-14
Also published as: KR20190027141A

Abstract

A printed circuit board assembly may comprise: a main printed circuit board; and a sub printed circuit board mounted on the main printed circuit board. The main printed circuit board may comprise: a first main conductor layer including a first main signal line and a second main signal line; a second main conductor layer including a third main signal line disposed between the first main signal line and the second main signal line; and a main dielectric layer for insulating the first main conductor layer from the second main conductor layer. The sub printed circuit board may comprise: a first sub conductor layer including a first sub signal line connected to the first main signal line and the second main signal line; and a sub dielectric layer for insulating the first sub conductor layer from the first main conductor layer.

Description

Printed Circuit Board Assembly

The disclosed invention relates to a printed circuit board assembly, and more particularly, to a printed circuit board assembly including a main printed circuit board on which a main circuit is formed and a sub printed circuit board on which a sub circuit is formed.

Generally, a printed circuit board mechanically supports electronic components and electrically connects electronic components (e.g., integrated circuit elements, resistors, capacitors, inductors, switches, etc.) electrically with conductive lines, pads and plates Connect each other. Conductive lines, pads, and plates are etched from a metal sheet (e.g., a copper sheet) on a nonconductive substrate. In addition, the electronic components are soldered onto a printed circuit board.

Printed circuit boards are distinguished as single-sided printed circuit boards, double-sided printed circuit boards or multilayer printed circuit boards depending on the number of conductive layers including conductive lines, conductive pads and conductive plates. The multilayer printed circuit board is variously classified into a four-layer printed circuit board, a six-layer printed circuit board, and an eight-layer printed circuit board.

The conductive lines, the conductive pads, and the conductive plate formed on the printed circuit board can be distinguished by a signal transmission member through which a signal is transmitted according to function, a power supply member supplied with electric power, and a ground member connected with the ground.

The signal may be transmitted to the signal receiving component as a signal transmitting component by the signal transmitting member. The transmission of the signal produces a current flow. In other words, when a signal is transmitted from the signal transmitting part to the signal receiving part through the signal transmitting member, a current flows from the signal transmitting part to the signal receiving part through the signal transmitting member. A return current flows from the signal receiving part to the signal transmitting part in order to eliminate the imbalance of the charge due to the current flow. At this time, the return current can be returned to the signal receiving part through the power supply member or the ground member.

Thus, the current by the signal is transmitted through the signal transmission member, and a return path is formed in which the return current returns to the power supply member or the ground member.

If the return path is disconnected or the length of the return path becomes long, electro-magnetic interference (EMI) may be generated from the printed circuit board, and the waveform of the signal may be distorted and the correct operation may not be possible. In particular, when an analog circuit or a high-speed digital circuit is mounted on a printed circuit board, the deformation of the electromagnetic interference signal waveform can be further increased.

One aspect of the disclosed invention is to provide a printed circuit board that ensures a return path corresponding to a signal transmission line.

One aspect of the disclosed invention is to provide a printed circuit board assembly that can provide a return path of a main printed circuit board using a sub printed circuit board.

One aspect of the disclosed invention is to provide a printed circuit board assembly having a sub-printed circuit board for providing a return path at a portion where signal transmission lines of a main printed circuit board intersect.

The printed circuit board assembly according to an aspect of the disclosed invention may include a main printed circuit board and a sub printed circuit board mounted on the main printed circuit board. The main printed circuit board includes: a first main conductor layer including a first main signal line and a second main signal line; A second main conductor layer including a third main signal line disposed between the first main signal line and the second main signal line; And a main dielectric layer for insulating the first main conductor layer and the second main conductor layer from each other. The sub printed circuit board includes a first sub conductor layer including a first sub signal line connected to the first main signal line and the second main signal line; And a sub-dielectric layer for insulating the first sub-conductor layer and the first main conductor layer from each other.

The second main conductor layer may further include a main ground plate separated from the third main signal line. The first main conductor layer may further include a main ground line connected to the main ground plate and at least partially overlapped with the third main signal line.

The first main signal line, the first sub signal line, and the second main signal line may form a signal transmission path. The main ground plate and the main ground line may form a return path for the signal transmission path.

The sub-printed circuit board may further include a second sub-conductor layer including a sub-ground plate connected to the main ground plate. The sub-dielectric layer may isolate the first sub-conductor layer from the second sub-conductor layer.

The first main signal line, the first sub signal line, and the second main signal line may form a signal transmission path. The main ground plate and the sub ground plate may form a return path for the signal transmission path.

The sub-printed circuit board includes a second sub signal line connected to the first main signal line and the first sub signal line, a third sub signal line connected to the second main signal line and the first sub signal line, And a second sub-conductor layer containing a line. The sub-dielectric layer may isolate the first sub-conductor layer from the second sub-conductor layer.

A first main soldering pad is formed at one end of the first main signal line to be in contact with the second sub signal line and a second main solder pad is formed at one end of the second main signal line, Can be formed.

A first sub solder pad is formed at one end of the second sub signal line to be in contact with the first main signal line and a second sub solder pad is formed at one end of the third sub signal line in contact with the second main signal line, Can be formed.

And a first electronic device and a second electronic device mounted on the main printed circuit board. The first electronic device may be connected to the first main signal line and the second electronic device may be connected to the second main signal line.

The sub printed circuit board may be mounted on the surface of the main printed circuit board by surface mounting technology.

The printed circuit board assembly according to an aspect of the disclosed invention may include a main printed circuit board and a sub printed circuit board mounted on the main printed circuit board. The main printed circuit board includes: a first main conductor layer including a first main signal line and a second main signal line separated from each other at a first position; A second main conductor layer including a first main ground plate and a second main ground plate separated from each other at a second position corresponding to the first position; And a main dielectric layer for insulating the first main conductor layer and the main second conductor layer. The sub printed circuit board includes a first sub conductor layer including a first sub signal line connected to the first main signal line and the second main signal line; And a sub-dielectric layer for insulating the first sub-conductor layer and the first main conductor layer from each other.

According to an aspect of the disclosed invention, it is possible to provide a printed circuit board ensuring a return path corresponding to a signal transmission line.

According to an aspect of the disclosed invention, a printed circuit board assembly capable of providing a return path of a main printed circuit board using a sub printed circuit board can be provided.

According to an aspect of the disclosed subject matter, there is provided a printed circuit board assembly having a sub printed circuit board for providing a return path at a portion where signal transmission lines of a main printed circuit board intersect.

1 illustrates an example of a printed circuit board assembly according to one embodiment.

Fig. 2 shows a cross section taken along the line A-A 'shown in Fig.

Figure 3 illustrates another example of a printed circuit board assembly according to one embodiment.

Fig. 4 shows a cross section taken along the line B-B 'shown in Fig.

FIG. 5 shows the intensity of electromagnetic waves generated by the printed circuit board assembly shown in FIG.

6 illustrates another example of a printed circuit board assembly according to one embodiment.

FIG. 7 shows an example of a main printed circuit board included in the printed circuit board assembly shown in FIG.

Fig. 8 shows an example of a sub printed circuit board included in the printed circuit board assembly shown in Fig.

Fig. 9 shows a cross section taken along line C-C 'shown in Fig.

FIG. 10 shows the intensity of electromagnetic waves generated by the printed circuit board assembly shown in FIG.

11 illustrates another example of a sub printed circuit board included in a printed circuit board assembly according to an embodiment.

12 shows another example of a main printed circuit board included in a printed circuit board assembly according to an embodiment.

Figures 13, 14 and 15 illustrate sub-printed circuit board libraries according to one embodiment.

Like reference numerals refer to like elements throughout the specification. The present specification does not describe all elements of the embodiments, and redundant description between general contents or embodiments in the technical field of the present invention will be omitted. The term 'part, module, member, or block' used in the specification may be embodied in software or hardware, and a plurality of 'part, module, member, and block' may be embodied as one component, It is also possible that a single 'part, module, member, block' includes a plurality of components.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only the case directly connected but also the case where the connection is indirectly connected, and the indirect connection includes connection through the wireless communication network do.

Also, when an element is referred to as " comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

Throughout the specification, when a member is located on another member, it includes not only when a member is in contact with another member but also when another member exists between the two members.

The terms first, second, etc. are used to distinguish one element from another, and the elements are not limited by the above-mentioned terms.

The singular forms " a " include plural referents unless the context clearly dictates otherwise.

In each step, the identification code is used for convenience of explanation, and the identification code does not describe the order of the steps, and each step may be performed differently from the stated order unless clearly specified in the context. have.

Hereinafter, the working principle and embodiments of the present invention will be described with reference to the accompanying drawings.

1 illustrates an example of a printed circuit board assembly according to one embodiment. Fig. 2 shows a cross section taken along the line A-A 'shown in Fig.

1 and 2, the printed circuit board assembly 1 may include at least two

conductor layers

10 and 30 and at least one dielectric layer 20. [

1, the printed circuit board assembly 1 includes a first conductor layer 10 and a second conductor layer 30 provided in parallel with each other, a first conductor layer 10 and a second conductor layer 30 And a dielectric layer 20 interposed between the dielectric layers. 1 illustrates a double-sided printed circuit board including first and second conductor layers 30 and dielectric layer 20, but is not limited thereto. For example, the printed circuit board assembly 1 may be a four-layer printed circuit board assembly comprising four conductor layers and two dielectric layers, or a six-layer printed circuit board assembly comprising six conductor layers and four dielectric layers Lt; / RTI > Further, the printed circuit board assembly may be a printed circuit board having eight or more layers.

The first conductor layer 10 may include a variety of conductive patterns, such as lines, pads, plates, etc., made of a conductive material (e.g., metal, carbon nanotube, etc.). These conductive patterns may include signal transmission patterns (e.g., lines, pads, plates), power supply patterns, and ground patterns depending on their function.

The signal transmission pattern may refer to lines, pads, plates, etc. that transmit electrical signals between elements.

The power supply pattern means a line, a pad, a plate, or the like for supplying electric power to the elements from a power supply (e.g., a battery or the like), and a predetermined voltage may be applied to the power supply pattern.

The ground pattern may refer to a line, pad, plate, or the like that outputs a reference potential with respect to a voltage applied by the power supply pattern.

In addition, various electronic components such as a resistor, a capacitor, an inductor, a switch, and an integrated circuit element may be mounted on the first conductor layer 10. A signal transmission pattern, a power supply pattern, and a ground pattern are provided between the electronic components. Power is supplied to the electronic components through the power supply pattern and the ground pattern. Through the signal transmission pattern, You can send and receive.

Thus, various conductive patterns and various electronic components receive signals, information, data, and the like from other circuits, process electrical signals, information, data, etc., and form electric circuits that output processed signals, information, and data can do.

The first electronic element 41 and the second electronic element 42 may be mounted on the first conductor layer 10. The first electronic device 41 and the second electronic device 42 may be various devices such as switches, resistors, capacitors, and integrated circuit devices, respectively, and may process input signals and output processed signals.

The first conductor layer 10 includes a first power line 11 that supplies power to the first electronic component 41 and a first ground line 13 that provides ground to the first electronic component 41 . The first conductor layer 10 also includes a second power line 12 for supplying power to the second electronic component 42 and a second ground line 14 for providing ground to the second electronic component 42 .

The first conductor layer 10 includes an upper signal line 15 provided between the first electronic element 41 and the second electronic element 42 and connected to the first electronic element 41 and the second electronic element 42, . The upper surface signal line 15 can transmit signals between the first electronic device 41 and the second electronic device 42. [ Other

top signal lines

15a and 15b may be further provided between the first electronic device 41 and the second electronic device 42 and other

top signal lines

15a and 15b may also be provided between the first electronic device 41 and the second electronic device 42. [ A signal can be transmitted between the element 41 and the second electronic element 42.

The first power line 11, the first ground line 13, the top signal line 15 and the other

signal top lines

15a and 15b are electrically conductive materials (e.g., metal, Carbon nanotubes, and the like).

The first electronic component 41 and the second electronic component 42 may be mounted by surface mount technology (SMT). The first and

second power lines

11 and 12 and the first and

second ground lines

13 and 14 are formed on the surface of the dielectric layer 20 by, for example, a deposition process and an etching process.

Conductive patterns

11, 12, 13, 14, and 15 including the upper surface signal line 15 may be formed. The first electronic component 41 and the second electronic component 42 may be mounted directly on the

conductive patterns

11, 12, 13, 14, 15 of the first conductor layer 10. In other words, the first electronic component 41 and the second electronic component 42 can be soldered directly onto the

conductive patterns

11, 12, 13, 14, 15 of the first conductor layer 10.

Specifically, the solder pads of the

conductive patterns

11, 12, 13, 14 and 15 are coated with a solder paste mixed with flux and solder powder, and the first electronic element 41 and the second electronic element 42 are electrically conductive Can be placed on the soldering pads of the

patterns

11, 12, 13, 14, 15. Thereafter, the first electronic element 41 and the second electronic element 42 can be soldered to the soldering pads of the

conductive patterns

11, 12, 13, 14, 15 by heating, The

elements

41 and 42 may be electrically connected to the

conductive patterns

11, 12, 13, 14 and 15, respectively.

The second conductor layer 30 may also include various patterns such as conductive lines, pads, and plates as well as the first conductor layer 10. In addition, the conductive patterns may include a signal transmission pattern, a power supply pattern, and a ground pattern depending on their functions.

In addition, various electronic components such as a resistor, a capacitor, an inductor, a switch, and an integrated circuit device can be mounted on the second conductor layer 30.

The second conductor layer 30 may include a ground plate 31.

The ground plate 31 may provide grounding to the entire printed circuit board assembly 1. In other words, the ground plate 31 provides the reference potential of the signal processing performed by the first electronic component 41 and the second electronic component 42 included in the printed circuit board assembly 1, It is possible to provide a reference potential of a signal transmitted between the element 41 and the second electronic element 42. [ The ground plate 31 may be made of a conductive material capable of passing electricity therethrough.

The dielectric layer 20 is provided between the first conductor layer 10 and the second conductor layer 30 and may be made of a dielectric material that is not electrically conductive. For example, the dielectric layer 20 may be composed of phenol resin, epoxy resin, polyimide resin, or the like.

The dielectric layer 20 can insulate the first conductor layer 10 and the second conductor layer 30 from each other. Therefore, the signal transmitted through the upper signal line 15 formed in the first conductor layer 10 may not be directly transmitted to the second conductor layer 30. [

A via hole may be formed in the dielectric layer 20 to penetrate the dielectric layer 20. The via hole may have the form of a hole passing through the first conductor layer 10, the dielectric layer 20, and the second conductor layer 30. Further, the inside of the via hole may be filled with a conductive material, or the inner surface of the via hole may be coated (coated) with a conductive material. The signal can be transferred from the first conductor layer 10 to the second conductor layer 30 through the via hole or from the second conductor layer 30 to the first conductor layer 10.

For example, a first via hole 21 and a second via hole 22 may be formed through the dielectric layer 20.

The first and second via

holes

21 and 22 are filled with a conductive material or have a conductive material coated on the inner surface thereof to allow electricity to pass therethrough.

The first via hole 21 can electrically connect the first ground line 13 of the first conductor layer 10 and the ground plate 31 of the second conductor layer 30. Specifically, one end of the first via hole 21 is connected to the first ground line 13, and the other end of the first via hole 21 is connected to the ground plate 31.

The second via hole 22 may electrically connect the second ground line 14 of the first conductor layer 10 and the ground plate 31 of the second conductor layer 30. One end of the second via hole 22 is connected to the second ground line 14 and the other end of the second via hole 22 is connected to the ground plate 31.

The first and

second ground lines

13 and 14 and the ground plate 31 can have the same potential by the first and second via

holes

21 and 22. In other words, the first ground line 13 can provide the same grounding as the ground plate 31 to the first electronic element 41 by the first via hole 21, The second ground line 14 can provide the same ground to the second electronic component 42 as the ground plate 31. Accordingly, the first electronic element 41 and the second electronic element 42 can be provided with the same ground as the ground plate 31. [

The first signal may be transmitted from the first electronic device 41 to the second electronic device 42 via the top signal line 15. [

2, the first signal current SC1 by the first signal can flow from the first electronic device 41 to the second electronic device 42 via the top signal line 15, for example, have.

As is well known, current represents the flow of charge. A positive charge is accumulated in the second electronic element 42 by the first signal current SC1 from the first electronic element 41 to the second electronic element 42 and negative charge Can be accumulated. Thus, a charge imbalance may occur between the first electronic element 41 and the second electronic element 42, which may result in a difference in potential between the first electronic element 41 and the second electronic element 42 .

Such a charge imbalance may result in a first return current RC1 from the second electronic component 42 to the first electronic component 41. [ In other words, the first return current RC1 can be generated by the first signal current SC1.

This first return current RC1 may be provided from the second electronic component 42 to the first electronic component 41 through the power supply patterns and / or ground patterns. For example, the first return current RC1 may be applied to the second electronic element 42 from the second ground line 14, the second via hole 22, the ground plate 31, the first via hole 21, May be provided to the first electronic element 41 via the first ground line 13.

The unbalance of the charge between the first electronic device 41 and the second electronic device 42 is canceled by the first return current RC1 and the first electronic device 41 and the second electronic device 42 are erroneously operated It is possible to operate without the need.

As such, the return current is generated by the signal current and can be transmitted from the signal receiving element to the signal transmitting element through the ground patterns and / or power supply patterns of the printed circuit board assembly 1. [

If the return path through which the return current flows is cut off or the length of the litter pass becomes long, electromagnetic interference (EMI) may occur.

Figure 3 illustrates another example of a printed circuit board assembly according to one embodiment. Fig. 4 shows a cross section taken along the line B-B 'shown in Fig. FIG. 5 shows the intensity of electromagnetic waves generated by the printed circuit board assembly shown in FIG.

3 and 4, the same reference numerals as those of FIGS. 1 and 2 are used for the same configurations as those shown in FIG. 1 and FIG.

3, 4, and 5, the printed circuit board assembly 2 may include at least two

conductor layers

10, 30 and at least one dielectric layer 20.

The printed circuit board assembly 2 may include a first conductor layer 10, a second conductor layer 30, and a dielectric layer 20, as shown in FIG.

The first conductor layer 10 includes a first power line 11, a second power line 12, a first ground line 13, a second ground line 14 and a top signal line 15, A first electronic element (41) and a second electronic element (42) are mounted on the first conductor layer (10). Here, the first and second

electronic elements

41 and 42, the first and

second power lines

11 and 12, the first and

second ground lines

13 and 14, 1 and 2 and the first and second

electronic elements

41 and 42, the first and

second power lines

11 and 12, the first and

second ground lines

13 and 14, 15).

The second conductor layer 30 may include a bottom signal line 32, a first ground plate 33, and a second ground plate 34.

The signal line 32 can transmit signals between electronic components not shown in the figure. The signal line 32 may be made of a conductive material capable of passing electricity therethrough.

The ground plate of the second conductor layer 30 can be partitioned into the first ground plate 33 and the second ground plate 34 by the signal line 32. The first and

second ground plates

33 and 34 may provide grounding to the

electronic components

41 and 42 of the printed circuit board assembly 2, respectively.

The dielectric layer 20 is provided between the first conductor layer 10 and the second conductor layer 30 and can insulate the first conductor layer 10 and the second conductor layer 30 from each other.

The dielectric layer 20 may be formed with first and second via

holes

21 and 22 through the dielectric layer 20. The first via hole 21 electrically connects the first ground line 13 of the first conductor layer 10 and the first ground plate 33 of the

second conductor layer

30, 22 may electrically connect the second ground line 14 of the first conductor layer 10 and the second ground plate 34 of the second conductor layer 30.

The second signal may be transmitted from the first electronic component 41 to the second electronic component 42 via the top signal line 15. [

For example, as shown in FIG. 4, the second signal current SC2 by the second signal can flow from the first electronic element 41 to the second electronic element 42 through the top surface signal line 15 have.

However, since the first ground plate 33 and the second ground plate 34 are separated by the lower signal line 32, a return current due to the second signal current SC2 in the second conductor layer 30 flows The return path can be disconnected.

Thus, the second return current due to the second signal current SC2 can flow from the second electronic component 42 to the first electronic component 41 via the bypass path. For example, the second return current may flow through a power supply path that provides power to the first and second

electronic devices

41, 42, or bypasses the bottom signal line 32, Lt; RTI ID = 0.0 > 33, < / RTI >

The length of the return path of the second return current is increased due to the second return current being transmitted by bypassing the signal line 32 and the length of the return path is increased, Electromagnetic interference (EMI) can be increased.

In addition, electromagnetic interference (EMI) is highly regulated internationally because it has a great influence on human bodies and other electronic devices. Regulations for Electromagnetic Interference (EMI) vary from country to country.

5 shows an example of an electromagnetic interference (EMI) intensity and electromagnetic interference (EMI) by the printed circuit board assembly 2 with the return path of the second conductor layer 30 disconnected.

Under international standards, electromagnetic interference (EMI) is limited to 40 dB below 230 MHz, and electromagnetic interference (EMI) at 230 MHz and above can be limited to 47 dB.

The intensity of electromagnetic interference (EMI) by the printed circuit board assembly 2 may vary depending on the operating frequency of the circuitry mounted on the printed circuit board assembly 2. [ For example, if the circuitry mounted on the printed circuit board assembly 2 operates at 100 megahertz, as shown in FIG. 5, the intensity of electromagnetic interference (EMI) is approximately 22 dB (decibel) When operating, the intensity of electromagnetic interference (EMI) may be approximately 30 dB.

In particular, if the circuit is operating at approximately 150 MHz, the intensity of electromagnetic interference (EMI) by the printed circuit board assembly 2 may exceed 40 dB, the international standard (ST). If the circuit operates at approximately 360 MHz or 370 MHz, the intensity of electromagnetic interference (EMI) may exceed 47 dB, the International Standard (ST). Also, if the circuit is operating at approximately 550 MHz or 600 MHz, the intensity of the electromagnetic interference (EMI) may exceed 47 dB, the international standard (ST).

As such, when the circuit operates at a high frequency, the electromagnetic interference (EMI) of the printed circuit board assembly 2 may exceed the international standard (ST). In other words, when the circuit operates at high speed, the electromagnetic interference (EMI) of the printed circuit board assembly 2 may exceed the international standard (ST).

Therefore, it is required to secure a return path from the second electronic element 42 to the first electronic element 41 in order to comply with the international standard (ST) concerning electromagnetic interference (EMI) The addition of an additional conductor layer to the substrate assembly 2 may be required. However, the addition of the conductor layer may cause the price of the printed circuit board assembly 2 to rise.

6 illustrates another example of a printed circuit board assembly according to one embodiment. FIG. 7 shows an example of a main printed circuit board included in the printed circuit board assembly shown in FIG. Fig. 8 shows an example of a sub printed circuit board included in the printed circuit board assembly shown in Fig. Fig. 9 shows a cross section taken along line C-C 'shown in Fig. FIG. 10 shows the intensity of electromagnetic waves generated by the printed circuit board assembly shown in FIG.

Referring to FIGS. 6, 7, 8, 9 and 10, the printed circuit board assembly 3 includes a main printed circuit board 100 on which electronic components are mounted, a return path on the main printed circuit board 100, And a sub-printed circuit board 200 that compensates for the disconnection of the printed circuit board 200.

The main printed circuit board 100 may include at least two main conductor layers 110 and 130 and at least one main dielectric layer 120.

7, the main printed circuit board 100 includes a first main conductor layer 110 and a second main conductor layer 130, a first main conductor layer 110, And a main dielectric layer 120 provided between the conductor layers 130. FIG. 7 shows a double-sided printed circuit board including the first and second main conductor layers 110 and 130 and the main dielectric layer 120, but is not limited thereto. For example, the main printed circuit board 100 may be a printed circuit board having four or more layers.

The first main conductor layer 110 includes a first main power line 111, a second main power line 112, a first main ground line 113, a second main ground line 114, Line 116, a second top surface main signal line 117 and a third main ground line 118. The first main conductor layer 110 may include a first electronic element 141, The printed circuit board 142 and the sub printed circuit board 200 may be mounted. Here, the first and second

electronic elements

141 and 142, the first and second

main power lines

111 and 112, and the first and second

main ground lines

113 and 114, respectively, The first and second

main power lines

111 and 112 and the first and second

main ground lines

113 and 114 may be identical to the first and second

electronic devices

141 and 142,

The second main conductor layer 130 may include a lower main signal line 132, a first main ground plate 133, and a second main ground plate 134. The main signal line 132 and the first and second

main ground plates

133 and 134 are identical to the bottom signal line 32 and the first and

second ground plates

33 and 34 shown in FIG. .

The third main conductor line 118 of the first main conductor layer 110 may be provided at a position corresponding to the position of the lower main signal line 132 of the second main conductor layer 130.

For example, at least a portion of the third main ground line 118 may overlap with the underside main signal line 132. In other words, when the lower main signal line 132 is projected onto the first main conductor layer 110, the lower main signal line 132 projected to the first main conductor layer 110 passes through the third main ground line 118, At least a portion of < / RTI >

As another example, the third main ground line 118 may overlap at least a portion of the underside main signal line 132. In other words, when the third main ground line 118 is projected onto the second main conductor layer 130, the third main ground line 118 projected on the second main conductor layer 130 passes through the lower main signal line 132 ). &Lt; / RTI >

As another example, at least a portion of the third main ground line 118 may overlap at least a portion of the underside main signal line 132.

The main dielectric layer 120 may be made of a dielectric material that is not electrically conductive and may insulate the first main conductor layer 110 and the second main conductor layer 130.

A first main via hole 121 and a second main via hole 122 may be formed in the main dielectric layer 120 to pass through the main dielectric layer 120.

The first and second main via

holes

121 and 122 are filled with a conductive material or coated with a conductive material on the inner surface of the first and second main via

holes

121 and 122, thereby allowing electricity to pass therethrough. The first main via hole 121 is electrically connected to the first main ground line 113 of the first main conductor layer 110 and the first main ground plate 133 of the second main conductor layer 130 And the second main via hole 122 electrically connects the second main ground line 114 of the first main conductor layer 110 and the second main ground plate 134 of the second main conductor layer 130 .

A third main via hole 123 and a fourth main via hole 124 may be further formed in the main dielectric layer 120 to pass through the main dielectric layer 120.

The third and fourth main via

holes

123 and 124 are filled with a conductive material or have a conductive material coated on the inner surface thereof.

Accordingly, the third and fourth main via

holes

123 and 124 are electrically connected to the third main ground line 118 of the first main conductor layer 110 and the first and second main conductor layers 130 and 130 of the second main conductor layer 130, The

ground plates

133 and 134 can be electrically connected to each other.

Specifically, the third main via hole 123 is electrically connected to the third main ground line 118 and the first main ground plate 133. One end of the third main via hole 123 is connected to the third main ground line 118 and the other end of the third main via hole 123 is connected to the first main ground plate 133.

The fourth main via hole 124 is electrically connected to the third main ground line 118 and the second main ground plate 134. One end of the fourth main via hole 124 is connected to the third main ground line 118 and the other end of the fourth main via hole 124 is connected to the second main ground plate 134.

The first, second and third main ground lines 118 and the first and second

main ground plates

133, 124 are connected to the first, second, third and fourth main via

holes

121, 122, , 134 may provide the same ground.

The first top surface main signal line 116 and the second top surface main signal line 117 may be provided between the first electronic element 141 and the second electronic element 142. [ The first upper surface main signal line 116 may be electrically connected to the first electronic device 141 and the second upper surface main signal line 117 may be electrically connected to the second electronic device 142. [

The first top surface main signal line 116 and the second top surface main signal line 117 may be physically separated as shown in FIG. 7, and the first top surface main signal line 116 and the second top surface main signal line 117 may be physically separated from each other, A third main ground line 118 may be provided between the signal lines 117. Also, the third main ground line 118 may be physically / electrically separated from the first and second top surface

main signal lines

116 and 117. 3, the top signal line 15 shown in FIG. 3 may be divided into a first top surface main signal line 116 and a second top surface main signal line 117 in FIG.

The signal output from the first electronic device 141 is transmitted to the second electronic device 142 through the first top surface main signal line 116, the second top surface main signal line 117 and the sub printed circuit board 200 .

A first main contact pad 116a and a second main contact pad 117a for contacting the sub printed circuit board 200 are provided at the ends of the first upper surface main signal line 116 and the second upper surface main signal line 117, May be provided. More specifically, one end of the first top surface main signal line 116 is connected to the first electronic element 141 and a first main contact pad 116a is provided at the other end of the first top surface main signal line 116 have. One end of the second top surface main signal line 117 is connected to the second electronic element 142 and a second main contact pad 116a is provided at the other end of the second top surface main signal line 117 .

Further, other top surface main signal lines may be further provided between the first electronic device 141 and the second electronic device 142, and other top surface main signal lines may also be provided between the first electronic device 141 and the second electronic device 142, And may be electrically connected to the device 142, respectively.

The first and second

main contact pads

116a and 117a may be soldering pads for electrically connecting the sub printed circuit board 200 and the first and second top surface

main signal lines

116 and 117, respectively. The sub printed circuit board 200 can be directly mounted on the main printed circuit board 100 by surface mounting technology. In other words, the sub printed circuit board 200 can be soldered directly onto the main printed circuit board 100.

Specifically, the first and second

main contact pads

116a and 117a are each coated with a solder paste mixed with flux and solder powder, and the sub printed circuit board 200 includes first and second

main contact pads

116a and 117a ). &Lt; / RTI > Subsequently, the sub printed circuit board 200 can be soldered to the first and second

main contact pads

116a and 117a by heating, and the sub printed circuit board 200 can be soldered to the first and second top surface

main signal lines

116, and 117, respectively.

The sub printed circuit board 200 may include at least two sub conductor layers 210 and 230 and at least one sub dielectric layer 220.

8A and 8B, the sub printed circuit board 200 includes a first sub conductor layer 210 and a second sub conductor layer 230 provided in parallel with each other, And a sub-dielectric layer 220 provided between the first sub-conductor layer 210 and the second sub-conductor layer 230. 8A and 8B illustrate a double-sided printed circuit board including the first and second sub conductor layers 230 and the sub dielectric layer 220, but the present invention is not limited thereto. For example, the sub printed circuit board 200 may be a printed circuit board having four or more layers.

The first sub conductor layer 210 may include a top sub signal line 211 formed of a conductive material capable of passing electricity therethrough. In addition, the first sub conductor layer 210 may further include other upper sub signal lines 211a and 211b.

A first sub via hole 221 and a second sub via hole 222 may be formed at both ends of the first sub conductor layer 210 to penetrate the sub dielectric layer 220.

The sub-dielectric layer 220 is provided between the first sub-conductor layer 210 and the second sub-conductor layer 230 and can isolate the first sub-conductor layer 210 and the second sub- conductor layer 230 from each other. have. As described above, the first sub-via hole 221 and the second sub-via hole 222 may be provided through the sub-dielectric layer 220.

The first and second

sub-via holes

221 and 222 are filled with a conductive material or coated with a conductive material on the inner surface of the first and second

sub-via holes

221 and 222.

The second sub-conductor layer 230 may include a first sub-sub signal line 231, a second sub-sub signal line 232, and a sub-ground plate 233 formed of a conductive material capable of passing electricity therethrough . The first lower sub signal line 231 and the second lower sub signal line 232 are provided separately from each other and between the first lower sub signal line 231 and the second lower sub signal line 232, (233) may be provided.

One end of the first lower sub signal line 231 is connected to the first sub via hole 221 and the first sub contact pad 231a is provided at the other end of the first lower sub signal line 231. One end of the second lower sub signal line 232 is connected to the second sub via hole 222 and the second sub contact pad 232a is provided at the other end of the second lower sub signal line 232 have.

The upper sub signal line 211 is connected to the first and second sub via

holes

221 and 222 and the first and second lower

sub signal lines

231 and 232 are connected to the first and second sub via

holes

221 and 221, The upper sub signal line 211 may be electrically connected to the first and second lower

sub signal lines

231 and 232. In other words, the upper sub signal line 211 and the first and second lower

sub signal lines

231 and 232 can form a signal path through which electric power can pass integrally.

The first sub contact pad 231a at the other end of the first lower sub signal line 231 and the second sub contact pad 232a at the other end of the second lower sub signal line 232 are connected to the sub printed circuit board 200, As shown in FIG. Specifically, the first sub contact pad 231a is located at an edge portion of one side of the sub printed circuit board 200, and the second sub contact pad 232a is located at the opposite side edge portion of the first sub contact pad 231a .

In particular, the first sub contact pad 231a and the second sub contact pad 232a are formed on the main printed circuit board 100 when the sub printed circuit board 200 is mounted on the main printed circuit board 100, May be provided at positions corresponding to the first main contact pad 116a and the second main contact pad 117a. Accordingly, when the sub printed circuit board 200 is mounted on the main printed circuit board 100, the first sub contact pad 231a and the second sub contact pad 232a are electrically connected to the first main contact pad 116a and the second

main contact pad

116a, 2 main contact pad 117a.

When the sub printed circuit board 200 is mounted on the main printed circuit board 100, the first sub contact pad 231a and the second sub contact pad 232a are electrically connected to the first

main contact pad

116a, 2 main contact pad 117a. Specifically, the first sub contact pad 231a is electrically connected to the first main contact pad 116a of the main printed circuit board 100, and the second sub contact pad 232a is electrically connected to the main printed circuit board 100, And may be electrically connected to the second main contact pad 117a.

Therefore, when the sub printed circuit board 200 is mounted on the main printed circuit board 100, the first and second top surface

main signal lines

116 and 117 of the main printed circuit board 100 and the sub- The upper sub signal line 211 and the first and second lower

sub signal lines

231 and 232 of the first and second

sub signal lines

200 and 200 may form a signal path through which electric power can pass integrally.

The subground plate 233 is physically / electrically separated from the first and second lower

sub signal lines

231 and 232 between the first lower sub signal line 231 and the second lower sub signal line 232 .

The subground plate 233 of the second sub conductor layer 230 may be provided at a position corresponding to the position of the upper sub signal line 211 of the first sub conductor layer 210. [ For example, at least a portion of the subground plate 233 may overlap with the top surface sub signal line 211. As another example, the subground plate 233 may overlap at least a portion of the top surface sub signal line 211. As another example, at least a portion of the subground plate 233 may overlap at least a portion of the top surface sub signal line 211.

The sub ground plate 233 is provided at a position corresponding to the third main ground line 118 of the main printed circuit board 100 when the sub printed circuit board 200 is mounted on the main printed circuit board 100 . Thus, when the sub printed circuit board 200 is mounted on the main printed circuit board 100, the sub ground plate 233 can be in contact with the third main ground line 118.

When the sub printed circuit board 200 is mounted on the main printed circuit board 100, the sub ground plate 233 may be electrically connected to the third main ground line 118.

Accordingly, when the sub printed circuit board 200 is mounted on the main printed circuit board 100, the first, second, and third

main ground lines

116, 117, and 118 of the main printed circuit board 100, And the second

main ground plates

133 and 134 and the sub ground plate 233 of the sub printed circuit board 200 can provide the same ground.

The sub printed circuit board 200 can be directly mounted on the main printed circuit board 100 by surface mounting technology.

The first main contact pad 116a, the second main contact pad 117a and the third main ground line 118 of the main printed circuit board 100 are electrically connected to the first sub contact pad The sub printed circuit board 200 may be mounted on the main printed circuit board 100 so as to be in contact with the first sub contact plate 231a, the second sub contact pad 232a and the sub ground plate 233.

As a result, the first main contact pad 116a is electrically connected to the first sub contact pad 231a, the second main contact pad 117a is electrically connected to the second

sub contact pad

232a, 3 main ground line 118 may be electrically connected to the sub ground plate 233. The first and second top surface

main signal lines

116 and 117 of the main printed circuit board 100 and the top surface sub signal line 211 of the sub printed circuit board 200, The

lines

231 and 232 can form a signal path through which electricity can pass integrally. When the sub printed circuit board 200 is mounted on the main printed circuit board 100, the first, second, and third

main ground lines

116, 117, and 118 of the main printed circuit board 100, And the second

main ground plates

The third signal passes from the first and second top surface

main signal lines

116 and 117 and the sub printed circuit board 200 of the main printed circuit board 100 to the first electronic element 141 through the second electronic element 141 142 < / RTI >

For example, as shown in FIG. 9, the third signal current SC3 from the third signal is supplied from the first electronic device 141 to the first top surface main signal line 116, the first bottom sub signal line 231 Via the first sub-via hole 221, the upper sub signal line 211, the second sub-via hole 222, the second lower sub signal line 232 and the second upper main signal line 117 2 < / RTI >

Also, the third return current RC3 may be generated by the third signal current SC3. A third return current RC3 may be provided from the second electronic component 142 to the first electronic component 141 through the power supply patterns and / or ground patterns.

For example, the third return current RC3 may be applied from the second electronic component 142 to the second main ground line 114, the second main via hole 122, the second main ground plate 134, The third main ground line 118, the sub ground plate 233, the third main via hole 123, the first main ground plate 133, the first main via

hole

121, 1 main ground line 113 to the first electronic device 141.

Even if the main ground plate 133 is divided into the first main ground plate 133 and the second main ground plate 134 as described above, the first printed circuit board 200 and the second printed circuit board 200 can separate the first electronic element 141 and the second electronic element 142 ) May not be disconnected.

10 shows the intensity of electromagnetic interference (EMI) caused by the printed circuit board assembly 3 on which the return path of the main printed circuit board 100 is formed due to the sub printed circuit board 200 and the electromagnetic interference (ST) is shown.

As described above, electromagnetic interference (EMI) is limited to 40 dB below 230 MHz, and electromagnetic interference (EMI) at 230 MHz and above can be limited to 47 dB, according to international standards.

The intensity of electromagnetic interference (EMI) by the printed circuit board assembly 3 may vary depending on the operating frequency of the circuitry mounted on the printed circuit board assembly 3. [ For example, when the circuit mounted on the printed circuit board assembly 3 operates at 100 MHz, as shown in FIG. 10, the intensity of the electromagnetic interference (EMI) by the printed circuit board assembly 3 is approximately 34 dB, The electromagnetic interference (EMI) intensity may be approximately 25 dB to 30 dB when operating at 200 MHz.

10, the intensity of electromagnetic interference (EMI) by the printed circuit board assembly 3 may not exceed the international standard (ST) of 40 dB or 47 dB even if the operating frequency of the circuit changes. In particular, even though the circuit operates at a high speed of 230 MHz or higher, the intensity of electromagnetic interference (EMI) may not exceed 47 dB, the international standard (ST).

In this way, the printed circuit board assembly 3 having the return path of the main printed circuit board 100 secured by the sub printed circuit board 200 can comply with the international standard (ST) without the addition of the additional conductor layer. Thus, the cause of the price increase due to the addition of the additional conductor layer can be eliminated.

As described above, when the upper main signal line and the lower main signal line 132 of the main printed circuit board 100 intersect with each other, the upper main signal line is connected to the first upper surface main signal line 116 and the second upper surface The first top surface main signal line 116 and the second top surface main signal line 117 are connected to each other by the top surface sub signal line 211 of the sub printed circuit board 200, do. The sub ground plate 233 of the sub printed circuit board 200 and the third main ground line 118 of the main printed circuit board 100 may provide a return path of the signal line.

The main printed circuit board 100 and the sub printed circuit board 200 for securing the return path are not limited to those shown in Figs. 6, 7, and 8.

Hereinafter, another example of the main printed circuit board 100 and the sub printed circuit board 200 will be described.

8, the same reference numerals as those in Fig. 8 are used for the same configurations as those shown in Fig.

The first sub printed circuit board 201 may include at least two sub conductor layers 210 and 230 and at least one sub dielectric layer 220.

11 (a) and 11 (b), the first sub-conductor layer 210, the second sub-conductor layer 230, and the sub-dielectric layer 220 are formed on the first sub- . 11A and 11B illustrate a double-sided printed circuit board, but the present invention is not limited thereto. For example, the first sub-printed circuit board 201 may be a printed circuit board having four or more layers.

The first sub conductor layer 210 may include upper sub signal lines 211 and other sub signal lines 211a and 211b. The sub-dielectric layer 220 may include a first sub-via hole 221 and a second sub-via hole 222 connected to both ends of the first sub-conductor layer 210. The second sub conductor layer 230 includes a first lower sub signal line 231 connected to the first sub via hole 221 and the first sub contact pad 231a and a second lower sub signal line 231 connected to the second sub via hole 222 and the second sub contact hole 231a. And a second lower sub signal line 232 coupled to the sub contact pad 232a. The above configurations may be the same as those included in the sub printed circuit board 200 shown in FIG.

Unlike the sub printed circuit board 200 shown in FIG. 8, the first sub printed circuit board 201 may not include a sub-ground plate.

7 and 9, the return current RC3 from the third signal is applied to the third main ground line 118 of the main printed circuit board 100 and the sub ground plate 233 of the sub printed circuit board 200 Through the second electronic component 142 to the second electronic component 142. [

8 is omitted, the return current RC3 is supplied from the first electronic element 141 to the second electronic element 141 via the third main ground line 118 of the main printed circuit board 100. Therefore, even when the subground plate 233 shown in FIG. To the device 142.

Therefore, even if the sub-ground plate is omitted, the first sub-printed circuit board 201 can provide a return path for the return current RC3.

The first main printed circuit board 101 may include at least two main conductor layers 110 and 130 and at least one main dielectric layer 120.

As shown in FIG. 12, the first main printed circuit board 101 may include a first main conductor layer 110, a second main conductor layer 130, and a main dielectric layer 120. 12 shows a double-sided printed circuit board, but the present invention is not limited thereto. For example, the first main printed circuit board 101 may be a printed circuit board having four or more layers.

The first main conductor layer 110 includes a first main power line 111, a second main power line 112, a first main ground line 113, a second main ground line 114, Line 116 and a second top surface main signal line 117. A first electronic element 141 and a second electronic element 142 are mounted on the first main conductor layer 110. [ The main dielectric layer 120 may include a first main via hole 121, a second main via hole 122, a third main via hole 123 and a fourth main via hole 124. The second main conductor layer 130 may include a bottom main signal line 132, a first main ground plate 133, and a second main ground plate 134. The above configurations may be the same as those included in the main printed circuit board 100 shown in FIG.

Unlike the main printed circuit board 100 shown in FIG. 7, the first main printed circuit board 101 does not include the third main ground line 118, and the fourth main ground line 118a and the fifth main ground line 118a, Line 118b. &Lt; / RTI > 7, the third main ground line 118 shown in FIG. 7 may be divided into a fourth main ground line 118a and a fifth main ground line 118b in FIG.

The fourth main ground line 118a is connected to the first main ground plate 133 through the third main via hole 123 and connected to the second main ground plate 134 through the fourth main via hole 124. [ ). The fifth main ground line 118b is connected to the first main ground plate 133 through the fifth main via hole 125 and connected to the second main ground plate 134 via the sixth main via hole 126. [ ). Therefore, the fourth main ground line 118a, the fifth main ground line 118b, the first main ground plate 133, and the second main ground plate 134 can provide the same ground.

The portion of the third main ground line 118 overlapping with the sub ground plate 233 is omitted and the return current RC3 flows through the sub ground plate 233 of the sub printed circuit board 200 And may flow from the second electronic component 142 to the first electronic component 141. [

Therefore, even if a part of the third main ground line 118 is omitted, the first sub printed circuit board 201 can provide a return path for the return current RC3.

As described above, when the top main signal line and the bottom main signal line of the main printed circuit board intersect with each other, the top main signal line can be separated. Further, the sub printed circuit board may connect the separated top surface main signal lines and provide a return path of the main main signal line.

Such a sub print circuit board can be variously provided according to the design specifications of the main printed circuit board, the characteristics of the circuit mounted on the main printed circuit board, the type of the signal on the main printed circuit board, the type of the crossed line,

A sub-printed circuit board can be libraryed to provide various sub-printed circuit boards. In other words, various sub printed circuit boards fabricated in accordance with a predetermined standard can be provided.

Examples of the sub-printed circuit board in the library are described below.

Figures 13, 14 and 15 illustrate libraries of sub-printed circuit boards according to one embodiment.

13A and 13B show the top and bottom surfaces of the sub-printed circuit board 300 by the first library, respectively.

As shown in Figs. 13A and 13B, a single end signal can be transmitted by the sub-printed circuit board 300 by the first library.

The sub-printed circuit board 300 according to the first library may include a top surface conductor layer 310 and a bottom surface conductor layer 330. In addition, the sub printed circuit board 300 may further include a dielectric layer not shown in the figure.

The upper surface conductor layer 310 may include a first upper surface signal line 311 composed of a conductive material capable of passing electricity and other upper surface signal lines. First and second via

holes

321 and 322 may be formed at both ends of the first upper signal line 311 to pass through the dielectric layer. In addition, a third via hole 323 and a fourth via hole 324 may be formed in the vicinity of the first upper signal line 311, separated from the first upper signal line 311.

The lower conductor layer 330 may include a first lower signal line 331, a second lower signal line 332, a lower ground plate 333 and other lower signal lines constructed of conductive material capable of passing electricity therethrough. have. One end of each of the first and second

lower signal lines

331 and 332 is connected to the first and second via

holes

321 and 322 and the other end of the first and second

lower signal lines

331 and 332 First and

second contact pads

331a and 332a may be formed, respectively. One side of the lower ground plate 333 may be connected to the third and fourth via

holes

323 and 324.

The first lower signal line 331, the first via hole 321, the first upper signal line 311, the second via hole 322 and the second lower signal line 332 integrally form a single-ended signal End signal path from the first contact pad 331a via the single-ended

signal path

331, 321, 311, 322, 332 to the second contact 331a through the

first contact pad

331, 321, 311, 322, 332, Pad 332a. Also, the lower ground plate 333, the third via hole 323, and the fourth via hole 324 can provide grounding.

The width W1 of the

signal lines

311, 331 and 332 can be changed in accordance with the impedance specification of the circuit and the distance D1 between the upper signal line 311 and the upper signal lines can be changed (crosstalk) specification. The distance D2 between the contact pads including the first and

second contact pads

331a and 332a may also be changed according to the crosstalk specification of the signal. The distance D3 between the

lower signal lines

331 and 332 and the lower surface ground plate 333 can be changed according to the insulation specification of the printed circuit board.

14 (a) and 14 (b) show the top and bottom surfaces of the sub-printed circuit board 400 by the second library, respectively.

14 (a) and 14 (b), a differential signal can be transmitted by the sub-printed circuit board 400 by the second library.

The sub-printed circuit board 400 according to the second library may include a top surface conductor layer 410, a bottom conductor layer 430, and a dielectric layer not shown in the figure.

The top surface conductor layer 410 may include a first top surface signal line 411, a second top surface signal line 412, and other top surface signal lines. A first via hole 421 and a second via hole 422 are formed at both ends of the first upper surface signal line 411 and a third via hole 423 and a second via hole 423 are formed at both ends of the second upper surface signal line 412. 4 via-holes 424 may be formed. A fifth via hole 425 and a sixth via hole 426 are formed separately from the first and second

upper signal lines

411 and 412 in the vicinity of the first and second upper

surface signal lines

411 and 412, .

The lower surface signal line 431, the lower surface signal line 432, the third lower surface signal line 433, the fourth lower surface signal line 434, the lower surface ground plate 435, And other down signal lines. Second, third and fourth via

signal lines

431, 432, 433 and 434 are connected to the first, second, third and fourth via

holes

421, 422, 423 and 424, respectively. Third, and

fourth contact pads

431a, 432a, 433a, and 433a are connected to the other ends of the first, second, third, and fourth lower signal lines 431, 432, 433, , And 434a may be formed. One side of the lower surface ground plate 435 may be connected to the fifth and sixth via

holes

425 and 426.

The first and third lower signal lines 431 and 433, the first and third via

holes

421 and 423, the first and second upper

surface signal lines

411 and 412, the second and fourth via holes 422 And 424 and the second and fourth lower signal lines 432 and 434 may form a single differential signal path and the differential signal may be transmitted from the first and

third contact pads

431a and 433a through a differential signal path To the second and fourth contact pads 432a and 434a. In addition, the lower surface ground plate 435 and the fifth and sixth via

holes

425 and 426 can provide grounding.

The width W2 of the

signal lines

411, 412, 431, 432, 433 and 434 can be changed in accordance with the impedance specification of the circuit, and the widths of the first top signal line 411 and the second top surface signal line 412, Can also be changed according to the impedance specification of the circuit. The distance D5 between the first and second top

surface signal lines

411 and 412 and other top surface signal lines may be changed according to the crosstalk specification of the signal. The distance D6 between the contact pads including the first, second, third and

fourth contact pads

431a, 432a, 433a and 434a may also be varied according to the crosstalk specification of the signal. The distance D7 between the

lower signal lines

431, 432, 433 and 434 and the lower surface ground plate 435 can be changed according to the insulation specification of the printed circuit board.

Figs. 15A and 15B show the top and bottom surfaces of the sub-printed circuit board 500 by the third library, respectively.

15 (a) and 15 (b), power can be supplied by the sub-printed circuit board 500 by the third library.

The sub-printed circuit board 500 according to the third library may include a top surface conductor layer 510, a bottom surface conductor layer 530, and a dielectric layer not shown in the figure.

The upper surface conductor layer 510 may include a top surface power plate 511. The first via hole 521 and the second via hole 522 may be formed at both ends of the upper surface power plate 511. [

The lower conductor plate 530 may include a first lower surface power plate 531, a second lower surface power plate 532 and a lower surface ground plate 533. The first and second

lower power plates

531 and 532 may be connected to the first and second

lower holes

521 and 522, respectively.

Power can be transmitted through the first lower power plate 531, the first via hole 521, the upper power plate 511, the second via hole 522 and the second lower power plate 532, The ground plate 533 may provide grounding.

The distance D8 between the lower

surface power plates

531 and 532 and the lower surface ground plate 533 can be changed according to the insulation specification of the printed circuit board.

As described above, the sub printed circuit board can be libraryed, and the user can mount the library sub-printed circuit board on the main printed circuit board if necessary.

Due to the addition of the sub-printed circuit board, a return path can be provided such that a layer is added to the main printed circuit board. In addition, the intensity of electromagnetic interference (EMI) generated from the printed circuit board assembly including the sub printed circuit board can be reduced.

Meanwhile, the disclosed embodiments may be embodied in the form of a recording medium storing instructions executable by a computer. The instructions may be stored in the form of program code and, when executed by a processor, may generate a program module to perform the operations of the disclosed embodiments. The recording medium may be embodied as a computer-readable recording medium.

The computer-readable recording medium includes all kinds of recording media in which instructions that can be decoded by a computer are stored. For example, it may be a ROM (Read Only Memory), a RAM (Random Access Memory), a magnetic tape, a magnetic disk, a flash memory, an optical data storage device, or the like.

The embodiments disclosed with reference to the accompanying drawings have been described above. It will be understood by those skilled in the art that the disclosed embodiments may be practiced in other forms than the disclosed embodiments without departing from the spirit or essential characteristics of the disclosed embodiments. The disclosed embodiments are illustrative and should not be construed as limiting.

Claims

A main printed circuit board,

And a sub printed circuit board mounted on the main printed circuit board,

The main printed circuit board includes:

A first main conductor layer including a first main signal line and a second main signal line;

A second main conductor layer including a third main signal line disposed between the first main signal line and the second main signal line; And

And a main dielectric layer for insulating the first main conductor layer and the second main conductor layer,

The sub-printed circuit board includes:

A first sub conductor layer including a first sub signal line connected to the first main signal line and the second main signal line; And

And a sub-dielectric layer for insulating the first sub-conductor layer and the first main conductor layer.
The method according to claim 1,

The second main conductor layer further includes a main ground plate separated from the third main signal line,

Wherein the first main conductor layer further comprises a main ground line connected to the main ground plate and at least partially overlapping the third main signal line.
3. The method of claim 2,

The first main signal line, the first sub signal line, and the second main signal line form a signal transmission path,

Wherein the main ground plate and the main ground line form a return path for the signal transmission path.
The method according to claim 1,

Wherein the sub printed circuit board further comprises a second sub conductor layer including a sub ground plate connected to the main ground plate,

Wherein the sub-dielectric layer isolates the first sub-conductor layer from the second sub-conductor layer.
5. The method of claim 4,

The first main signal line, the first sub signal line, and the second main signal line form a signal transmission path,

Wherein the main ground plate and the sub ground plate form a return path for the signal transmission path.
The method according to claim 1,

The sub-printed circuit board includes a second sub signal line connected to the first main signal line and the first sub signal line, a third sub signal line connected to the second main signal line and the first sub signal line, And a second sub-conductor layer comprising a line,

Wherein the sub-dielectric layer isolates the first sub-conductor layer from the second sub-conductor layer.
The method according to claim 6,

A first main solder pad is formed at one end of the first main signal line to be in contact with the second sub signal line,

And a second main solder pad is formed at one end of the second main signal line to be in contact with the third sub signal line.
8. The method of claim 7,

A first sub solder pad is formed at one end of the second sub signal line to be in contact with the first main signal line,

And a second sub solder pad is formed at one end of the third sub signal line to be in contact with the second main signal line.
A main printed circuit board,

And a sub printed circuit board mounted on the main printed circuit board,

The main printed circuit board includes:

A first main conductor layer including a first main signal line and a second main signal line separated from each other at a first position;

A second main conductor layer including a first main ground plate and a second main ground plate separated from each other at a second position corresponding to the first position; And

And a main dielectric layer for insulating the first main conductor layer and the main second conductor layer,

The sub-printed circuit board includes:

A first sub conductor layer including a first sub signal line connected to the first main signal line and the second main signal line; And

And a sub-dielectric layer for insulating the first sub-conductor layer and the first main conductor layer.
10. The method of claim 9,

The second main conductor layer further includes a third main signal line provided at the second position,

Wherein the first main conductor layer further comprises a main ground line connected to the first and second main ground plates and at least partially overlapping the third main signal line.
11. The method of claim 10,

The first main signal line, the first sub signal line, and the second main signal line form a signal transmission path,

Wherein the main ground plate and the main ground line form a return path for the signal transmission path.
10. The method of claim 9,

Wherein the sub printed circuit board further comprises a second sub conductor layer including a sub ground plate connected to the main ground plate,

Wherein the sub-dielectric layer isolates the first sub-conductor layer from the second sub-conductor layer.
13. The method of claim 12,

The first main signal line, the first sub signal line, and the second main signal line form a signal transmission path,

Wherein the main ground plate and the sub ground plate form a return path for the signal transmission path.
10. The method of claim 9,

The sub-printed circuit board includes a second sub signal line connected to the first main signal line and the first sub signal line, a third sub signal line connected to the second main signal line and the first sub signal line, And a second sub-conductor layer comprising a line,

Wherein the sub-dielectric layer isolates the first sub-conductor layer from the second sub-conductor layer.
15. The method of claim 14,

A first main solder pad is formed at one end of the first main signal line to be in contact with the second sub signal line,

A second main solder pad is formed at one end of the second main signal line to contact the third sub signal line,

A first sub solder pad is formed at one end of the second sub signal line to be in contact with the first main signal line,

And a second sub solder pad is formed at one end of the third sub signal line to be in contact with the second main signal line.