WO2018223739A1

WO2018223739A1 - Display drive circuit and control method therefor, and display device

Info

Publication number: WO2018223739A1
Application number: PCT/CN2018/078420
Authority: WO
Inventors: 丛乐乐; 孙建; 秦文文; 张寒
Original assignee: 京东方科技集团股份有限公司; 鄂尔多斯市源盛光电有限责任公司
Priority date: 2017-06-05
Filing date: 2018-03-08
Publication date: 2018-12-13
Also published as: US20190228730A1; CN107039015B; CN107039015A; US10692460B2

Abstract

Provided are a display drive circuit (01) and control method therefor, and a display device. The display drive circuit (01) comprises a plurality of function multiplex circuits (10), with each function multiplex circuit (10) being connected to at least one data line (data) by means of a data transmission end (101). The function multiplex circuit (10) is also connected to an enabling signal end (SW), a first signal end (102) and a second signal end (103), and is configured to provide, under the action of the enabling signal end (SW), the first signal end (102) and the second signal end (103), a detection signal to the data line (data), and is further used for releasing static electricity on a data transmission end (101) through the first signal end (102) or second signal end (103).

Description

Display driving circuit and control method thereof, display device

The present application claims priority to Chinese Patent Application No. PCT Application No.

Technical field

The present disclosure relates to the field of display technologies, and in particular, to a display driving circuit, a control method thereof, and a display device.

Background technique

In the production process of the display panel, due to the limitation of space and manufacturing process, for the small-sized display panel, the static elimination unit for the data line cannot be set, which will affect the normal operation of the display panel.

Summary of the invention

According to an aspect of an embodiment of the present disclosure, a display driving circuit includes: a plurality of function multiplexing circuits, each of the plurality of function multiplexing circuits being connected to at least one data line via a data transmission end; The function multiplexing circuit has an enable signal end, a first signal end, and a second signal end, and is configured to be under the control of the signal of the enable signal end, the first signal end, and the second signal end, A detection signal is supplied to the data line, and static electricity on the data transmission end is released via the first signal terminal or the second signal terminal.

For example, the function multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the first multiplexing sub-circuit is connected to the enabling signal end, the first signal end, and the data transmission End, configured to input a signal of the first signal end to the data transmission end and static electricity on the data transmission end under control of a signal of the enable signal end and the first signal end The first signal end is released;

The second multiplex sub-circuit is connected to the second signal end and the data transmission end, and configured to stabilize the voltage of the data transmission end under the control of the signal of the second signal end and the data transmission end The static electricity on the data transmission end is released via the second signal terminal.

For example, the first multiplex sub-circuit includes a first transistor; a gate of the first transistor is connected to the enable signal terminal, a first pole is connected to the data transmission end, and a second pole is connected to the first signal end.

For example, the second multiplex sub-circuit includes a second transistor; a gate and a first pole of the second transistor are connected to the data transmission end, and a second pole is connected to the second signal end.

For example, the display driving circuit further includes a multiplexer; the multiplexer is connected to the gate control terminal, the data line, and the data transmission end of the function multiplexing circuit; the multiplexer And configured to output the signal of the data transmission end to a data line matching the strobe signal under the control of the strobe signal output by the strobe control terminal. The multiplexer includes a plurality of strobe subcircuits, each of the strobe subcircuits being coupled to two adjacent function multiplex circuits; each strobe subcircuit includes L strobes, wherein The odd-numbered gates are connected to the odd-bit function multiplexing circuit and the odd-numbered data lines, and the even-numbered gates are connected to the even-numbered function multiplexing circuit and the even-numbered data lines; where L is a positive integer.

For example, the display driver circuit further includes a source driver coupled to the data transfer terminal of the function multiplexing circuit, the source driver configured to provide a data signal to the data transfer terminal.

In another aspect of an embodiment of the present disclosure, there is provided a display device comprising any of the display driving circuits as described above.

In still another aspect of an embodiment of the present disclosure, there is provided a method for controlling any of the display driving circuits as described above, in a case where the function multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit The method includes: after the signal of the enable signal end and the signal of the first signal end, the first multiplexing sub-circuit inputs a signal of the first signal end to the data transmission end, to a data line connected to the data transmission end provides a detection signal; under the control of the signal of the second signal end and the data transmission end, the second multiplexing sub-circuit stabilizes the voltage of the data transmission end; at the enable signal Controlling, by the terminal and the signal of the first signal end, the first multiplex sub-circuit releases static electricity on the data transmission end via the first signal end; at the second signal end and the data The second multiplex sub-circuit releases the static electricity on the data transmission end via the second signal terminal under the control of the signal at the transmitting end.

For example, the first multiplex sub-circuit includes a first transistor, and the first multiplex sub-circuit releases the static electricity on the data transmission end via the first signal end, including: to the enable signal end and The first signal terminal applies the same voltage signal such that the first transistor is in a diode conducting state.

For example, the two adjacent first multiplex sub-circuits respectively providing the detection signal to the data line include: for the first image frame, the first signal connected to the odd-numbered first multiplex sub-circuit Inputting a high level, inputting a low level to a first signal end connected to the even-numbered first multiplex sub-circuit; and connecting to the first multiplex sub-circuit of the odd-numbered bit for the second image frame The first signal terminal inputs a low level, and inputs a high level to the first signal end connected to the even-numbered first multiplex sub-circuit; wherein the first image frame and the second image frame are Adjacent two image frames.

DRAWINGS

In order to more clearly illustrate the embodiments of the present disclosure or the conventional technical solutions, the drawings to be used in the embodiments or the description of the conventional technology will be briefly described below. It is apparent that the drawings in the following description are only some of the embodiments of the present disclosure, and other drawings may be obtained from those skilled in the art without departing from the drawings.

FIG. 1 is a schematic structural diagram of a display driving circuit according to an embodiment of the present disclosure;

2 is a schematic structural diagram of a function multiplexing circuit in the display driving circuit shown in FIG. 1;

3 is a schematic diagram showing a specific structure of the function multiplexing circuit shown in FIG. 2;

4a-4b are equivalent circuit diagrams of the function multiplexing circuit shown in FIG. 3;

FIG. 5 is a schematic structural diagram of another display driving circuit according to an embodiment of the present disclosure;

6 is a schematic structural view showing a case where a multiplex sub-circuit is a transistor in the display driving circuit shown in FIG. 5;

7 is a control timing chart of the display driving circuit shown in FIG. 6;

FIG. 8 illustrates a schematic diagram of a display device in accordance with an embodiment of the present disclosure;

FIG. 9 illustrates a flow chart of a control method of a display driving circuit according to an embodiment of the present disclosure.

detailed description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. It is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all of them. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the disclosure.

Embodiments of the present disclosure provide a display driving circuit. As shown in FIG. 1, the display driving circuit 01 includes a plurality of (at least two) function multiplexing circuits 10, and the function multiplexing circuit 10 is connected to at least one data line data in the display panel through the data transmission end 101 to detect The signal is input to the data line data. The function multiplexing circuit 10 further has an enable signal terminal SW, a first signal terminal 102 and a second signal terminal 103. Only the connection lines of the two function multiplexing circuits 10 are shown in Fig. 1, and the connection lines for the other function multiplexing circuits 10 can be referred to.

The display driving circuit 01 can multiplex the display performance detection and the static electricity protection function of the display panel. Wherein, in the panel detection phase, the detection signal input to the display panel can be transmitted to the data line data of the display panel through the function multiplexing circuit 10. For example, the function multiplexing circuit 10 supplies a detection signal to the data line data under the control of the signals of the enable signal terminal SW, the first signal terminal 102, and the second signal terminal 103. In addition, in the display phase (because of the need for electrostatic protection at this stage, it may also be referred to as an electrostatic protection phase), the function multiplexing circuit 10 performs static electricity on the data transmission end 101 by the first signal terminal 102 or the second signal terminal 103. freed. The data transmission terminal 101 may be a signal terminal for transmitting a data signal to the data line. The source driver may be connected to the data transmission terminal 101 to input a data signal to the data line data, however, static electricity in the data signal may be released through the function multiplexing circuit 10.

It should be noted that the detection signal is used to drive pixels in the display panel to display before the display panel does not form a driving circuit (source driver, or source driver IC) for transmitting signals to the data lines, thereby The display performance of the pixel is detected. Among them, the detection signal can be provided by an external controller.

Further, the display driving circuit 01 further includes a source driver connected to the data transmission terminal 101. The source driver is used to provide a data signal to the data transmission end 101 during the display phase. Since the data transmission end 101 is connected to the data line data in the display panel, the source driver can transmit the above data signal to the data line data. When the data signal provided by the source driver has a higher static electricity, that is, when the data transmission end 101 has a higher static electricity, the static electricity may be released through the first signal terminal 102 or the second signal terminal 103. The example release process is described during the operation of the subsequent function multiplexing circuit 10.

Based on this, by performing time-division driving on the display driving circuit 01, in the test (Cell Test) stage, under the action of the enabling signal terminal SW, the first signal terminal 102 and the second signal terminal 103, the first signal terminal is The signal of 102 is input to the data transmission terminal 101 to provide a detection signal to the data line connected to the data transmission terminal 101, thereby detecting the display performance of the pixels in the display panel. At the same time, in the electrostatic protection phase, under the control of the enable signal terminal SW, the first signal terminal 102 or the second signal terminal 103, the static electricity of the data transmission end 101 is released through the first signal terminal 102 or the second signal terminal 103. Therefore, after the display driving circuit 01 is designed, the related wiring and layout of the static elimination and the display performance detection can be simultaneously completed, thereby effectively solving the layout design of the small-sized display panel, and the layout can be difficult due to the small space, and the static elimination cannot be designed. The problem with the circuit.

In addition, after the display performance detection of the conventional panel, there is a problem that the detecting unit is idle. For a small-sized display panel, especially a small-sized display panel having a circular shape, a polygonal shape, or other shapes having an arc shape, a large waste of wiring space is caused. In the limited space, the display driving circuit 01 having the function multiplexing circuit 10 is designed to detect the display performance of the display panel during the display performance test phase, and the static electricity on the data transmission end 101 can be performed in the electrostatic protection phase. freed. Thereby, the idleness of the display driving circuit 01 can be avoided.

As shown in FIG. 2, the function multiplexing circuit 10 may include a first multiplex sub-circuit 11 and a second multiplex sub-circuit 12.

The first multiplex sub-circuit 11 is connected to the enable signal terminal SW, the first signal terminal 102, and the data transmission terminal 101. The first multiplex sub-circuit 11 is configured to input the signal of the first signal end 102 to the data transmission end 101 and the static electricity on the data transmission end 101 under the control of the signals of the enable signal terminal SW and the first signal terminal 102. Release is performed via the first signal terminal 101.

The second multiplex sub-circuit 12 is connected to the second signal terminal 103 and the data transmission terminal 101. The second multiplex sub-circuit 12 is configured to stabilize the voltage of the data transmission terminal 101 and release the static electricity on the data transmission terminal 101 via the second signal terminal 103 under the control of the signals of the second signal terminal 103 and the data transmission terminal 101. .

An example structure of the first multiplex sub-circuit 11 and the second multiplex sub-circuit 12 will be described below. As shown in FIG. 3, the first multiplex sub-circuit 11 may include a first transistor T1, the gate of the first transistor T1 is connected to the enable signal terminal SW, the first pole is connected to the data transmission terminal 101, and the second pole is coupled to the first signal. The ends 102 are connected.

The second multiplex sub-circuit 12 may include a second transistor T2 having a gate and a first pole connected to the data transmission terminal 101 and a second pole connected to the second signal terminal 103.

It should be noted that when the transistors are all N-type transistors, the first source is the first source and the second electrode is the drain. A constant high level is applied to the second signal terminal 103. When the above transistors are all P-type transistors, their first extreme drain and the second extreme source. A constant low level is applied to the second signal terminal 103.

In addition, the data transmission end 101 is connected to the data line through the data lead. If a data transmission end 101 is only connected to one data line, for a small-sized high-PPI display panel, the data lead traces in the display panel are dense, so Short-circuit phenomenon is prone to occur. Therefore, as shown in FIG. 5, the display driving circuit 01 may further include a multiplexer 20. The multiplexer 20 is connected to the gate control terminal MUX _n , the data line data, and the data transfer terminal 101 of the function multiplexing circuit 10. The multiplexer 20 is configured to output the signal of the function multiplexing circuit 10 to the data line data corresponding to the strobe signal under the control of the strobe signal of the strobe control terminal MUX _n , thereby reducing data. The setting of the lead wire reduces the probability of the wire being dense and causing a short circuit phenomenon.

As shown in FIG. 5, the multiplexer 20 may include a plurality of strobe sub-circuits 201, each of which is connected to two adjacent functional multiplex circuits 10.

For example, each of the strobe sub-circuits 201 may include L gates 2011, wherein the odd-numbered gates 2011 connect the odd-numbered functional multiplexing circuits 10 and the odd-numbered data lines data, the even-numbered gates 2011 is an even-numbered functional multiplexing circuit 10 and an even-numbered data line data; where L is a positive integer.

It should be noted that FIG. 5 is an illustration of L=6, that is, one gate sub-circuit 201 including six gates 2011 as an example. In this case, one data transmission terminal 101 can provide data signals for six data lines. In the embodiment of the present disclosure, each of the strobe sub-circuits 201 includes six transistors, and the gates of the transistors are respectively connected to the gate control terminals MUX ₁ -MUX ₆ , the first poles are connected to the data lines data, and the second poles are connected. The data transmission terminal 101 of the multiplexing circuit 10. A gate device 2011 includes a transistor, the first transistor is connected to the first functional multiplexing circuit 10 and the first data line, and the second transistor is connected to the second functional multiplexing circuit 10 and the second data line. analogy.

Of course, each of the gates 201 may also include other numbers of strobe subunits 2011, for example, three, that is, L=3. In this case, one data transmission end 101 can provide data signals for three data lines. With respect to the case of L=6, when each of the gate sub-circuits 201 includes three gates 2011, the number of wirings of the data leads is increased.

The operation of the display driving circuit 01 shown in FIG. 6 will be exemplified below in conjunction with the timing control chart shown in FIG.

In the detection phase of the display performance, the enable signal terminal SW is at a high level. At this time, the first transistor T1 is turned on, and the detection signals CTDO and CTDE input by the first signal terminal 102 are input to the multiplexer 20 through the data transmission terminal 101. in.

When the gate control terminal MUX ₁ is at a high level, the first and fourth transistors in the multiplexer 20 are turned on. Since the first transistor is different from the data transmission terminal 101 connected to the fourth transistor, the detection signal in the first functional multiplexing circuit 10 is transmitted to the data line data1 connected to the first transistor, and the second The detection signal in the function multiplexing circuit 10 is transmitted to the data line data4 connected to the fourth transistor. When the gate control terminal MUX ₁ is at a low level, the first and fourth transistors are turned off, and at this time, writing of signals to the data lines data1 and data4 is stopped.

The principle of writing signals to other data lines data is the same as the principle of writing signals in the above data lines data1 and data4, and will not be described herein. In addition, the column inversion driving can be realized by controlling the high and low level transitions of the adjacent detection signals CTDO and CTDE in the adjacent two image frames, thereby reducing the rotation angle of the liquid crystal in the display panel for a long time or the rotation angle is small, resulting in a small rotation angle. The probability of liquid crystal aging. For example, in the first image frame, the detection signal CTDO is at a high level, and the detection signal CTDE is at a low level; in the second image frame, the detection signal CTDO is at a low level, and the detection signal CTDE is at a high level. The first image frame and the second image frame are adjacent two image frames.

Thus, the levels of the data signals written by the adjacent two columns of data lines are opposite. When the screen is displayed, the data signal is continuously inverted between the high and low levels. Even if the gray scale change of the screen is small, the rotation angle of the liquid crystal will constantly change, so that the liquid crystal aging caused by the rotation angle of the liquid crystal is not changed for a long time. The phenomenon is relieved.

Next, in the electrostatic protection phase, a data signal is supplied from the source driver in the display panel and input to the data transmission terminal 101. The enable control terminal SW changes to a low level, the first signal terminal 102 is at a low level, and the second signal terminal 103 is at a high level. At this time, the equivalent circuit diagram of FIG. 3 is as shown in FIGS. 4a and 4b, in which the first transistor T1 and the second transistor T2 operate as a diode D1 and a diode D2, respectively. The anode of diode D1 is connected to a low level; the cathode of diode D2 is connected to a high level.

When the source driver provides a large forward static (eg, +30V) in the data signal of the data line data, the static current flows to the diode D2, and the direction of the static current is directed by the solid arrow in FIG. 4a. Wherein, the anode of the diode D2 is connected to +30V, and the cathode is connected to +5V, so the diode D2 is in an on state, at which time a large forward static electricity is conducted to the diode D2, and is released through the second signal terminal 103.

When the source driver provides a large negative electrostatic charge (for example, -30V) in the data signal of the data line data, the static electricity flows to the diode D1, and the direction of the electrostatic current is directed by the arrow in FIG. 4b. Wherein, the anode of the diode D1 is connected to -5V, and the cathode of the diode is connected to -30V, so the diode D1 is in a reverse breakdown state. At this time, the diode D1 is turned off, a large forward static electricity is conducted to the diode D2, and passes through the first signal end 102. Release.

As shown in FIG. 8, an embodiment of the present disclosure provides a display device including a display driving circuit according to an embodiment of the present disclosure.

The display device according to an embodiment of the present disclosure may further include a gate drive circuit (GOA), a circuit detection terminal (ET), a fast discharge circuit (Rapid), a ground terminal (GND), and the like located in the non-display area. Wherein, in the detection phase, the signals of the detection signals CTDO, CTDE and the enable signal terminal SW can be input through the circuit detection terminal ET.

The embodiment of the present disclosure provides a method for driving the display driving circuit 01 according to an embodiment of the present disclosure, wherein the function multiplexing circuit 10 includes a first multiplexing sub-circuit 11 and a second multiplexing sub-circuit 12. The following is an example in which the transistors are all N-type transistors, with a high level of +5V and a low level of -5V. As shown in FIG. 9, the method can include the following steps.

In step S91, under the control of the enable signal terminal SW and the first signal terminal 102, the first multiplexing sub-circuit 11 inputs the signal of the first signal terminal 102 to the data transmission terminal 101 to be associated with the data transmission terminal 101. The connected data line provides a detection signal. This phase can be referred to as the "detection phase."

Further, under the control of the second signal terminal 103 and the data transmission terminal 101, the second multiplex sub-circuit 12 stabilizes the voltage of the data transmission terminal 101.

For example, in the detection phase, the enable control terminal SW is always kept at a high level, so that the first transistor T1 is turned on. The second signal terminal 103 outputs a high level. The detection signal is input to the first signal terminal 102. Since the first transistor T1 is turned on, the detection signal can be transmitted to the data line data of the display panel through the data transmission terminal 101.

When the first signal terminal 102 is set to the same high level as the second signal terminal 103, the data transmission terminal 101 is at a high level at this time. In this case, since the potential of the gate of the second transistor T2 is the same as the potential of the second electrode, the gate-source voltage Vgs of the second transistor T2 is 0, and the second transistor T2 is turned off.

In this case, if the signal input from the first signal terminal 102 has a higher static electricity, the signal output through the data transmission terminal 101 also has a higher static electricity, and at this time, the gate potential of the second transistor T2 rises. When the gate-source voltage Vgs of the second transistor T2 is greater than its threshold voltage Vth, the second transistor T2 is turned on. At this time, the static electricity is conducted to the second signal terminal 103 through the second transistor T2, thereby causing the data transmission terminal 101 to maintain the above-described high level. Therefore, the second transistor T2 can stabilize the voltage of the data transfer terminal 101.

When the first signal terminal 102 is at a low level, the data transmission terminal 101 is at a low level, and at this time, the second transistor T2 is turned off.

In step S82, under the control of the enable signal terminal SW and the first signal terminal 102, the first multiplex sub-circuit 11 releases the static electricity on the data transmission terminal 101 through the first signal terminal 102. Under the control of the second signal terminal 103 and the data transmission terminal 101, the second multiplex sub-circuit 12 releases the static electricity on the data transmission terminal 101 through the second signal terminal 103. Therefore, this stage can be referred to as an "electrostatic protection stage."

For example, in the electrostatic protection phase, the data signal supplied from the source driver is transmitted to the data line data of the display panel through the data transmission terminal 101. The control terminal SW is enabled, the first signal terminal 102 is at a low level, and the third signal terminal 103 is at a high level. At this time, the equivalent circuit diagram of FIG. 3 is as shown in FIGS. 4a and 4b, in which the first transistor T1 and the second transistor T2 operate as a diode D1 and a diode D2, respectively. The anode of diode D1 is connected to a low level; the cathode of diode D2 is connected to a high level.

When the source driver provides a large negative electrostatic charge (for example, -30V) in the data signal of the data line data, the static electricity flows to the diode D1, and the direction of the electrostatic current is directed by the arrow in FIG. 4b. Wherein, the anode of the diode D1 is connected to -5V, and the cathode of the diode is connected to -30V, so the diode D1 is in a reverse breakdown state. At this time, the diode D1 is turned off, and the static electricity is conducted to the diode D2 and is released through the first signal terminal 102.

Based on this, by performing time-division driving on the display driving circuit 01, in the cell test phase, under the control of the enable signal terminal SW, the first signal terminal 102 and the second signal terminal 103, the first signal terminal is used. The signal of 102 is input to the data transmission terminal 101 to provide a detection signal to the data line connected to the data transmission terminal 101, thereby detecting the display performance of the pixels in the display panel. In the static protection phase, the static electricity of the data transmission end 101 is released through the first signal terminal 102 or the second signal terminal 103 under the control of the enable signal terminal SW, the first signal terminal 102 or the second signal terminal 103. In this way, after the display driving circuit 01 is designed, the relevant wiring and layout of the unit for static elimination and the unit for detecting display performance can be simultaneously completed, thereby effectively solving the small size display panel due to small space, place and route. Difficult to design a static elimination circuit.

In addition, in the above step S92, the first multiplex sub-circuit 11 includes the first transistor T1, and the first multiplex sub-circuit 11 releases the static electricity on the data transmission end 101 via the first signal terminal 102.

A signal of the same voltage is input to the enable signal terminal SW and the first signal terminal 102 such that the first transistor T1 is in a diode off state.

When the first transistor T1 is an N-type transistor, a low level is input to the enable signal terminal SW and the first signal terminal 102 such that the first transistor T1 is in a diode-off state. When the signal of the data transmission terminal 101 has a large negative static electricity, the first transistor T1 is reversely reversed, so that the larger negative static electricity is released through the first signal terminal 102.

In order to avoid the problem that the liquid crystal ages due to the long-term rotation angle of the liquid crystal in the display panel or the rotation angle is small, the display driving circuit generally adopts a column inversion driving method. For example, in the foregoing step S91, the providing, by the first multiplex sub-circuit 11 to the data line connected to the data transmission end 101, the detection signal may include:

For the first image frame, a high level is input to the first signal terminal 102 connected to the odd-numbered first multiplex sub-circuit 11; and input to the first signal terminal 102 connected to the even-numbered first multiplex sub-circuit 11 Low level.

For the second image frame, a low level is input to the first signal terminal 102 connected to the odd-numbered first multiplex sub-circuit 11; and input to the first signal terminal 102 connected to the even-numbered first multiplex sub-circuit 11 High level. The first image frame and the second image frame are adjacent two image frames.

The data signals of the adjacent two columns of data lines have opposite levels. When the screen display of two adjacent image frames is performed, the data signal is continuously inverted between the high and low levels, and even if the gray scale change of the screen is small, the rotation angle of the liquid crystal is constantly changed, so that the rotation angle of the liquid crystal is long. The phenomenon of liquid crystal aging caused by constant changes is alleviated.

The above is only the specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the disclosure. It should be covered within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be determined by the scope of the claims.

Claims

A display driving circuit includes a plurality of function multiplexing circuits, each of the plurality of function multiplexing circuits including:

a data transmission end connected to at least one data line in the display panel;

The signal end, the first signal end and the second signal end are enabled;

The function multiplexing circuit is configured to provide a detection signal to the data line and static electricity on the data transmission end under the control of signals of the enable signal end, the first signal end, and the second signal end Release by the first signal terminal or the second signal terminal.
The display driving circuit according to claim 1, wherein said function multiplexing circuit comprises a first multiplexing sub-circuit and a second multiplexing sub-circuit;

The first multiplex sub-circuit is connected to the enable signal end, the first signal end, and the data transmission end, and is configured to be under the control of the signal of the enable signal end and the first signal end, Inputting a signal of the first signal end to the data transmission end and discharging static electricity on the data transmission end through the first signal end;

The second multiplex sub-circuit is connected to the second signal end and the data transmission end, and configured to stabilize the voltage of the data transmission end and the device under the control of the second signal end and the data transmission end The static electricity on the data transmission end is released through the second signal terminal.
The display driving circuit according to claim 2, wherein said first multiplex sub-circuit comprises a first transistor;

The gate of the first transistor is connected to the enable signal end, the first pole is connected to the data transmission end, and the second pole is connected to the first signal end.
The display driving circuit according to claim 2 or 3, wherein said second multiplex sub-circuit comprises a second transistor;

The gate of the second transistor and the first pole are connected to the data transmission end, and the second pole is connected to the second signal end.
The display driving circuit according to claim 1, wherein said display driving circuit further comprises a multiplexer;

The multiplexer is connected to the gate control terminal, the data line, and the data transmission end of the function multiplexing circuit, and configured to control the data under the control of the strobe signal of the strobe control terminal The signal of the transmitting end is output to a data line matching the strobe signal;

The multiplexer includes a plurality of strobe subcircuits, each of the strobe subcircuits being coupled to two adjacent function multiplex circuits;

Each of the strobe sub-circuits includes L gates, wherein the odd-numbered gates are connected to the odd-bit function multiplexing circuit and the odd-numbered data lines, and the even-numbered gates are connected to the even-numbered function multiplexing circuit and the even-numbered data lines Where L is a positive integer.
The display driving circuit according to claim 1, further comprising a source driver connected to a data transmission end of said function multiplexing circuit, said source driver for supplying a data signal to said data transmission terminal.
A display device comprising the display driving circuit according to any one of claims 1-6.
A method for controlling a display driving circuit according to any one of claims 1 to 6, the function multiplexing circuit comprising a first multiplexing sub-circuit and a second multiplexing sub-circuit, the method comprising:

Controlling, by the signal of the enable signal end and the signal of the first signal end, the first multiplexing sub-circuit inputting a signal of the first signal end to the data transmission end to be connected to the data transmission end The data line provides a detection signal; the second multiplexing sub-module stabilizes the voltage of the data transmission end under the control of the second signal end and the data transmission end;

The first multiplex sub-circuit releases the static electricity on the data transmission end via the first signal end under the control of the enable signal end and the first signal end; in the second signal The second multiplex sub-circuit releases the static electricity on the data transmission end via the second signal end under the control of the terminal and the data transmission end.
The method of claim 8, wherein the first multiplex sub-circuit comprises a first transistor, the first multiplex sub-circuit releasing static electricity on the data transmission terminal via the first signal terminal include:

And inputting a signal of the same voltage to the enable signal terminal and the first signal terminal, so that the first transistor is in a diode off state.
The method according to claim 8, wherein the providing of the detection signal by the first multiplex sub-circuit to the data line connected to the data transmission end comprises:

And inputting a high level to the first signal end connected to the first multiplex sub-circuit of the odd-numbered bit for the first image frame; and inputting to the first signal end connected to the first multiplex sub-circuit of the even-numbered bit Low level

And inputting a low level to the first signal end connected to the first multiplex sub-circuit of the odd-numbered bit for the second image frame; and inputting to the first signal end connected to the first multiplex sub-circuit of the even-numbered bit High level

The first image frame and the second image frame are two adjacent image frames.