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WO2018209519A1 - Goa电路、阵列基板和显示装置 - Google Patents

Goa电路、阵列基板和显示装置 Download PDF

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Publication number
WO2018209519A1
WO2018209519A1 PCT/CN2017/084397 CN2017084397W WO2018209519A1 WO 2018209519 A1 WO2018209519 A1 WO 2018209519A1 CN 2017084397 W CN2017084397 W CN 2017084397W WO 2018209519 A1 WO2018209519 A1 WO 2018209519A1
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WO
WIPO (PCT)
Prior art keywords
transistor
node
goa
signal
unit
Prior art date
Application number
PCT/CN2017/084397
Other languages
English (en)
French (fr)
Inventor
管曦萌
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to US16/334,475 priority Critical patent/US20210280108A1/en
Priority to PCT/CN2017/084397 priority patent/WO2018209519A1/zh
Priority to CN201780050125.7A priority patent/CN109564746B/zh
Priority to EP17910449.2A priority patent/EP3627489A4/en
Publication of WO2018209519A1 publication Critical patent/WO2018209519A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit, an array substrate, and a display device.
  • GOA Gate driver on array
  • the parasitic coupling capacitance from the input to the output of the GOA unit increases, so that even when the output transistor is turned off, the pulse signal of the output clock is fed forward to the output through the capacitor. causes the voltage at the output to generate unnecessary small floating. After a small floating through the cascaded GOA unit, it will become a larger float. After a certain number of stages, the output transistor of a certain level of GOA unit is outputting all the pulses of the clock signal. When the trigger edge arrives, it is turned on, causing false triggering, resulting in redundant or erroneous pulse output.
  • the present invention aims to at least solve one of the technical problems existing in the related art. To this end, embodiments of the present invention are required to provide a GOA circuit, an array substrate, and a display device.
  • a GOA circuit of an embodiment of the present invention is configured to provide a scan pulse signal for a pixel matrix, the GOA circuit comprising a plurality of cascaded GOA units, each of the GOA units having a shutdown mechanism, the shutdown mechanism including an active state and a non- In an active state, each of the GOA units includes an enable input, a clock signal end, and an output, the enable input is configured to receive an enable input signal, and the clock signal end is configured to receive a clock signal when When the shutdown mechanism is in an inactive state, the output terminal outputs the scan pulse signal according to the enable input signal and the clock signal, and when the shutdown mechanism is in an active state, the output terminal cuts off the scan. Pulse signal.
  • the shutdown mechanism is in an inactive state during a period in which a scan pulse signal needs to be generated, and may be in an active state at other times. In this way, the conduction and amplification mechanisms that generate false triggers are cut off, and the false triggering of the GOA circuit can be effectively suppressed.
  • each of the GOA units includes an adjustment unit, a switching device, a first capacitor, and a a node
  • the adjusting unit is connected to the enabling input and the first node
  • the switching device is connected to the first node, the clock signal end and the output end, the first capacitor connection
  • the first node and the output end when the shutdown mechanism is in an inactive state, the adjusting unit is configured to adjust a voltage of the first node to a first set voltage, and the switching device is turned on;
  • the first capacitor is configured to further adjust a voltage of the first node from the first set voltage to a second set voltage, the switching device is turned on, and the output terminal outputs the scan pulse signal, wherein The absolute value of the second set voltage is greater than the absolute value of the first set voltage.
  • the adjustment unit includes a first transistor having a gate and a source coupled to the enable input, and a drain of the first transistor coupled to the first node.
  • each of the GOA units includes a high level end, a reset end, a reset unit, a holding unit, a low level end, and a second node
  • the reset unit is connected to the high level end, the reset end And the second node
  • the holding unit is connected to the first node, the second node, the output end, and the low level end
  • the reset unit is used by the reset unit And adjusting the voltage of the second node to the first set voltage
  • the holding unit is configured to clamp the voltage of the first node and the voltage of the output terminal to a third set voltage
  • the switch The device is turned off, and the output terminal turns off the scan pulse signal, wherein an absolute value of the third set voltage is less than an absolute value of the first set voltage.
  • the switching device includes a third transistor, a gate of the third transistor is coupled to the first node, a source of the third transistor is coupled to the clock signal terminal, and the third A drain of the transistor is coupled to the output.
  • the reset unit includes a sixth transistor, a gate of the sixth transistor is connected to the reset terminal, a source of the sixth transistor is connected to the high level end, and the sixth transistor The drain is connected to the second node.
  • the holding unit includes a second transistor and a fifth transistor, a gate of the second transistor is connected to the second node, and a source of the second transistor is connected to the output end.
  • a drain of the second transistor is connected to the low-level end, a gate of the fifth transistor is connected to the second node, a source of the fifth transistor is connected to the first node, and the fifth transistor is A drain is connected to the low level terminal.
  • each of the GOA units includes a second capacitor, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is connected to the low-level end, where A second capacitor is used to maintain the voltage of the second node at the first set voltage.
  • each of the GOA units includes a slack unit and a slack signal terminal, the slack unit connecting the enable input or the first node, the slack signal end, the second node And the low level end, the slack unit is configured to adjust a voltage of the second node to the third set voltage.
  • the relaxation unit includes a fourth transistor and a seventh transistor, a gate of the fourth transistor is coupled to the enable input or the first node, a source of the fourth transistor Connecting the second node, a drain of the fourth transistor is connected to the low level end, a gate of the seventh transistor is connected to the slack signal end, and a source of the seventh transistor is connected to the second end a node, a drain of the seventh transistor is connected to the low level terminal.
  • the reset terminal is configured to receive a reset signal
  • the slack signal terminal is configured to receive a slack signal, the enable input signal, the clock signal, the reset signal, and the slack signal
  • the duty cycle is less than or equal to 25%.
  • the enable input signal of the GOA unit of the stage coincides with the scan pulse signal of the GOA unit of the previous stage.
  • the shutdown mechanism is in an inactive state during a period in which a scan pulse signal needs to be generated, and is in an active state at other times. In this way, the conduction and amplification mechanisms that generate false triggers are cut off, and the false triggering of the GOA circuit can be effectively suppressed.
  • the pixel matrix includes a plurality of rows of pixels, and the output of the GOA unit of each stage is configured to output a scan pulse signal to a corresponding row of pixels of the pixel matrix, the row of pixels being connected The enable input of the GOA unit of the lower stage.
  • a display device includes the array substrate according to any of the above embodiments.
  • the shutdown mechanism is in an inactive state during a period in which a scan pulse signal needs to be generated, and is in an active state at other times. In this way, the conduction and amplification mechanisms that generate false triggers are cut off, and the false triggering of the GOA circuit can be effectively suppressed.
  • FIG. 1 is a block diagram of a display device according to an embodiment of the present invention.
  • FIG. 2 is a block diagram of a GOA unit in accordance with an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a GOA unit according to an embodiment of the present invention.
  • FIG. 4 is a timing chart of a GOA circuit according to an embodiment of the present invention.
  • Fig. 5 is a diagram showing the operation waveform of the first stage of the GOA unit according to the embodiment of the present invention.
  • Figure 6 is a schematic diagram showing the operation of the first stage of the GOA unit of the embodiment of the present invention.
  • Fig. 7 is a view showing the operation waveform of the second stage of the GOA unit of the embodiment of the present invention.
  • Figure 8 is a schematic diagram showing the operation of the second stage of the GOA unit of the embodiment of the present invention.
  • Fig. 9 is a view showing the operation waveform of the third stage of the GOA unit of the embodiment of the present invention.
  • Figure 10 is a schematic diagram showing the operation of the third stage of the GOA unit of the embodiment of the present invention.
  • Figure 11 is a diagram showing the operation waveform of the fourth stage of the GOA unit of the embodiment of the present invention.
  • Figure 12 is a diagram showing the operation of the fourth stage of the GOA unit of the embodiment of the present invention.
  • Figure 13 is a diagram showing the operation waveform of the fifth stage of the GOA unit of the embodiment of the present invention.
  • Figure 14 is a diagram showing the operation of the fifth stage of the GOA unit of the embodiment of the present invention.
  • Figure 15 is a diagram showing the operation waveform of the sixth stage of the GOA unit of the embodiment of the present invention.
  • Figure 16 is a diagram showing the operation of the sixth stage of the GOA unit of the embodiment of the present invention.
  • Figure 17 is a diagram showing the operation waveform of the seventh stage of the GOA unit of the embodiment of the present invention.
  • Figure 18 is a diagram showing the operation of the seventh stage of the GOA unit of the embodiment of the present invention.
  • Fig. 19 is a view showing simulation results of a GOA circuit according to an embodiment of the present invention.
  • a GOA circuit 10 a GOA unit 12, an adjustment unit 121, a switching device 122, a reset unit 123, a holding unit 124, a relaxation unit 125, a pixel matrix 20, an array substrate 100, and a display device 1000;
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Or implicitly indicating the number of technical features indicated. Thus, features defining “first”, “second” may explicitly or implicitly include one or more of the features. In the description, “a plurality” means two or more, unless specifically defined otherwise.
  • connection should be understood broadly, and may be fixed connection, for example, or Removable connection, or integral connection; can be mechanical connection, electrical connection or communication with each other; can be direct connection or indirect connection through intermediate medium, can be internal connection of two components or two components Interaction relationship.
  • connection should be understood broadly, and may be fixed connection, for example, or Removable connection, or integral connection; can be mechanical connection, electrical connection or communication with each other; can be direct connection or indirect connection through intermediate medium, can be internal connection of two components or two components Interaction relationship.
  • the "on" or “below” of the second feature may include direct contact of the first and second features, and may also include the first sum, unless otherwise specifically defined and defined.
  • the second feature is not in direct contact but through additional features between them.
  • the first feature “above”, “above” and “above” the second feature includes the first feature directly above and above the second feature, or merely indicating that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature includes the first feature directly below and below the second feature, or merely the first feature level being less than the second feature.
  • the transistors used in all embodiments of the present invention may each be a field effect transistor, and more specifically may be a thin film transistor (TFT). Since the source and drain of the FET used here are symmetrical, they are usually used interchangeably. In order to facilitate distinguishing the two poles of the FET except the gate, the upper end of the FET is defined as the source, the middle end is the gate, and the lower end is the drain according to the form in the drawing.
  • TFT thin film transistor
  • each transistor M1 to M7 is an N-type field effect transistor.
  • a similar implementation can be implemented using a P-type field effect transistor In this way, it is only necessary to reverse the polarity of the input signal, that is, the high level is turned to a low level, and the low level is turned to a high level. Therefore, embodiments of the invention are not limited to embodiments of N-type field effect transistors.
  • the GOA circuit 10 of the embodiment of the present invention is used to provide a scan pulse signal to the pixel matrix 20.
  • the GOA circuit 10 includes a plurality of cascaded GOA units 12.
  • Each GOA unit 12 has a shutdown mechanism.
  • the shutdown mechanism includes an active state and an inactive state.
  • Each GOA unit 12 includes an enable input EN, a clock signal terminal CLKB, and an output terminal OUT.
  • the enable input EN is used to receive an enable input signal.
  • the clock signal terminal CLKB is used to receive a clock signal.
  • the output terminal OUT When the shutdown mechanism is in an inactive state, the output terminal OUT outputs a scan pulse signal according to the enable input signal and the clock signal.
  • the shutdown mechanism is active, the output terminal OUT turns off the output scan pulse signal.
  • the shutdown mechanism is in an inactive state during a period in which a scan pulse signal needs to be generated, and is in an active state at other times. In this way, the conduction and amplification mechanisms that generate false triggers are cut off, and the false triggering of the GOA circuit 10 can be effectively suppressed.
  • the array substrate 100 of the embodiment of the present invention includes a pixel matrix 20 and a GOA circuit 10.
  • the array substrate 100 of the embodiment of the present invention can be used in the display device 1000 of the embodiment of the present invention.
  • the display device 1000 of the embodiment of the present invention includes the array substrate 100 of the embodiment of the present invention.
  • the display device 1000 may be a display device such as an LCD (Liquid Crystal Display) or an AMOLED (Active-Matrix Organic Light Emitting Diode).
  • LCD Liquid Crystal Display
  • AMOLED Active-Matrix Organic Light Emitting Diode
  • pixel matrix 20 includes a plurality of rows of pixels.
  • the output OUT of the GOA unit 12 of each stage is used to output a scan pulse signal to a corresponding row of pixels of the pixel matrix 20, and a row of pixels is connected to the enable input EN of the GOA unit 12 of the lower stage.
  • adjacent two levels of GOA units 12 are located on either side of the pixel matrix 20.
  • each GOA unit 12 includes an adjustment unit 121, a switching device 122, a first capacitor C1, and a first node PU.
  • the adjustment unit 121 connects the enable input EN and the first node PU.
  • the switching device 122 is connected to the first node PU, the clock signal terminal CLKB, and the output terminal OUT.
  • the first capacitor C1 is connected to the first node PU and the output terminal OUT.
  • the adjusting unit 121 is configured to adjust the voltage of the first node PU to the first set voltage, and the switching device 122 is turned on.
  • the first capacitor C1 is used to further adjust the voltage of the first node PU from the first set voltage to the second set voltage, the switching device 122 is turned on deeply, and the output terminal OUT outputs a scan pulse signal.
  • the absolute value of the second set voltage is greater than the absolute value of the first set voltage.
  • each transistor employs an N-type field effect transistor.
  • the adjusting unit 121 is configured to charge the first node PU such that the voltage of the first node PU rises to the first set voltage VGH. At this time, the adjusting unit 121 functions as a pull-up, for example, the first set voltage is 2V. .
  • the first capacitor C1 is used to make the first node PU The voltage is further increased from the first set voltage to a second set voltage, for example, the second set voltage is 3V.
  • the first capacitor C1 is a bootstrap capacitor.
  • the enable input terminal EN and the first capacitor C1 together cause the voltage of the first node PU to rise by 2 (VGH-VGL), the switching device 122 is turned on deeply, and the output terminal OUT outputs a scan pulse signal.
  • VGH is the first set voltage
  • (2VGH - VGL) is the second set voltage
  • VGL is the third set voltage.
  • the first set voltage VGH may be a high level voltage
  • the third set voltage VGL may be a low level voltage.
  • each transistor employs a P-type field effect transistor.
  • the adjusting unit 121 is configured to discharge the first node PU such that the voltage of the first node PU drops to the first set voltage VGH. At this time, the adjusting unit 121 functions as a pull-down, for example, the first set voltage VGH is -2V.
  • the first capacitor C1 is used to cause the voltage of the first node PU to further drop from the first set voltage VGH to the second set voltage (2VGH - VGL), for example, the second set voltage (2VGH - VGL) is -3V. It will not be expanded in detail here.
  • the adjustment unit 121 includes a first transistor M1.
  • the gate and source of the first transistor M1 are connected to the enable input terminal EN, and the drain of the first transistor M1 is connected to the first node PU.
  • the enable input signal charges the first node PU through the first transistor M1, so that the voltage of the first node PU rises to the first set voltage VGH, thereby turning on the switching device 122 to complete the output scan. Preparation of the pulse.
  • each GOA unit 12 includes a high level terminal VGH, a reset terminal CLKRST, a reset unit 123, a holding unit 124, a low level terminal VGL, and a second node PD.
  • the reset unit 123 is connected to the high level terminal VGH, the reset terminal CLKRST, and the second node PD.
  • the holding unit 124 is connected to the first node PU, the second node PD, the output terminal OUT, and the low level terminal VGL.
  • the reset unit 123 is configured to adjust the voltage of the second node PD to the first set voltage VGH.
  • the holding unit 124 is configured to clamp the voltage of the first node PU voltage and the output terminal OUT to the third set voltage VGL.
  • the switching device 122 is turned off, and the output terminal OUT turns off the output scan pulse signal.
  • the absolute value of the third set voltage VGL is smaller than the absolute value of the first set voltage VGH.
  • each transistor employs an N-type field effect transistor.
  • the reset unit 123 is configured to charge the second node PD such that the voltage of the second node PD rises to the first set voltage VGH. At this time, the reset unit 123 functions as a pull-up, for example, the first set voltage VGH is 2V.
  • the holding unit 124 is configured to discharge the first node PU and the output terminal OUT such that the voltage of the first node PU voltage and the output terminal OUT is clamped at the third set voltage VGL, for example, the third set voltage VGL is 1V.
  • the switching device 122 When the shutdown mechanism is in an active state, the switching device 122 is turned off, and the holding unit 124 directly introduces the minute floating of the output of the previous stage to the ground to prevent it from affecting the closing depth of the switching device 122 of the present stage. In this way, the conduction and amplification mechanisms that generate false triggers are cut off, and false triggering caused by parasitic effects can be effectively suppressed.
  • each transistor employs a P-type field effect transistor.
  • the reset unit 123 is configured to discharge the second node PD such that the voltage of the second node PD drops to the first set voltage VGH. At this time, the reset unit 123 functions as a pull-down, for example, the first set voltage VGH is -2V.
  • the holding unit 124 is configured to charge the first node PU and the output terminal OUT such that the voltages of the first node PU voltage and the output terminal OUT are clamped at the third set voltage VGL, for example, the third set voltage VGL is -1V. It will not be expanded in detail here.
  • the switching device 122 includes a third transistor M3.
  • the gate of the third transistor M3 is connected to the first node PU, the source of the third transistor M3 is connected to the clock signal terminal CLKB, and the drain of the third transistor M3 is connected to the output terminal OUT.
  • the GOA unit 12 of each stage only needs one large-sized third transistor M3, and therefore, the occupied area of the GOA unit 12 is optimized. Moreover, the large current flowing through the third transistor M3 alternates in two directions, and the metal electrode of the third transistor M3 is less likely to undergo electro-migration, which enhances the reliability of the GOA circuit 10.
  • the reset unit 123 includes a sixth transistor M6.
  • the gate of the sixth transistor M6 is connected to the reset terminal CLKRST, the source of the sixth transistor M6 is connected to the high-level terminal VGH, and the drain of the sixth transistor M6 is connected to the second node PD.
  • the sixth transistor M6 is used to charge the second node PD such that the voltage of the second node PD rises to the first set voltage VGH, thereby turning on the holding unit 124, and the shutdown mechanism is activated to enter the active state.
  • the holding unit 124 includes a second transistor M2 and a fifth transistor M5.
  • the gate of the second transistor M2 is connected to the second node PD, the source of the second transistor M2 is connected to the output terminal OUT, and the drain of the second transistor M2 is connected to the low-level terminal VGL.
  • the gate of the fifth transistor M5 is connected to the second node PD, the source of the fifth transistor M5 is connected to the first node PU, and the drain of the fifth transistor M5 is connected to the low level terminal VGL.
  • the second transistor M2 is configured to discharge the output terminal OUT such that the voltage of the output terminal OUT is clamped at the third set voltage VGL
  • the fifth transistor M5 is configured to discharge the first node PU such that the voltage of the first node PU The clamp is at the third set voltage VGL.
  • the voltage glitch of the clock signal terminal CLKB fed forward to the output terminal OUT through the switching device 122 is released by the second transistor M2, and the clock signal terminal CLKB of the previous stage GOA unit 12 is fed forward to be enabled to the GOA unit 12 of the present stage.
  • the voltage glitch of the input terminal EN is released by the fifth transistor M5.
  • each GOA unit 12 includes a second capacitor C2.
  • One end of the second capacitor C2 is connected to the second node PD, the other end of the second capacitor C2 is connected to the low-level terminal VGL, and the second capacitor C2 is used to maintain the voltage of the second node PD at the first set voltage VGH.
  • each GOA unit 12 includes a slack unit 125 and a slack signal terminal PDRST.
  • the slack unit 125 is connected to the enable input terminal EN or the first node PU, the slack signal terminal PDRST, and the second node PD And low level VGL.
  • the slack unit 125 is configured to adjust the voltage of the second node PD to the third set voltage VGL.
  • each transistor employs an N-type field effect transistor.
  • the slack unit 125 is configured to discharge the second node PD such that the voltage of the second node PD is lowered to the third set voltage VGL. At this time, the slack unit 125 functions as a pull-down, for example, the third set voltage VGL is 1V.
  • the relaxation unit 125 facilitates mitigating the pressure of the second node PD.
  • the holding unit 124 includes the second transistor M2 and the fifth transistor M5
  • the slack unit 125 discharges the second node PD such that the gate voltages of the second transistor M2 and the fifth transistor M5 are released, which is advantageous for reducing The threshold voltages of the second transistor M2 and the fifth transistor M5 drift and extend the lifetime.
  • each transistor employs a P-type field effect transistor.
  • the slack unit 125 is configured to charge the second node PD such that the voltage of the second node PD rises to the third set voltage VGL. At this time, the slack unit 125 functions as a pull-up, for example, the third set voltage is -1V. It will not be expanded in detail here.
  • the slack unit 125 includes a fourth transistor M4 and a seventh transistor M7.
  • the gate of the fourth transistor M4 can be connected to the enable input terminal EN or to the first node PU, the source of the fourth transistor M4 is connected to the second node PD, and the drain of the fourth transistor M4 is connected to the low-level terminal VGL.
  • the gate of the seventh transistor M7 is connected to the slack signal terminal PDRST, the source of the seventh transistor M7 is connected to the second node PD, and the drain of the seventh transistor M7 is connected to the low-level terminal VGL.
  • the reset terminal CLKRST is used to receive a reset signal.
  • the slack signal terminal PDRST is used to receive the slack signal.
  • the duty ratios of the enable input signal, clock signal, reset signal, and slack signal are all less than or equal to 25%.
  • the duty ratio of the enable input signal, the clock signal, the reset signal, and the slack signal may be 25%.
  • the enable input signal, the clock signal, the slack signal, and the reset signal are sequentially high level signals.
  • the enable input signal in the first stage, is a high level signal; in the second stage, the clock signal is a high level signal; in the third stage, the slack signal is a high level signal.
  • the reset signal is a high level signal.
  • the enable input signal is used to turn on the output transistor of the stage (third transistor M3), and thus the enable input signal can first output a high level signal to complete the preparation.
  • the clock signal, the slack signal, and the reset signal sequentially output a high level signal after the input signal is enabled to complete the bootstrap output, output the scan pulse signal, and turn off the output transistor after outputting the scan pulse signal to block the subsequent clock signal from passing.
  • the expected output voltages of the first node PU, the second node PD, and the output terminal OUT as shown in FIG. 4 can be obtained.
  • the enable input signal of the GOA unit 12 of the present stage coincides with the scan pulse signal of the GOA unit 12 of the previous stage.
  • the enable input letter of the GOA unit 12 of the present stage is both high level signals. (The division of the specific stage will be described in detail in the subsequent sections)
  • the output OUT of the GOA unit 12 of each stage is used to output a scan pulse signal to a corresponding row of pixels of the pixel matrix 20.
  • a row of pixels is connected to the enable input EN of the GOA unit 12 of the lower stage. That is to say, the scan pulse signal of the GOA unit 12 of the previous stage is used as a read signal of the next-stage GOA unit 12 in addition to the scan signal used as the pixel of the previous line.
  • Phase 1 Precharge phase
  • the enable input signal charges the voltage of the first node PU to the first set voltage VGH.
  • the enable input signal turns on the fourth transistor M4, and the fourth transistor M4 discharges the second node PD.
  • the third transistor M3 is turned on, and the output terminal OUT is ready to output a scan pulse signal.
  • Second stage bootstrap output stage
  • the clock signal raises the output terminal OUT voltage to the first set voltage VGH, and the first capacitor C1 raises the first node PU voltage to the second set voltage (2VGH-VGL), the third transistor.
  • the M3 is turned on deeply, so that the clock signal terminal CLKB is rapidly charged to the output terminal OUT, and the output terminal OUT outputs a scan pulse signal.
  • the third stage the output decline phase
  • the third transistor M3 continues to be turned on.
  • the third transistor M3 discharges the output terminal OUT, so that the voltage of the output terminal OUT falls back to the third with the clock signal terminal CLKB.
  • the slack signal turns on the seventh transistor M7 such that the second node PD remains at the third set voltage VGL.
  • the GOA unit 12 of each stage only needs one large-sized third transistor M3, and therefore, the occupied area of the GOA unit 12 is optimized. Moreover, the large current flowing through the third transistor M3 alternates in two directions, and the metal electrode of the third transistor M3 is less likely to undergo electro-migration, which enhances the reliability of the GOA circuit 10.
  • the shutdown mechanism in the first phase, the second phase and the third phase, the shutdown mechanism is in an inactive state.
  • the fourth stage the first node PU reset phase
  • the reset signal turns on the sixth transistor M6.
  • the sixth transistor M6 charges the second node PD, the voltage of the second node PD rises to the first set voltage VGH, turns on the second transistor M2 and the fifth transistor M5, and the shutdown mechanism is activated.
  • the fifth transistor M5 discharges the first node PU, resets the voltage of the first node PU to the third set voltage VGL, and turns off the third transistor M3.
  • the second transistor M2 maintains the output terminal OUT at the third set voltage VGL.
  • the fifth stage the first stage of preservation
  • the second capacitor C2 maintains the second node PD at the first set voltage VGH
  • the second transistor M2 maintains the output terminal OUT at the third set voltage VGL
  • the fifth transistor M5 maintains the first node PU.
  • the voltage glitch that is conducted to the enable input terminal EN of the current stage due to the feed-forward of the clock signal CLKB of the previous stage is directly released to the ground by the fifth transistor M5, and therefore does not raise the first node of the GOA unit of the present stage.
  • the voltage of the PU is directly released to the ground by the fifth transistor M5, and therefore does not raise the first node of the GOA unit of the present stage.
  • the fifth transistor M5 and the first capacitor C1 in the on state form a first-order low-pass filter that filters out the high-frequency glitch current signal from the enable input EN.
  • the fourth phase, the fifth phase, the sixth phase, and the seventh phase will be continuously and alternately performed, and the cycle will be repeated, that is, the third phase, the fourth phase, the fifth phase, and the sixth phase.
  • the first node PU and the output terminal OUT are clamped at the third set voltage VGL, which is slightly different from the first fourth stage which occurs immediately after the end of the third stage, the latter There is an action of discharging the first node PU to the third set voltage VGL, and the fourth stage after the start of the cycle is to maintain the first node PU at the third set voltage VGL.
  • the second capacitor C2 maintains the second node PD at the first set voltage VGH
  • the second transistor M2 maintains the output terminal OUT at the third set voltage VGL
  • the fifth transistor M5 maintains the first node PU at The third set voltage VGL.
  • the seventh stage the second node PD pressure mitigation stage
  • the slack signal turns on the seventh transistor M7, and the seventh transistor M7 discharges the second node PD.
  • the gate voltages of the second transistor M2 and the fifth transistor M5 are released, which is advantageous for reducing drift and extending life.
  • the shutdown mechanism is activated in the fourth phase, and in the fifth phase and the sixth phase, the shutdown mechanism is active.
  • the circuit is cycled in the fourth phase, the fifth phase, the sixth phase, and the seventh phase, and the voltages of the first node PU and the output terminal OUT are clamped at the third set voltage VGL.
  • the circuit Until the next frame of the scan pulse signal arrives, the circuit returns to the first stage.
  • FIG. 19 is a simulation result of the GOA circuit 10 according to an embodiment of the present invention.
  • the GOA circuit 10 can work normally even if the voltage of the output terminal OUT shifts from -2V to +3V. .
  • the output glitch of the preceding stage GOA unit 12 is not accumulated on the first node PU of the lower stage GOA unit 12, but is discharged by the second node PD through the fifth transistor M5.
  • the GOA circuit 10 of the embodiment of the present invention has the following advantages:
  • the present invention designs a new shutdown mechanism by changing the internal circuit design and employing new operational timing.
  • the shutdown mechanism is inactive during the period in which the scan pulse signal needs to be generated, and can be active at other times.
  • the active shutdown mechanism can directly introduce the small floating of the previous stage output to the ground, preventing it from affecting the closing depth of the output transistor of the stage (ie, the third transistor M3). In this way, the conduction and amplification mechanisms that generate false triggers are cut off, and false triggering caused by parasitic effects can be effectively suppressed.
  • the number of transistors required for the GOA circuit 10 of the embodiment of the present invention is small, and the size of each transistor is not large. Therefore, the occupied area is small, which is advantageous for reducing the size of the screen frame.
  • the GOA circuit 10 of the embodiment of the present invention does not have a node that maintains a constant high voltage for a long time. Compared with a circuit having a constant high voltage node, the GOA circuit 10 of the embodiment of the present invention has a small pressure on the transistor, which is advantageous for improving the GOA circuit 10. And the stability of the screen display.
  • the transistor responsible for driving the output load (ie, the third transistor M3) in the GOA circuit 10 of the embodiment of the present invention is responsible for both charging and discharging, and is subjected to bidirectional current, thereby avoiding the collision of electrons against the lattice in a single direction.
  • the electric migration effect is beneficial to extend the life of the circuit.
  • a "computer-readable medium” can be any apparatus that can contain, store, communicate, propagate, or transport a program for use in an instruction execution system, apparatus, or device, or in conjunction with the instruction execution system, apparatus, or device.
  • computer readable media include the following: electrical connections (IPM overcurrent protection circuits) with one or more wires, portable computer disk cartridges (magnetic devices), random access memories (RAM), read only memory (ROM), erasable editable read only memory (EPROM or flash memory), fiber optic devices, and portable compact disk read only memory (CDROM).
  • the computer readable medium may even be a paper or other suitable medium on which the program can be printed, as it may be optically scanned, for example by paper or other medium, followed by editing, interpretation or, if appropriate, other suitable The method is processed to obtain the program electronically and then stored in computer memory.
  • portions of the embodiments of the invention may be implemented in hardware, software, firmware or a combination thereof.
  • multiple steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system.
  • a suitable instruction execution system For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques well known in the art: having logic gates for implementing logic functions on data signals. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium.
  • the above mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

公开了一种GOA电路(10)，用于为像素矩阵(20)提供扫描脉冲信号。GOA电路(10)包括级联的多个GOA单元(12)。每个GOA单元(12)具有关闭机制，关闭机制包括活跃状态和非活跃状态。每个GOA单元(12)包括使能输入端(EN)、时钟信号端(CLKB)和输出端(OUT)。使能输入端(EN)用于接收使能输入信号，时钟信号端(CLKB)用于接收时钟信号。当关闭机制处于非活跃状态时，输出端(OUT)根据使能输入信号和时钟信号输出扫描脉冲信号。当关闭机制处于活跃状态时，输出端(OUT)截止输出扫描脉冲信号。此外，还公开了一种阵列基板(100)和显示装置(1000)。

Description

GOA电路、阵列基板和显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种GOA电路、阵列基板和显示装置。
背景技术
近年来，GOA(Gate driver on array，阵列基板栅极驱动)电路广泛应用于LCD和AMOLED等电子显示器中。它是显示面板的关键部分，用于向像素矩阵提供扫描脉冲信号。GOA电路通常被设计成级联形式。随着人们对显示面板的分辨率要求越来越高，每一行像素的数目增加，每一级GOA单元需要驱动的负载也相应地增加。这就要求GOA单元采用更大尺寸的输出晶体管，以便在产生扫描脉冲信号时提供更大的驱动电流。然而，当输出晶体管的尺寸增大时，GOA单元的输入端到输出端的寄生耦合电容也会增加，以至于即使在输出晶体管关闭时，输出时钟的脉冲信号仍然会通过电容前馈到输出端，引起输出端的电压产生不必要的微小浮动，微小浮动经过级联的GOA单元后会变成更大的浮动，最终导致一定级数之后，某级GOA单元的输出晶体管在输出时钟信号的所有脉冲的触发沿到来时都被处于打开状态，引起误触发，产生多余或错误的脉冲输出。
发明内容
本发明旨在至少解决相关技术中存在的技术问题之一。为此，本发明实施方式需要提供一种GOA电路、阵列基板和显示装置。
本发明实施方式的GOA电路，用于为像素矩阵提供扫描脉冲信号，所述GOA电路包括级联的多个GOA单元，每个所述GOA单元具有关闭机制，所述关闭机制包括活跃状态和非活跃状态，每个所述GOA单元包括使能输入端、时钟信号端和输出端，所述使能输入端用于接收使能输入信号，所述时钟信号端用于接收时钟信号，当所述关闭机制处于非活跃状态时，所述输出端根据所述使能输入信号和所述时钟信号输出所述扫描脉冲信号，当所述关闭机制处于活跃状态时，所述输出端截止输出所述扫描脉冲信号。
本发明实施方式的GOA电路中，关闭机制在需要产生扫描脉冲信号的周期内处于非活跃状态，而可在其他时间内都处于活跃状态。如此，切断了产生误触发的传导和放大机制，能够有效抑制GOA电路的误触发。
在某些实施方式中，每个所述GOA单元包括调整单元、开关器件、第一电容和第 一节点，所述调整单元连接所述使能输入端和所述第一节点，所述开关器件连接所述第一节点、所述时钟信号端和所述输出端，所述第一电容连接所述第一节点和所述输出端，当所述关闭机制处于非活跃状态时，所述调整单元用于将所述第一节点的电压调整至第一设定电压，所述开关器件开启；所述第一电容用于使得所述第一节点的电压从所述第一设定电压进一步调整至第二设定电压，所述开关器件深度开启，所述输出端输出所述扫描脉冲信号，其中，所述第二设定电压的绝对值大于所述第一设定电压的绝对值。
在某些实施方式中，所述调整单元包括第一晶体管，所述第一晶体管的栅极和源极连接所述使能输入端，所述第一晶体管的漏极连接所述第一节点。
在某些实施方式中，每个所述GOA单元包括高电平端、复位端、复位单元、保持单元、低电平端和第二节点，所述复位单元连接所述高电平端、所述复位端和所述第二节点，所述保持单元连接所述第一节点、所述第二节点、所述输出端和所述低电平端，当所述关闭机制处于活跃状态时，所述复位单元用于将所述第二节点的电压调整至所述第一设定电压，所述保持单元用于使得所述第一节点的电压和所述输出端的电压钳制在第三设定电压，所述开关器件关闭，所述输出端截止输出所述扫描脉冲信号，其中，所述第三设定电压的绝对值小于所述第一设定电压的绝对值。
在某些实施方式中，所述开关器件包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述时钟信号端，所述第三晶体管的漏极连接所述输出端。
在某些实施方式中，所述复位单元包括第六晶体管，所述第六晶体管的栅极连接所述复位端，所述第六晶体管的源极连接所述高电平端，所述第六晶体管的漏极连接所述第二节点。
在某些实施方式中，所述保持单元包括第二晶体管和第五晶体管，所述第二晶体管的栅极连接所述第二节点，所述第二晶体管的源极连接所述输出端，所述第二晶体管的漏极连接所述低电平端，所述第五晶体管的栅极连接所述第二节点，所述第五晶体管的源极连接所述第一节点，所述第五晶体管的漏极连接所述低电平端。
在某些实施方式中，每个所述GOA单元包括第二电容，所述第二电容的一端连接所述第二节点，所述第二电容的另一端连接所述低电平端，所述第二电容用于使得所述第二节点的电压保持在所述第一设定电压。
在某些实施方式中，每个所述GOA单元包括松弛单元和松弛信号端，所述松弛单元连接所述使能输入端或所述第一节点、所述松弛信号端、所述第二节点和所述低电平端，所述松弛单元用于将所述第二节点的电压调整至所述第三设定电压。
在某些实施方式中，所述松弛单元包括第四晶体管和第七晶体管，所述第四晶体管的栅极连接所述使能输入端或所述第一节点，所述第四晶体管的源极连接所述第二节点，所述第四晶体管的漏极连接所述低电平端，所述第七晶体管的栅极连接所述松弛信号端，所述第七晶体管的源极连接所述第二节点，所述第七晶体管的漏极连接所述低电平端。
在某些实施方式中，所述复位端用于接收复位信号，所述松弛信号端用于接收松弛信号，所述使能输入信号、所述时钟信号、所述复位信号和所述松弛信号的占空比均小于或等于25％。
在某些实施方式中，本级的所述GOA单元的所述使能输入信号与前级的所述GOA单元的所述扫描脉冲信号一致。
本发明实施方式的阵列基板，包括：
像素矩阵；和
如上述任一实施方式所述的GOA电路。
本发明实施方式的阵列基板中，关闭机制在需要产生扫描脉冲信号的周期内处于非活跃状态，而在其他时间内都处于活跃状态。如此，切断了产生误触发的传导和放大机制，能够有效抑制GOA电路的误触发。
在某些实施方式中，所述像素矩阵包括多行像素，每级的所述GOA单元的所述输出端用于输出扫描脉冲信号给所述像素矩阵的对应的一行像素，所述一行像素连接下级的所述GOA单元的所述使能输入端。
本发明实施方式的显示装置，包括如上述任一实施方式所述的阵列基板。
本发明实施方式的显示装置中，关闭机制在需要产生扫描脉冲信号的周期内处于非活跃状态，而在其他时间内都处于活跃状态。如此，切断了产生误触发的传导和放大机制，能够有效抑制GOA电路的误触发。
本发明实施方式的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点可以从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1是本发明实施方式的显示装置的模块示意图。
图2是本发明实施方式的GOA单元的模块示意图。
图3是本发明实施方式的GOA单元的电路图。
图4是本发明实施方式的GOA电路的时序图。
图5是本发明实施方式的GOA单元第一阶段的工作波形图。
图6是本发明实施方式的GOA单元第一阶段的工作原理图。
图7是本发明实施方式的GOA单元第二阶段的工作波形图。
图8是本发明实施方式的GOA单元第二阶段的工作原理图。
图9是本发明实施方式的GOA单元第三阶段的工作波形图。
图10是本发明实施方式的GOA单元第三阶段的工作原理图。
图11是本发明实施方式的GOA单元第四阶段的工作波形图。
图12是本发明实施方式的GOA单元第四阶段的工作原理图。
图13是本发明实施方式的GOA单元第五阶段的工作波形图。
图14是本发明实施方式的GOA单元第五阶段的工作原理图。
图15是本发明实施方式的GOA单元第六阶段的工作波形图。
图16是本发明实施方式的GOA单元第六阶段的工作原理图。
图17是本发明实施方式的GOA单元第七阶段的工作波形图。
图18是本发明实施方式的GOA单元第七阶段的工作原理图。
图19是本发明实施方式的GOA电路的仿真结果图。
主要元件及符号说明：
GOA电路10、GOA单元12、调整单元121、开关器件122、复位单元123、保持单元124、松弛单元125、像素矩阵20、阵列基板100、显示装置1000；
第一电容C1、第二电容C2、第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、使能输入端EN、时钟信号端CLKB、输出端OUT、第一节点PU、第二节点PD、高电平端VGH、低电平端VGL、复位端CLKRST、松弛信号端PDRST。
具体实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中，相同或类似的标号自始至终表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明的实施方式，而不能理解为对本发明的实施方式的限制。
在本发明的实施方式的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆 时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明的实施方式和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的实施方式的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的实施方式的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的实施方式的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“连接”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接连接，也可以通过中间媒介间接连接，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明的实施方式中的具体含义。
在本发明的实施方式中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的实施方式的不同结构。为了简化本发明的实施方式的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明的实施方式可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明的实施方式提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明所有实施方式中采用的晶体管均可以为场效应管，更具体地可以为薄膜晶体管(Thin-film transistor，TFT)。由于这里采用的场效应管的源极、漏极是对称的，通常可以互换使用。为了便于区分场效应管除栅极之外的两极，可以按照附图中的形态规定场效应管的上侧端为源极、中间端为栅极、下侧端为漏极。
除特别说明外，以下对本发明实施方式GOA电路的描述主要是基于各晶体管(M1～M7)为N型场效应晶体管的特例。使用P型场效应晶体管可以采取类似的实施 方式，而仅需将输入信号的电压极性反转，即高电平转成低电平，低电平转为高电平。因此本发明实施方式并不限定于N型场效应晶体管的实施方式。
请参阅图1-3，本发明实施方式的GOA电路10用于为像素矩阵20提供扫描脉冲信号。GOA电路10包括级联的多个GOA单元12。每个GOA单元12具有关闭机制。关闭机制包括活跃状态和非活跃状态。每个GOA单元12包括使能输入端EN、时钟信号端CLKB和输出端OUT。使能输入端EN用于接收使能输入信号。时钟信号端CLKB用于接收时钟信号。当关闭机制处于非活跃状态时，输出端OUT根据使能输入信号和时钟信号输出扫描脉冲信号。当关闭机制处于活跃状态时，输出端OUT截止输出扫描脉冲信号。
本发明实施方式的GOA电路10中，关闭机制在需要产生扫描脉冲信号的周期内处于非活跃状态，而在其他时间内都处于活跃状态。如此，切断了产生误触发的传导和放大机制，能够有效抑制GOA电路10的误触发。
本发明实施方式的阵列基板100包括像素矩阵20和GOA电路10。
本发明实施方式的阵列基板100可以用于本发明实施方式的显示装置1000。或者说，本发明实施方式的显示装置1000包括本发明实施方式的阵列基板100。
在一些示例中，显示装置1000可以为LCD(Liquid Crystal Display，液晶显示器)或AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体)等显示装置。
在某些实施方式中，像素矩阵20包括多行像素。每级的GOA单元12的输出端OUT用于输出扫描脉冲信号给像素矩阵20的对应的一行像素，一行像素连接下级的GOA单元12的使能输入端EN。
在一个例子中，相邻的两级的GOA单元12位于像素矩阵20的两侧。
在某些实施方式中，每个GOA单元12包括调整单元121、开关器件122、第一电容C1和第一节点PU。调整单元121连接使能输入端EN和第一节点PU。开关器件122连接第一节点PU、时钟信号端CLKB和输出端OUT。第一电容C1连接第一节点PU和输出端OUT。当关闭机制处于非活跃状态时，调整单元121用于将第一节点PU的电压调整至第一设定电压，开关器件122开启。第一电容C1用于使得第一节点PU的电压从第一设定电压进一步调整至第二设定电压，开关器件122深度开启，输出端OUT输出扫描脉冲信号。其中，第二设定电压的绝对值大于第一设定电压的绝对值。
在一个实施方式中，各晶体管采用N型场效应晶体管。调整单元121用于对第一节点PU充电使得所述第一节点PU的电压上升至第一设定电压VGH，此时，调整单元121起到上拉的作用，例如第一设定电压为2V。第一电容C1用于使得第一节点PU 的电压从第一设定电压进一步上升至第二设定电压，例如第二设定电压为3V。
可以理解，第一电容C1为自举电容。使能输入端EN和第一电容C1共使得第一节点PU的电压上升了2(VGH-VGL)，开关器件122深度开启，输出端OUT输出扫描脉冲信号。其中，VGH为第一设定电压，(2VGH–VGL)为第二设定电压，VGL为第三设定电压。第一设定电压VGH可为高电平电压，第三设定电压VGL可为低电平电压。
在另一个实施方式中，各晶体管采用P型场效应晶体管。调整单元121用于对第一节点PU进行放电使得所述第一节点PU的电压下降至第一设定电压VGH，此时，调整单元121起到下拉的作用，例如第一设定电压VGH为-2V。第一电容C1用于使得第一节点PU的电压从第一设定电压VGH进一步下降至第二设定电压(2VGH–VGL)，例如第二设定电压(2VGH–VGL)为-3V。在此不再详细展开。
在某些实施方式中，调整单元121包括第一晶体管M1。第一晶体管M1的栅极和源极连接使能输入端EN，第一晶体管M1的漏极连接第一节点PU。
当关闭机制处于非活跃状态时，使能输入信号通过第一晶体管M1对第一节点PU充电，使得第一节点PU的电压上升至第一设定电压VGH，从而开启开关器件122，完成输出扫描脉冲的准备工作。
在某些实施方式中，每个GOA单元12包括高电平端VGH、复位端CLKRST、复位单元123、保持单元124、低电平端VGL和第二节点PD。复位单元123连接高电平端VGH、复位端CLKRST和第二节点PD。保持单元124连接第一节点PU、第二节点PD、输出端OUT和低电平端VGL。当关闭机制处于活跃状态时，复位单元123用于将第二节点PD的电压调整至第一设定电压VGH。保持单元124用于使得第一节点PU电压和输出端OUT的电压钳制在第三设定电压VGL。开关器件122关闭，输出端OUT截止输出扫描脉冲信号。其中，第三设定电压VGL的绝对值小于第一设定电压VGH的绝对值。
在一个实施方式中，各晶体管采用N型场效应晶体管。复位单元123用于对第二节点PD充电使得第二节点PD的电压上升至第一设定电压VGH。此时，复位单元123起到上拉的作用，例如第一设定电压VGH为2V。保持单元124用于对第一节点PU和输出端OUT进行放电使得第一节点PU电压和输出端OUT的电压钳制在第三设定电压VGL，例如第三设定电压VGL为1V。
当关闭机制处于活跃状态时，开关器件122关闭，保持单元124将前级输出的微小浮动直接导入到地，避免其影响本级开关器件122的关闭深度。如此，切断了产生误触发的传导和放大机制，能够有效抑制由寄生效应导致的误触发。
在另一个实施方式中，各晶体管采用P型场效应晶体管。复位单元123用于对第二节点PD进行放电使得第二节点PD的电压下降至第一设定电压VGH。此时，复位单元123起到下拉的作用，例如第一设定电压VGH为-2V。保持单元124用于对第一节点PU和输出端OUT充电使得第一节点PU电压和输出端OUT的电压钳制在第三设定电压VGL，例如第三设定电压VGL为-1V。在此不再详细展开。
在某些实施方式中，开关器件122包括第三晶体管M3。第三晶体管M3的栅极连接第一节点PU，第三晶体管M3的源极连接时钟信号端CLKB，第三晶体管M3的漏极连接输出端OUT。
由于输出端OUT的充放电均是通过第三晶体管M3进行，每级的GOA单元12只需一个大尺寸的第三晶体管M3，因此，GOA单元12的占用面积得到优化。而且，流经第三晶体管M3的大电流为两个方向交替进行，第三晶体管M3的金属电极不易发生电迁徙(electro-migration)，增强了GOA电路10的可靠性。
在某些实施方式中，复位单元123包括第六晶体管M6。第六晶体管M6的栅极连接复位端CLKRST，第六晶体管M6的源极连接高电平端VGH，第六晶体管M6的漏极连接第二节点PD。
也即是说，第六晶体管M6用于对第二节点PD充电使得第二节点PD的电压上升至第一设定电压VGH，从而打开保持单元124，关闭机制激活以进入活跃状态。
在某些实施方式中，保持单元124包括第二晶体管M2和第五晶体管M5。第二晶体管M2的栅极连接第二节点PD，第二晶体管M2的源极连接输出端OUT，第二晶体管M2的漏极连接低电平端VGL。第五晶体管M5的栅极连接第二节点PD，第五晶体管M5的源极连接第一节点PU，第五晶体管M5的漏极连接低电平端VGL。
具体地，第二晶体管M2用于对输出端OUT进行放电使得输出端OUT的电压钳制在第三设定电压VGL，第五晶体管M5用于对第一节点PU进行放电使得第一节点PU的电压钳制在第三设定电压VGL。
如此，时钟信号端CLKB通过开关器件122前馈到输出端OUT的电压毛刺被第二晶体管M2释放，前一级GOA单元12的时钟信号端CLKB前馈而传导到本级GOA单元12的使能输入端EN的电压毛刺被第五晶体管M5释放。
在某些实施方式中，每个GOA单元12包括第二电容C2。第二电容C2的一端连接第二节点PD，第二电容C2的另一端连接低电平端VGL，第二电容C2用于使得第二节点PD的电压保持在第一设定电压VGH。
在某些实施方式中，每个GOA单元12包括松弛单元125和松弛信号端PDRST。松弛单元125连接使能输入端EN或第一节点PU、松弛信号端PDRST、第二节点PD 和低电平端VGL。松弛单元125用于将第二节点PD的电压调整至第三设定电压VGL。
在一个实施方式中，各晶体管采用N型场效应晶体管。松弛单元125用于对第二节点PD进行放电使得第二节点PD的电压降低至第三设定电压VGL。此时，松弛单元125起到下拉的作用，例如第三设定电压VGL为1V。
如此，松弛单元125有利于缓解第二节点PD的压力。而且，当保持单元124包括第二晶体管M2和第五晶体管M5时，松弛单元125对第二节点PD进行放电，使得第二晶体管M2和第五晶体管M5的栅极电压被释放，有利于减小第二晶体管M2和第五晶体管M5的阈值电压漂移、延长寿命。
在另一个实施方式中，各晶体管采用P型场效应晶体管。松弛单元125用于对第二节点PD充电使得第二节点PD的电压上升至第三设定电压VGL。此时，松弛单元125起到上拉的作用，例如第三设定电压为-1V。在此不再详细展开。
在某些实施方式中，松弛单元125包括第四晶体管M4和第七晶体管M7。第四晶体管M4的栅极既可连接使能输入端EN也可连接第一节点PU，第四晶体管M4的源极连接第二节点PD，第四晶体管M4的漏极连接低电平端VGL。第七晶体管M7的栅极连接松弛信号端PDRST，第七晶体管M7的源极连接第二节点PD，第七晶体管M7的漏极连接低电平端VGL。
在某些实施方式中，复位端CLKRST用于接收复位信号。松弛信号端PDRST用于接收松弛信号。使能输入信号、时钟信号、复位信号和松弛信号的占空比均小于或等于25％。
请参阅图4，在一个例子中，使能输入信号、时钟信号、复位信号、松弛信号的占空比可以均为25％。使能输入信号、时钟信号、松弛信号、复位信号依次为高电平信号。具体地，在本发明实施方式中，在第一阶段，使能输入信号为高电平信号；在第二阶段，时钟信号为高电平信号；在第三阶段，松弛信号为高电平信号；在第四阶段，复位信号为高电平信号。(具体阶段的划分将在后续部分详细介绍)
在某些实施方式中，使能输入信号用于打开本级的输出晶体管(第三晶体管M3)，因而使能输入信号可以最先输出高电平信号，以完成准备工作。时钟信号、松弛信号、复位信号在使能输入信号后依次输出高电平信号，以完成自举输出，输出扫描脉冲信号，并在输出扫描脉冲信号后关闭输出晶体管，阻挡后续时钟信号通过。如此，可以得到如图4所示的第一节点PU、第二节点PD和输出端OUT预期的输出电压。
在某些实施方式中，本级的GOA单元12的使能输入信号与前级的GOA单元12的扫描脉冲信号一致。
具体地，在本发明实施方式中，在第一阶段，本级的GOA单元12的使能输入信 号与前级的GOA单元12的扫描脉冲信号均为高电平信号。(具体阶段的划分将在后续部分详细介绍)
可以理解，每级的GOA单元12的输出端OUT用于输出扫描脉冲信号给像素矩阵20的对应的一行像素。一行像素连接下级的GOA单元12的使能输入端EN。也即是说，前级的GOA单元12的扫描脉冲信号除了用作前一行像素的扫描信号，也用作下一级GOA单元12的准备信号。
下面分阶段来说明本发明实施方式的GOA电路10的工作原理。
第一阶段：预充电阶段
请参阅图5及6，使能输入信号将第一节点PU的电压充高至第一设定电压VGH。使能输入信号打开第四晶体管M4，通过第四晶体管M4对第二节点PD放电。第三晶体管M3开启，输出端OUT准备输出扫描脉冲信号。
第二阶段：自举输出阶段
请参阅图7及8，时钟信号抬高输出端OUT电压的至第一设定电压VGH，第一电容C1抬高第一节点PU电压至第二设定电压(2VGH-VGL)，第三晶体管M3深度开启，使得时钟信号端CLKB对输出端OUT迅速充电，输出端OUT输出扫描脉冲信号。
第三阶段：输出下降阶段
请参阅图9及10，第三晶体管M3继续打开，当时钟信号端CLKB的电压回落时，第三晶体管M3对输出端OUT放电，使得输出端OUT的电压随时钟信号端CLKB一同回落至第三设定电压VGL。松弛信号打开第七晶体管M7，使得第二节点PD保持在第三设定电压VGL。
由于输出端OUT的充放电均是通过第三晶体管M3进行，每级的GOA单元12只需一个大尺寸的第三晶体管M3，因此，GOA单元12的占用面积得到优化。而且，流经第三晶体管M3的大电流为两个方向交替进行，第三晶体管M3的金属电极不易发生电迁徙(electro-migration)，增强了GOA电路10的可靠性。
可以理解，在第一阶段、第二阶段和第三阶段，关闭机制处于非活跃状态。
第四阶段：第一节点PU重置阶段
请参阅图11及12，复位信号打开第六晶体管M6。第六晶体管M6对第二节点PD充电，第二节点PD的电压抬高至第一设定电压VGH，打开第二晶体管M2和第五晶体管M5，关闭机制激活。第五晶体管M5对第一节点PU放电，将第一节点PU的电压重置为第三设定电压VGL，关闭第三晶体管M3。第二晶体管M2保持输出端OUT为第三设定电压VGL。
第五阶段：第一保持阶段
请参阅图13及14，第二电容C2保持第二节点PD为第一设定电压VGH，第二晶体管M2保持输出端OUT为第三设定电压VGL，第五晶体管M5保持第一节点PU在第三设定电压VGL。
由于前一级的时钟信号端CLKB前馈而传导到本级的使能输入端EN的电压毛刺被第五晶体管M5直接释放到地，因此，不会抬高本级的GOA单元的第一节点PU的电压。
等效来看，开启状态的第五晶体管M5和第一电容C1组成一个一阶低通滤波器，滤除了来自使能输入端EN的高频毛刺电流信号。
可以理解，第三阶段结束后，第四阶段、第五阶段、第六阶段、第七阶段会连续、交替进行，循环往复，即第三阶段、第四阶段、第五阶段、第六阶段、第七阶段、第四阶段、第五阶段、第六阶段、第七阶段、第四阶段、第五阶段、第六阶段、第七阶段……。因此除了第三阶段结束以后的第一个第四阶段，其余第四阶段都是在第七阶段结束后进行的。以上进入循环以后的第四阶段，第一节点PU和输出端OUT都被钳制在第三设定电压VGL，和紧接在第三阶段结束后出现的第一个第四阶段略不同，后者有一个将第一节点PU放电到第三设定电压VGL的动作，而循环开始后的第四阶段都是保持第一节点PU在第三设定电压VGL。
第六阶段：第二保持阶段
请参阅图15及16，第二电容C2保持第二节点PD在第一设定电压VGH，第二晶体管M2保持输出端OUT在第三设定电压VGL，第五晶体管M5保持第一节点PU在第三设定电压VGL。
时钟信号端CLKB通过第三晶体管M3前馈到输出端OUT的电压毛刺被第二晶体管M2释放。
第七阶段：第二节点PD压力缓解阶段
请参阅图17及18，松弛信号打开第七晶体管M7，第七晶体管M7对第二节点PD放电。
第二晶体管M2和第五晶体管M5的栅压被释放，有利于减小漂移、延长寿命。
可以理解，关闭机制在第四阶段激活，在第五阶段、第六阶段，关闭机制处于活跃状态。
如此，电路在第四阶段、第五阶段、第六阶段、第七阶段，这三个阶段循环往复，第一节点PU和输出端OUT的电压被钳制在第三设定电压VGL。
直到下一帧扫描脉冲信号到来，电路回到第一阶段。
需要说明的是，附图所示的电路图中，当晶体管上显示“X”时，表明该晶体管处 于截止状态。
请参阅图19，图19为本发明实施方式的GOA电路10的仿真结果，当输出端OUT有负载时，即使输出端OUT的电压发生-2V到+3V的漂移，GOA电路10仍能正常工作。前级GOA单元12的输出毛刺没有累积在下级GOA单元12的第一节点PU上，而是被第二节点PD通过第五晶体管M5放电。
综上，本发明实施方式的GOA电路10具有如下优点：
1、通过改变内部电路设计和采用新的工作时序，本发明设计了新的关闭机制。关闭机制在需要产生扫描脉冲信号的周期内处于非活跃状态，而可在其他时间内都处于活跃状态。处于活跃状态的关闭机制可以将前级输出的微小浮动直接导入到地，避免其影响本级输出晶体管(即第三晶体管M3)的关闭深度。如此，切断了产生误触发的传导和放大机制，能够有效抑制由寄生效应导致的误触发。
2、本发明实施方式的GOA电路10所需的晶体管的数量少，对每个晶体管的尺寸要求也不大，因此，占用面积小，有利于减小屏幕边框的尺寸。
3、本发明实施方式的GOA电路10内部没有长时间保持恒定高压的节点，与有恒定高压节点的电路相比，本发明实施方式的GOA电路10对晶体管的压力小，有利于提高GOA电路10和屏幕显示的稳定性。
4、本发明实施方式的GOA电路10内负责驱动输出负载的晶体管(即第三晶体管M3)既负责充电也负责放电，承受的是双向电流，因而避免了由于电子对晶格持续单一方向碰撞引起的电迁徙效应，有利于延长电路寿命。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本发明的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本发明的实施例所属技术领域的技术人员所理解。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中， 以供指令执行系统、装置或设备(如基于计算机的系统、包括处理模块的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，"计算机可读介质"可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例(非穷尽性列表)包括以下：具有一个或多个布线的电连接部(IPM过流保护电路)，便携式计算机盘盒(磁装置)，随机存取存储器(RAM)，只读存储器(ROM)，可擦除可编辑只读存储器(EPROM或闪速存储器)，光纤装置，以及便携式光盘只读存储器(CDROM)。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸或其他介质进行光学扫描，接着进行编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本发明的实施方式的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本发明的各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。
尽管上面已经示出和描述了本发明的实施方式，可以理解的是，上述实施方式是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施实施进行变化、修改、替换和变型。

Claims (15)

  1. 一种GOA电路，用于为像素矩阵提供扫描脉冲信号，其特征在于，所述GOA电路包括级联的多个GOA单元，每个所述GOA单元具有关闭机制，所述关闭机制包括活跃状态和非活跃状态，每个所述GOA单元包括使能输入端、时钟信号端和输出端，所述使能输入端用于接收使能输入信号，所述时钟信号端用于接收时钟信号，当所述关闭机制处于非活跃状态时，所述输出端根据所述使能输入信号和所述时钟信号输出所述扫描脉冲信号，当所述关闭机制处于活跃状态时，所述输出端截止输出所述扫描脉冲信号。
  2. 如权利要求1所述的GOA电路，其特征在于，每个所述GOA单元包括调整单元、开关器件、第一电容和第一节点，所述调整单元连接所述使能输入端和所述第一节点，所述开关器件连接所述第一节点、所述时钟信号端和所述输出端，所述第一电容连接所述第一节点和所述输出端，当所述关闭机制处于非活跃状态时，所述调整单元用于将所述第一节点的电压调整至第一设定电压，所述开关器件开启；所述第一电容用于使得所述第一节点的电压从所述第一设定电压进一步调整至第二设定电压，所述开关器件深度开启，所述输出端输出所述扫描脉冲信号，其中，所述第二设定电压的绝对值大于所述第一设定电压的绝对值。
  3. 如权利要求2所述的GOA电路，其特征在于，所述调整单元包括第一晶体管，所述第一晶体管的栅极和源极连接所述使能输入端，所述第一晶体管的漏极连接所述第一节点。
  4. 如权利要求2所述的GOA电路，其特征在于，每个所述GOA单元包括高电平端、复位端、复位单元、保持单元、低电平端和第二节点，所述复位单元连接所述高电平端、所述复位端和所述第二节点，所述保持单元连接所述第一节点、所述第二节点、所述输出端和所述低电平端，当所述关闭机制处于活跃状态时，所述复位单元用于将所述第二节点的电压调整至所述第一设定电压，所述保持单元用于使得所述第一节点的电压和所述输出端的电压钳制在第三设定电压，所述开关器件关闭，所述输出端截止输出所述扫描脉冲信号，其中，所述第三设定电压的绝对值小于所述第一设定电压的绝对值。
  5. 如权利要求2或4所述的GOA电路，其特征在于，所述开关器件包括第三晶体管，所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述时钟信号端，所述第三晶体管的漏极连接所述输出端。
  6. 如权利要求4所述的GOA电路，其特征在于，所述复位单元包括第六晶体管，所述第六晶体管的栅极连接所述复位端，所述第六晶体管的源极连接所述高电平端，所述第六晶体管的漏极连接所述第二节点。
  7. 如权利要求4所述的GOA电路，其特征在于，所述保持单元包括第二晶体管和第五晶体管，所述第二晶体管的栅极连接所述第二节点，所述第二晶体管的源极连接所述输出端，所述第二晶体管的漏极连接所述低电平端，所述第五晶体管的栅极连接所述第二节点，所述第五晶体管的源极连接所述第一节点，所述第五晶体管的漏极连接所述低电平端。
  8. 如权利要求4所述的GOA电路，其特征在于，每个所述GOA单元包括第二电容，所述第二电容的一端连接所述第二节点，所述第二电容的另一端连接所述低电平端，所述第二电容用于使得所述第二节点的电压保持在所述第一设定电压。
  9. 如权利要求4所述的GOA电路，其特征在于，每个所述GOA单元包括松弛单元和松弛信号端，所述松弛单元连接所述使能输入端或所述第一节点、所述松弛信号端、所述第二节点和所述低电平端，所述松弛单元用于将所述第二节点的电压调整至所述第三设定电压。
  10. 如权利要求9所述的GOA电路，其特征在于，所述松弛单元包括第四晶体管和第七晶体管，所述第四晶体管的栅极连接所述使能输入端或所述第一节点，所述第四晶体管的源极连接所述第二节点，所述第四晶体管的漏极连接所述低电平端，所述第七晶体管的栅极连接所述松弛信号端，所述第七晶体管的源极连接所述第二节点，所述第七晶体管的漏极连接所述低电平端。
  11. 如权利要求10所述的GOA电路，其特征在于，所述复位端用于接收复位信号，所述松弛信号端用于接收松弛信号，所述使能输入信号、所述时钟信号、所述复位信号和所述松弛信号的占空比均小于或等于25％。
  12. 如权利要求1所述的GOA电路，其特征在于，本级的所述GOA单元的所述使能输入信号与前级的所述GOA单元的所述扫描脉冲信号一致。
  13. 一种阵列基板，其特征在于，包括：
    像素矩阵；和
    权利要求1-12任意一项所述的GOA电路。
  14. 如权利要求13所述的阵列基板，其特征在于，所述像素矩阵包括多行像素，每级的所述GOA单元的所述输出端用于输出所述扫描脉冲信号给所述像素矩阵的对应的一行像素，所述一行像素连接下级的所述GOA单元的所述使能输入端。
  15. 一种显示装置，其特征在于，包括如权利要求13或14所述的阵列基板。
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