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WO2018120731A1 - Manufacturing method for silicon epitaxial wafer - Google Patents

Manufacturing method for silicon epitaxial wafer Download PDF

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Publication number
WO2018120731A1
WO2018120731A1 PCT/CN2017/091796 CN2017091796W WO2018120731A1 WO 2018120731 A1 WO2018120731 A1 WO 2018120731A1 CN 2017091796 W CN2017091796 W CN 2017091796W WO 2018120731 A1 WO2018120731 A1 WO 2018120731A1
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Prior art keywords
layer
growth
silicon
flow rate
slm
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PCT/CN2017/091796
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French (fr)
Chinese (zh)
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刘勇
金龙
谭卫东
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南京国盛电子有限公司
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the invention relates to a silicon epitaxial wafer, that is, a method for manufacturing an ultrathin layer low resistance epitaxial wafer.
  • the monolithic atmospheric pressure epitaxial device with SiHCl 3 as the silicon source tends to have a growth rate of more than 2 ⁇ m/min, while for the 8-inch ultra-thin layer epitaxy with an epitaxial layer thickness of less than 2 ⁇ m, the faster growth rate leads to poor uniformity of the epitaxial layer thickness.
  • the transition region between the epitaxial layer and the substrate is wider, which reduces the effective thickness of the epitaxial layer and cannot meet the requirements of the device end (the theoretical longitudinal resistivity distribution of the device end requirement is shown in FIG. 2).
  • thin layer epitaxy of less than 2 ⁇ m for 8-inch silicon epitaxial products often uses decompression epitaxy or replacement of other silicon sources such as silane (SiH 4 ), which requires additional production costs and reduces the compatibility of atmospheric pressure epitaxy equipment.
  • SiH 4 silane
  • the invention proposes a novel manufacturing method of the epitaxial wafer, which can be optimized compared with the conventional epitaxial method.
  • Epitaxial layer thickness and resistivity uniformity optimize the transition region width of the substrate and epitaxial layer.
  • the present invention can adopt the following technical solutions:
  • a method for manufacturing a silicon epitaxial wafer comprising the steps of:
  • First layer epitaxial growth an intrinsic layer is grown on the surface of the substrate to encapsulate the surface of the substrate;
  • Second layer epitaxial growth When the second layer is epitaxially grown, HCl and TCS are simultaneously introduced, wherein 0.5-1 slm of HCl, 2-5 g of TCS, and 120-180 slm of H2 are introduced.
  • the method for fabricating the epitaxial wafer of the present invention can optimize the thickness and resistivity uniformity of the 8-inch ultra-thin epitaxial layer and optimize the transition region width of the substrate and the epitaxial layer as compared with the conventional epitaxial method.
  • HCl and TCS are simultaneously introduced during the epitaxial growth of the two layers, in order to reduce the growth thickness of the epitaxial layer and suppress the self-doping effect of the silicon wafer, which plays a key role in achieving the above technical effects.
  • the susceptor is cooled to 850 °C.
  • the baking temperature is 1150-1180 ° C
  • the baking time is 40 seconds
  • the H 2 flow rate is 120-180 slm.
  • the appropriate epitaxial conditions for the first layer epitaxial growth are: baking temperature 1150-1180 ° C, baking main H 2 flow rate is 120-180 slm; first layer epitaxy, growth temperature 1100-1130 ° C, precipitation The product rate is 0.8-1.0 ⁇ m/min; when the second layer is epitaxially grown, the temperature is 1100-1130 ° C, and the deposition rate is 0.4-0.6 ⁇ m/min.
  • the first layer is epitaxially grown without doping
  • the second layer is doped epitaxially grown with an H2 flow rate of 120-180 slm.
  • the deposition is selected to be: a growth temperature of 1100-1130 ° C, a growth silicon source flow rate of 2-5 g, a growth HCl flow rate of 0.5-1 slm, and a growth main H 2 flow rate of 120-180 slm.
  • the substrate sheet is selected: an 8-inch heavy-doped phosphorus-silicon polished sheet is used, the resistivity is ⁇ 0.001 ⁇ cm, the partial flatness of the substrate sheet is ⁇ 1.5 m (10 mm ⁇ 10 mm); the silicon dioxide back sealing layer (LTO) ) + Polysilicon back seal (Poly) back seal.
  • LTO silicon dioxide back sealing layer
  • Poly Polysilicon back seal
  • Figure 1 is a process flow diagram of an 8-inch thin layer epitaxy
  • FIG. 2 is a schematic view showing the longitudinal structure of an 8-inch thin layer epitaxial layer
  • Figure 3 is a structural diagram of the ASM E2000 reaction chamber
  • Figure 4 shows the measured longitudinal carrier distribution of an 8-inch thin-layer epitaxial layer.
  • the invention discloses a method for manufacturing an epitaxial wafer, which is preferably suitable for the manufacture of an 8-inch ultra-thin layer low-resistance epitaxial wafer.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the manufacturing method of an 8-inch ultra-thin layer low-resistance epitaxial wafer of this embodiment comprises the following steps:
  • the device used in the invention is the American ASM E2000 silicon epitaxial growth system. As shown in FIG. 3, the high-purity graphite base is used as the infrared heating body, and the purity of the main carrier gas H2 is 99.9999% or more.
  • Reaction chamber cleaning The quartz bell and the quartz parts used in the reaction chamber must be carefully cleaned before the epitaxy to completely remove the deposition residue on the inner wall of the quartz bell jar and the quartz piece.
  • the first step high temperature treatment of the reaction chamber: before each epitaxial growth, the graphite pedestal must be subjected to high temperature treatment of HC1 to remove residual reactants on the susceptor and deposit a layer of intrinsic polycrystalline silicon.
  • the second step cooling the reaction chamber to a low temperature (850 ° C), loading the substrate wafer.
  • the third step heating to 1150 ° C, H 2 flow 100slm, and holding for 30 seconds for wafer baking, reducing epitaxial layer defects.
  • the fourth step the first intrinsic epitaxial layer, 1100 ° C, 2 g of silicon source, 120 slm of main H2, deposition rate of 0.8 ⁇ m / min, growth time of 7 seconds.
  • Step 5 The temperature is set to 1100 ° C, H 2 is 120 slm, and the blow is performed for 10 seconds.
  • the sixth step the second layer growth temperature is 1100 ° C, the HCl flow rate is 0.5 slm, and the silicon source is 2 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 120 slm, and the deposition rate is 0.4-0.6 ⁇ m/min. The growth time is 82 seconds.
  • the first three steps are the same as those described in the first embodiment.
  • the fourth step the first intrinsic epitaxial layer, 1120 ° C, 3 g of silicon source, 150 slm of main H2, deposition rate of 0.8 ⁇ m / min, growth time of 7 seconds.
  • Step 5 The temperature is set to 1130 ° C, H 2 is 150 slm, and the blow is performed for 90 seconds.
  • the sixth step the second layer growth temperature is 1120 ° C, the HCl flow rate is 0.8 slm, and the silicon source is 3 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 150 slm, and the deposition rate is 0.4-0.6 ⁇ m/min. The growth time is 82 seconds.
  • the first three steps are the same as those described in the first embodiment.
  • the fourth step the first intrinsic epitaxial layer, 1130 ° C, 5 g of silicon source, 180 slm of main H2, deposition rate of 0.8 ⁇ m / min, growth time of 7 seconds.
  • Step 5 The temperature is set to 1150 ° C, H 2 is 120 slm, and the blow is performed for 120 seconds.
  • the sixth step the second layer growth temperature is 1130 ° C, the HCl flow rate is 1 slm, and the silicon source is 5 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 180 slm, and the deposition rate is 0.4-0.6 ⁇ m/min. The growth time is 82 seconds.
  • the prepared silicon epitaxial wafer After testing the silicon epitaxial wafer manufactured by the methods of Embodiments 1, 2 and 3, the prepared silicon epitaxial wafer has a good lattice structure, the surface is bright and has no fine spots, no warping and edge crystallization, and enters the gas phase. The impurity is less, the self-doping effect is reduced, the dislocation is ⁇ 100/cm 2 , and the stacking fault is ⁇ 10/cm 2 .
  • the epitaxial thickness is less than 0.7 ⁇ m
  • the epitaxial transition region is less than 0.2 ⁇ m
  • the longitudinal resistivity distribution diagram is as shown in the figure. 4, fully meet the requirements of device fabrication.

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Abstract

Disclosed is a manufacturing method for a silicon epitaxial wafer, comprising the following technical process: First, a monolithic atmospheric-pressure silicon epitaxy apparatus is used and a suitable H2 flow rate, temperature, and time are selected to conduct baking treatment on a substrate silicon wafer to remove a natural oxide layer on the surface and ensure the quality of the surface before epitaxy. A first layer is epitaxially grown: an undoped intrinsic layer is grown on the surface of the heavily doped substrate to encapsulate the substrate surface, and the growth temperature, growth rate, and growth time of the intrinsic layer are controlled to achieve a desirable encapsulation effect. A second layer is epitaxially grown: SiHCl3 is used as a silicon source, the flow rate of main H2 is increased, and HCl fed at a suitable flow rate, so as to reduce the growth rate to grow a thinner epitaxial layer having a thickness meeting a requirement for a device.

Description

一种硅外延片的制造方法Method for manufacturing silicon epitaxial wafer 技术领域Technical field
本发明涉及硅外延片，即一种超薄层低阻外延片的制造方法。The invention relates to a silicon epitaxial wafer, that is, a method for manufacturing an ultrathin layer low resistance epitaxial wafer.
背景技术Background technique
以SiHCl3为硅源的单片常压外延设备，其生长速率往往大于2μm/min，而针对外延层厚度小于2μm的8英寸超薄层外延，其较快的生长速率导致外延层厚度均匀性差，外延层和衬底的过渡区较宽，减少了外延层的有效厚度，无法满足器件端的需求(器件端需求的理论纵向电阻率分布图如图2所示)。目前针对8英寸硅外延产品小于2μm的薄层外延常采用减压外延或更换其它硅源如硅烷(SiH4)，这些都需要额外增加生产成本，同时降低了常压外延设备的兼容性。The monolithic atmospheric pressure epitaxial device with SiHCl 3 as the silicon source tends to have a growth rate of more than 2 μm/min, while for the 8-inch ultra-thin layer epitaxy with an epitaxial layer thickness of less than 2 μm, the faster growth rate leads to poor uniformity of the epitaxial layer thickness. The transition region between the epitaxial layer and the substrate is wider, which reduces the effective thickness of the epitaxial layer and cannot meet the requirements of the device end (the theoretical longitudinal resistivity distribution of the device end requirement is shown in FIG. 2). At present, thin layer epitaxy of less than 2 μm for 8-inch silicon epitaxial products often uses decompression epitaxy or replacement of other silicon sources such as silane (SiH 4 ), which requires additional production costs and reduces the compatibility of atmospheric pressure epitaxy equipment.
综上所述，有必要设计一种针对微型液压驱动系统的快速高精度的控制方法。In summary, it is necessary to design a fast and highly accurate control method for the micro hydraulic drive system.
发明内容Summary of the invention
针对现有技术中存在的问题,依据外延工艺自掺杂效应的产生机理、抑制方法以及固态扩散理论，本发明提出了一种新型的外延片的制造方法,与常规外延方法相比较，能够优化外延层厚度和电阻率均匀性,优化衬底和外延层的过渡区宽度。Aiming at the problems existing in the prior art, according to the generation mechanism, the suppression method and the solid state diffusion theory of the epitaxial process self-doping effect, the invention proposes a novel manufacturing method of the epitaxial wafer, which can be optimized compared with the conventional epitaxial method. Epitaxial layer thickness and resistivity uniformity optimize the transition region width of the substrate and epitaxial layer.
为达到上述目的，本发明可采用如下技术方案：In order to achieve the above object, the present invention can adopt the following technical solutions:
一种硅外延片的制造方法,包括以下步骤：A method for manufacturing a silicon epitaxial wafer, comprising the steps of:
(1)、对基座进行HC1高温处理，去除基座上残余的反应物，并淀积一层本征多晶硅；(1) performing high temperature treatment of the susceptor on the susceptor, removing residual reactants on the susceptor, and depositing a layer of intrinsic polysilicon;
(2)、冷却基座后载入衬底硅片(2) loading the substrate wafer after cooling the pedestal
(3)、进行硅片烘烤(3), wafer baking
(4)、第一层外延生长：在衬底表面生长一层本征层，对衬底表面进行包封；(4) First layer epitaxial growth: an intrinsic layer is grown on the surface of the substrate to encapsulate the surface of the substrate;
(5)、第二层外延生长：第二层外延生长时将HCl和TCS同时通入，其中通入0.5-1slm流量的HCl、2-5g流量的TCS和120-180slm流量的H2。(5) Second layer epitaxial growth: When the second layer is epitaxially grown, HCl and TCS are simultaneously introduced, wherein 0.5-1 slm of HCl, 2-5 g of TCS, and 120-180 slm of H2 are introduced.
有益效果：本发明的外延片的制造方法,与常规外延方法相比较，能够优化8英寸超薄外延层厚度和电阻率均匀性,优化衬底和外延层的过渡区宽度。尤其是在二层外延生长时将HCl和TCS同时通入，目的是为了降低外延层的生长厚度和抑制硅片的自掺杂效应，对达到上述技术效果起到了关键的作用。Advantageous Effects: The method for fabricating the epitaxial wafer of the present invention can optimize the thickness and resistivity uniformity of the 8-inch ultra-thin epitaxial layer and optimize the transition region width of the substrate and the epitaxial layer as compared with the conventional epitaxial method. In particular, HCl and TCS are simultaneously introduced during the epitaxial growth of the two layers, in order to reduce the growth thickness of the epitaxial layer and suppress the self-doping effect of the silicon wafer, which plays a key role in achieving the above technical effects.
优选的，步骤(2)中，冷却基座至850℃。Preferably, in step (2), the susceptor is cooled to 850 °C.
优选的，步骤(3)中，烘烤温度1150-1180℃，烘烤的时间40秒，烘烤H2 流量120-180slm。Preferably, in the step (3), the baking temperature is 1150-1180 ° C, the baking time is 40 seconds, and the H 2 flow rate is 120-180 slm.
优选的，其特征在于第一层外延生长时选择合适的外延条件是:烘烤温度1150-1180℃，烘烤主H2流量为120-180slm；第一层外延，生长温度1100-1130℃，淀积速率在0.8-1.0μm/min；第二层外延生长时，温度为1100-1130℃，淀积速率在0.4-0.6μm/min。Preferably, it is characterized in that the appropriate epitaxial conditions for the first layer epitaxial growth are: baking temperature 1150-1180 ° C, baking main H 2 flow rate is 120-180 slm; first layer epitaxy, growth temperature 1100-1130 ° C, precipitation The product rate is 0.8-1.0 μm/min; when the second layer is epitaxially grown, the temperature is 1100-1130 ° C, and the deposition rate is 0.4-0.6 μm/min.
优选的，第一层外延生长时不加掺杂，第二层掺杂外延生长时H2流量为120-180slm。Preferably, the first layer is epitaxially grown without doping, and the second layer is doped epitaxially grown with an H2 flow rate of 120-180 slm.
优选的，淀积选择为：生长温度1100-1130℃，生长硅源流量2-5g，生长时HCl流量0.5-1slm，生长主H2流量120-180slm。Preferably, the deposition is selected to be: a growth temperature of 1100-1130 ° C, a growth silicon source flow rate of 2-5 g, a growth HCl flow rate of 0.5-1 slm, and a growth main H 2 flow rate of 120-180 slm.
优选的，衬底片的选择:使用8英寸重掺磷硅抛光片,电阻率≤0.001Ω·cm，该衬底片局部平整度≤l.5m(10mm×10mm)；二氧化硅背封层(LTO)+多晶硅背封层(Poly)背封。Preferably, the substrate sheet is selected: an 8-inch heavy-doped phosphorus-silicon polished sheet is used, the resistivity is ≤0.001 Ω·cm, the partial flatness of the substrate sheet is ≤1.5 m (10 mm×10 mm); the silicon dioxide back sealing layer (LTO) ) + Polysilicon back seal (Poly) back seal.
附图说明DRAWINGS
图1为8寸薄层外延的工艺流程图；Figure 1 is a process flow diagram of an 8-inch thin layer epitaxy;
图2为8寸薄层外延层纵向结构示意图；2 is a schematic view showing the longitudinal structure of an 8-inch thin layer epitaxial layer;
图3为ASM E2000反应室结构图；Figure 3 is a structural diagram of the ASM E2000 reaction chamber;
图4为8寸薄层外延层实测纵向载流子分布图。Figure 4 shows the measured longitudinal carrier distribution of an 8-inch thin-layer epitaxial layer.
具体实施方式detailed description
本发明公开了一种外延片的制造方法，优选的适用于8英寸超薄层低阻外延片的制造。The invention discloses a method for manufacturing an epitaxial wafer, which is preferably suitable for the manufacture of an 8-inch ultra-thin layer low-resistance epitaxial wafer.
实施例一：Embodiment 1:
本实施例的一种8英寸超薄层低阻外延片的制造方法包括如下步骤：The manufacturing method of an 8-inch ultra-thin layer low-resistance epitaxial wafer of this embodiment comprises the following steps:
本发明采用设备为美国ASM E2000硅外延生长系统，如图3所示，高纯石墨基座作为红外加热体，主要载气H2纯度为99.9999％以上。The device used in the invention is the American ASM E2000 silicon epitaxial growth system. As shown in FIG. 3, the high-purity graphite base is used as the infrared heating body, and the purity of the main carrier gas H2 is 99.9999% or more.
反应室清洗：石英钟罩以及反应室中使用的石英零件在进行外延前必须仔细清洗，彻底清除石英钟罩内壁和石英件上的淀积残留物。Reaction chamber cleaning: The quartz bell and the quartz parts used in the reaction chamber must be carefully cleaned before the epitaxy to completely remove the deposition residue on the inner wall of the quartz bell jar and the quartz piece.
第一步：反应室高温处理：每次外延生长之前，石墨基座必须进行HC1高温处理，去除基座上残余的反应物，并淀积一层本征多晶硅。The first step: high temperature treatment of the reaction chamber: before each epitaxial growth, the graphite pedestal must be subjected to high temperature treatment of HC1 to remove residual reactants on the susceptor and deposit a layer of intrinsic polycrystalline silicon.
第二步：冷却反应腔至低温(850℃)，载入衬底硅片。The second step: cooling the reaction chamber to a low temperature (850 ° C), loading the substrate wafer.
第三步：升温至1150℃，H2流量100slm，并保持30秒进行硅片烘烤，减少外延层缺陷。 The third step: heating to 1150 ° C, H 2 flow 100slm, and holding for 30 seconds for wafer baking, reducing epitaxial layer defects.
第四步：第一层本征外延层，1100℃，硅源2g，主H2为120slm，淀积速率在0.8μm/min，生长时间7秒。The fourth step: the first intrinsic epitaxial layer, 1100 ° C, 2 g of silicon source, 120 slm of main H2, deposition rate of 0.8 μm / min, growth time of 7 seconds.
第五步：温度设定1100℃，H2为120slm，保持10秒进行吹除。Step 5: The temperature is set to 1100 ° C, H 2 is 120 slm, and the blow is performed for 10 seconds.
第六步：第二层生长温度1100℃，HCl流量为0.5slm，硅源2g，此时将HCl和硅源同时通入进行生长，主H2为120slm，淀积速率在0.4-0.6μm/min，生长时间82秒。The sixth step: the second layer growth temperature is 1100 ° C, the HCl flow rate is 0.5 slm, and the silicon source is 2 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 120 slm, and the deposition rate is 0.4-0.6 μm/min. The growth time is 82 seconds.
实施例二Embodiment 2
前三步同实施例一所述。The first three steps are the same as those described in the first embodiment.
第四步：第一层本征外延层，1120℃，硅源3g，主H2为150slm，淀积速率在0.8μm/min，生长时间7秒。The fourth step: the first intrinsic epitaxial layer, 1120 ° C, 3 g of silicon source, 150 slm of main H2, deposition rate of 0.8 μm / min, growth time of 7 seconds.
第五步：温度设定1130℃，H2为150slm，保持90秒进行吹除。Step 5: The temperature is set to 1130 ° C, H 2 is 150 slm, and the blow is performed for 90 seconds.
第六步：第二层生长温度1120℃，HCl流量为0.8slm，硅源3g，此时将HCl和硅源同时通入进行生长，主H2为150slm，淀积速率在0.4-0.6μm/min，生长时间82秒。The sixth step: the second layer growth temperature is 1120 ° C, the HCl flow rate is 0.8 slm, and the silicon source is 3 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 150 slm, and the deposition rate is 0.4-0.6 μm/min. The growth time is 82 seconds.
实施例三Embodiment 3
前三步同实施例一所述。The first three steps are the same as those described in the first embodiment.
第四步：第一层本征外延层，1130℃，硅源5g，主H2为180slm，淀积速率在0.8μm/min，生长时间7秒。The fourth step: the first intrinsic epitaxial layer, 1130 ° C, 5 g of silicon source, 180 slm of main H2, deposition rate of 0.8 μm / min, growth time of 7 seconds.
第五步：温度设定1150℃，H2为120slm，保持120秒进行吹除。Step 5: The temperature is set to 1150 ° C, H 2 is 120 slm, and the blow is performed for 120 seconds.
第六步：第二层生长温度1130℃，HCl流量为1slm，硅源5g，此时将HCl和硅源同时通入进行生长，主H2为180slm，淀积速率在0.4-0.6μm/min，生长时间82秒。The sixth step: the second layer growth temperature is 1130 ° C, the HCl flow rate is 1 slm, and the silicon source is 5 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 180 slm, and the deposition rate is 0.4-0.6 μm/min. The growth time is 82 seconds.
以上的操作步骤见附图1。The above operation steps are shown in Figure 1.
经过对通过实施例一、二、三的方法制造的硅外延片进行测试可得，所制作的硅外延片晶格结构完好，表面光亮无细亮点，无翘边和边缘结晶现象，同时进入气相的杂质少，减小了自掺杂效应，位错＜100/cm2，层错＜10/cm2，在外延厚度小于0.7μm时，外延过渡区小于0.2μm，纵向电阻率分布图如图4所示，完全满足器件制作的要求。After testing the silicon epitaxial wafer manufactured by the methods of Embodiments 1, 2 and 3, the prepared silicon epitaxial wafer has a good lattice structure, the surface is bright and has no fine spots, no warping and edge crystallization, and enters the gas phase. The impurity is less, the self-doping effect is reduced, the dislocation is <100/cm 2 , and the stacking fault is <10/cm 2 . When the epitaxial thickness is less than 0.7 μm, the epitaxial transition region is less than 0.2 μm, and the longitudinal resistivity distribution diagram is as shown in the figure. 4, fully meet the requirements of device fabrication.
本发明具体实现该技术方案的方法和途径很多，以上所述仅是本发明的优选实施方式。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原 理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。本实施例中未明确的各组成部分均可用现有技术加以实现。 There are many ways and means for implementing the technical solution of the present invention, and the above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art will not deviate from the original invention. Under the premise of the rationale, a number of improvements and refinements can also be made, and these improvements and retouchings should also be considered as protection scope of the present invention. The components that are not clear in this embodiment can be implemented by the prior art.

Claims (7)

  1. 一种硅外延片的制造方法,其特征在于，包括以下步骤：A method for manufacturing a silicon epitaxial wafer, comprising the steps of:
    (1)、对基座进行HC1高温处理，去除基座上残余的反应物，并淀积一层本征多晶硅；(1) performing high temperature treatment of the susceptor on the susceptor, removing residual reactants on the susceptor, and depositing a layer of intrinsic polysilicon;
    (2)、冷却基座后载入衬底硅片(2) loading the substrate wafer after cooling the pedestal
    (3)、进行硅片烘烤(3), wafer baking
    (4)、第一层外延生长：在衬底表面生长一层本征层，对衬底表面进行包封；(4) First layer epitaxial growth: an intrinsic layer is grown on the surface of the substrate to encapsulate the surface of the substrate;
    (5)、第二层外延生长：第二层外延生长时将HCl和TCS同时通入，其中通入0.5-1slm流量的HCl、2-5g流量的TCS和120-180slm流量的H2。(5) Second layer epitaxial growth: When the second layer is epitaxially grown, HCl and TCS are simultaneously introduced, wherein 0.5-1 slm of HCl, 2-5 g of TCS, and 120-180 slm of H2 are introduced.
  2. 根据权利要求1所述的硅外延片的制造方法，其特征在于，步骤(2)中，冷却基座至850℃。The method of manufacturing a silicon epitaxial wafer according to claim 1, wherein in the step (2), the susceptor is cooled to 850 °C.
  3. 根据权利要求1所述的硅外延片的制造方法，其特征在于，步骤(3)中，烘烤温度1150-1180℃，烘烤的时间40秒，烘烤H2流量120-180slm。The method of manufacturing a silicon epitaxial wafer according to claim 1, wherein in the step (3), the baking temperature is 1150-1180 ° C, the baking time is 40 seconds, and the H 2 flow rate is 120-180 slm.
  4. 根据权利要求1或2或3所述的硅外延片的制造方法，其特征在于第一层外延生长时选择合适的外延条件是:烘烤温度1150-1180℃，烘烤主H2流量为120-180slm；第一层外延，生长温度1100-1130℃，淀积速率在0.8-1.0μm/min；第二层外延生长时，温度为1100-1130℃，淀积速率在0.4-0.6μm/min。The method for fabricating a silicon epitaxial wafer according to claim 1 or 2 or 3, wherein the epitaxial growth condition of the first layer is selected to be: a baking temperature of 1150-1180 ° C, and a baking main H 2 flow rate of 120 - 180slm; first layer epitaxy, growth temperature 1100-1130 ° C, deposition rate of 0.8-1.0 μm / min; second layer epitaxial growth, temperature of 1100-1130 ° C, deposition rate of 0.4-0.6 μm / min.
  5. 根据权利要求4所述的硅外延片的制造方法，其特征在于第一层外延生长时不加掺杂，第二层掺杂外延生长时H2流量为120-180slm。The method of manufacturing a silicon epitaxial wafer according to claim 4, wherein the first layer is epitaxially grown without doping, and the second layer is doped epitaxially grown with an H2 flow rate of 120-180 slm.
  6. 根据权利要求4所述的硅外延片的制造方法，其特征在于淀积选择为：生长温度1100-1130℃，生长硅源流量2-5g，生长时HCl流量0.5-1slm，生长主H2流量120-180slm。The method for fabricating a silicon epitaxial wafer according to claim 4, wherein the deposition is selected by a growth temperature of 1100-1130 ° C, a growth silicon source flow rate of 2-5 g, a growth HCl flow rate of 0.5-1 slm, and a growth main H 2 flow rate. 120-180slm.
  7. 根据权利要求1所述的硅外延片的制造方法，其特征在于衬底片的选择:使用8英寸重掺磷硅抛光片,电阻率≤0.001Ω·cm，该衬底片局部平整度≤l.5m(10mm×10mm)，二氧化硅背封层+多晶硅背封层背封。 The method for fabricating a silicon epitaxial wafer according to claim 1, wherein the substrate sheet is selected by using an 8-inch heavy-doped phosphorus-silicon polished sheet, the resistivity is ≤0.001 Ω·cm, and the partial flatness of the substrate sheet is ≤1.5 m. (10mm × 10mm), silicon dioxide back sealing layer + polysilicon back sealing layer back sealing.
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