WO2018186313A1

WO2018186313A1 - Silicon carbide semiconductor device

Info

Publication number: WO2018186313A1
Application number: PCT/JP2018/013935
Authority: WO
Inventors: 友生森野; 永岡　達司; 一平高橋
Original assignee: 株式会社デンソー; トヨタ自動車株式会社
Priority date: 2017-04-04
Filing date: 2018-03-30
Publication date: 2018-10-11
Also published as: JP2018181917A

Abstract

According to the present invention, an on-resistance Ron(SBD) of an SBD (10) and an on-resistance Ron(PND) of a PN diode are set so that the relationship Ron(SBD) × 105 < Ron(PND) is satisfied in a contact between a Schottky electrode (4) and a second conductive layer (11) or a drift layer (2). In addition, the contact between the outer surface of the second conductive layer (11) and the Schottky electrode (4) is configured to not enter an insulated state.

Description

Silicon carbide semiconductor device

Cross-reference to related applications

This application is based on Japanese Patent Application No. 2017-74624 filed on April 4, 2017, the contents of which are incorporated herein by reference.

The present disclosure relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a junction barrier Schottky diode (hereinafter referred to as JBS) in which a PN diode is added to a Schottky barrier diode (hereinafter referred to as SBD).

Conventionally, in Patent Document 1, an SiC semiconductor device having JBS in which a PN diode is further added to SBD has been proposed. In this SiC semiconductor device, an SBD is formed by forming a Schottky electrode on the surface of an n ⁻ type epitaxial layer made of SiC. In addition, a PN diode is configured by forming a p-type layer in the surface layer portion of the n ⁻ -type epitaxial layer and bringing a Schottky electrode into ohmic contact with the surface of the p-type layer. With such a structure, a SiC semiconductor device having JBS in which a PN diode is further added to SBD is configured. By adopting such a configuration, a reverse leakage current is suppressed and a high breakdown voltage can be obtained by a depletion layer formed at a PN junction constituting the PN diode. When the SBD is operated in the forward direction, the PN diode is also operated in the forward direction through the p-type layer that is in ohmic contact with the Schottky electrode.

Also, conventionally, in a SiC semiconductor device having JBS, a structure in which a p-type layer constituting a PN diode is brought into contact with a Schottky electrode in an insulating state has been proposed. In this SiC semiconductor device, crystal defects are included in the p-type layer that is brought into contact with the Schottky electrode in an insulating state. In this way, by causing the p-type layer to be in contact with the Schottky electrode in an insulated state so that the crystal defect is included in the p-type layer, the influence of the crystal defect can be suppressed, and the characteristics of the SiC semiconductor device can be improved. It becomes possible to make it good.

JP 2010-50267 A

However, when the p-type layer for forming the PN diode is in ohmic contact with the Schottky electrode, since the PN diode is a bipolar device, a sudden hole deficiency occurs during reverse recovery. As a result, the recovery current rises sharply and the recovery current change amount dir / dt increases. For this reason, the surge voltage ΔV (= L · dir / dt) determined by the product of the reactance L of the entire circuit and the amount of change dir / dt of the recovery current increases, and a large surge is generated during reverse recovery.

Also, in the case where the p-type layer is in contact with the Schottky electrode in an insulating state, the depletion layer spreading around the p-type layer does not return at the time of reverse bias, and the on-resistance is deteriorated.

This disclosure is intended to provide a SiC semiconductor device having a JBS that can suppress a surge during reverse recovery and can suppress deterioration of on-resistance.

An SiC semiconductor device according to one aspect of the present disclosure includes a first conductivity type substrate made of SiC having a main surface and a back surface, and a first conductivity type substrate formed on the main surface and having a lower impurity concentration than the substrate. A drift layer made of SiC, an insulating film disposed on the drift layer and having a cell portion as an opening, and formed in the cell portion, and brought into Schottky contact with the surface of the drift layer through the opening of the insulating film. A plurality of second conductivity type layers formed on the surface layer portion of the drift layer and in contact with the Schottky electrode and arranged apart from each other. And an SBD having a Schottky electrode, a drift layer, a substrate, and an ohmic electrode, and a plurality of second conductivity type layers and drift layers. By de is configured, JBS is configured. In such a configuration, the on-resistance Ron (SBD) of the SBD and the on-resistance Ron (PND) of the PN diode satisfy a relationship of Ron (SBD) × 10 ⁵ <Ron (PND).

Thus, since the relationship of Ron (SBD) × 10 ⁵ <Ron (PND) is satisfied, the rise of the recovery current can be moderated and the change amount dir / dt of the recovery current can be reduced. For this reason, the effect that generation | occurrence | production of the surge at the time of reverse recovery is suppressed is acquired.

In the SiC semiconductor device according to another aspect of the present disclosure, the specific resistance of the second conductivity type layer is 1 Ωcm or less. Thus, when the specific resistance of the second conductivity type layer is 1 Ωcm or less, the contact between the surface of the second conductivity type layer and the Schottky electrode can be prevented from being in an insulating state. As a result, the depletion layer that has spread at the time of reverse bias can be returned and reduced, and an effect of suppressing deterioration of the on-resistance can be obtained.

Note that reference numerals with parentheses attached to each component and the like indicate an example of a correspondence relationship between the component and the like and specific components described in the embodiments described later.

It is sectional drawing of the SiC semiconductor device provided with JBS concerning 1st Embodiment. FIG. 2 is a top surface layout diagram of the SiC semiconductor device shown in FIG. 1. It is the circuit diagram of the model used for the operation simulation of a SiC semiconductor device. It is the figure which showed the change of the voltage and electric current between both ends of SW1, SW2, or JBS connected in parallel when SW1 and SW2 are switched on and off. It is sectional drawing which showed the state of the carrier in a PN diode. It is sectional drawing which showed the state of the carrier in a PN diode. It is sectional drawing which showed the state of the carrier in a PN diode. It is sectional drawing which showed the state of the carrier in a PN diode. It is the figure which showed the waveform of electric current [A] with respect to voltage [V] when a forward current flows into JBS. It is sectional drawing which showed the state of the depletion layer extended at the time of reverse bias in case a p-type layer will be in an insulation state. It is sectional drawing which showed the state of the depletion layer extended at the time of reverse bias when a p-type layer does not become an insulation state.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present disclosure will be described. First, the structure of the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 1 corresponds to a cross-sectional view taken along the line II in FIG. 2 and FIG. Further, FIG. 2 is not a cross-sectional view, but is partially hatched for easy understanding of the drawing.

As shown in FIG. 1, the SiC semiconductor device is formed using an n ⁺ type substrate 1 made of SiC. The n ⁺ type substrate 1 has an impurity concentration of about 2 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , for example. When the upper surface of the n ⁺ type substrate 1 is the main surface 1a and the lower surface opposite to the main surface 1a is the back surface 1b, the main surface 1a is made of SiC having a lower dopant concentration than the n ⁺ type substrate 1. An n ⁻ type epitaxial layer 2 corresponding to the drift layer is stacked. The n ⁻ type epitaxial layer 2 has an impurity concentration of, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . The JBS having the SBD 10 and the PN diode is formed in the cell portion of the SiC semiconductor substrate constituted by the n ⁺ type substrate 1 and the n ⁻ type epitaxial layer 2, and the termination structure is formed in the outer peripheral region. An SiC semiconductor device is configured.

Specifically, as the n ⁺ type substrate 1, a SiC substrate having a main surface 1a having an off angle with respect to the (0001) plane is used. In the present embodiment, as shown in FIG. 2, the off direction is the (11-20) direction, and an SiC substrate having an off angle of 4 °, for example, is used as the n ⁺ type substrate 1. An n ⁻ type epitaxial layer 2 is formed thereon by epitaxial growth, and the n ⁻ type epitaxial layer 2 is also a crystal whose (11-20) direction is the off direction.

On the surface of the n ⁻ type epitaxial layer 2, an insulating film 3 made of, for example, a silicon oxide film is formed. In the insulating film 3, an opening 3a is partially formed in the cell portion, and a Schottky electrode 4 in contact with the n ⁻ type epitaxial layer 2 is formed in the opening 3a of the insulating film 3. . The Schottky electrode 4 is made of a metal material that is in Schottky contact with the n ⁻ -type epitaxial layer 2 and that does not contact with a p-type layer 11 constituting a PN diode described later. Here, the Schottky electrode 4 is made of, for example, Mo (molybdenum).

An ohmic electrode 5 is formed so as to be in contact with the back surface of the n ⁺ type substrate 1. The ohmic electrode 5 is also formed by a laminated structure of a plurality of layers, and is constituted by, for example, a Ni silicide layer, a Ti layer, a Ni layer, and an Au layer in order from the n ⁺ type substrate 1 side.

Thus, the cell structure of the SBD 10 is configured. Any layout may be used for the top surface of the SBD 10, but in the present embodiment, each corner is rounded as shown in FIG.

As a termination structure formed in the outer peripheral region of the SBD 10, a p-type RESURF layer 6 is formed on the surface layer portion of the n ⁻ -type epitaxial layer 2 at the outer edge portion of the Schottky electrode 4 so as to be in contact with the Schottky electrode 4. ing. A plurality of p-type guard ring layers 7 are arranged so as to further surround the outer periphery of the p-type RESURF layer 6. The p-type RESURF layer 6 and the p-type guard ring layer 7 form a termination structure. The p-type RESURF layer 6 and the p-type guard ring layer 7 are formed using, for example, Al as an impurity. For example, the p-type RESURF layer 6 and the p-type guard ring layer 7 are formed with an impurity concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^−3. Yes. By disposing the p-type RESURF layer 6 and the p-type guard ring layer 7, the electric field can extend over a wide range on the outer periphery of the SBD 10, and the electric field concentration can be reduced. For this reason, a proof pressure can be improved. With such a structure, the SBD 10 is configured.

Note that a surface electrode structure 8 in which a bonding electrode 8a serving as a barrier layer, a surface electrode 8b for external connection, a plating layer 8c, and the like are sequentially laminated on the surface of the Schottky electrode 4 is configured. For example, the bonding electrode 8a is Ti (titanium), the surface electrode 8b is Al—Si / TiN (arsili / titanium nitride), and the plating layer 8c is a film in which an Au (gold) layer is laminated on a Ni (nickel) layer. Thus, the surface electrode structure 8 is configured. By forming such a surface electrode structure 8, it is possible to satisfactorily connect to a bonding wire or the like, and electrical connection between the SBD 10 and the outside can be achieved. Moreover, the surface protection of the SBD 10 is performed by providing a protective film 9 made of PIQ (polyimide) or the like so as to surround the surface electrode structure 8.

Further, the portion formed in the surface layer portion of the n ⁻ -type epitaxial layer 2 and further on the inner side than the inner end portion of the p-type RESURF layer 6 located closest to the cell portion among the portions constituting the termination structure and shot A p-type layer 11 configured to be in contact with the key electrode 4 is formed. As shown in FIG. 2, the p-type layer 11 has a stripe shape in which a plurality of strips having the same direction as the off direction as the longitudinal direction are arranged in the (1-100) direction. As shown in FIG. 1, the p-type layers 11 are arranged so that the p-type layers 11 are spaced at equal intervals so as to be arranged symmetrically with respect to the center of the cell portion. The layer 11 has the same width. Such a p-type layer 11 is configured with an impurity concentration at which the specific resistance is 1 Ωcm or less, for example. The interval between the p-type layers 11 is, for example, 2.0 ± 1.0 μm. The width of each p-type layer 11 is, for example, not less than 0.1 μm and not more than 3 μm. Further, the depth of each p-type layer 11 is, for example, not less than 0.3 μm and not more than 1.0 μm.

The p-type layer 11 thus configured forms a PN diode with the n ⁻ -type epitaxial layer 2. The contact between the surface of the p-type layer 11 and the Schottky electrode 4 is not brought into an insulating state based on the adjustment of the specific resistance of the p-type layer 11. The contact between the Schottky electrode 4 and the p-type layer 11 or the n ⁻ -type epitaxial layer 2 is such that the on-resistance Ron (SBD) at the SBD 10 and the on-resistance Ron (PND) at the PN diode are Ron (SBD). It is set to satisfy the relationship of × 10 ⁵ <Ron (PND). For example, the material of the Schottky electrode 4 is selected, the specific resistance is adjusted based on the impurity concentration of the p-type layer 11, and the area between the p-type layer 11 and the n ⁻ -type epitaxial layer 2 at the contact point with the Schottky electrode 4. The above relationship is satisfied based on the ratio and the like.

Thus, a JBS provided with a PN diode in addition to the SBD 10 is configured. In the SiC semiconductor device provided with the JBS having such a structure, the Schottky electrode 4 functions as an anode and the ohmic electrode 5 functions as a cathode. Specifically, by applying a voltage exceeding the Schottky barrier to the Schottky electrode 4, a current flows between the Schottky electrode 4 and the ohmic electrode 5. In addition, since the p-type RESURF layer 6 and the p-type guard ring layer 7 are provided for the outer peripheral region, the equipotential lines can be extended over a wide range without deviation. As a result, a high breakdown voltage element can be obtained.

As described above, the relationship of Ron (SBD) × 10 ⁵ <Ron (PND) is satisfied. For this reason, the rise of the recovery current can be moderated, the amount of change dir / dt of the recovery current can be reduced, and the effect of suppressing the occurrence of surge during reverse recovery can be obtained (hereinafter referred to as effect 1). Further, the contact between the surface of the p-type layer 11 and the Schottky electrode 4 is prevented from being in an insulating state. For this reason, the depletion layer that has spread at the time of reverse bias can be returned and reduced, and an effect of suppressing deterioration of the on-resistance can be obtained (hereinafter referred to as effect 2). The reason why these

effects

1 and 2 are obtained will be described below with reference to the drawings.

First, the reason why Effect 1 is obtained will be described with reference to FIGS.

An operation simulation of the SiC semiconductor device was performed using a simulation model when the SiC semiconductor device including the JBS having the above structure was applied to a bridge circuit. FIG. 3 is a circuit diagram of a model used for the simulation. As shown in this figure, a model is used in which the JBS of this embodiment is connected in parallel to MOSFETs constituting SW1 and SW2 provided in the upper arm and the lower arm, respectively. Using this model, SW1 and SW2 were alternately switched on and off, and changes in voltage and current between both ends of SW1 and SW2 or JBS connected in parallel at that time were examined. FIG. 4 shows the result. 5A to 5D show the state of the PN diode in the JBS connected in parallel to SW1 when SW1 is switched off and SW2 is switched on.

In the model shown in FIG. 3, it is assumed that SW1 is switched from the on state to off, and at the same time, SW2 is switched from the off state to on. In this case, the voltage and current between both ends of SW1, SW2 or JBS connected in parallel to these change as shown in period t1 and period t2 in FIG. As for the polarity of the voltage and current shown in FIG. 4, the intermediate position between SW1 and SW2 is positive as shown in FIG.

When SW2 is turned on, the current gradually flows into the MOSFET that constitutes SW2, and the current gradually increases.

On the other hand, with respect to SW1, a current flows while it is on, and the voltage of SW1 becomes a low voltage value corresponding to the voltage drop corresponding to the on resistance of SW1. This region is a region where forward loss occurs as shown in FIG. When SW1 is switched from on to off, reverse recovery occurs in the PN diode of JBS connected in parallel to SW1.

Specifically, in a state in which current is normally supplied with a forward bias, as shown in FIG. 5A, electrons are supplied from the negative electrode to the n ⁻ -type epitaxial layer 2 that becomes an N-type semiconductor, and from the positive electrode, a P-type semiconductor. In this state, holes are supplied to the p-type layer 11. Furthermore, electrons and holes move due to the electric field generated by the bias from the power supply 20, and the n ⁻ type epitaxial layer 2 and the p type layer 11 are filled with carriers. Since the reverse bias is applied by switching off SW1 from this state, as shown in FIG. 5B, each carrier is caused to flow backward in the direction opposite to the direction in which the carrier was moving at the time of forward bias. For this reason, in the period t2 of FIG. 4, that is, SW1, a current in the reverse direction flows through the PN diode during the turn-off period, and the voltage of SW1 protrudes in the reverse direction as a large surge. Recovery loss occurs in this area.

Thereafter, there is no supply of carriers from the negative electrode or the positive electrode, and holes are attracted to the negative electrode and electrons are attracted to the positive electrode. Therefore, as shown in FIG. A depleted layer is formed. When the backflow of the carriers is settled, as shown in FIG. 5D, the diode is not energized by the depletion layer formed in the vicinity of the PN junction.

And during this reverse recovery time, an inrush current flows through the MOSFET constituting SW2. This is a turn-on loss. In addition, the voltage becomes a low voltage value corresponding to the voltage drop corresponding to the ON resistance of SW2, and only the steady steady loss occurs after SW2 is turned on.

When such an operation is performed, the amount of change dir / dt in the recovery current during reverse recovery, that is, the change from when the recovery current reaches the peak to zero is applied to the PN diode of the SiC semiconductor device connected in parallel to SW1. The steeper the slope, the greater the surge. For this reason, reducing the amount of change dir / dt is important for suppressing the surge.

On the other hand, in the case of the present embodiment, the relationship of Ron (SBD) × 10 ⁵ <Ron (PND) is satisfied. That is, the p-type layer 11 and the Schottky electrode 4 are connected with a high contact resistance. By doing so, the injection of holes from the p-type layer 11 is suppressed, and the forward operation is suppressed. And since there is little injection | pouring of a hole, recovery operation | movement decreases and the rise of a recovery current can be made loose. Therefore, the effect 1 that the amount of change dir / dt of the recovery current can be reduced and the occurrence of surge during reverse recovery is suppressed is obtained.

Here, the amount of holes injected is basically determined by the on-resistance Ron (SBD) of the SBD 10 and the on-resistance Ron (PND) of the PN diode. In the simulation, the result that the effect 1 is obtained satisfactorily is obtained in a range satisfying at least the relationship of Ron (SBD) × 10 ⁵ <Ron (PND). For this reason, the contact between the Schottky electrode 4 and the p-type layer 11 is set so as to satisfy the relationship of Ron (SBD) × 10 ⁵ <Ron (PND).

Specifically, as the contact resistance between the Schottky electrode 4 and the p-type layer 11 increases, the on-resistance Ron (PND) of the PN diode increases. Further, the smaller the contact area between the Schottky electrode 4 and the p-type layer 11, the larger the on-resistance Ron (PND) of the PN diode. Based on these, in order to satisfy the above relationship, for example, as the contact area of the p-type layer 11 increases, the contact resistance is increased so that hole injection can be further suppressed.

In the SiC semiconductor device provided with JBS, the waveform of current [A] with respect to voltage [V] when forward current flows through JBS is the waveform shown in FIG. The slope of this waveform is 1 / Ron (SBD) for the

SBD

10 and 1 / Ron (PND) for the PN diode. Therefore, each of the on-resistances Ron (SBD) and Ron (PND) can be obtained based on characteristics when a forward current flows.

Next, the reason why Effect 2 is obtained will be described with reference to FIGS. 7A and 7B.

As described above, the contact between the surface of the p-type layer 11 and the Schottky electrode 4 is prevented from being in an insulating state. When the contact between the surface of the p-type layer 11 and the Schottky electrode 4 is in an insulating state, as shown in FIG. 7A, the depletion layer spreading at the time of reverse bias does not return and the depletion layer remains in a wide range. It becomes the state of. For this reason, the current path is narrowed by the depletion layer, and the on-resistance Ron (SBD) of the SBD 10 is increased.

On the other hand, when the contact between the surface of the p-type layer 11 and the Schottky electrode 4 is in an insulating state as in the present embodiment, the depletion layer that has spread at the time of reverse bias returns as shown in FIG. 7B. Reduced. For this reason, the range in which the current path is narrowed by the depletion layer is reduced, an increase in the on-resistance Ron (SBD) of the SBD 10 is suppressed, and an effect 2 that the deterioration of the on-resistance is suppressed is obtained.

As described above, in the SiC semiconductor device having the JBS of the present embodiment, since the relationship of Ron (SBD) × 10 ⁵ <Ron (PND) is satisfied, the rise of the recovery current can be moderated, The amount of change dir / dt in the recovery current can be reduced. For this reason, the effect 1 that generation | occurrence | production of the surge at the time of reverse recovery is suppressed can be acquired. In addition, since the contact between the surface of the p-type layer 11 and the Schottky electrode 4 is not in an insulating state, the depletion layer that has spread at the time of reverse bias can be returned and reduced, and the on-resistance can be deteriorated. The effect 2 of being suppressed can be acquired.

(Other embodiments)
Although the present disclosure has been described based on the above-described embodiment, the present disclosure is not limited to the embodiment, and includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

For example, the layout of the p-type layer 11 described in the above embodiment is arbitrary, and other layouts, for example, the circular p-type layer 11 is arranged at the center position of the cell portion, and a plurality of layers are formed around that. The structure etc. which arrange | positioned the p-type layer 11 concentrically may be sufficient.

In the above-described embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described. However, an SiC semiconductor device in which each conductivity type is reversed may be used.

It should be noted that when indicating the orientation of a crystal, a bar (-) should be attached on a desired number, but there is a limitation in terms of expression based on an electronic application. A bar shall be placed in front of the number.

Claims

A silicon carbide semiconductor device having a cell portion in which a junction barrier Schottky diode is formed,
A first conductivity type substrate (1) made of silicon carbide having a main surface (1a) and a back surface (1b);
A drift layer (2) made of silicon carbide of the first conductivity type formed on the main surface and having a lower impurity concentration than the substrate;
An insulating film (3) disposed on the drift layer and having the cell portion as an opening (3a);
A Schottky electrode (4) formed in the cell portion and brought into Schottky contact with the surface of the drift layer through the opening of the insulating film;
An ohmic electrode (5) formed on the back surface of the substrate;
A plurality of second conductivity type layers (11) formed on a surface layer portion of the drift layer and in contact with the Schottky electrode and arranged apart from each other,
The Schottky barrier diode (10) is configured by including the Schottky electrode, the drift layer, the substrate, and the ohmic electrode, and a PN diode is formed by the plurality of second conductivity type layers and the drift layer. Is configured, the junction barrier Schottky diode is configured,
A silicon carbide semiconductor device in which the on-resistance Ron (SBD) of the Schottky barrier diode and the on-resistance Ron (PND) of the PN diode satisfy a relationship of Ron (SBD) × 10 5 <Ron (PND).
The silicon carbide semiconductor device according to claim 1, wherein a specific resistance of the second conductivity type layer is 1 Ωcm or less.