WO2018182607A1

WO2018182607A1 - Thermally conductive dielectric layers for thin film transistors

Info

Publication number: WO2018182607A1
Application number: PCT/US2017/024963
Authority: WO
Inventors: Abhishek A. Sharma; Van H. Le; Gilbert Dewey; Ravi Pillarisetty; Shriram SHIVARAMAN
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

Thermally conductive dielectric layers for thermal management of thin film transistors (TFTs). TFTs fabricated in a backend-of-line (BEOL) may experience high operating temperatures increasing leakage current within the thin film semiconductor material. Dielectric materials that provide electrical device isolation while offering enhanced thermal conductivity may reduce thermal excursions during TFT operation. In some embodiments, thermally conductive layers having a Debye temperature close to that of the channel semiconductor are in placed in close proximity with the channel semiconductor, improving local heat flux away from the channel and/or spreading heat generated by the TFT. In some embodiments, a thermally conductive dielectric layer is near a surface a thin film select transistor of a memory device.

Description

Thermally Conductive Dielectric Layers for Thin Film Transistors

BACKGROUND

Thin-film transistors (TFTs) are a class of field-effect transistors (FETs) in which the channel material is a deposited thin film rather than a monocrystalline material. A common application of TFT technology is liquid crystal displays (LCD), but TFT technology is also advantageous in other applications because the thin film deposition processes employed in TFT fabrication can be relatively low (e.g., below 450 °C). TFTs can be made using a wide variety of semiconductor materials, such as silicon, germanium, silicon-germanium, as well as various oxide semiconductors (a.k.a. semiconducting oxides) including metal oxides like indium gallium zinc oxide (IGZO). Embedded memory is one area where TFTs may be advantageous. Embedded memory may be integrated with a host IC as a multi-chip module (MCM) or may be monolithically integrated with a host IC (i.e., both memory and the host IC fabricated on the same chip). For embedded memory applications, reducing the overall memory array footprint helps achieve larger memories and/or reduce device cost. One form of embedded memory is embedded dynamic random access memory (eDRAM). The architecture of eDRAM is based on a 1T-1C cell that includes a "write" or "selection" transistor and a storage capacitor. eDRAM may be integrated with a host microprocessor chip (such as a central processing unit or "CPU") at the package level, for example, to form an central processor MCM. Integration of both a memory device and a processor proximate to one another in a same package may, for example, enable communication between the memory device and the processor through a local bus capable of higher bandwidths and/or lower signal latencies relative to separately packaged chips communicating through a printed circuit board (PCB) bus.

For some eDRAM devices, a transistor of a memory cell is fabricated on and/or within a monocrystalline semiconductor during front-end-of-line (FEOL) processing. The capacitor may either be fabricated in the FEOL as well, or fabricated in the back-end-of-line (BEOL). A transistor and capacitor of each cell are electrically coupled through one or more metal interconnect layers formed in the BEOL. The BEOL is the portion of IC fabrication where individual semiconductor devices (whether embedded memory or logic transistors) are interconnected to one another with electrically conductive features such as metal interconnect traces (lines) within a given metallization level and metal-filled conductive vias between multiple metallization levels. These conductive interconnects are embedded in a dielectric material so that the memory device is a monolithic integrated circuit.

Selection transistors may be fabricated as a 2D array of field effect transistors (FETs) employing a monocrystalline semiconductor device layer for at least the transistor channel. TFTs may instead implement selection transistors, enabling more of components of an eDRAM to be fabricated in the BEOL. Moving transistors from a substrate and into the BEOL stack may however pose difficulties with respect to thermal management.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example, and not by way of limitation, in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures: FIG. 1 A and IB illustrate cross-sectional views through dielectric layers over a thin film semiconductor layer, in accordance with some embodiments;

FIG. 2A, 2B, 2C, 2D and 2E illustrate cross-sectional views through a length of a TFT structure including a thermally conductive dielectric layer, in accordance with some embodiments; FIG. 3 A and 3B are cross-sectional views of a substrate the TFT cells of FIG. 1A-1D may be fabricated upon, in accordance with some embodiments;

FIG. 4 illustrates a cross-sectional side view of a memory device structure, in accordance with some exemplary embodiments of the structures illustrated in FIG 2D-2E;

FIG. 5 is a flow diagram illustrating methods for fabricating a TFT structure, in accordance with some embodiments;

FIG. 6A, 6B, 6C, 6D, and 6E illustrate cross-sectional views through a length of the TFT structure depicted in FIG. 2A evolving as operations in the methods shown in FIG. 5 are practiced, in accordance with some embodiments; FIG. 7A, 7B, 7C, 7D, and 7E illustrate cross-sectional views through a length of the TFT structure depicted in FIG. 2B evolving as operations in the methods shown in FIG. 5 are practiced, in accordance with some embodiments;

FIG. 8A, 8B, 8C, 8D, and 8E illustrate cross-sectional views through a length of the TFT structure depicted in FIG. 2C evolving as operations in the methods shown in FIG. 5 are practiced, in accordance with some embodiments;

FIG. 9A, 9B, 9C, and 9D illustrate cross-sectional views through a length of the TFT structure depicted in FIG. 2D evolving as operations in the methods shown in FIG. 5 are practiced, in accordance with some embodiments;

FIG. 10A, 10B, IOC, and 10D illustrate cross-sectional views through a length of the TFT structure depicted in FIG. 2E evolving as operations in the methods shown in FIG. 5 are practiced, in accordance with some embodiments;

FIG. 11 illustrates a mobile computing platform and a data server machine including a memory device with BEOL capacitors and TFTs and a thermally conductive dielectric layer, in accordance with some embodiments; and

FIG. 12 is a functional block diagram of an electronic computing device, in accordance with some embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms "a", "an" and

"the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Thin film transistors incorporating a deposited semiconductor layer are described herein. A deposited semiconductor layer can be amorphous (i.e., having no structural order), or poly crystalline (e.g., having micro-scale to nano-scale crystal grains). TFT device performance depends at least in part on the composition of the semiconductor layer. The TFT structures described herein are applicable to any thin film semiconductor material, including traditional group IV semiconductor materials such as silicon (Si), germanium (Ge), and SiGe alloys. In some advantageous embodiments however, an oxide semiconductor is utilized for at least the TFT channel material. An oxide semiconductor is a semiconducting oxide, or a semiconductor comprising oxygen. For such embodiments, the wide band gap oxide channel material offers low leakage characteristics. In such materials the minority carrier population is small compared to that of materials such as silicon and germanium, making the TFT an exclusively majority carrier device. With essentially no minority carriers, majority -minority carrier recombination cannot generate significant off-state leakage current. TFT device performance also depends on the temperature of the semiconductor layer.

Leakage current with in the semiconductor layer can increase significantly with higher temperatures. The temperature of the semiconductor layer may be a function of current density within the semiconductor layer as well as heat transfer coefficients associated with the surrounding structures. High current density can be expected for applications where the TFT has been highly scaled, for example where TFT gate dimensions are in the tens of nanometers, for example. The inventors have found that during operation, aggressively scaled TFTs fabricated in a BEOL may experience temperatures of 150 °C, or more, during operation. At such temperatures, even a comparatively low-leakage semiconductor layer (e.g., an oxide semiconductor material) may display significant leakage current (e.g., off-state leakage current). Memory devices comprising one or more arrays in which individual memory cells include a thin film select transistor and a capacitor (1TFT-1C) may show poorer retention times for a given memory density as leakage current increases with the semiconductor layer temperature.

In some embodiments a thermally conductive dielectric material is employed within a device structure including a thin film semiconductor layer. The thermally conductive dielectric material may be incorporated within a device structure as a means of enhancing the flux of heat generated in the semiconductor layer during device operation into surrounding structures, thereby lowering the maximum temperature of the semiconductor layer. The thermally conductive dielectric material may also function as a heat spreader, increasing the area over which heat generated within the confines of the semiconductor layer may be dissipated. As a dielectric, the thermally conductive material may advantageously maintain electrical isolation of the semiconductor layer. FIG. 1 A illustrates a cross-sectional view through dielectric layers over a thin film semiconductor layer, in accordance with some embodiments. In structure 101, a thermally conductive dielectric layer 165 is located between an interlay er dielectric (ILD) layer 170 and a surface of a semiconductor material layer 110. In the example shown, thermally conductive dielectric layer 165 is in direct contact with a surface of semiconductor layer 110. Although thermally conductive dielectric layer 165 is illustrated to be on semiconductor layer 110, structure 101 may be inverted so that semiconductor layer 110 is instead on dielectric layer 165 with dielectric layer 165 then on ILD layer 170.

In some exemplary embodiments, semiconductor layer 110 is an oxide

semiconductor. Examples include metal oxides with a transition metal (e.g., IUPAC group 4- 10) or post-transition metal (e.g., IUPAC groups 11-15). In advantageous embodiments, the metal oxide includes at least one of Mg, Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo. The metal oxide may be a suboxide (A2O), monoxide (AO), binary oxide (AO2), ternary oxide (ABO3), or mixture thereof. Semiconductor layer 110 may be a p-type, n-type, or intrinsic material. In exemplary embodiments, semiconductor layer 110 is n-type, and a number of oxide semiconductors have been found to be capable of significant electron densities. Some oxide semiconductors have also been found to be capable of significant electron hole densities. Many oxide semiconductors have high defect density nearer the valence band, but display good n-type electrical properties. Some oxide semiconductors have high defect density in the conduction band, but display good p-type electrical properties.

In some embodiments, semiconductor layer 110 comprises a tin oxide (SnOx), such as Tin (IV) oxide, or SnC . In other embodiments, the tin oxide is Tin (II) oxide (SnO) or a mixture of SnO and Sn02, where x may range between 1 and 2. While the range of x may be expanded, semiconducting properties may be lost (e.g., the material becomes a pure conductor if x is to low, and a pure insulator if x is too high). In some other embodiments, semiconductor layer 110 comprises a zinc oxide (ZnOx), such as Zn(II) oxide, or ZnO. In other embodiments, the zinc oxide is zinc dioxide (Zn02) or a mixture of ZnO and Zn02, where x may range between 1 and 2. In some other embodiments, semiconductor layer 110 comprises titanium oxide (TiOx), or SnOx. Exemplary oxide semiconductors that may have suitable p-type conductivity include copper oxide (CuOx). In some CuOx embodiments, semiconductor layer 110 is Cu(I) oxide, or CmO. In other embodiments, semiconductor layer 110 is Cu(II) oxide (CuO) or a mixture of CuO and CU2O, where x may range between 0.5 and 1. Still other exemplary oxide semiconductor compositions include NiOx.

Oxide semiconductor conductivity type is a function of composition. Although not bound by theory, the basis for semi-conductive properties in many oxide semiconductors may be the presence of oxygen vacancies. The presence of other electrically active dopants, such as hydrogen, or one or more metal species, may also serve as a means of tuning the semiconducting properties of an oxide semiconductor. Semiconductor layer 110 or various portions thereof, may be intentionally doped, or not. Compared to intrinsic oxide

semiconductor that is not intentionally doped, n-type and p-type oxide semiconductors may have a higher concentration of impurities, such as, but not limited to, one or more group III element, group V element, and/or elemental hydrogen (H), and/or oxygen vacancies. In some embodiments where semiconductor layer 110 comprises ZnOx, the dopants may include In and Ga. In some specific examples, semiconductor layer 110 is InGa03(ZnO)5, often referred to simply as IGZO.

ILD layer 170 may be any dielectric material known to be suitable for electrical isolation of monolithic circuitry, but has a composition different than that of thermally conductive dielectric layer 165. ILD layer 170 may, for example, include one or more conventional material layers, such as, but not limited to SiOx (e.g., SiC ), SiN_x (e.g. S13N4), and SiOxNy. In some embodiments, ILD layer 170 is any low-k dielectrics (e.g., having a relative permittivity less than 3.5) known to be suitable for electrical isolation of monolithic circuitry, such as, but not limited to, carbon-doped oxide (e.g., SiOC(H)), HSQ, or MSQ. ILD layer 170 may also serve as a hermetic seal protecting one or more of thermally conductive dielectric layer 165 and semiconductor layer 110. While ILD layer 170 may be well-suited to the demands of an interlay er dielectric, it may have a relatively poor thermal conductivity. Silicon dioxide, for example, typically has a thermal conductivity of 0.5-1.4 W/m*K. Silicon nitrides may be somewhat higher, but are generally also less than 10 W/m*K.

Thermally conductive dielectric layer 165 may advantageously have a higher thermal conductivity than ILD layer 170. With higher thermal conductivity, insertion of dielectric layer 165 may facilitate removal of heat away from semiconductor layer 110. In some embodiments, thermally conductive dielectric layer 165 has a thermal conductivity, in at least one dimension (e.g., z-dimension), that is at least 30 W/m*K, advantageously at least 100 W/m*K, and more advantageously at least 200 W/m*K. These high thermal conductivities compare favorably with many metal thin films. For example, tungsten (W) typically has a thermal conductivity of 5-150 W/m*K. Hence, the composition of thermally conductive dielectric layer 165 may be chosen based, at least in part, to increase thermal conductivity of the dielectric. Exemplary dielectric materials that can have high thermal conductivity even as thin films include, but are not limited to, A1N_X, AlOx, MgOx, MoOx, A10_xN_y, ALSiyOz, HfxAlyOz, and SiCx. In addition to having a high thermal conductivity, thermally conductive dielectric layer 165 may provide to semiconductor layer 110 a thermal interface that is superior to what ILD layer 170 can provide. Thermal interface properties may be improved by matching the Debye temperature of dielectric layer 165 with that of semiconductor layer 110. The greater the degree of match in the density of phonon states between semiconductor layer 1 10 and the dielectric layer 165, the more efficiently phonons in semiconductor layer 110 may be coupled out of semiconductor layer 110 and into thermally conductive dielectric material 165. Hence, composition of thermally conductive dielectric material 165 may be chosen based, at least in part, on the composition of semiconductor layer 1 10. The phonon density of states is also dependent on microstructure of the dielectric, so both composition and microstructure of semiconductor layer 165 may be tuned to improve the phonon state density match with semiconductor layer 1 10.

In some embodiments, thermally conductive dielectric layer 165 further serves as a passivation of semiconductor layer 1 10. In the context of oxide semiconductor embodiments, a passivation material may reduce compositional changes within semiconductor layer 1 10 during, and/or subsequent to, deposition of dielectric layer 165 and/or ILD layer 170. Absent a passivation material, subsequent thermal processing and/or reactive species employed during processing may disadvantageously alter the oxygen and/or metal content of semiconductor layer 1 10. For example, ILD layer 170 may getter oxygen from an oxide semiconductor embodiment of semiconductor layer 1 10, and/or change the oxidation state of metal species in the oxide semiconductor unless thermally conductive dielectric layer 165 provides a sufficient passivation and/or barrier. Dielectric materials suitable for passivation include, but are not limited to, metal nitrides, metal oxides, and metal silicates. Specific examples include A1N_X, AlOx, TiOx, and TaOx. Not all such materials have high thermal conductivity and/or some such materials may have a phonon density of states that is a better match than others for the chosen semiconductor composition (e.g., oxide semiconductor).

In some embodiments, thermally conductive dielectric layer 165 has greater crystallinity than ILD layer 170. ILD For example, where ILD layer 170 is amorphous, thermally conductive dielectric layer 165 may be advantageously poly crystalline. A granular thermally conductive dielectric layer 165 may improve the phonon density of states match with semiconductor layer 1 10 relative to an amorphous dielectric such as ILD layer 170. In some further embodiments, thermally conductive dielectric layer 165 has greater crystallinity (i.e., is more ordered) than semiconductor layer 110. While semiconductor layer 110 may display some level of structural ordering (e.g., nanocrystallinity), in some embodiments amenable to lowest processing temperatures, semiconductor layer 110 may be deposited in an amorphous state. Semiconductor layer 110 may therefore be amorphous while dielectric layer 165 is polycrystalline. The size of crystal grains within dielectric layer 165 may vary (e.g., from nanocrystalline to microcrystalline). However, for embodiments where semiconductor layer 110 is polycrystalline, the size of the crystal grains within thermally conductive dielectric layer 165 may be significantly (e.g., greater than 15%) larger than those semiconductor layer 110. In some exemplary embodiments, thermally conductive dielectric layer 165 has a crystal texture relative to at least the interface with semiconductor layer 110. Grains within thermally conductive dielectric layer 165 may have a non-random distribution of

crystallographic orientations with some preferred orientation relative to the interface with semiconductor layer 110. In some embodiments, thermally conductive dielectric layer 165 has columnar grain structure, either as deposited, or upon subsequent thermal processing. In some embodiments, columnar grains within thermally conductive dielectric layer 165 have their longitudinal axes preferentially oriented perpendicular to the interface of semiconductor layer 110 and/or perpendicular to the interface of ILD layer 170. For example, c-axis (002) oriented A1N films or (0001) oriented SiC films offer high thermal conductivity with low phonon scattering or inefficiency in phonon transport from the channel semiconductor, through the thickness of thermally conductive dielectric layer 165 and into surrounding ILD layers (e.g., ILD layer 170).

In some exemplary embodiments, thermally conductive dielectric layer 165 comprises AlNx (A1N). As noted above, A1N_X has a high thermal conductivity (e.g., 150-300 W/m*K). The inventors have also found A1N_X to have a phonon density of states that appears well- matched to some oxide semiconductors, particularly for the ZnOx family. AlNx therefore also provides a good thermal interface to such a semiconductor. The thermally conductive dielectric layer 165 may be predominantly the binary compound A1N_X in direct contact with a surface of semiconductor layer 110. The Al/N ratio of such a layer may vary. A binary compound of A1N_X may further include impurities, such as oxygen and/or carbon, for example as a result of doping during deposition and/or subsequent solid-state interdiffusion of dissimilar materials in intimate contact. The A1N_X may have any microstructure, which may depend, for example, on the deposition method and on the deposition parameters, such as deposition temperature. The A1N_X dielectric layer may be crystalline (e.g., poly crystalline), and if so, may have a preferential texture (e.g., columnar) even when deposited over an amorphous surface (e.g., semiconductor layer 110 or an underlying ILD layer). The A1N_X dielectric layer may be deposited to any thickness. In some exemplary embodiments, a thermally conductive dielectric layer 165 comprising predominantly AlNx has a thickness of at least 5 nm. Within such a thickness range, crystallinity may develop within the first nanometer of thickness (as measured from an underlying material interface) even when deposited on an amorphous material. Once developed, such crystallinity may be maintained through the remaining layer thickness (e.g., 2-100 nm).

In some other embodiments, thermally conductive dielectric layer 165 comprises carbon-doped silicon or silicon carbide (SiCx). SiCx has a reasonably high thermal conductivity, for example exceeding 30 W/m*K. SiCx may also have a phonon density of states that is well-matched to some oxide semiconductors, including those of the ZnOx family. The thermally conductive dielectric layer 165 may be predominantly the binary compound SiCx in direct contact with a surface of semiconductor layer 160. The Si/C ratio of such a layer may vary with x ranging from 0.8 to 1.1 at %. A binary compound of SiCx may further include impurities, such as oxygen and/or hydrogen (SiC:H) for example as a result of doping during deposition and/or subsequent solid-state interdiffusion of dissimilar materials in intimate contact. Exemplary embodiments include SiC:4H and SiC:6H. The SiCx may have any microstructure, which may depend, for example, on the deposition method and on the deposition parameters, such as deposition temperature. The SiCx material layer may be crystalline (e.g., poly crystalline), and if so, may have a preferential texture even when deposited over an amorphous surface (e.g., semiconductor layer 110 or an underlying ILD layer). SiCx may be deposited to any thickness. In some exemplary embodiments, a thermally conductive dielectric layer 165 comprising predominantly SiCx has a thickness of at least 10 nm. Within such a thickness range, crystallinity may develop over within the first 5-7 nanometers of thickness as measured from an underlying material interface. The crystallinity may then be maintained through the remaining layer thickness (e.g., 8-100 nm). In some other embodiments, thermally conductive dielectric layer 165 comprises

AlOx (e.g., AI2O3), AlOxNy, BeO_x(e.g., x=0.85-l), BN(e.g., stoichiometric), HBN(e.g., stoichiometric), or MoOx. All of these material can also have relatively high thermal conductivity, for example exceeding 30 W/m*K. These material may also have a suitable phonon density of states for various oxide semiconductor compositions, including, but not limited to, those of the ZnOx family. The compositions may vary and may have an impurity percentage. Exemplary impurities include hydrogen and carbon. These materials may also have any microstructure, which may depend, for example, on the deposition method and on the deposition parameters, such as deposition temperature. These materials may be crystalline (e.g., poly crystalline), and if so, may have a preferential texture even when deposited over an amorphous surface (e.g., semiconductor layer 110 or an underlying ILD layer 170). These materials may also be deposited to any thickness. In some exemplary embodiments, a thermally conductive dielectric layer 165 comprising AlOx, AlOxNy, BN, HBN, BeOx or MoOx has a thickness of 10-200 nm. Within this thickness range, crystallinity may develop over some thickness from an underlying material interface and then be maintained through the remaining thickness.

In some embodiments, two or more thermally conductive dielectric layers are employed in a stack between a semiconductor layer and an ILD layer. FIG. IB illustrates a cross-sectional view through dielectric layers over a thin film semiconductor layer, in accordance with some embodiments. In structure 102, thermally conductive dielectric layer 165 includes a first thermal layer 165 A in direct contact with semiconductor layer 110, and a second thermal layer 165B located between first layer 165 A and ILD layer 170.

Semiconductor layer 110 and ILD layer 170 are substantially as described above in the context of structure 101. Structure 102 may be inverted so that semiconductor layer 110 is instead on dielectric layer 165 A with dielectric layer 165 A on dielectric layer 165B, and dielectric layer 165B on ILD layer 170.

Multi -layered embodiments in accordance with structure 102 may advantageously offer additional degrees of freedom in material selection. The first thermal layer 165 A may be selected, for example, to have a better phonon density of states match with semiconductor layer 110. Second thermal layer 165B may be selected, for example, to have higher thermal conductivity and/or provide better semiconductor passivation than first thermal layer 165A. In some exemplary embodiments where semiconductor layer 110 is an oxide semiconductor, first thermal layer 165 A comprises A1N_X and second thermal layer 165B comprises TiOx (e.g., TiC ). The A1N_X may have any of the properties described in the context of FIG. 1A, for example. In some embodiments where semiconductor layer 110 is ZnOx, A1N_X phonon density of states is better aligned with that of ZnOx. In the presence of the A1N_X thermal interface however, TiOx may employed for the sake of passivating the ZnOx. For such embodiments, first thermal layer 165 A need only have a thickness sufficient to achieve a good thermal interface to semiconductor layer 110 (e.g., 2-5 nm of A1N_X). Second thermal layer 165B need only have a thickness sufficient to achieve good passivation of

semiconductor layer 110 (e.g., 5-200 nm of TiC ).

In other embodiments, any of the other materials described above as suitable for thermally conducive layer 165 in the context of structure 101 may be utilized as the first thermal layer 165 A in the context of structure 201. Any of the other materials described above as being suitable passivation layers may be utilized as the second thermal layer 165B. Second thermal layer 165B may be also, or in the alternative, any dielectric material having a high thermal conductivity (e.g., 30 W/m*K, or more).

For some embodiments of structure 201, at least first thermal layer 165 A has greater crystallinity than ILD layer 170. At least first thermal layer 165 A may also have greater crystallinity than semiconductor layer 110. Second thermal layer 165B may also have greater crystallinity than ILD layer 170 and/or semiconductor layer 110. In some such embodiments, second thermal layer 165B has crystalline texture associated with that of first thermal layer 165 A. For example, crystal grain growth within second thermal layer 165B may template from crystal grains in first thermal layer 165 A. A thermally conductive dielectric layer (or stack of such layers), for example as described above, may be integrated into a variety of TFT structures and devices employing such transistor structures. For example, the thermally conductive dielectric may be deposited subsequent to deposition of the semiconductor layer, or prior to deposition of the

semiconductor layer. Such thermally conductive dielectric layers may also be integrated into transistor architectures having top or bottom gate electrodes, and top or bottom source and drain contacts, for example. FIG. 2A, 2B, 2C, 2D, and 2E illustrate cross-sectional views through a length TFT structures including a thermally conductive dielectric layer, in accordance with some embodiments. In FIG. 2A-2E, semiconductor layer 110, thermally conductive dielectric layer 165 and ILD layer 170 may be any of the materials described above in the context of FIG. 1 A. Referring first to FIG. 2A, in TFT structure 201 semiconductor layer 110 is disposed over a gate dielectric 220. In this "bottom-side" gate architecture, gate dielectric 220 is disposed over a gate electrode 240 that is embedded in a substrate layer 206. In some exemplary embodiments, substrate layer 206 is an amorphous dielectric, such as, but not limited to, SiOx, SiN_x, SiO_xN_y, or a low-k dielectric. Depending on the conductivity type of semiconductor layer 110, gate electrode 240 is to modulate a channel portion of

semiconductor layer 110 between intrinsic and n-type or p-type material through the field effect. In some exemplary embodiments, gate dielectric 220 comprises a high-k dielectric having a bulk relative dielectric constant greater than at least 9. The gate dielectric may include one or more material layers. In some such embodiments, the high-k gate dielectric comprises a metal oxide. In some embodiments, the metal oxide comprises at least one of AlOx, HfOx, TiOx, TaOx, or HfAlOx in direct contact with semiconductor layer 110. Silicates such as HfSiOx or TiSiOx may also be suitable for either direct contact with semiconductor layer 110. HfCh may give better gate control in zinc oxide (e.g., IGZO) embodiments than altematives such as AI2O3. However, both AI2O3 and HfCh have been found to display results superior to silicon-based dielectrics (e.g., SiCh).

In some advantageous embodiments, gate electrode 240 includes a metal. The metal gate electrode may include an elemental metal layer, a metal alloy layer, or laminate structure of either or both. In some embodiments the gate electrode is a metal nitride, such as TiN_x. The gate electrode may also comprise Al (e.g., TiAl_xN_y). Other alloy constituents may also be employed, such as, but not limited to C, Ta, W, Pt, and Zn. Gate electrode 240 may have any lateral critical dimension.

As further illustrated in FIG. 2A, thermally conductive dielectric layer 165 is disposed over semiconductor layer 110 on a side opposite gate dielectric 220. Thermally conductive dielectric layer 165 is disposed over the channel region, spanning the channel length of semiconductor layer 110 between source and drain contacts 260. For such embodiments, thermally conductive dielectric layer 165 may improve flux of heat from semiconductor layer 110 resulting from current between source and drain contacts 260 into overlying material layers. Source and drain contacts 260 may have any metal composition that when interfacing the chosen semiconductor will, either as deposited, or upon subsequent annealing, have suitable contact resistance. In some embodiments, source and drain contacts 260 include a metal nitride at the interface of (i.e., in direct contact with) semiconductor conductor layer 1 10. Metal nitrides offer good stability and do not ready oxidize. Exemplary metal nitrides include TiN_x, TaN_x, and WN_X. In other exemplary embodiments, source/drain contacts 160 include a noble metal (e.g., Pt) at the interface of (i.e., in direct contact with) semiconductor layer 1 10. As illustrated in FIG. 2A, source and drain contacts 260 extend through thermally conductive dielectric layer 165. Although not depicted in FIG. 2A, the terminals of TFT structure 201 may be interconnected with one or more other TFT structure, or a FET structure, by one or more interconnect metallization levels to form a functional integrated circuit.

A TFT structure 202 in accordance with some non-planar oxide semiconductor embodiments is further illustrated in FIG. 2B. As shown, gate electrode 240 is again embedded in substrate layer 206 in a "bottom-gate" architecture. The channel region of semiconductor layer 110 is disposed between gate dielectric 220 and thermally conductive dielectric layer 165, substantially as described for TFT structure 201. Thermally conductive dielectric layer 165 is further disposed over a sidewall of semiconductor layer 1 10 where the film has been patterned, for example with a through-film etch that exposes gate dielectric 220 and/or substrate layer 206. Substrate layer 206, gate electrode 240, gate dielectric 220, semiconductor layer 110, thermally conductive dielectric layer 165, and source and drain contacts 260 may have any of the compositions, microstructure, thickness etc. described above in the context of one or more of structures 101 (FIG. 1A), 102 (FIG. IB), and 201 (FIG. 2A), for example.

A TFT including a thermally conductive dielectric layer in accordance with some other embodiments may include bottom-side source/drain contacts and/or a "top-side" gate stack rather than (or in addition to) the top-side source/drain contacts and bottom-side gate stack illustrated in FIG. 2A, 2B. A TFT structure 203 in accordance with some exemplary embodiments is further illustrated in FIG. 2C. As shown, source and drain contacts 260 are embedded in substrate layer 206. Semiconductor layer 1 10 is disposed over (e.g., in direct contact with) source/drain contacts 260. A gate stack is further disposed over a channel region of semiconductor layer 1 10. The gate stack includes gate electrode 240 disposed over (e.g., in direct contact with) gate dielectric 220. Thermally conductive dielectric layer 165 and ILD layer 170 is disposed adjacent to gate electrode 240. Top-side source/drain contacts 260 extend through thermally conductive dielectric layer 165 substantially as described above for TFT structure 202. Thermally conductive dielectric layer 165 is also disposed on sidewalls of semiconductor layer 1 10.

In some top gate embodiments, the semiconductor layer is over a thermally conductive layer. TFT structure 204, as illustrated in FIG. 2D, includes a thermally conductive dielectric layer 165 disposed under semiconductor layer 110 and opposite gate dielectric 220. Thermally conductive dielectric layer 165 is disposed under the channel region, spanning the channel length of semiconductor layer 1 10 between source and drain contacts 260. For such embodiments, thermally conductive dielectric layer 165 may improve flux of heat from semiconductor layer 1 10 resulting from current between source and drain contacts 260 into substrate layer 206. FIG. 2D further illustrates embodiments where ILD layer 170 also functions as a self-aligned gate sidewall spacer that separates source and drain contacts 260 from sidewalls of gate electrode 120 (e.g., providing a x-dimension separation of 5-20 nm). For such embodiments ILD layer 170 may have a composition distinct from other ILD material layers, such as ILD layer 280. ILD layer 280 may be any composition known to be suitable as an ILD, such as, but not limited to SiO, SiN, SiON, or low-k dielectric.

In TFT structure 205 of FIG. 2E, gate dielectric 220 is disposed between gate electrode 240 and semiconductor layer 1 10, while thermally conductive dielectric layer 165 is located beyond the edge or sidewall of gate electrode 240 and covered with ILD layer 170. Depending on the fabrication process, gate dielectric 220 may be thinner or thicker than thermally conductive dielectric layer 165. Top-side source and drain contacts 260 extend through thermally conductive dielectric layer 165 substantially as described above for TFT structures 201 and 202. Thermally conductive dielectric layer 165 is also disposed on sidewalls of semiconductor layer 110. The embodiments described in the context of FIG. 2A-2E may be further combined and/or modified without departing from the illustrated principles. For example, the TFT structures 204 (FIG. 2D) and 205 (FIG. 2E) may be combined. As another example, a TFT architecture may include a bottom-side gate stack and bottom-side source/drain contacts with a thermally conductive dielectric disposed over the oxide semiconductor layer substantially as illustrated in FIG. 2B or 2C. As another example, a TFT architecture may include a topside replacement gate stack in which a portion of the thermally conductive dielectric is replaced with a gate dielectric. In still other embodiments, a TFT includes a vertical channel architecture with a thermally conductive dielectric disposed over a sidewall of the semiconductor feature extending between source/drain contacts. These various examples illustrate how a thermally conductive dielectric in accordance with embodiments herein is widely applicable to TFT structures, particularly those employing an oxide semiconductor channel.

FIG. 3A and 3B are cross-sectional views of substrates 301 and 302, respectively, upon which a TFT structure including a thermally conductive dielectric layer may be fabricated. Any of TFT structures 201-204 may be fabricated on substrate 301 or 302, for example. In some embodiments, a TFT structure including a thermally conductive dielectric layer is fabricated over one or more interconnect metallization levels integrating a plurality of silicon CMOS FETs. In the example shown in FIG. 3A, substrate 301 includes a plurality of CMOS FETs 306 that employ a substantially monocrystalline channel material, such as, but not limited to, silicon. CMOS FETs 306 may be finFETs, for example. CMOS FETs 406 are interconnected with one or more levels of interconnect metallization 307. A TFT structure may be fabricated over any given interconnect metallization level (e.g., metal 4). The interconnect metallization may, at least in part, serve as the gate electrode and/or contact metallization, and or heat sink, of the overlying TFT.

In some embodiments, a TFT structure including a thermally conductive dielectric layer is fabricated on a back-side of a plurality of silicon CMOS FETs. In the example shown in FIG. 3B, substrate 302 includes a plurality of CMOS FETs 306 that employ a substantially monocrystalline channel material, such as, but not limited to, silicon. In the context of substrate 302, CMOS FETs 306 may again be finFETs, for example. CMOS FETs 306 are interconnected with one or more levels of interconnect metallization 307 disposed over a front-side of CMOS FETs 306. On a side of CMOS FETs 306 opposite interconnect metallization 307, a TFT structure having a thermally conductive dielectric layer may be fabricated over substrate layer 206 as part of a transistor substrate back-side fabrication process.

In some embodiments, a TFT structure including a thermally conductive dielectric layer is employed in an eDRAM device. FIG. 4 illustrates a cross-sectional side view of a memory device structure 400, in accordance with some exemplary top-gate TFT structures (e.g., as illustrated in FIG 2D-2E). Structure 400 represents a portion of a monolithic IC including CMOS circuitry 480 fabricated over and/or on a substrate 401. CMOS circuitry 480 includes a plurality of MOSFETs 481 that employ a monocrystalline semiconductor for at least the channel semiconductor 471. CMOS circuitry 480 may further include one or more levels of interconnect metallization 405 embedded in dielectric material layers 403, 404. In the exemplary embodiment illustrated, CMOS circuitry 480 includes metal-one (Ml), metal- two (M2) and metal-three (M3) interconnect metallization levels.

A plurality of TFTs 482 is located over CMOS circuitry 480. As shown, TFTs 482 employ portions of semiconductor layer 110. Memory cells 421A and 421B are denoted by dot-dashed line in FIG. 4. Individual ones of TFTs 482 include a gate electrode 240 separated from semiconductor layer 110 by a gate dielectric 220. In the exemplary embodiment illustrated, TFTs 482 are "top-gate" devices with gate electrode 240 having been fabricated over semiconductor layer 110. A dielectric spacer 430 separates a sidewall of gate electrode 240 from semiconductor terminal contacts 260, which land on source and drain regions of semiconductor layer 110.

It should be appreciated from FIG. 4 that dielectric spacer 430 may be self-aligned to gate electrode 240. Self-aligned techniques may include any unmasked anisotropic dielectric spacer etch process known to be suitable for the chosen dielectric composition. Contacts 260 backfill the region between adjacent dielectric spacers. With no bifurcation of semiconductor layer 110, TFTs 482 make a highly regular array that can be fabricated with only a few masks that establish initial grating patterns. Such 2D line patterns can be fabricated at nanometer dimensions (e.g., 10-50 nm features). In some embodiments, TFT gate terminals comprise continuous traces extending between multiple bitlines. This gate trace continuity allows the TFT gate terminals to function as wordlines with in a memory array.

FIG. 4 further illustrates thermally conductive dielectric layer 165 between semiconductor layer 110 and underlying interconnect traces 410, which may be any suitable BEOL metal. Thermally conductive dielectric layer 165 in any of the other locations within a TFT structure may be similarly integrated into structure 400.

In some exemplary embodiments illustrated by FIG. 4, a bitline 446 comprises an interconnect metallization trace within a metallization level (e.g., M6) immediately above the metallization level (e.g., M5) in which TFTs 482 reside. In FIG. 4, bitline 446 is illustrated in dashed line as an indication that bitline 446 is behind the plane of the cross-sectional view illustrated. Hence, the bitline 446 metallization trace is what might be visible if a portion of dielectric layer 403 flush with the plane of the cross-section was milled out (e.g., with a FIB during a deprocessing). As further shown, via 448 provides electrical connection between bitline 446 and contact metallization landing on a semiconductor terminal (e.g. drain semiconductor) of a selection TFT. A source terminal of selection TFT is electrically connected through interconnect metallization 449. Local interconnect metallization 449 is within the same metallization level (e.g., M6) as bitline 4466. Local interconnect metallization 449 is adjacent to, but electrically insulated, from bitline 446.

In further reference to FIG. 4, an individual local interconnect metallization 449 electrically interconnects a first trench capacitor terminal 460 with a semiconductor terminal (e.g., source semiconductor) of a selection TFT. Capacitors 420 each further include a second terminal 461 that is separated from terminal 460 by an intervening dielectric material 462 having a suitable relative permittivity, etc. In the exemplary embodiment shown, terminal 461 is continuous across at least all capacitors 420 associated bitline 446. Terminal 461 may also be continuous across capacitors 420 associated multiple bitlines. Capacitor terminal 461 may then tie one side of all capacitors of a memory array to a common plate reference potential through circuit node 425, implemented for example with another metallization level (e.g., M8).

Any number of interconnect metallization levels may be employed to route circuit nodes of the memory array to the underlying CMOS circuitry. In the example shown in FIG. 4, the capacitor reference potential at circuit node 425 is routed down through five metallization levels (e.g., M8-M3) to be in electrical communication with one or more control circuit amplifier implemented in CMOS circuitry 480. Likewise, bitline 446 is routed down through three metallization levels (e.g., M6-M3) to be in electrical communication with one or more sense amplifier implemented in CMOS circuitry 480. Wordlines may also be routed down through one or more metallization levels (e.g., M4-M3) to be in electrical communication with one or more wordline driver amplifier implemented in CMOS circuitry 480.

As further illustrated in FIG. 4, FETs 481 include a gate terminal 470 separated from channel semiconductor 471 by a gate dielectric 472. Channel semiconductor 471 separates semiconductor terminals 474 (source semiconductor and drain semiconductor). Contact metallization 475 lands on semiconductor terminals 474 and is separated from gate terminal 470 by an intervening dielectric spacer 477. Any materials and techniques known to be suitable for fabricating FETs may be employed for forming FETs 481. FETs 481 may be planar or non-planar devices, for example. In some advantageous embodiments, FETS 481 are finFETs. One or more semiconductor materials may be employed in FETs 481. As one example, FETs 481 employ a surface layer of a substantially monocrystalline substrate 401. Substrate 401 may be any material known to be suitable for the fabrication of MOSFET (CMOS) circuitry, such as, but not limited to, group IV materials (e.g., silicon, germanium, and SiGe).

The TFT structures described above may be fabricated with a variety of techniques. FIG. 5 is a flow diagram illustrating methods 501 for fabricating TFT structures, in accordance with some embodiments. Methods 501 begin at operation 502 where a substrate is received. The substrate received at operation 502 may have been processed upstream of methods 501, for example to fabricate FETs and one or more levels of BEOL interconnect metallization over the FETs according to any known techniques. Methods 501 continue either with deposition of a thermally conductive dielectric layer over the substrate at operation 505 or with deposition of a semiconductor material layer at operation 510. Operation 505 is denoted with a dashed box as being optional. If operation 505 is not performed and methods 501 proceed to operation 510, then methods 501 further include operation 515 where a thermally conductive dielectric layer is subsequently deposited over the semiconductor layer. Operation 515 is however optional for embodiments where a conductive dielectric layer is deposited at operation 505. Methods 501 therefore include at least one of operations 505 and 515 and some embodiments of methods 501 may include both operations 505 and 515.

If operation 505 is performed, any of the thermally conductive dielectric materials described above may be deposited over an underlying substrate layer, which may comprise another dielectric material and/or an interconnect metallization. Operation 505 may entail any deposition process known to be suitable for the desired thermally conductive dielectric composition and microstructure. For example, any of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer CVD (ALCVD), plasma-enhanced CVD (PECVD), e-beam deposition (EBD), or pulsed laser deposition (PLD) may be employed to deposit a layer of thermally conductive dielectric material. Any of the thermally conductive dielectric materials described above may be so deposited as a blanket layer over the substrate, for example. At operation 510, a semiconductor layer is formed over an underlying dielectric layer, which may be a thermally conductive dielectric layer. Operation 510 may entail any deposition process known to be suitable for the semiconductor composition and

microstructure desired. For example, any of PVD, CVD, ALCVD, EBD, or PLD may be employed to deposit a thin film of a semiconductor. In some embodiments, a layer of oxide semiconductor is deposited at operation 510, and any of the oxide semiconductor materials described above may be so deposited as a blanket layer over the substrate. If desired, the semiconductor layer may then be patterned, for example with any known lithographic mask patterning process followed by any etch process known to be suitable for the semiconductor material. In some embodiments, for example, an anisotropic dry (plasma) etch is employed to pattern the semiconductor layer into a plurality of stripes forming a 2D grating pattern extending in a first) direction.

If operation 515 is performed, any of the thermally conductive dielectric materials described above may be deposited over the semiconductor layer. Operation 515 may entail any deposition process known to be suitable for the desired thermally conductive dielectric composition and microstructure. For example, any of PVD, CVD, PECVD, ALCVD, EBD, or PLD may be employed to deposit a layer of thermally conductive dielectric material. Any of the thermally conductive dielectric materials described above may be so deposited as a blanket layer over the substrate, for example. Methods 501 continue at operation 520 where an ILD material is deposited over the thermally conductive dielectric layer and/or over the semiconductor layer. One or more deposition and planarization techniques may be employed in any manner known in the art to form the ILD layer at operation 520. For example, spin-on, CVD, or PECVD processes may be employed to deposit the ILD layer. Source and drain contacts and/or a gate stack may also be formed on a top side of the semiconductor layer using any known additive or subtractive fabrication techniques. In some embodiments, the ILD layer is patterned to form openings exposing the thermally conductive dielectric layer. The exposed thermally conductive dielectric layer may then be removed where a gate stack or source/drain contact is to be located. A gate electrode and/or source/drain contact material may be deposited within openings in the thermally conductive dielectric layer. Alternatively, the ILD may be deposited over portions of the thermally conductive dielectric subsequent to fabrication of the gate electrode and/or source/drain contacts. In other embodiments, source and drain contacts and/or a gate stack may have been formed prior to deposition of the semiconductor layer according to any suitable bottom-gate fabrication technique(s). Methods 501 then complete at operation 540 where the TFTs fabricated thus far are interconnected to each other and/or to other components of an IC through one or more metallization levels formed using any suitable BEOL process. At operation 540, MIM trench capacitors may also be formed according to any known technique and TFTs interconnect to such capacitors to form a memory device.

Methods 501 may be employed to fabricate TFT structure 201 (FIG. 2A), TFT structure 202 (FIG. 2B), TFT structure 203 (FIG. 2C), TFT structure 204 (FIG. 2D), or TFT structure 205 (FIG. 2E), for example. FIG. 6A, 6B, 6C, 6D, and 6E illustrate cross-sectional views through a length of TFT structure 201 evolving as operations in methods 501 are practiced, in accordance with some embodiments. As shown in FIG. 6A, a substrate may include gate dielectric 220 disposed over gate electrode 240 embedded in substrate layer 206. As shown in FIG. 6B, a semiconductor layer 110 (e.g., comprising IGZO) is deposited directly on gate dielectric 220, for example with a PLD process. As illustrated in FIG. 6C, thermally conductive dielectric layer 165 (e.g., comprising AlNx or SiCx) is blanket deposited over semiconductor layer 110 and ILD layer 170 is blanket deposited over thermally conductive dielectric layer 165. In some embodiments, thermally conductive dielectric layer 165 is deposited with a low temperature process (e.g., below 350 °C) to facilitate passivation of semiconductor layer 110. In some embodiments, thermally conductive dielectric layer 165 is deposited by PVD, CVD or ALD. In some embodiments, ILD layer 170 is deposited with a higher temperature process (e.g., above 350 °C). In some embodiments, ILD layer 170 is deposited by CVD, PECVD, or with a spin-on/cure process. Source/drain contact openings 620 are then patterned through ILD layer 170 and thermally conductive dielectric layer, for example with any suitable masking and etch process(es). TFT structure 201 is substantially complete as shown in FIG. 6E following a backfilling of the source/drain contact openings with metal(s) suitable for source/drain contacts 260. Source/drain contacts 260 may include one or more metal deposited, for example, by CVD, ALD, physical vapor deposition (PVD), or any technique known to be suitable for the desired metal(s). Alternatively, source/drain contacts 260 may be fabricated prior to deposition of thermally conductive dielectric layer 165 and ILD layer 170. The presence of thermally conductive dielectric layer 165 on sidewalls of source and drain contacts 260 is indicative of such a contact metal-first technique. FIG. 7A, 7B, 7C, 7D, and 7E illustrate cross-sectional views through a length of TFT structure 202 evolving as operations in methods 501 are practiced, in accordance with some embodiments. As shown in FIG. 7A, a substrate may include gate dielectric 220 disposed over gate electrode 240 embedded in substrate layer 206. As shown in FIG. 7B,

semiconductor layer 110 (e.g., comprising IGZO) is deposited directly on gate dielectric 220, for example with a PLD process. Semiconductor layer 110 is then patterned, for example with any known masking and etch process, to form a non-planar semiconductor body. As illustrated in FIG. 7C, thermally conductive dielectric layer 165 (e.g., comprising A1N_X or SiCx) is blanket deposited over semiconductor layer 110, directly contacting sidewalls of the non-planar semiconductor body. In some embodiments, thermally conductive dielectric layer 165 is deposited with a low temperature process (e.g., below 350 °C). As further depicted in FIG. 7D, ILD layer 170 is blanket deposited over thermally conductive dielectric layer 165. In some embodiments, ILD layer 170 is deposited with a higher temperature process (e.g., above 350 °C). Source/drain contact openings 620 are then patterned through ILD layer 170 and thermally conductive dielectric layer 165, for example with any suitable masking and etch process(es). TFT structure 202 is substantially complete as shown in FIG. 7E following a backfilling of source/drain contact openings with metal(s) suitable as source/drain contacts 260. Source/drain contacts 260 may include one or more metal deposited, for example, by CVD, ALD, PVD. Alternatively, source/drain contacts 260 may be fabricated prior to deposition of thermally conductive dielectric layer 165 and ILD layer 170. The presence of thermally conductive dielectric layer 165 on sidewalls of source and drain contacts 260 is indicative of such a technique.

FIG. 8A, 8B, 8C, and 8D illustrate cross-sectional views through a length of TFT structure 203 evolving as operations in methods 501 are practiced, in accordance with some embodiments. As shown in FIG. 8 A, a substrate may include source/drain contacts 260 embedded in substrate layer 206. As shown in FIG. 8B, semiconductor layer 110 (e.g., comprising IGZO) is deposited directly on source/drain contacts 260 and substrate layer 206, for example with a PLD process. Semiconductor layer 110 is then patterned with any known masking and etch process to form a non-planar semiconductor body. As illustrated in FIG. 8C, thermally conductive dielectric layer 165 (e.g., comprising A1N_X or SiCx) is blanket deposited over semiconductor layer 110, directly contacting sidewalls of the non-planar semiconductor body. In some embodiments, thermally conductive dielectric layer 165 is deposited with a low temperature process (e.g., below 350 °C). As further depicted in FIG. 8D, ILD layer 170 is deposited over thermally conductive dielectric layer 165. In some embodiments, ILD layer 170 is deposited with a higher temperature process (e.g., above 350 °C). In some embodiments, ILD layer 170 is deposited by CVD, PECVD, or with a spin- on/cure process. Gate electrode 240 and gate dielectric 220 may be backfilled into an opening patterned in IDL layer 170 and thermally conductive dielectric layer 165. Alternatively, ILD layer 170 may be deposited over a patterned gate electrode 240. ILD layer 170 and gate electrode 240 may be then planarized.

In some gate replacement embodiments, a sacrificial gate material (not depicted) is first deposited over thermally conductive dielectric layer 165. The sacrificial gate material is then patterned into a sacrificial gate mandrel. ILD layer 170 may then be deposited over the sacrificial gate mandrel and planarized with a top surface of the sacrificial gate mandrel. The gate mandrel may then removed to expose thermally conductive dielectric layer 165. In some embodiments, the exposed thermally conductive dielectric layer 165 is then removed from the gate mandrel opening. A replacement gate dielectric and replacement gate electrode may then be deposited within the gate mandrel opening. For such embodiments, the gate dielectric may form a liner (not depicted) within the gate mandrel opening, contacting a sidewall of ILD layer 170 and sidewall of thermally conductive layer 165, as well as contacting the underlying semiconductor. Alternatively, thermally conductive dielectric layer 165 may be deposited over a previously fabricated sacrificial gate mandrel. The thermally conductive layer 165 may then either be etched into a self-aligned spacer or protected by such during subsequent replacement of the sacrificial gate mandrel.

FIG. 9A, 9B, 9C, and 9D illustrate cross-sectional views through a length of TFT structure 204 evolving as operations in methods 501 are practiced, in accordance with some embodiments. As shown in FIG. 9A, a substrate may include only substrate layer 206 (i.e., neither source/drain contacts nor a gate electrode are embedded in substrate layer 206). Thermally conductive dielectric layer 165 (e.g., comprising AINx or SiCx) is blanket deposited over substrate 206. In some embodiments, thermally conductive dielectric layer 165 is deposited with a low temperature process (e.g., below 350 °C). In some embodiments, thermally conductive dielectric layer 165 is deposited by PVD, CVD, or ALD.

Semiconductor layer 110 (e.g., comprising IGZO) is deposited directly on thermally conductive dielectric layer 165, for example with a PLD process. If desired, a second thermally conductive dielectric material (not depicted) may then be deposited over semiconductor layer 110.

As shown in FIG. 9B, a sacrificial gate mandrel 940 is formed over semiconductor layer 110. ILD layer 170 is deposited over mandrel 940 and anisotropically etched into a spacer self-aligned to an edge of gate mandrel 940. As further depicted in FIG. 9C, ILD layer 280 is deposited over semiconductor layer 110, and planarized with a top surface of sacrificial gate mandrel 940. Source/drain contact openings are patterned through ILD layer 270 (and thermally conductive dielectric layer 165, if present), for example with any suitable masking and etch process(es). Before or after formation of source/drain contacts, sacrificial gate mandrel 904 may be removed to expose semiconductor layer 110 and gate dielectric 220 and gate electrode 240 deposited within the gate mandrel opening. For such embodiments, the gate dielectric may form a liner within the gate mandrel opening, contacting a sidewall of ILD layer 170, as well as the underlying semiconductor layer 110. TFT structure 204 is substantially complete as shown in FIG. 9D following a backfilling of source/drain contact openings with metal(s) suitable as source/drain contacts 260.

FIG. 10A, 10B, IOC, and 10D illustrate cross-sectional views through a length of TFT structure 205 evolving as operations in methods 501 are practiced, in accordance with some embodiments. As shown in FIG. 10A, a substrate may include only substrate layer 206 (i.e., neither source/drain contacts nor a gate electrode are embedded in substrate layer 206). Semiconductor layer 110 (e.g., comprising IGZO) is deposited directly on substrate layer 206, for example with a PLD process. Semiconductor layer 110 is then patterned, for example with any known masking and etch process, to form a non-planar oxide

semiconductor body. As illustrated in FIG. 10B, thermally conductive dielectric layer 165 (e.g., comprising A1N_X or SiCx) is blanket deposited over semiconductor layer 110, directly contacting sidewalls of the non-planar semiconductor body. In some embodiments, thermally conductive dielectric layer 165 is deposited with a low temperature process (e.g., below 350 °C). In some embodiments, thermally conductive dielectric layer 165 is deposited by PVD, CVD or ALD. A sacrificial gate mandrel 940 is formed over thermally conductive dielectric layer 165 and an ILD layer 170 is anisotropically etched into a spacer self-aligned to an edge of gate mandrel 940.

As further depicted in FIG. IOC, an ILD layer 280 may be deposited over thermally conductive dielectric layer 165, and planarized with a top surface of sacrificial gate mandrel 940. Source/drain contact openings may then be patterned through ILD layer 280 and thermally conductive dielectric layer 165, for example with any suitable masking and etch process(es). Before or after formation of source/drain contacts, sacrificial gate mandrel 904 may be removed to expose thermally conductive dielectric layer 165 disposed over a channel region of the semiconductor layer 1 10. In some embodiments, the exposed thermally conductive dielectric layer 165 is then removed from the gate mandrel opening. Gate dielectric 220 and gate electrode 240 may then be deposited within the gate mandrel opening. For such embodiments, the gate dielectric may form a liner within the gate mandrel opening, contacting a sidewall of ILD layer 170 and a sidewall of thermally conductive dielectric layer 165, as well as contacting the underlying semiconductor layer 110. TFT structure 205 is substantially complete as shown in FIG. 10D following a backfilling of source/drain contact openings with a metal suitable for source/drain contacts 260.

FIG. 1 1 illustrates a mobile computing platform and a data server machine employing an SoC including TFT structures having a thermally conductive dielectric, for example as described elsewhere herein. The server machine 1 106 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic or MCM IC-eDRAM device further comprising one or more thermally conductive dielectric layers. The mobile computing platform 1105 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1105 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 11 10, and a battery 1115. Disposed within the integrated system 11 10, a substrate 1 160 includes an eDRAM

1 130 and processor circuitry 1 140 (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like). eDRAM 1 130 includes 1C-1TFT cells, with each cell including a BEOL TFT 1 131 and a BEOL capacitor 1 132, for example as described elsewhere herein. For monolithic embodiments, substrate 1 160 is a semiconductor chip. For MCM embodiments, substrate 1 160 may be any package substrate, or an interposer.

Processor circuitry 1140, or a separate RFIC chip may be further coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 1402.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. FIG. 12 is a functional block diagram of an electronic computing device, in accordance with some embodiments. Computing device 1200 may be found inside platform 1105 or server machine 1106, for example. Device 1200 further includes a motherboard 1202 hosting a number of components, such as, but not limited to, a processor 1204 (e.g., an applications processor). Processor 1204 may be physically and/or electrically coupled to motherboard 1202. In some examples, processor 1204 includes an integrated circuit die packaged within the processor 1204. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 1206 may also be physically and/or electrically coupled to the motherboard 1202. In further implementations,

communication chips 1206 may be part of processor 1204. Depending on its applications, computing device 1200 may include other components that may or may not be physically and electrically coupled to motherboard 1202, and/or packaged with processor 1204, and/or monolithically integrated with processor 1204 . These other components include, but are not limited to, volatile memory (e.g., eDRAM that further incorporates at least one oxide semiconductor TFT structure as described elsewhere herein), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips 1206 may enable wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 1206 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1200 may include a plurality of communication chips 1206. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that principles of the disclosure are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

What is claimed is:

1. A thin film transistor (TFT) structure comprising:

a semiconductor material comprising oxygen;

a gate electrode coupled to the semiconductor material through a gate dielectric layer;

source and drain contacts coupled to the semiconductor material on opposite sides of the gate electrode;

an interlay er dielectric (ILD) layer over or under the semiconductor material; and a thermally conductive dielectric layer between the ILD layer and a surface of the

semiconductor material, wherein the thermally conductive dielectric layer has greater thermal conductivity and crystallinity than the ILD layer.

2. The TFT structure of claim 1, wherein the thermally conductive dielectric layer is in direct physical contact with the surface of the semiconductor material.

3. The TFT structure of claim 1, wherein the thermally conductive dielectric layer has a layer thickness of 0.5 nm to 10 nm.

4. The TFT structure of claim 1, wherein the thermally conductive dielectric layer has greater crystallinity than the semiconductor material.

5. The TFT structure of claim 1, wherein the thermally conductive dielectric layer has a thermal conductivity of at least 30 W/m*K.

6. The TFT structure of claim 1, wherein the thermally conductive dielectric layer comprises

AINx, AlOx, A10_xN_y, MoO_x, or SiC_x.

7. The TFT structure of claim 6, wherein the semiconductor comprises ZnOx, and the

thermally conductive dielectric layer comprises A1N_X having a thickness of at least 5 nm, or comprises SiC having a thickness of at least 8 nm.

8. The TFT structure of claim 7, further comprising a metal oxide layer between the thermally conductive dielectric layer and the ILD layer.

9. The TFT structure of claim 8, wherein the metal oxide layer comprises at least one of Ti,

Al, or Hf.

10. The TFT structure of claim 1, wherein:

the semiconductor material comprises a metal oxide including at least one of Cu, Zn, Sn, Ti,

Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo;

the thermally conductive dielectric layer comprises a 0.5 nm to 10 nm thick layer of A1N_X,

AlOx, AlOxNy, MoOx, or SiCx having greater crystallinity than the semiconductor material;

the gate dielectric comprises a metal oxide having a composition different than that of the thermally conductive dielectric layer.

11. The TFT structure of claim 1, wherein the thermally conductive dielectric layer is over a length of the semiconductor material separating the source contact from the drain contact.

12. The TFT structure of claim 1, wherein the semiconductor material is between the gate dielectric and the thermally conductive dielectric layer, with the thermally conductive dielectric layer in contact with a surface of the semiconductor material opposite that contacted by the gate dielectric.

14. An integrated circuit (IC), comprising:

a plurality of n-type fin field effect transistors (finFET) structures and p-type finFET

structures;

one or more metallization levels interconnecting the n-type and p-type finFET structures into CMOS circuitry; and

a plurality of thin film transistor (TFT) structures over the metallization levels, or on a side of a substrate opposite the finFET structures, and interconnected with the CMOS circuitry, wherein each TFT structure further comprises:

a semiconductor material comprising oxygen;

a gate electrode coupled to the semiconductor material through a gate dielectric layer; source and drain contacts coupled to the semiconductor material on opposite sides of the gate electrode;

an interlay er dielectric (ILD) layer over or under the semiconductor material; and a thermally conductive dielectric layer between the ILD layer and a surface of the semiconductor material, wherein the thermally conductive dielectric layer has greater thermal conductivity and crystallinity than the ILD layer.

15. The device of claim 14, wherein:

the thermally conductive dielectric layer has a thermal conductivity of at least 30 W/m*K; individual ones of the FETs comprise a monocrystalline semiconductor channel;

a first of the source or drain of one of the TFT structures is electrically coupled to a capacitor fabricated in the one or more metallization levels;

a second of the source or drain of one of the TFT structures is electrically coupled to a bitline of a memory array; and

the gate electrode of the one of the TFT structures is electrically coupled to a wordline of the memory array.

16. The device of claim 15, wherein the thermally conductive dielectric layer is between the surface of the semiconductor material one of the metallization levels.

17. A computer platform including:

one or more processor; and

the memory device of any one of claims 14-16.

18. A method of fabricating a thin film transistor (TFT) structure, the method comprising: depositing a semiconductor layer over a substrate, the semiconductor layer comprising

oxygen;

forming source and drain contacts to the semiconductor layer on opposite sides of a gate stack, the gate stack including a gate electrode separated from the semiconductor layer by a gate dielectric;

depositing a thermally conductive dielectric layer over the semiconductor layer and adjacent to at least one of the source and drain contacts; and depositing an interlay er dielectric (ILD) layer over the thermally conductive dielectric layer, wherein the thermally conductive dielectric layer has greater thermal conductivity and crystallinity than the ILD layer.

19. The method of claim 18 wherein depositing the thermally conductive dielectric layer comprises depositing a layer of A1N_X, AlOx, A10_xN_y, MoOx, or SiCx onto a surface of the semiconductor layer.

20. The method of claim 19, wherein:

depositing the semiconductor material comprises depositing an amorphous metal oxide

comprising at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo; and depositing the layer of AINx, AlOx, AlOxNy, MoOx, or SiCx comprises depositing a

poly crystalline layer of the A1N_X, AlOx, AlOxNy, MoOx, or SiCx.

21. The method of claim 18, wherein forming the contact metallization further comprises depositing a metal into openings formed in the thermally conductive dielectric layer.

22. A method of fabricating a thin film transistor (TFT) structure, the method comprising: depositing a semiconductor layer over a thermally conductive dielectric layer, the

semiconductor layer comprising oxygen;

forming source and drain contacts to the semiconductor layer on opposite sides of a gate stack, the gate stack including a gate electrode separated from the semiconductor layer by a gate dielectric; and

depositing an interlay er dielectric (ILD) layer over the source and drain contacts, wherein the thermally conductive dielectric layer has greater thermal conductivity and crystallinity than the ILD layer.

23. The method of claim 22, wherein depositing the thermally conductive dielectric layer comprises depositing a layer of A1N_X, AlOx, AlOxNy, MoOx, or SiCx onto a surface of the semiconductor layer.

24. The method of claim 23, wherein:

comprising at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo; and depositing the layer of A1N_X, AlOx, AlOxNy, MoOx, or SiCx comprises depositing a poly crystalline layer of the A1N_X, AlOx, AlOxNy, MoOx, or SiCx.