WO2018009940A1

WO2018009940A1 - Stacked stud bump contacts for wafer test contactors, and associated methods

Info

Publication number: WO2018009940A1
Application number: PCT/US2017/041401
Authority: WO
Inventors: Alistair Nicholas SPORCK; Gary Grube; Morgan T. Johnson
Original assignee: Translarity, Inc.
Priority date: 2016-07-08
Filing date: 2017-07-10
Publication date: 2018-01-11
Also published as: TWI737765B; TW201812311A

Abstract

Systems and methods for testing semiconductor wafers are disclosed herein. In one embodiment, an apparatus for testing dies on a semiconductor wafer includes a test contactor for contacting the dies. The test contactor has a substrate having a wafer-side facing the wafer, and an inquiry-side facing away from the wafer-side. The test contactor also has a wafer-side contact pad carried by the wafer-side of the substrate, and a stud bump pin attached to the wafer-side contact pad. The stud bump pin terminates in a stud bump tip for probing a contact pad of a die.

Description

STACKED STUD BUMP CONTACTS FOR WAFER TEST CONTACTORS, AND

ASSOCIATED METHODS

CROSS-REFERENCE(S) TO RELATED APPLICATION S) This application claims the benefit of U.S. Provisional Application

No. 62/360068, filed July 8, 2016, and U.S. Provisional Application No. 62/436713, filed December 20, 2016, both of which are hereby incorporated by reference in their entirety.

BACKGROUND

Integrated circuits are used in a wide variety of products. Integrated circuits have continuously decreased in price and increased in performance, becoming ubiquitous in modern electronic devices. These improvements in the performance/cost ratio are based, at least in part, on miniaturization, which enables more semiconductor dies to be produced from a wafer with each new generation of the integrated circuit manufacturing technology. Furthermore, the total number of the signal and power/ground contacts on a semiconductor die generally increases with new, more complex die designs.

Prior to shipping semiconductor dies to customers, the performance of the integrated circuits is tested, either based on a statistical sample or by testing each die. An electrical test of the semiconductor die typically includes powering the die through the power/ground contacts, transmitting signals to the input contacts of the die, and measuring the resulting signals at the output contacts of the die. Therefore, during the electrical test at least some contacts on the die must be electrically contacted to connect the die to sources of power and test signals.

Conventional test contactors include an array of contact pins attached to a substrate that can be a relatively stiff printed circuit board (PCB). In operation, the test contactor is pressed against a wafer such that the array of contact pins makes electrical contact with the corresponding array of die contacts (e.g., pads or solderballs) on the dies (i.e., devices under test or DUTs) of the wafer. Next, a wafer tester sends electrical test sequences (e.g., test vectors) through the test contactor to the input contacts of the dies of the wafer. In response to the test sequences, the integrated circuits of the tested die produce output signals that are routed through the test contactor back to the wafer tester for analysis and determination whether a particular die passes the test. Next, the test contactor is stepped onto another die or group of dies that are tested in parallel to continue the testing till the entire wafer is tested. In general, an increasing number of die contacts that are distributed over a decreasing area of the die results in smaller contacts spaced apart by smaller distances (e.g., a smaller pitch). Furthermore, the characteristic diameter of the contact pins of the test contactor generally scales with a characteristic dimension of the contact structures on the semiconductor die or the package. Therefore, as the contact structures on the die become smaller and/or have a smaller pitch, the contact pins of the test contactors become smaller, too. However, it is difficult to significantly reduce the diameter and pitch of the contact pins of the test contactor, e.g., because of the difficulties in machining and assembling such small parts, resulting in low yield and inconsistent performance from one test contactor to another. Additionally, the contact pins of the test contactor can be relatively easily damaged because of their small size. Furthermore, a repetitive application of contact pins of the test contactor over the contact pads of the device under the test may wear out the contact pins.

Accordingly, there remains a need for cost effective test contactors that can scale down in size with the size and pitch of the contact structure on the die.

SUMMARY

The present invention relates generally to equipment for semiconductor wafer test. More particularly, the present invention relates to methods and systems for contacting ("probing") the dies of the semiconductor wafer where the contact pins are constructed from wirebond stud bumps. Furthermore, the present invention relates to plating of the wirebond stud bumps and contact pads.

Briefly described, methods and devices for testing dies on the semiconductor wafers are disclosed. The semiconductor wafers can be produced in different diameters, e.g., 150 mm, 200 mm, 300 mm, 450mm, etc. The disclosed methods and systems enable operators to test the devices having pads, solderballs and/or other contact structures having small sizes and/or pitches. Solderballs, pads, and/or other suitable conductive elements on the dies are collectively referred to herein as "contact pads."

In some embodiments, a wafer-side of the test contactor (e.g., a wafer translator) carries the wafer-side contact structures having relatively small sizes and/or pitches (collectively, "scale"). The wafer-side contact structures of the test contactor are electrically connected to corresponding inquiry-side contact structures that may have relatively larger sizes and/or pitches at the opposite, inquiry-side of the test contactor. Therefore, once the wafer-side contact structures are properly aligned to contact the semiconductor wafers, the larger size/pitch of the opposing inquiry-side contact structures enable more robust contact (e.g., requiring less precision). The larger size/pitch of the inquiry-side contact structures may provide more reliable contact and be easier to align against the pins of the probe card or other contactor. In some embodiments, the inquiry- side contacts may have mm scale, while the wafer-side contacts have sub-mm or μιη scale.

In some embodiments, the contact structures at the wafer-side of the test contactor can be stud bumps made by wirebonding. For example, the wirebonds may be attached to the wafer-side of the test contactor, followed by severing the wirebonds to leave a stud bump on the test contactor (e.g., a wafer translator or another contactor for probing the wafer). In some embodiments, multiple stud bumps are stacked to form a stacked stud bump contact for probing the wafer. In some embodiments, the stud bumps can be shaped and/or sharpened with a shaping wafer.

In some embodiments, the stud bumps may be coated by a material that is relatively resistant to wear (e.g., Platinum-Iridium (Ptlr) alloy). In some embodiments, the contact pads on the space transformer and/or test contactor are coated to improve the resistance against the contact pins (e.g., cobra needle) of the probe card.

DESCRIPTION OF THE DRAWINGS

The aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on clearly illustrating the principles of the present disclosure.

FIGURE 1A is an exploded view of a portion of a test stack for testing semiconductor wafers in accordance with prior art technology.

FIGURE IB is a partially schematic, top view of a wafer translator configured in accordance with prior art technology.

FIGURE 1C is a partially schematic, bottom view of a wafer translator configured in accordance with prior art technology.

FIGURE 2 is a side view of representative contact structures in accordance with prior art technology.

FIGURE 3A is an isometric view of chip wirebonding in accordance with prior art technology.

FIGURE 3B is a side view of chip wirebonding in accordance with prior art technology. FIGURES 4-6 are side, cross-sectional views of test contactors in accordance with embodiments of the presently disclosed technology.

FIGURE 7 is a side, exploded view of a test stack in accordance with an embodiment of the presently disclosed technology.

FIGURE 8 is a side, cross-sectional view of a system for shaping the contact structures in accordance with the embodiments of the presently disclosed technology.

DETAILED DESCRIPTION

Specific details of several embodiments of representative wafer translators and associated methods for use and manufacture are described below. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to Figures 1 A-8.

Figure 1A is an exploded view of a portion of a test stack 100 for testing semiconductor wafers in accordance with prior art technology. The test stack 100 routes signals and power from a tester (not shown) to a wafer or other substrate carrying one or more devices under test (DUTs), and transfers the output signals from the DUTs (e.g., semiconductor dies) back to the tester for analysis and determination about an individual DUT's performance (e.g., whether the DUT is suitable for packaging and shipment to the customer). The signals and power from the tester are routed through a test contactor 30 to a wafer translator 10, and further to the semiconductor dies on the wafer 20.

The signals and power are routed from the tester to the test contactor 30 using cables 39. Conductive traces 38 carried by a test contactor substrate 32 can electrically connect the cables 39 to contacts 36 on the opposite side of the test contactor substrate 32. In operation, the test contactor 30 can contact an inquiry-side 13 of a wafer translator 10 as indicated by arrows A. In at least some embodiments, relatively large inquiry-side contact structures 14 can improve alignment with the corresponding contacts 36 of the test contactor 30. The contact structures 14 at the inquiry-side 13 are electrically connected with relatively small wafer-side contact structures 16 on a wafer- side 15 of the translator 10 through conductive traces 18 of a wafer translator substrate 12. The size and/or pitch of the wafer-side contact structures 16 are suitable for contacting the corresponding die contacts 26 of the wafer 20. Arrows B indicate a movement of the wafer translator 10 to make contact with an active side 25 of the wafer 20. As explained above, the signals and power from the tester can test the DUTs of the wafer 20, and the output signals from the tested DUTs can be routed back to the tester for analysis and a determination as to whether the DUTs are suitable for packaging and shipment to the customer.

A wafer chuck 40 supports the wafer 20. Arrows C indicate the direction of the wafer 20 mating with the wafer chuck 40. In operation, the wafer 20 can be held against the wafer chuck 40 using, e.g., vacuum V or mechanical clamping.

Figures IB and 1C are partially schematic, top and bottom views, respectively, of a wafer translator configured in accordance with embodiments of the presently disclosed technology. Figure IB illustrates the inquiry-side 13 of the wafer translator 10. Distances between the adjacent inquiry-side contact structures 14 (e.g., pitch) are denoted Pi in the horizontal direction and P₂ in the vertical direction. The illustrated inquiry-side contact structures 14 have a width Di and a height D₂. Depending upon the embodiment, the inquiry-side contact structures 14 may be squares, rectangles, circles or other shapes. Furthermore, the inquiry-side contact structures 14 can have a uniform pitch (e.g., Pi and P₂ being equal across the wafer translator 10) or a non-uniform pitch.

Figure 1C illustrates the wafer-side 15 of the wafer translator 10. In some embodiments, the pitch between the adjacent wafer-side contact structures 16 can be pi in the horizontal direction and p₂ in the vertical direction. The width and height of the wafer-side contact structures 16 ("characteristic dimensions") are denoted as di and d₂. In some embodiments, the wafer-side contact structures 16 can be pins that touch corresponding die contacts on the wafer 20. Such pins are described in more details in Figure 2 below. In general, the size/pitch of the inquiry-side contact structures 14 is larger than the size/pitch of the wafer-side contact structures 16, therefore improving alignment and contact between the test contactor and the wafer translator. The individual dies of the wafer 20 are typically separated from each other by wafer streets 19.

Figure 2 is a side view of representative contact structures 16 in accordance with prior art technology. In one example, the contact structure 16 has a crown tip 16a for contacting the solderball 26a on the wafer or on the singulated die. In another example, the contact structure 16 has a conical tip 16b for contacting a relatively flat contact 26b on the wafer or on the singulated die. Generally, the tips 16a/16b may wear out relatively quickly, therefore limiting performance of the contact structures 16. Figure 3A is an isometric view of chip wirebonding in accordance with prior art technology. Figure 3A shows a substrate (e.g., a PCB) 50 that carries semiconductor dies 20a and 20b, where one semiconductor die 20a is disposed over two semiconductor dies 20b. Each semiconductor die 20a, 20b has arrays of the die contact pads 26 at the periphery. The die contact pads 26 are connected to the corresponding substrate contact pads 56 with the bonding wires (wirebonds) 55. In operation, the wirebonds 55 transfer power and signals between the dies and the substrate 50.

Figure 3B is a side view of chip wirebonding in accordance with prior art technology. In operation, a wirebonder 60 dispenses the bonding wire 55 from a bonding needle 55t (also referred to as a "capillary"). The tip of the bonding wire 55 can be melted by electrical arc or by ultrasound. Melted bonding wire 55 forms a ball because of the surface tension of the molten metal in the ball. This molten ball is then attached to the die contact pad 26 as a stud bump 54 to form permanent electrical contact with the die 20. Next, the opposite side of the bonding wire 55 is bonded to a contact pad 56 on the substrate 50, thus establishing electrical connection from the die 20 to the substrate 50 and further to other elements of the system (e.g., power supply, source of signals, etc.). The wirebonding process can continue to the next pair of contact pads 26/56, till the die contact pads 26 of the die 20 are completely wirebonded to the substrate 50.

Figure 4 is a side, cross-sectional view of a test contactor 100 in accordance with embodiments of the presently disclosed technology. In some embodiments, the test contactor 1000 may be a translator having smaller pitch/size of the contacts at the wafer- side, and larger pitch/size of the contacts on the inquiry-side. In some embodiments, the test contactor 1000 includes a substrate 120 (e.g., a PCB or ceramic board) having a wafer-side 150 and an inquiry-side 130. In general, the inquiry-side 130 can be connected to the tester (not shown) that has sources of power/signal and/or instruments for signal measurements. In some embodiment, vias 180 electrically connect contact pads 260 at the wafer-side 150 to the contact pads 140. The substrate 120 may also include one or more routing layers 181 for electrical traces that interconnect the contact pads 260/140. In some embodiments, stud bump pins 160 (also referred to as the wafer- side contact structure 160) are formed on the contact pads 260 from the wirebond. For example, a stud bump may be formed from the wirebond, followed by attaching the stud bump onto the contact pad 260, and removing the excess wirebond to form the stud bump pins 160 on the contact pad 260. In some embodiments, as the excess wirebond is removed (e.g., by pulling, repeatedly bending, or heating the wirebond 55), a stud bump tip 161 is formed as a narrowed portion at the periphery of the stud bump pin 160. As the wafer-side 150 of the test contactor 100 makes contact with the dies on the wafer, the stud bump tips 161 may provide more precise contact with the contact pads on the wafer and better removal of the surface oxides on the contact pads. In some embodiments, the resistance and inductance of the stud bump pin 160 is relatively low because of its shape (e.g., being relatively bulky and not long/slander) and size (e.g., having relatively large cross-section). In some embodiments, the stud bump pin 160 may be made of copper or copper-alloy wirebond.

Figure 5 is a side, cross-sectional view of the test contactor 1000 in accordance with embodiments of the presently disclosed technology. In some embodiments, the stud bump pins 160-i may be stacked on the contact pads 260. For example, two stud bump pins 160-1 and 160-2 may form a stack 160S. In some embodiments, the stud bump pins 160-i may be formed by successively forming individual stud bump pins 160-i on top of each other. In some embodiments, the stud bump pins 160-i may be pre-formed away from the test contactor 1000, and then stacked on the contact pads 260 by, for example, heating the stud bump pins 160-i to about their melting point, and then stacking them on top of each other.

Figure 6 is a side, cross-sectional view of the test contactor 1000 in accordance with embodiments of the presently disclosed technology. In some embodiments, the stacks of the stud bump pins 160 may include two, three, four or more stud bump pins to achieve required height of the stack 160S. In some embodiments, the last stud bump pin 160 in the stack 160S ends in the stud bump tip 161 that contacts the contact pads on the wafer.

FIGURE 7 is a side, exploded view of a test stack 2000 in accordance with an embodiment of the presently disclosed technology. The illustrated test stack 2000 includes the wafer chuck 40 that carries the wafer 20. The active side 25 of the wafer 20 (i.e., the side that carries the dies) faces the wafer-side 150 of the test contactor 1000, and a probe card 300 faces the inquiry-side 130 of the test contactor 1000. The test stack 2000 may be electrically connected through the tester cable 39 with the tester (not shown). In operation, the signals/power from the tester propagate through a space transformer 330 and contact pins 310 (also referred to as needle pins or cobra pins), and further through the contactor 100 to the wafer 20. The dies of the wafer 20 respond to the input signals/power from the tester by producing output signals that are routed back to the tester for the determination whether a particular die operates according to the specification or not. In some embodiments, all or most of the dies on the wafer may be contacted and tested in parallel. In other embodiments, a single die or groups of dies (e.g., two, three, four dies) may be contacted and tested in parallel.

In many embodiments, the test contactor 1000 may be reused over multiple wafers 25, therefore subjecting the stack 160-S to wearout. In some embodiments, the stack 160S may be plated with a plating 170 to, for example, improve the wearout resistance of the stack, reduce corrosion, change hardness of the material of the stack, etc. In some embodiments, a platinum-iridium (Ptlr) plating 170 may be deposited over the stack 160-S by electrolysis or by ion sputtering. In some embodiments, the plating 170 may include hard noble materials like rhodium, platinum, iridium, palladium, ruthenium, osmium, and/or their alloys. In some embodiments, the plating 170 may be about 10 μπι thick. In some embodiments, the plating may extend to the contact pad 260.

In some embodiments, the contact pins (e.g., cobra pins) 310 are kept in place by a first guide plate 321 and a second guide plate 322. When the contact pin 310 touches the inquiry-side of the test contactor 1000, the tip of the contact pin 310 typically slightly digs into the contact pad, and then slides horizontally across the contact pad. This motion of the tip of the contact pin 310 with respect to the contact pad is sometimes called "scrub." Multiple scrubs on the contact pad 140 of the contactor 100 may lead to excessive abrasion of the material of the contact pad and/or accumulation of the material of the contact pad over the contact pin 310. In some embodiments, a plating 370 may be placed over the contact pads 140 to reduce the abrasion/skratching of the contact pad 140. Furthermore, the plating 370 may be placed over the contact pads 340 of the space transformer 330 to protect the contact pads 340 from abrasion/skratching. In some embodiments, the plating 370 may be flattened stud bump made of Ptlr alloy. For example, a stud bump may be first made following the process that is analogous to that described with reference to Figure 4. Next, the stud bump may be flattened by, for example, forging, rolling, or smashing the stud bump. Once the stud bump is flattened into the plating 370, it can be attached to the contact pads 340 or 140. In some embodiments, the plating 170/370 may be deposited by electrolysis or by ion sputtering. In some embodiments, the contact pads 140 are made of copper or aluminum. Figure 8 is a side, cross-sectional view of a system for shaping the contact structures in accordance with the embodiments of the presently disclosed technology. In some embodiments, the system includes the test contactor 100 and a shaping wafer 500. In some embodiments, the shaping wafer 500 repeatedly contacts the stacks 160-S to shape them. The test contactor 100, or the shaping wafer 500, or both may be moved into contact in a Z-direction shown by a coordinate system CS by one or more actuators (not shown). The actuation may be provided by pressure driven actuators, electrical motors, or other actuators. In some embodiments, the movement of the wafer translator 10 and/or the shaping wafer 500 may be limited to control the shaping of the stacks 160- S. For example, the test contactor 100 may be moved into a position Z for cycles, followed by forcing the test contactor 100 into a position Z₂ for N₂ cycles, where Z₂ is greater than Z . In some embodiments, and/or N₂ may be several hundred or several thousand cycles.

As a result of the repeated contacts between sides and/or tips of the stacks 160-S against side surfaces 510 the shaping wafer 500, the stacks 160-S are shaped to approximate the shape of the cavities formed by the surfaces 510. In at least some embodiments, such shaping of the tips/sides of the stacks 160-S may bring the stacks 160-S back to their within-specification dimensions. For example, the previously out-of-specification stacks 160-S with an out-of-specification pitch pi may become suitable again for testing semiconductor dies on a production wafer by shaping the stacks 160-S back to within-the-specification pitch p₂. Analogously, the out-of- specification height or width of the stacks 160-S may be brought to within-the- specification by shaping the stacks 160-S with the shaping wafer 500. In some embodiments, the shaping of the stacks 160-S may include abrasion or plastic deformation of the stacks 160-S. In some embodiments, a single stud bump pin 160 may be used in place of a stack 160-S. In some embodiments, the stacks 160S or the stud bump pins 160 may include plating 170. The repetitive contacts between the stacks 160-S or the stud bump pins 160 and the shaping wafer 500 may be termed coining or forging of the contact structures.

In some embodiments, the shaping wafer 500 can be made of silicon or metals.

The side surfaces 510 may be made by, for example, lithographically defined etching. Since the location precision is defined by the precision of a lithographic mask over the shaping wafer 500, the resulting location precision of the side surfaces 510 is also relatively high. In at least some embodiments, the precision of the location of the side surfaces 510 (e.g., tolerances) generally corresponds to the precision of the location of the die contacts 26.

Many embodiments of the technology described above may take the form of computer- or controller-executable instructions, including routines executed by a programmable computer or controller. Those skilled in the art will appreciate that the technology can be practiced on computer/controller systems other than those shown and described below. The technology can be embodied in a special-purpose computer, controller, or data processor that is specifically programmed, configured, or constructed to perform one or more of the computer-executable instructions described below. Accordingly, the terms "computer" and "controller" as generally used herein refer to any data processor and can include Internet appliances and hand-held devices (including palm-top computers, wearable computers, cellular or mobile phones, multi-processor systems, processor-based or programmable consumer electronics, network computers, mini computers and the like). Information handled by these computers can be presented by any suitable display medium, including a CRT display or LCD.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Moreover, while various advantages and features associated with certain embodiments have been described above in the context of those embodiments, other embodiments may also exhibit such advantages and/or features, and not all embodiments need necessarily exhibit such advantages and/or features to fall within the scope of the technology. Accordingly, the disclosure can encompass other embodiments not expressly shown or described herein.

Claims

CLAIMS The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus for testing dies of a semiconductor wafer, comprising:

a test contactor configured to contact the dies, comprising:

a substrate having a wafer-side configured to face the wafer, and an inquiry-side facing away from the wafer-side;

a wafer-side contact pad carried by the wafer-side of the substrate; and a stud bump pin attached to the wafer-side contact pad, wherein the stud bump pin terminates in a stud bump tip configured to probe a contact pad of a die.

2. The apparatus of Claim 1, wherein the stud bump pin is a first stud bump pin and the stud bump tip is a first stud bump tip, the apparatus further comprising a second stud bump pin stacked over the first stud bump pin, wherein the second stud bump pin terminates in a second stud bump tip configured to probe the contact pad of the die.

3. The apparatus of Claim 2, wherein the first and second stud bump pins form a stack of stud bump pins, the apparatus further comprising a plurality of stacks of stud bump pins configured to probe contact pads of dies.

4. The apparatus of Claim 3, wherein the test contactor is configured to contact all or most of the dies on the wafer in parallel.

5. The apparatus of Claim 3, further comprising a plurality of inquiry-side contact pads carried by the test contactor, wherein the stacks of stud bump pins have a first scale, wherein the inquiry-side contact structures have a second scale, and wherein the first scale is smaller than the second scale.

6. The apparatus of Claim 1, wherein the stud bump pin is plated with a stud bump pin plating.

7. The apparatus of Claim 6, wherein the stud bump pin plating is a Platinum Iridium (Ptlr) plating.

8. The apparatus of Claim 7, wherein the stud bump pin plating is about 10 μπι thick.

9. The apparatus of Claim 1, further comprising:

an inquiry-side contact pad carried by the inquiry-side of the substrate; and an inquiry-side contact pad plating disposed over the inquiry-side contact pad, wherein the plating is a Platinum Iridium (Ptlr) plating.

10. The apparatus of Claim 1, further comprising:

a probe card comprising:

a plurality of contact pins, wherein individual contact pins have a first end configured to contact the inquiry-side of the test contactor, and a second end configured to contact a contact pad of a space transformer; and

the space transformer that carries a plurality of the contact pads facing the second end of the contact pins; and

a plating over the contact pads of the space transformer.

11. The apparatus of Claim 10, wherein the plating over the contact pads of the space transformer is a Platinum Iridium (Ptlr) plating.

12. The apparatus of Claim 1, further comprising:

a shaping wafer, comprising:

a shaping wafer substrate, and

a plurality of cavities in the shaping wafer substrate, wherein individual cavities face individual stud bump pins of the test contactor, and wherein the individual stud bump pins are shaped by surfaces of the cavities of the shaping wafer substrate.

13. The apparatus of Claim 12, wherein the stud bump pins are shaped by abrasion or by plastic deformation.

14. The apparatus of Claim 11, wherein the shaping wafer substrate comprises silicon.

15. A method for testing a semiconductor wafer, comprising:

contacting a die on the semiconductor wafer with a wafer-side of a test contactor, wherein the test contactor includes a stud bump pin attached to a contact pad at the wafer- side, and wherein the stud bump pin terminates in a stud bump tip that probes a contact pad of a die.

16. The method of Claim 15, wherein the stud bump pin is plated with a Platinum Iridium (Ptlr) plating.

17. The method of Claim 15, further comprising:

contacting a contact pad on an inquiry-side of the test contactor with a probe card, wherein the inquiry-side of the test contactor faces away from the wafer-side of the test contactor, and wherein the contact pad on the inquiry-side of the test contactor is plated with a plating.

18. The method of Claim 17, wherein the wafer-side of the test contactor carries stud bump pins having a first scale, and the inquiry-side of the wafer translator carries the contact pads having a second scale, and wherein the first scale is smaller than the second scale.

19. The method of Claim 17, further comprising testing the dies on the semiconductor wafer.

20. The method of Claim 17, wherein the probe card includes:

a plurality of contact pins, wherein individual contact pins have a first end configured to contact the inquiry-side of the test contactor, and a second end configured to contact a contact pad of a space transformer;

a plating over the contact pads of the space transformer.

21. The method of Claim 20, wherein the plating over the contact pads of the space transformer is a Platinum Iridium (Ptlr) plating.

22. The method of Claim 15, wherein the stud bump pin is a first stud bump pin having a first stud bump tip, the apparatus further comprising a second stud bump pin stacked over the first stud bump pin, wherein the second stud bump pin terminates in a second stud bump tip configured to probe the contact pad of the die.

23. The method of Claim 15, further comprising:

shaping the stud bump pin by:

aligning the test contactor and a shaping wafer, wherein the stud bump pin faces a cavity of the shaping wafer;

repeatedly contacting the stud bump pin by surfaces of the cavity of the shaping wafer; and

shaping the stud bump pin into a within-specification value by abrasion or plastic deformation of the stud bump pin.

24. The method of Claim 23, further comprising:

moving the test contactor into a position Z for cycles; and

moving the test contactor into a position Z₂ for N₂ cycles, wherein Z₂ is greater than Z .