WO2018000927A1 - 像素电路、半导体摄像头检测电路以及显示装置 - Google Patents
像素电路、半导体摄像头检测电路以及显示装置 Download PDFInfo
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Definitions
- the present disclosure relates to a pixel circuit, a semiconductor camera detection circuit, and a display device.
- CMOS Complementary Metal-Oxide Semiconductor
- APS Active Pixel Sensor
- the APS pixel circuit is composed of a switching transistor T1, a switching transistor T3, a driving transistor T2, and a photodiode PD, and the driving transistor T2 functions as a source follower.
- the switching transistor T1 is turned on under the control of an initialization signal (Reset) input to the initialization signal terminal, and the photodiode PD is reverse biased to a voltage Vrst, and the voltage Vrst charges the PN junction capacitance of the photodiode PD.
- the photon excitation When the incident light is irradiated on the PN junction of the photodiode PD, the photon excitation generates an electron-hole pair on the PN junction, recombining the charge on the PN junction capacitance, so that the gate potential of the driving transistor T2 is lowered. Finally, the switching transistor T3 is turned on, and the magnitude of the photocurrent at this time is confirmed by the output signal line 10. Based on the actual measured photocurrent, the illumination before the current lens is finally confirmed.
- the current read by the output signal line 10 is related to the threshold voltage of the driving transistor T2, and in the actual manufacturing process, the driving transistor T2 will be processed due to the process and long-term operation.
- the threshold voltage Vth of the driving transistor T2 is caused to drift, so that the magnitude of the final output current differs from the magnitude of the current generated after the actual illumination to the photodiode PD, thereby causing distortion of the display image.
- the drift of the threshold voltage of the driving transistor causes a difference in the magnitude of the output current and the magnitude of the current generated by the actual illumination.
- a pixel circuit provided by an embodiment of the present disclosure includes: a photodiode, a driving module, and an initial a initialization module, a transmission module, a voltage writing module, and a compensation module;
- One end of the photodiode is electrically connected to the ground end, and the other end is electrically connected to the transmission module;
- the initialization module is electrically connected to the initialization signal terminal and the initialization voltage terminal, and is configured to pull the voltage of the first node to the initialization voltage input by the initialization voltage terminal under the control of the initialization signal terminal;
- the transmission module is electrically connected to the initialization module and the first scan signal end, and configured to pull the voltage of the first node from the initialization voltage to a data voltage under the control of the first scan signal end Wherein the value of the data voltage decreases as the intensity of illumination received by the photodiode increases;
- the voltage writing module is electrically connected to the first node, the driving module, the compensation module, the grounding end, and the second scanning signal end, and is configured to: under the control of the second scanning signal end, Writing, by the driving module, the data voltage; and outputting a ground voltage to the compensation module;
- the compensation module is electrically connected to the driving module, the high voltage level signal end, the compensation signal end and the second scan signal end, and is configured to be under the control of the compensation signal end and the second scan signal end Performing threshold voltage compensation on the driving module;
- the first node is an intersection of the initialization module, the transmission module, and the voltage writing module.
- the compensation module includes a first capacitor, a first switching transistor, a second switching transistor, and an inverter;
- One end of the first capacitor is electrically connected to the voltage writing module, and the other end is electrically connected to the driving module;
- the gate of the first switching transistor is electrically connected to the compensation signal end, and the other two poles are respectively electrically connected to the high voltage level signal end and the driving module;
- One end of the inverter is electrically connected to the second scan signal end, and the other end is electrically connected to a gate of the second switch transistor;
- the other two poles of the second switching transistor are electrically connected to the voltage writing module and the driving module, respectively.
- the initialization module includes a third switching transistor and a second capacitor
- One end of the second capacitor is electrically connected to the first node, and the other end is electrically connected to the ground end;
- a gate of the third switching transistor is electrically connected to the initialization signal terminal, and the other two poles are respectively And the initialization voltage terminal and the first node are electrically connected.
- the transmission module includes a fourth switching transistor, a gate of the fourth switching transistor is electrically connected to the first scanning signal terminal, and the other two poles are electrically connected to the photodiode and the first node, respectively.
- the voltage writing module includes a fifth switching transistor, a sixth switching transistor, and a seventh switching transistor;
- a gate of the fifth switching transistor is electrically connected to the second scan signal end, and the other two poles are respectively electrically connected to the ground end and the compensation module;
- the gate of the sixth switching transistor is electrically connected to the second scanning signal end, and the other two poles are electrically connected to the first node and the driving module respectively;
- the gate of the seventh switching transistor is electrically connected to the second scan signal end, and the other two poles are electrically connected to the ground end and the driving module respectively.
- the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, the sixth switching transistor, and the seventh switching transistor are P-type thin film transistors.
- the driving module includes a driving transistor, a gate of the driving transistor is electrically connected to the compensation module and the voltage writing module, a source is electrically connected to the compensation module, and a drain and the voltage are written.
- the input module and the output signal line are electrically connected.
- the drive transistor is a P-type thin film transistor.
- Embodiments of the present disclosure also provide a semiconductor camera detection circuit including the above-described pixel circuit.
- Embodiments of the present disclosure also provide a display device including the above-described semiconductor camera detection circuit.
- FIG. 1 is a schematic circuit diagram of a prior art pixel circuit
- FIG. 2 is a schematic structural diagram of a module of a pixel circuit according to an embodiment of the present disclosure
- FIG. 3 is a schematic structural diagram of a specific circuit of a pixel circuit according to an embodiment of the present disclosure
- FIG. 4 is a timing chart of the pixel circuit shown in FIG. 3;
- FIG. 5 is a schematic circuit diagram of a working principle of a pixel circuit in different working stages according to an embodiment of the present disclosure.
- Embodiments of the present disclosure provide a pixel circuit, a semiconductor camera detection circuit, and a display device for solving a problem in that a magnitude of an output current due to a shift in a threshold voltage of a driving transistor and a magnitude of a current generated by actual illumination are different.
- an embodiment of the present disclosure provides a pixel circuit including: a photodiode PD, a driving module 23, an initialization module 20, a transmission module 21, a voltage writing module 22, and a compensation module 24;
- One end of the photodiode PD is electrically connected to the ground end, and the other end is electrically connected to the transmission module 21;
- the initialization module 20 is electrically connected to the initialization signal terminal (the initialization signal Reset of the corresponding pixel circuit) and the initialization voltage terminal (the initialization voltage Vcom of the corresponding pixel circuit), and is configured to pull the voltage of the first node N1 under the control of the initialization signal terminal.
- Initialization voltage Vcom input to the initialization voltage terminal;
- the transmission module 21 is electrically connected to the initialization module 20 and the first scan signal end (the first scan signal Scan1 corresponding to the pixel circuit), and is configured to pull the voltage of the first node N1 from the initialization voltage under the control of the first scan signal end. As low as the data voltage; the value of the data voltage decreases as the light intensity received by the photodiode PD increases;
- the voltage writing module 22 is electrically connected to the first node N1, the driving module 23, the compensation module 24, the grounding end, and the second scanning signal end (the second scanning signal Scan2 corresponding to the pixel circuit), and is configured to: Under the control of the second scanning signal end, the data voltage is written to the driving module 23; and the ground voltage is output to the compensation module 24;
- the compensation module 24 and the driving module 23 the high voltage level signal end (corresponding to the high voltage level signal VDD), the compensation signal end (the compensation signal EM corresponding to the pixel circuit), and the second scanning signal end (the second scan corresponding to the pixel circuit)
- the signal Scan2 is electrically connected, and is configured to perform threshold voltage compensation on the driving module 23 under the control of the compensation signal end and the second scanning signal end;
- the first node N1 is an intersection of the initialization module 20, the transmission module 21, and the voltage writing module 22.
- the first node N1 is an intersection when the initialization module 20, the transmission module 21, and the voltage writing module 22 are electrically connected to each other.
- the driving module 23 in the embodiment of the present disclosure includes a driving transistor DTFT.
- the gate of the driving transistor DTFT is electrically connected to the compensation module 24 and the voltage writing module 22, and the source is electrically connected to the compensation module 24.
- the drain is electrically connected to the voltage writing module 22 and the output signal line 10.
- the driving transistor DTFT in the specific embodiment of the present disclosure is a P-type thin film transistor.
- the compensation module 24 in the specific embodiment of the present disclosure includes a first capacitor C1, a first switching transistor T1, an inverter M, and a second switching transistor T2;
- One end of the first capacitor C1 is electrically connected to the voltage writing module 22, and the other end is electrically connected to the driving module 23;
- the gate of the first switching transistor T1 is electrically connected to the compensation signal terminal (compensation signal EM corresponding to the pixel circuit), and the other two electrodes are electrically connected to the high voltage level signal terminal (corresponding to the high voltage level signal VDD) and the driving module 23, respectively.
- One end of the inverter M is electrically connected to the second scan signal end (the second scan signal Scan2 corresponding to the pixel circuit), and the other end is electrically connected to the gate of the second switch transistor T2;
- the other two poles of the second switching transistor T2 are electrically connected to the voltage writing module 22 and the driving module 23, respectively.
- the initialization module 20 in the specific embodiment of the present disclosure includes a third switching transistor T3 and a second capacitor C2;
- One end of the second capacitor C2 is electrically connected to the first node N1, and the other end is electrically connected to the ground end;
- the gate of the third switching transistor T3 is electrically connected to the initialization signal terminal (the initialization signal Reset of the corresponding pixel circuit), and the other two electrodes are electrically connected to the initialization voltage terminal (the initialization voltage Vcom of the corresponding pixel circuit) and the first node N1, respectively.
- the transmission module 21 in the specific embodiment of the present disclosure includes a fourth switching transistor T4, a gate of the fourth switching transistor T4 and a first scanning signal end (corresponding to the first scanning signal Scan1 of the pixel circuit) Electrically connected, the other two poles are electrically connected to the photodiode PD and the first node N1, respectively.
- the voltage writing module 22 in the specific embodiment of the present disclosure includes a fifth switching transistor T5, a sixth switching transistor T6, and a seventh switching transistor T7;
- the gate of the fifth switching transistor T5 is electrically connected to the second scanning signal end (the second scanning signal Scan2 corresponding to the pixel circuit), and the other two electrodes are electrically connected to the grounding end and the compensation module 24 respectively;
- the gate of the sixth switching transistor T6 is electrically connected to the second scanning signal end (the second scanning signal Scan2 corresponding to the pixel circuit), and the other two poles are electrically connected to the first node N1 and the driving module 23 respectively;
- the gate of the seventh switching transistor T7 is electrically connected to the second scanning signal terminal (the second scanning signal Scan2 corresponding to the pixel circuit), and the other two electrodes are electrically connected to the ground terminal and the driving module 23, respectively.
- the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, and the seventh switching transistor T7 are both It is a P-type thin film transistor.
- the P-type thin film transistor When the gate of the P-type thin film transistor is loaded with a low voltage, the P-type thin film transistor is turned on.
- the switching transistor in the specific embodiment of the present disclosure may also adopt an N-type thin film transistor or a hybrid design of a P-type thin film transistor and an N-type thin film transistor.
- the source of the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, and the seventh switching transistor T7 The drains are interchangeable depending on the type of switching transistor and the signal at the signal end, and no specific distinction is made here.
- the initialization signal Reset is at a low level; the first scan signal Scan1, the second scan signal Scan2, and the compensation signal EM are both at a high level; at this time, the first in FIG.
- the three-switch transistor T3 is turned on; the first switching transistor T1, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, and the seventh switching transistor T7 are all turned off; in addition, because the second switching transistor T2 is inverted
- the device M is connected, and the signal applied to the gate of the second switching transistor T2 is at a low level, and therefore, the second switching transistor T2 is also in an on state.
- the simplified circuit diagram of FIG. 3 is as shown in FIG. 5.
- the third switching transistor T3 in the open state is replaced by a conductive line, and the generated current direction is indicated by the direction of the arrow in the figure.
- the voltage of a node N1 is pulled to the initialization voltage Vcom of the initialization voltage terminal input.
- the value of the initialization voltage Vcom can be set according to the needs of the actual circuit.
- the purpose of the pixel circuit in the first embodiment of the present disclosure is to reset the previous voltage signal.
- the first scan signal Scan1 is at a low level; the initialization signal Reset, the second scan signal Scan2, and the compensation signal EM are both at a high level; at this time, the first in FIG.
- the four-switching transistor T4 is turned on; the first switching transistor T1, the third switching transistor T3, the fifth switching transistor T5, the sixth switching transistor T6, and the seventh switching transistor T7 are all turned off; in addition, because the second switching transistor T2 is inverted
- the device M is connected, and the second switching transistor T is in an open state.
- the simplified circuit diagram of Fig. 3 is as shown in Fig. 6.
- the fourth switching transistor T4 in the open state is replaced by a conducting straight line, and the generated current direction is indicated by the direction of the arrow in the figure.
- the photon excitation generates an electron-hole pair on the PN junction, causing the charges on the PN junction capacitance to recombine, so that the voltage of the first node N1 is lowered.
- the voltage of the first node N1 is lowered from the initialization voltage Vcom to the data voltage Vdata, and is stored at the first node N1 at one end of the second capacitor C2.
- the value of the data voltage Vdata of the first node N1 stored at one end of the second capacitor C2 decreases as the light intensity received by the photodiode PD increases.
- the second scan signal Scan2 and the compensation signal EM are at a low level; the first scan signal Scan1 and the initialization signal Reset are at a high level; at this time, the first in FIG.
- the switching transistor T1, the fifth switching transistor T5, the sixth switching transistor T6, and the seventh switching transistor T7 are both turned on; the third switching transistor T3 and the fourth switching transistor T4 are both turned off; in addition, because the second switching transistor T2 is inverted
- the device M is connected, so that the second switching transistor T2 is turned off.
- the simplified circuit diagram of FIG. 3 is as shown in FIG. 7, in which the first switching transistor T1, the fifth switching transistor T5, the sixth switching transistor T6, and the seventh switching transistor T7 in the open state are turned on. Instead, the resulting current direction is indicated by the direction of the arrow in the figure.
- the data voltage Vdata is written to the drive module 23, that is, the voltage of the second node N2 in the specific embodiment of the present disclosure is the data voltage Vdata.
- one end of the first capacitor C1 is grounded, the voltage is, for example, 0V, and the other end is connected to the high voltage level signal end (corresponding to the high voltage level signal VDD), and the voltage is the high level voltage Vdd.
- the second scan signal Scan2 is at a low level; the initialization signal Reset, the first scan signal Scan1, and the compensation signal EM are both at a high level; at this time, the first in FIG.
- the fifth switching transistor T5, the sixth switching transistor T6 and the seventh switching transistor T7 are both turned on; the first switching transistor T1, the third switching transistor T3 and the fourth switching transistor T4 are both turned off; in addition, due to the second switching transistor T2 and the opposite The phase switch M is connected, so that the second switching transistor T2 is turned off.
- the simplified circuit diagram of FIG. 3 is as shown in FIG. 8.
- the fifth switching transistor T5, the sixth switching transistor T6 and the seventh switching transistor T7 in the open state are replaced by a conducting straight line, and the generated current direction is generated.
- the first capacitor C1 is discharged. Since the voltage of the second node N2 is Vdata, the voltage of the a terminal after the discharge of the first capacitor C1 is Vdata+Vth, and Vth is the threshold voltage of the driving transistor DTFT.
- the b-end of the first capacitor C1 is grounded, and the voltage at the b-side is 0V. At this time, the voltage difference across the first capacitor C1 is Vdata+Vth.
- the compensation signal EM is at a low level; the initialization signal Reset, the first scan signal Scan1, and the second scan signal Scan2 are both at a high level; at this time, the first in FIG. a switching transistor T1 is turned on; the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, and the seventh switching transistor T7 are both turned off; in addition, because the second switching transistor T2 is inverted
- the device M is connected, so that the second switching transistor T2 is turned on.
- FIG. 9 The simplified circuit diagram of Fig. 3 in the Vth stage is shown in Fig. 9.
- the first switching transistor T1 in the open state is replaced by a conducting straight line, and the generated current direction is indicated by the direction of the arrow in the figure.
- the a terminal of the first capacitor C1 is connected to the high voltage level signal terminal (corresponding to the high voltage level signal VDD), and the voltage is the high level voltage Vdd;
- the b terminal of the first capacitor C1 is floating, due to the first capacitor C1 should maintain the original differential pressure, so an isobaric jump occurs.
- Vdd-Vdata-Vth that is, the voltage of the second node N2 is Vdd-Vdata-Vth.
- the magnitude of the current output to the output signal line 10 is:
- K is a preset constant and V GS is the gate-to-source voltage difference of the driving transistor DTFT.
- the operating current I is not affected by the threshold voltage Vth of the driving transistor DTFT, and Vdata is generated by the photodiode illumination, which solves the threshold voltage generated by the driving transistor due to the process and long-term operation. Drift problem, so it can help Reimbursement, so as to ensure the accuracy of the signal data.
- a specific embodiment of the present disclosure further provides a semiconductor camera detection circuit including the above pixel circuit provided by the specific embodiment of the present disclosure.
- the semiconductor camera detection circuit in the specific embodiment of the present disclosure is a CMOS camera detection circuit.
- a specific embodiment of the present disclosure further provides a display device, which includes the above-mentioned semiconductor camera detection circuit provided by a specific embodiment of the present disclosure, which may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, or an organic light emitting diode (Organic Light).
- a display device which includes the above-mentioned semiconductor camera detection circuit provided by a specific embodiment of the present disclosure, which may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, or an organic light emitting diode (Organic Light).
- OLED Emitting Diode
- a specific embodiment of the present disclosure provides a pixel circuit including: a photodiode, a driving module, an initialization module, a transmission module, a voltage writing module, and a compensation module; one end of the photodiode is electrically connected to the ground end, and the other end is Electrically connecting with the transmission module; the initialization module is electrically connected to the initialization signal terminal and the initialization voltage terminal, and is configured to pull the voltage of the first node to the initialization voltage of the initialization voltage terminal under the control of the initialization signal terminal; the transmission module and the initialization module Electrically connected to the first scan signal end, configured to pull the voltage of the first node from the initialization voltage to the data voltage under the control of the first scan signal end; the value of the data voltage is dependent on the light intensity received by the photodiode Increasing and decreasing; the voltage writing module is electrically connected to the first node, the driving module, the compensation module, the grounding end and the second scanning signal end, and is configured to write a data voltage to the
- the transmission module in the specific embodiment of the present disclosure is configured to pull the voltage of the first node from the initialization voltage to the data voltage under the control of the first scan signal end; the value of the data voltage varies with the light intensity received by the photodiode Increasing and decreasing; the voltage writing module is configured to write a data voltage to the driving module under the control of the second scanning signal end; the compensation module is configured to control the driving module under the control of the compensation signal end and the second scanning signal end Perform threshold voltage compensation. Therefore, the data voltage written in the driving module of the embodiment of the present disclosure is only related to the illumination intensity received by the photodiode, and the compensation module performs threshold voltage compensation on the driving module, which solves the prior art drift due to the threshold voltage of the driving transistor. There is a problem in the difference between the magnitude of the output current and the magnitude of the current generated by the actual illumination.
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Abstract
Description
Claims (10)
- 一种像素电路,包括:光电二极管、驱动模块、初始化模块、传输模块、电压写入模块和补偿模块;其中,所述光电二极管的一端与接地端电连接,另一端与所述传输模块电连接;所述初始化模块与初始化信号端和初始化电压端电连接,被配置为在所述初始化信号端的控制下,将第一节点的电压拉至所述初始化电压端输入的初始化电压;所述传输模块与所述初始化模块和第一扫描信号端电连接,被配置为在所述第一扫描信号端的控制下,将所述第一节点的电压从所述初始化电压拉低至数据电压,其中,所述数据电压的值随着所述光电二极管接收到的光照强度的增加而减小;所述电压写入模块与所述第一节点、所述驱动模块、所述补偿模块、所述接地端和第二扫描信号端电连接,被配置为:在所述第二扫描信号端的控制下,对所述驱动模块写入所述数据电压;以及,输出接地电压给补偿模块;所述补偿模块与所述驱动模块、高电压电平信号端、补偿信号端和所述第二扫描信号端电连接,被配置为在所述补偿信号端和所述第二扫描信号端的控制下,对所述驱动模块进行阈值电压补偿;其中,所述第一节点为所述初始化模块、所述传输模块和所述电压写入模块的交点。
- 根据权利要求1所述的像素电路,其中,所述补偿模块包括第一电容、第一开关晶体管、第二开关晶体管和反相器;所述第一电容的一端与所述电压写入模块电连接,另一端与所述驱动模块电连接;所述第一开关晶体管的栅极与所述补偿信号端电连接,另外两极分别与所述高电压电平信号端和所述驱动模块电连接;所述反相器的一端与所述第二扫描信号端电连接,另一端与所述第二开关晶体管的栅极电连接;所述第二开关晶体管的另外两极分别与所述电压写入模块和所述驱动模块电连接。
- 根据权利要求1所述的像素电路,其中,所述初始化模块包括第三开关晶体管和第二电容;所述第二电容的一端与所述第一节点电连接,另一端与接地端电连接;所述第三开关晶体管的栅极与所述初始化信号端电连接,另外两极分别与所述初始化电压端和所述第一节点电连接。
- 根据权利要求1所述的像素电路,其中,所述传输模块包括第四开关晶体管,所述第四开关晶体管的栅极与所述第一扫描信号端电连接,另外两极分别与所述光电二极管和所述第一节点电连接。
- 根据权利要求1所述的像素电路,其中,所述电压写入模块包括第五开关晶体管、第六开关晶体管和第七开关晶体管;所述第五开关晶体管的栅极与所述第二扫描信号端电连接,另外两极分别与接地端和所述补偿模块电连接;所述第六开关晶体管的栅极与所述第二扫描信号端电连接,另外两极分别与所述第一节点和所述驱动模块电连接;所述第七开关晶体管的栅极与所述第二扫描信号端电连接,另外两极分别与接地端和所述驱动模块电连接。
- 根据权利要求2-5任一权利要求所述的像素电路,其中,所述第一开关晶体管、所述第二开关晶体管、所述第三开关晶体管、所述第四开关晶体管、所述第五开关晶体管、所述第六开关晶体管和所述第七开关晶体管均为P型薄膜晶体管。
- 根据权利要求1所述的像素电路,其中,所述驱动模块包括驱动晶体管,所述驱动晶体管的栅极与所述补偿模块和所述电压写入模块电连接,源极与所述补偿模块电连接,漏极与所述电压写入模块和输出信号线电连接。
- 根据权利要求7所述的像素电路,其中,所述驱动晶体管为P型薄膜晶体管。
- 一种半导体摄像头检测电路,包括权利要求1-8任一项所述的像素电路。
- 一种显示装置,包括权利要求9所述的半导体摄像头检测电路。
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CN109870470B (zh) * | 2017-06-30 | 2024-07-16 | 京东方科技集团股份有限公司 | 探测像素电路、探测面板和光电检测装置 |
CN108766361A (zh) * | 2018-05-31 | 2018-11-06 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示装置 |
CN109410844B (zh) * | 2018-10-29 | 2023-12-29 | 武汉华星光电技术有限公司 | 像素驱动电路及显示装置 |
CN110797364B (zh) * | 2019-11-08 | 2022-01-11 | 京东方科技集团股份有限公司 | 一种探测基板、探测面板及光电检测装置 |
CN113763870B (zh) * | 2020-06-03 | 2024-06-04 | 原相科技股份有限公司 | 像素电路及像素阵列 |
KR20220015112A (ko) * | 2020-07-30 | 2022-02-08 | 엘지디스플레이 주식회사 | 표시장치와 이를 포함한 모바일 단말기 |
CN112532899B (zh) | 2020-11-27 | 2023-06-30 | 京东方科技集团股份有限公司 | 光电转换电路、驱动方法、光电检测基板、光电检测装置 |
CN114397975B (zh) * | 2022-01-24 | 2024-04-09 | 武汉天马微电子有限公司 | 显示面板及其驱动方法和显示装置 |
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