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WO2018086298A1 - 表面传感晶片封装结构及其制作方法 - Google Patents

表面传感晶片封装结构及其制作方法 Download PDF

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Publication number
WO2018086298A1
WO2018086298A1 PCT/CN2017/078339 CN2017078339W WO2018086298A1 WO 2018086298 A1 WO2018086298 A1 WO 2018086298A1 CN 2017078339 W CN2017078339 W CN 2017078339W WO 2018086298 A1 WO2018086298 A1 WO 2018086298A1
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Prior art keywords
wafer
surface sensing
sensing
package structure
chip package
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PCT/CN2017/078339
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English (en)
French (fr)
Inventor
肖智轶
于大全
邹益朝
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华天科技（昆山）电子有限公司
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Publication of WO2018086298A1 publication Critical patent/WO2018086298A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor

Definitions

  • the present invention relates to the field of packaging of semiconductor chips, and more particularly to a surface sensing chip package structure and a method of fabricating the same.
  • Surface sensing wafers or surface sensing wafers are expanding in application fields due to their simplicity and practicality.
  • Intelligent terminal devices with increasingly powerful functions are also beginning to be equipped with more and more surface sensor chips.
  • today's devices have high requirements for short and thin packaged devices, and the package size of such surface sensor chips is also required. Minimize the pursuit.
  • the fingerprint recognition glass cover solution, the traditional single package and the wafer level package are cut into a single chip, all of which are laminated with glass in the module section, the overall yield and efficiency are not high, and the cost is high. .
  • the present invention provides a surface sensing chip package structure and a manufacturing method thereof, which greatly improves production efficiency, reduces cost, improves yield of packaged products, and improves reliability of packaged products. .
  • a surface sensing chip package structure comprising a surface sensing wafer having opposing first and second surfaces, the first surface comprising a sensing element and a periphery of the sensing element a plurality of pads having a metal interconnect structure extending from the second surface to a pad surface of the first surface, and the metal interconnect structure a metal line disposed on the second surface is connected to the metal line, and a conductive body is formed on the metal line, and a protective layer is wrapped on the second surface on which the metal line is disposed and the side surface of the surface sensing wafer, and the thickness of the protective layer is lower than Determining the height of the conductor and exposing the conductor, the first surface of the surface sensing wafer and the surrounding protective layer are attached with a functional cover, at least the surface sensing the first surface of the wafer and the functional cover There is a glue between them.
  • the surface sensing chip is a fingerprint identification chip.
  • the functional cover bonding surface is provided with a colored layer.
  • the functional cover is glass, sapphire, aluminum nitride or ceramic material.
  • the protective layer is a molding compound.
  • the thickness of the protective layer covering the side of the surface sensing wafer is not less than 5 micrometers.
  • a method of fabricating a surface sensing chip package structure comprising the steps of:
  • the thickness of the function cover wafer reaches a preset value or temporarily bonding a carrier on the back surface of the function cover wafer;
  • the plastic sealing function covers the front side of the wafer, so that the molding plastic wraps the surface to sense the second surface and the surrounding sides of the wafer, and exposes the electrical conductor;
  • the wafer wafer and the functional cover wafer are diced into a single package chip to form a surface sensing chip package structure.
  • step B there is a step of laying a colored layer on the bonding surface of the functional cover.
  • step C is bonded by applying an adhesive to the front surface of the functional cover wafer, attaching the pre-packaged surface sensing wafer to the front surface of the functional cover wafer, or sensing the wafer on the pre-packaged surface.
  • the first surface is coated with an adhesive and placed on the front side of the functional cover wafer.
  • step E the wafer cutting step is to cut into the vicinity of the temporary bonding glue of the carrier, so that the adjacent chips are separated, or the temporary bonding is performed to remove the carrier, and then the wafer is diced to form a single packaged chip, or Cutting the wafer and the carrier to form a single package chip with a carrier
  • the present invention realizes the bonding of the wafer level cover, which simultaneously realizes the wafer level chip package and the wafer level cover package, compared with the conventional single chip pasting single cover and the wafer level chip package separately. , greatly improving production efficiency and reducing Cost, and because the pre-packaged wafer after dicing is reassembled through the patch, and wafer-level cover is packaged, the yield of the packaged product will be greatly improved.
  • the protective layer in the package structure wraps around the sides and surfaces of the wafer, improving the reliability of the product.
  • FIG. 1 is a cross-sectional view showing a surface sensing chip package structure of the present invention, wherein the metal interconnection structure includes vertical holes;
  • Figure 2 is an enlarged schematic view of a portion A in Figure 1;
  • FIG. 3 is a cross-sectional view showing a surface sensing chip package structure of the present invention, wherein the metal interconnection structure includes a slanted hole;
  • FIG. 4 is a cross-sectional view showing a surface sensing chip package structure of the present invention, wherein the metal interconnection structure is a combination including a groove and a slant hole;
  • FIG. 5 is a cross-sectional view of a surface sensing wafer after pre-packaging according to the present invention, wherein the metal interconnection structure includes vertical holes;
  • FIG. 6 is a cross-sectional view of a pre-packaged surface sensing wafer of the present invention, wherein the metal interconnect structure comprises a combination of a groove and a slanted hole;
  • Figure 7 is a schematic structural view of a functional cover of the present invention.
  • Figure 8 is a schematic view showing the temporary bonding structure of the functional cover and the carrier of the present invention.
  • Figure 9 is a schematic view showing the structure of applying a colored layer on the bonding surface of the functional cover according to the present invention.
  • Figure 10 is a schematic view showing the structure of the adhesive layer coated on the colored layer of the present invention.
  • Figure 11 is a view of the present invention, the pre-packaged surface sensing wafer is adhered to the function cover Schematic diagram of the structure.
  • the surface sensing wafer package structure of the present invention includes a surface sensing wafer 100 having opposing first and second surfaces.
  • the first surface of the surface sensing chip comprises a sensing component and a plurality of solder pads 104 located around the sensing component.
  • the soldering pad and the sensing component are connected by a circuit, and the cross-sectional view of the soldering pad is shown. The component is measured, so the sensing component is not shown.
  • the surface sensing wafer has a metal interconnect structure 101 extending from the second surface of the surface sensing wafer to the surface of the pad of the first surface, and the second surface of the surface sensing wafer is provided with a metal line 102, and the surface is transmitted
  • the metal interconnect structure of the second surface of the sense wafer is electrically connected, and the metal trace is formed with the conductor 103.
  • the protective layer 300 is wrapped on the second surface provided with the metal wiring and the peripheral side of the surface sensing wafer such that the thickness of the protective layer is lower than the height of the conductor and the electrical conductor is exposed.
  • a functional cover 200 is attached to the first surface of the surface sensing wafer and the protective layer of the periphery. At least the adhesive surface 202 is disposed between the first surface of the surface sensing wafer and the functional cover.
  • the surface sensing chip is a fingerprint identification chip.
  • the functional cover bonding surface is provided with a colored layer 201 for making the wafer
  • the sensing surface is beautiful.
  • the metal interconnect structure comprises a vertical hole (as in Figures 1 and 5) or a slanted hole (as in Figure 3) or an opening 101a of the combination of the slot and the straight/oblique hole (as in Figures 4 and 6), further comprising a vertical hole or a slanted hole or a metal layer 101b in the opening, and an insulating layer 101c between the metal layer and the surface sensing wafer to prevent leakage and improve electrical properties of the metal interconnection structure; metal lines and vertical holes or inclined holes or A solder resist layer 101d is laid on the metal layer in the opening 101a.
  • the functional cover is made of glass, sapphire, aluminum nitride or ceramic. More preferably, the functional cover has a hardness greater than 7.
  • the protective layer is a molding compound, which can protect the metal circuit from being exposed to corrosion in the air, and can also prevent the side of the wafer from being exposed, thereby improving the reliability of the wafer.
  • the thickness of the protective layer covering the side of the surface sensing wafer is not less than 5 ⁇ m, and more preferably, the thickness is 20 to 200 ⁇ m.
  • the method for fabricating the surface sensing chip package structure comprises the following steps:
  • a wafer on a wafer wafer is selected as an illustration to illustrate a method of fabricating a surface sensing chip package structure.
  • a carrier is temporarily bonded on the back surface of the wafer process surface, that is, the first surface of the wafer.
  • the metal interconnect structure includes a vertical hole, or a slanted hole, or an opening of a combination of a groove and a straight/oblique hole, and a metal layer located inside the opening.
  • a metal layer located inside the opening.
  • the support strength of the functional cover can be ensured by selecting a functional cover wafer whose thickness reaches a preset value (for example, greater than 200 ⁇ m).
  • the function cover wafer material is glass, sapphire, aluminum nitride or ceramic material. More preferably, the functional cover has a hardness of more than 7, and is resistant to scratches.
  • the bonding adhesive 401 temporarily bonded between the carrier and the function cover wafer is photolyzed, such as laser or ultraviolet light, or pyrolyzed material, and the adhesive of the bonding adhesive is released by, for example, laser or ultraviolet light illumination or heating. It is convenient to remove the carrier after the package is completed.
  • Adhesive 202 is used to adhere the first surface of several pre-packaged surface sensing wafers to the functional cover wafer. Referring to FIG. 11, a certain distance is reserved between adjacent surface sensing wafers to form a plastic package. Wrap the surface of the surface sensing wafer.
  • the bonding may be performed by applying an adhesive to the front side of the functional cover wafer, pasting the pre-packaged surface sensing wafer through the placement machine to the front side of the functional cover wafer, or sensing the surface of the pre-packaged surface.
  • the first surface of the wafer is coated with an adhesive and placed on the front surface of the functional cover wafer by a mounter.
  • the functional cover wafer is coated with a colored layer 201 on the front side, see FIG.
  • the first surface of the pre-packaged surface sensing wafer is adhered to the colored layer of the functional cover wafer by an adhesive, see FIG.
  • the molding function covers the front side of the wafer, and the molding compound wraps the second surface and the peripheral sides of the pre-packaged surface sensing wafer, and exposes the electrical conductor, see FIG.
  • the molding compound integrally covers the front surface of the functional cover wafer, and the thickness of the molding compound on the second surface of the surface sensing wafer is lower than the height of the conductor.
  • the method of exposing the conductor is dry etching, laser ablation, and the like.
  • the wafer wafer and the functional cover wafer are diced into a single package chip to form a surface sensing chip package structure.
  • the wafer cutting step can be cut to the vicinity of the temporary bonding glue to ensure separation of adjacent chips.
  • the carrier plate is removed, and the corresponding bonding method of the temporary bonding glue is used, photolysis, such as laser or ultraviolet light, or pyrolysis to reduce the viscosity of the glue, and then the carrier is removed.
  • photolysis such as laser or ultraviolet light
  • pyrolysis to reduce the viscosity of the glue
  • the present invention realizes the bonding of the wafer level cover, that is, the wafer level chip package and the wafer level at the same time, compared with the conventional single chip pasting single cover and the wafer level chip package separately.
  • the cover plate package greatly improves the production efficiency and reduces the cost, and the yield of the packaged product is also very high because the pre-packaged wafer after dicing is reassembled through the patch and then wafer-level cover is packaged.
  • the protective layer in the package structure wraps around the sides and surfaces of the wafer, improving Product reliability.

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Abstract

一种表面传感晶片封装结构及其制作方法，将表面传感晶片（100）第一表面焊垫（104）通过金属互连结构（101）引到表面传感晶片的第二表面后，切割形成单颗表面传感晶片，然后将分离的表面传感晶片贴到功能盖板（200）上重组成晶圆，在重组晶圆上对晶片第二表面与四周侧面包覆模塑料，最后切割形成单颗表面传感芯片。该封装结构的制作方法可以实现晶圆级功能盖板的贴合，极大的提高了生产效率，降低了成本，并且由于将切割后晶片通过贴片重组晶圆，进行晶圆级封装，封装产品的良率也会有很大的提升。封装结构中保护层（300）包裹住晶片的四周侧面，提高了产品的可靠性。

Description

表面传感晶片封装结构及其制作方法 技术领域
本发明涉及半导体芯片的封装领域，尤其涉及一种表面传感晶片封装结构及其制作方法。
背景技术
表面传感晶片或表面感应晶片，如指纹识别表面传感芯片、触摸型表面传感芯片等因其简便、实用性，应用领域不断拓展。功能逐渐强大的智能终端设备，也开始搭载越来越多的表面传感芯片，然而，现在的设备对于封装器件短小轻薄有较高的要求，搭载的此类表面传感芯片的封装体积也必将追求最小化。
目前指纹识别玻璃盖板方案，传统的单颗封装以及晶圆级封装完毕切割成单颗芯片，都是在模组段单颗贴合玻璃，整体的良率和效率不高，并且成本较高。
发明内容
为了解决上述技术问题，本发明提出了一种表面传感晶片封装结构及其制作方法，极大的提高了生产效率，降低了成本，提升了封装产品的良率，提高了封装产品的可靠性。
一种表面传感晶片封装结构，包括一表面传感晶片，该表面传感晶片具有相对的第一表面和第二表面，所述第一表面包含有感测元件及位于该感测元件周围的多个焊垫，该表面传感晶片内有金属互连结构，所述金属互连结构从所述第二表面延伸至所述第一表面的焊垫表面，且所述金属互连结构与所述第二表面设置的金属线路相连接，该金属线路上制作有导电体，在设置有金属线路的第二表面及所述表面传感晶片的四周侧面包裹保护层，该保护层厚度低于所述导电体高度，并暴露出所述导电体，该表面传感晶片的第一表面及周边的保护层上贴合一功能盖板，至少该表面传感晶片第一表面与所述功能盖板之间有粘结胶。
进一步的，所述表面传感晶片为指纹识别芯片。
进一步的，所述功能盖板粘结面设有一着色层。
进一步的，所述功能盖板为玻璃、蓝宝石、氮化铝或者陶瓷材料。
进一步的，所述保护层为模塑料。
进一步的，包裹所述表面传感晶片侧面的保护层厚度不小于5微米。
一种表面传感晶片封装结构的制作方法，包括以下步骤：
A.提供一具有若干表面传感晶片的晶片晶圆，具有相对的第一表面和第二表面，通过晶圆级封装，在各表面传感晶片上第二表面制作金属互连结构、金属线路和导电体，并将晶片晶圆切割成单颗表面传感晶片，完成预封装；
B.提供一功能盖板晶圆，该功能盖片晶圆的厚度达到预设值或在该功能盖板晶圆的背面临时键合一载板；
C.用粘结胶将若干预封装的表面传感晶片第一表面朝下粘结至功能盖板晶圆上，相邻表面传感晶片之间预设一定距离；
D.塑封功能盖板晶圆正面，使模塑料包裹表面传感晶片的第二表面及四周侧面，并暴露出导电体；
E.将晶片晶圆及功能盖板晶圆切割成单颗封装芯片，形成表面传感晶片封装结构。
进一步的，步骤B和步骤C之间还有在功能盖板粘结面铺设一着色层的步骤。
进一步的，步骤C粘结的方式为，将粘结胶涂至功能盖板晶圆正面，将预封装的表面传感晶片贴至功能盖板晶圆正面；或者在预封装的表面传感晶片的第一表面涂上粘结胶，再放置在功能盖板晶圆正面。
进一步的，步骤E中，晶圆切割步骤为切割到载板临时键合胶的附近，使相邻芯片分离，或先解临时键合去除载板后再切割晶圆形成单颗封装芯片，或者切割晶圆与载板形成带载板的单颗封装芯片
本发明的有益效果：
相比传统单颗芯片贴单个盖板及晶圆级芯片封装单独贴盖板，本发明实现了晶圆级盖板的贴合，即同时实现了晶圆级芯片封装及晶圆级盖板封装，极大的提高了生产效率，降低了 成本，并且由于将切割后的预封装晶片通过贴片重组晶圆，再进行晶圆级盖板封装，封装产品的良率也会有很大的提升。封装结构中保护层包裹住晶片的四周侧面及表面，提高了产品的可靠性。
附图说明
图1为本发明表面传感晶片封装结构剖面图，其中金属互连结构包括垂直孔；
图2为图1中A处放大示意图；
图3为本发明表面传感晶片封装结构剖面图，其中金属互连结构包括斜孔；
图4为本发明表面传感晶片封装结构剖面图，其中金属互连结构为包括槽与斜孔的组合；
图5为本发明预封装后的表面传感晶片剖面图，其中金属互连结构包括垂直孔；
图6为本发明预封装后的表面传感晶片剖面图，其中金属互连结构包括槽与斜孔的组合；
图7为本发明功能盖板结构示意图；
图8为本发明功能盖板与载板临时键合结构示意图；
图9为本发明在功能盖板粘结面涂覆着色层的结构示意图；
图10为本发明在着色层上涂粘结胶的结构示意图；
图11为本发明将预封装后的表面传感晶片黏在功能盖板 上的结构示意图。
具体实施方式
为使本发明能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。为方便说明，实施例附图的结构中各组成部分未按正常比例缩放，故不代表实施例中各结构的实际相对大小。
本发明表面传感晶片封装结构，如图1、图3和图4所示，该封装结构包括表面传感晶片100，具有相对的第一表面和第二表面。表面传感晶片第一表面包含有感测元件，及位于感测元件周边的多个焊垫104，焊垫与感测元件通过电路相连接，图示为焊垫处剖面图，未剖至感测元件，故感测元件未示出。表面传感晶片内有一金属互连结构101，金属互连结构从表面传感晶片第二表面延伸至第一表面的焊垫表面，表面传感晶片第二表面设有金属线路102，与表面传感晶片第二表面的金属互连结构电连接，且该金属线路上制作有导电体103。在设置有金属线路的第二表面及表面传感晶片的四周侧面包裹保护层300，使该保护层厚度低于导电体高度，并暴露出导电体。该表面传感晶片的第一表面及周边的保护层上贴合一功能盖板200，至少该表面传感晶片第一表面与所述功能盖板之间有粘结胶202。
优选的，表面传感晶片为指纹识别芯片。
优选的，功能盖板粘结面设有一着色层201，用以使晶片 感测面美观。
优选的，金属互连结构包括垂直孔(如图1和图5)或者斜孔(如图3)或者槽与直/斜孔的组合(如图4和图6)的开口101a，还包括位于垂直孔或斜孔或开口内的金属层101b，金属层与表面传感晶片之间有一绝缘层101c，以防止漏电，提高金属互连结构的电性能；金属线路上及垂直孔或斜孔或开口101a内的金属层上铺设一层防焊层101d。
优选的，功能盖板为玻璃、蓝宝石、氮化铝或者陶瓷等材料。更优选的，该功能盖板的硬度大于7。
优选的，保护层为模塑料，可以保护金属线路不暴露在空气中被腐蚀，也可以避免晶片侧面裸露，提高晶片可靠性。
优选的，包裹表面传感晶片侧面的保护层厚度不小于5微米，更优选的，厚度为20至200微米。
该表面传感晶片封装结构的制作方法，包括以下步骤：
A.提供一具有若干表面传感晶片的晶片晶圆，具有相对的第一表面和第二表面，通过晶圆级封装，在各表面传感晶片第二表面上制作金属互连结构、金属线路和导电体，并将晶片晶圆切割成单颗晶片，完成预封装。如图5所示，为方便示意，选取了晶片晶圆上一颗晶片作为示意，说明表面传感晶片封装结构的制作方法。
优选的，在上述晶圆级封装过程中，为了确保各制程的支撑强度，在晶圆工艺面的背面，也即晶片的第一表面，临时键合一载片。
金属互连结构包括垂直孔，或者斜孔，或者槽与直/斜孔的组合的开口，及位于开口内的金属层。金属互连结构中，金属层与晶片之间有一绝缘层，防止漏电，提高金属互连结构的电性能。由于金属互连结构为晶圆级封装中常规的制程，这里不再赘述。
B.提供一功能盖板晶圆，参见图7，在功能盖板晶圆的背面临时键合一载板400，以确保各制程的支撑强度，参见图8。或者，通过选取厚度达到预设值(如大于200μm)的功能盖板晶圆，保证功能盖板的支撑强度。
该功能盖板晶圆材质如玻璃，蓝宝石、氮化铝或者陶瓷材料。更优选的，该功能盖板的硬度大于7，耐磨耐刮伤。
优选的，载板与功能盖板晶圆临时键合的键合胶401为光解，如激光或紫外光，或者热解材料，分别通过如激光或紫外光光照或者加热解除键合胶的粘性，便于封装完毕后载板的拆除。
C.用粘结胶202将若干预封装的表面传感晶片第一表面朝下黏至功能盖板晶圆上，参见图11，相邻表面传感晶片之间预留有一定距离，以塑封包裹表面传感晶片的侧面。
粘结的方式可以为，将粘结胶涂至功能盖板晶圆正面，将预封装的表面传感晶片通过贴片机，贴至功能盖板晶圆正面；或者在预封装的表面传感晶片的第一表面涂上粘结胶，再通过贴片机安置在功能盖板晶圆正面。
优选的，功能盖板晶圆正面涂覆着色层201，参见图9， 预封装的表面传感晶片第一表面通过粘结胶贴至功能盖板晶圆的着色层之上，参见图10。
D.塑封功能盖板晶圆正面，模塑料包裹预封装的表面传感晶片的第二表面及四周侧面，并暴露出导电体，参见图1。
该模塑料整体覆盖功能盖板晶圆的正面，表面传感晶片第二表面上的模塑料厚度低于导电体高度，暴露导电体的方法为干法刻蚀、激光烧蚀等。
E.将晶片晶圆及功能盖板晶圆切割成单颗封装芯片，形成表面传感晶片封装结构。
晶圆切割步骤可以是切割到临时键合胶的附近，保证相邻芯片的分离即可。
或者先解键合去除载板，在切割晶圆形成单颗封装芯片。
还可以同时切割晶圆和载板，形成带载板的单颗封装芯片，后续将芯片贴合到软板上后再解键合，以便在后期工艺过程起保护作用。
去除载板，采用临时键合胶相应的解键合的方法，光解，如激光或者紫外光，或者热解降低胶的粘度，然后去除载板。
综上，相比传统单颗芯片贴单个盖板及晶圆级芯片封装单独贴盖板，本发明实现了晶圆级盖板的贴合，即同时实现了晶圆级芯片封装及晶圆级盖板封装，极大的提高了生产效率，降低了成本，并且由于将切割后的预封装晶片通过贴片重组晶圆，再进行晶圆级盖板封装，封装产品的良率也会有很大的提升。封装结构中保护层包裹住晶片的四周侧面及表面，提高了 产品的可靠性。
以上实施例是参照附图，对本发明的优选实施例进行详细说明，本领域的技术人员通过对上述实施例进行各种形式上的修改或变更，但不背离本发明的实质的情况下，都落在本发明的保护范围之内。

Claims (10)

  1. 一种表面传感晶片封装结构，包括一表面传感晶片，该表面传感晶片具有相对的第一表面和第二表面，所述第一表面包含有感测元件及位于该感测元件周围的多个焊垫，该表面传感晶片内有金属互连结构，所述金属互连结构从所述第二表面延伸至所述第一表面的焊垫表面，且所述金属互连结构与所述第二表面设置的金属线路相连接，该金属线路上制作有导电体，其特征在于，在设置有金属线路的第二表面及所述表面传感晶片的四周侧面包裹保护层，该保护层厚度低于所述导电体高度，并暴露出所述导电体；该表面传感晶片的第一表面及周边的保护层上贴合一功能盖板，至少该表面传感晶片第一表面与所述功能盖板之间有粘结胶。
  2. 根据权利要求1所述的表面传感晶片封装结构，其特征在于，所述表面传感晶片为指纹识别芯片。
  3. 根据权利要求1所述的表面传感晶片封装结构，其特征在于，所述功能盖板粘结面设有一着色层。
  4. 根据权利要求1所述的表面传感晶片封装结构，其特征在于，所述功能盖板为玻璃、蓝宝石、氮化铝或者陶瓷材料。
  5. 根据权利要求1所述表面传感晶片封装结构，其特征在于，所述保护层为模塑料。
  6. 根据权利要求1或5所述的表面传感晶片封装结构，其特征在于，包裹所述表面传感晶片侧面的保护层厚度不小于5 微米。
  7. 一种表面传感晶片封装结构的制作方法，其特征在于，包括以下步骤：
    A.提供一具有若干表面传感晶片的晶片晶圆，具有相对的第一表面和第二表面，通过晶圆级封装，在各表面传感晶片上第二表面制作金属互连结构、金属线路和导电体，并将晶片晶圆切割成单颗表面传感晶片，完成预封装；
    B.提供一功能盖板晶圆，该功能盖片晶圆的厚度达到预设值或在该功能盖板晶圆的背面临时键合一载板；
    C.用粘结胶将若干预封装的表面传感晶片第一表面朝下粘结至功能盖板晶圆上，相邻表面传感晶片之间预设一定距离；
    D.塑封功能盖板晶圆正面，使模塑料包裹表面传感晶片的第二表面及四周侧面，并暴露出导电体；
    E.将晶片晶圆及功能盖板晶圆切割成单颗封装芯片，形成表面传感晶片封装结构。
  8. 根据权利要求7所述的表面传感晶片封装结构的制作方法，其特征在于，步骤B和步骤C之间还有在功能盖板粘结面铺设一着色层的步骤。
  9. 根据权利要求7所述的表面传感晶片封装结构的制作方法，其特征在于，步骤C粘结的方式为，将粘结胶涂至功能盖板晶圆正面，将预封装的表面传感晶片贴至功能盖板晶圆正面；或者在预封装的表面传感晶片的第一表面涂上粘结胶，再 放置在功能盖板晶圆正面。
  10. 根据权利要求7所述的表面传感晶片封装结构的制作方法，其特征在于，步骤E中，晶圆切割步骤为切割到载板临时键合胶的附近，使相邻芯片分离，或先解临时键合去除载板后再切割晶圆形成单颗封装芯片，或者切割晶圆与载板形成带载板的单颗封装芯片。
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