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WO2018076766A1 - 一种抑制谐波与杂散的射频功率放大器、芯片及通信终端 - Google Patents

一种抑制谐波与杂散的射频功率放大器、芯片及通信终端 Download PDF

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Publication number
WO2018076766A1
WO2018076766A1 PCT/CN2017/091347 CN2017091347W WO2018076766A1 WO 2018076766 A1 WO2018076766 A1 WO 2018076766A1 CN 2017091347 W CN2017091347 W CN 2017091347W WO 2018076766 A1 WO2018076766 A1 WO 2018076766A1
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Prior art keywords
power amplifier
inductor
radio frequency
stage
matching network
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PCT/CN2017/091347
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English (en)
French (fr)
Inventor
赵锦鑫
白云芳
林升
Original Assignee
唯捷创芯(天津)电子技术股份有限公司
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Priority to US16/346,037 priority Critical patent/US10879850B2/en
Priority to EP17866024.7A priority patent/EP3534537A4/en
Publication of WO2018076766A1 publication Critical patent/WO2018076766A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/108—A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/15—Indexing scheme relating to amplifiers the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/391—Indexing scheme relating to amplifiers the output circuit of an amplifying stage comprising an LC-network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/402—A series resonance being added in shunt in the output circuit, e.g. base, gate, of an amplifier stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/405—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising more than three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/459—Ripple reduction circuitry being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits

Definitions

  • the present invention relates to a radio frequency power amplifier, and more particularly to an RF power amplifier capable of suppressing harmonics and spurs, and also relates to a chip and a communication terminal including the radio frequency power amplifier, and belongs to the field of integrated circuit technology.
  • the RF power amplifier acts as the last stage in the transmitter, which greatly affects the linear performance of the entire transceiver.
  • the final stage of the RF power amplifier uses a Class A or Class B power amplifier. Due to the influence of nonlinear distortion, when the signal is increased to a certain extent, the RF power amplifier generates a series of harmonics and spurs due to working in the nonlinear region, which greatly affects the linear performance of the RF power amplifier, so the harmonic suppression Waves and spurs are important measures to improve the linearity of RF power amplifiers.
  • a circuit structure for improving the harmonic performance of a radio frequency power amplifier comprises a radio frequency power amplifier tube, a second harmonic suppression network, a third harmonic suppression network, a harmonic suppression network, a first matching inductor, a second matching inductor and a DC blocking capacitor; wherein, the first matching inductor, The second matching inductor, the third harmonic suppression network, and the higher harmonic suppression network form a low-pass output matching network of the power amplifier and are connected to the collector of the power amplifier tube; the second harmonic suppression network is connected to the collector of the power amplifier tube, Independent of the output matching network and suppressing the frequency adjustable, the tertiary and higher harmonic suppression networks are included in the output matching network and the higher harmonic rejection frequency is adjustable.
  • the circuit structure effectively suppresses harmonic components generated by the RF power amplifier and improves the performance of the power amplifier.
  • the RF power amplifier in the transmitter may also generate out-of-band spurious outputs, which are located in the receiver band and may be coupled to the low-noise amplifier input at the receiver front end if not well isolated. End, form interference, or may also interfere with other adjacent channels. Therefore, RF power amplifiers need to be further improved to not only suppress harmonics but also to limit out-of-band parasitic outputs.
  • the primary technical problem to be solved by the present invention is to provide an RF power amplifier capable of suppressing harmonics and spurs.
  • Another technical problem to be solved by the present invention is to provide a chip and a communication terminal including the above-described radio frequency power amplifier.
  • a radio frequency power amplifier for suppressing harmonics and spurs which includes a power supply, an LDO circuit, a harmonic suppression unit, a spur suppression unit, an amplification unit, and a low-pass matching network; ,
  • the power source is connected to the harmonic suppression unit, and the spurious suppression unit is disposed between the LDO circuit and the amplification unit;
  • the power source includes a first power source and a second power source, and the first power source and the second power source share the harmonic suppression unit.
  • one end of the harmonic suppression unit is respectively connected to the power source, and the other end is grounded; a plurality of resonance frequencies are generated by the harmonic suppression unit, and harmonics of the power source at the resonance frequency are suppressed. With stray.
  • the harmonic suppression unit is an LC array composed of a plurality of LC series resonant circuits connected in parallel, and each LC series resonant circuit is composed of a capacitor and an inductor connected in series.
  • the spur suppression unit is composed of a plurality of load cascades, and each stage load is connected to the next-stage load through an isolation inductor to achieve isolation of spurs.
  • the load of each stage includes a load inductor and an LC array, one end of the LC array is respectively connected to the load inductor and the isolation inductor, and the other end is grounded;
  • the other end of the load inductor is connected to a collector or a drain of a corresponding transistor in the amplifying unit, and an emitter or a source of the transistor is grounded;
  • a plurality of resonance points lower than the operating frequency and a resonance frequency corresponding to the resonance point are generated by the each stage load, and the spur of the transistor at the resonance frequency is suppressed.
  • the number of resonance points generated in each stage of the load and the resonance frequency are independent of each other, and the spurs of the transistors at different frequencies are suppressed by flexible configuration.
  • the low-pass matching network is a multi-level horse composed of multiple matching network cascades.
  • a network, each level matching network is composed of a first inductor, a first capacitor, a second inductor, and a second capacitor;
  • the first inductor and the first capacitor are connected in parallel to form an LC parallel resonant circuit, and the second inductor and the second capacitor are connected in series to form an LC series resonant circuit;
  • One end of the LC series resonant circuit is respectively connected to the LC parallel resonant circuit of the matching network of the present stage and the LC parallel resonant circuit of the next-stage matching network, and the other end of the LC series resonant circuit is grounded.
  • the resonant frequency of the LC parallel resonant circuit is higher than the operating frequency
  • the resonant frequency of the LC series resonant circuit is higher than the operating frequency
  • the voltage is divided and applied.
  • the shunting suppresses harmonics and spurs of the radio frequency signal at the resonant frequency.
  • the amplifying unit is composed of at least one level of amplifying circuit
  • Each stage of the amplifying circuit is composed of a transistor, and the amplifying circuits of each stage are connected by a capacitor;
  • Each of the stage amplifying circuits is respectively connected to the spurious suppression unit.
  • a chip comprising the radio frequency power amplifier of any of the above.
  • a communication terminal comprising the radio frequency power amplifier of any of the above.
  • the radio frequency power amplifier provided by the present invention achieves suppression of harmonics and spurs at the resonant frequency of the first power source and the second power source by sharing the harmonic suppression unit with the first power source and the second power source, and through the spurs
  • the suppression unit reduces the gain of the amplification unit at the resonance frequency, thereby reducing output spurs.
  • harmonics and spurs of the RF signal amplified by the amplification unit at different frequencies are suppressed.
  • the RF power amplifier is mainly connected to the LC array in the power path and the low-pass matching network is used to effectively suppress harmonics and spurs, the design complexity of the RF power amplifier is simplified, and the related design is realized. the cost of.
  • FIG. 1 is a circuit schematic diagram of a radio frequency power amplifier according to the present invention.
  • FIG. 2 is a schematic diagram of a harmonic suppression unit in a radio frequency power amplifier provided by the present invention
  • FIG. 3 is a stray suppression unit and amplification in a radio frequency power amplifier provided by the present invention Connection diagram of the unit;
  • FIG. 4 is a schematic diagram of connection between each stage of a spur suppression unit and a corresponding amplifying circuit in the radio frequency power amplifier provided by the present invention
  • FIG. 5 is a circuit schematic diagram of a low-pass matching network in a radio frequency power amplifier provided by the present invention.
  • FIG. 6 is a circuit schematic diagram of another RF power amplifier according to the present invention.
  • the communication terminal involved refers to a computer device that can be used in a mobile environment and supports various communication systems such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, and the like, including a mobile phone. , laptops, tablets, car computers, etc.
  • the RF power amplifier is also suitable for applications in other power amplifier circuits, such as communication base stations compatible with various communication systems.
  • FIG. 1 is a circuit schematic diagram of a radio frequency power amplifier capable of suppressing harmonics and spurs according to the present invention.
  • the RF power amplifier includes a control circuit 101, an LDO (low dropout regulator) circuit 103, a spur suppression unit 105, a harmonic suppression unit 108, an amplification unit, and a low-pass matching network.
  • the first power source 106 supplies a supply voltage to the control circuit 101, causes the control circuit 101 to generate a control voltage 102, and controls the LDO circuit 103 through the control voltage 102 and the second power source 107 to output different voltages 104 according to different power levels.
  • the harmonic suppression unit 108 By providing the harmonic suppression unit 108 between the second power source 107 and the ground, the harmonic spurs generated during the power supply of the second power source 107 are effectively suppressed, and a stable supply voltage is supplied to the LDO circuit 103, thereby suppressing the LDO circuit 103.
  • the harmonic spur component in the output voltage 104 By providing the spur suppression unit 105 between the voltage 104 and the amplification unit, the amplification unit can be reduced in gain at the resonance frequency, thereby reducing output spurs (spurs are mainly generated by the amplification unit, not generated by the LDO circuit).
  • the amplified RF signal is ultimately output to a load (e.g., an antenna) through a low pass matching network 114.
  • the low-pass matching network 114 not only achieves impedance matching, but also suppresses harmonics and spurs in the output RF signal, so that the RF signal falls into the receiving band of another system without causing interference.
  • the amplifying unit may be composed of one or more
  • the transistor including but not limited to a field effect transistor or a bipolar transistor, the same below
  • the transistor is composed of a plurality of amplifying circuits which are cascaded by a plurality of amplifying circuits. These transistors can be the same type of transistor or different types of transistors.
  • the multistage amplifying circuit is composed of a first-stage amplifying circuit 111 and a Nth (N is a positive integer)-stage amplifying circuit 112. In FIG. 1, only the first-stage amplifying circuit is indicated for the sake of simplicity.
  • a plurality of amplifying circuits may be provided between the first stage amplifying circuit 111 and the last stage amplifying circuit 112, and by connecting the plurality of amplifying circuits to the spurious suppression unit 105, respectively, it is possible to effectively suppress The spur generated by the amplification unit.
  • the LDO circuit 103 can be any low dropout linear regulator capable of outputting different voltages depending on different power levels.
  • the low-dropout linear regulator ensures that the voltage difference between each port of each transistor does not exceed its own nominal voltage value, preventing the voltage difference at the transistor terminal from exceeding the nominal voltage of its own process as the power supply voltage rises. The value puts the device at risk of burnout.
  • the harmonic suppression unit 108 is an LC array in which M (M is a positive integer, the same as the same) LC series resonant circuits are connected in parallel.
  • the LC series resonant circuit is composed of a capacitor and an inductor in series. Referring to the dotted line frame in FIG. 2, the capacitor 202 and the inductor 203 are connected in series to form a first-stage series resonant circuit, the capacitor 204 and the inductor 205 form a second-stage series resonant circuit, and so on, the capacitor 206 and the inductor 207 form an M-th series connection. Resonant circuit.
  • the LC array can have any number of stages, and the LC array is composed of a first-stage series resonant circuit, a second-stage series resonant circuit, and an M-th series resonant circuit connected in parallel.
  • One end 201 of the harmonic suppression unit 108 of the present radio frequency power amplifier is connected to the second power supply 107, and the other end 208 of the harmonic suppression unit 108 is grounded.
  • the capacitor 202 and the inductor 203 generate the resonant frequency f1
  • the capacitor 204 and the inductor 205 generate the resonant frequency f2
  • the capacitors 206 and 207 generate the resonant frequency fM
  • the second power source 107 exhibits a low impedance to the ground at the frequency f1, the frequency f2, and the frequency fM.
  • the resistance is such that harmonics and spurs of the second power source 107 at the frequency f1, the frequency f2, and the frequency fM can be suppressed.
  • the frequency f1, the frequency f2, and the frequency fM can be set to any different frequency (higher than the operating frequency or lower than the operating frequency).
  • the first stage load (ie, the load of the first stage amplifying circuit) is composed of an inductor 307, an LC array 308, and an inductor 309.
  • One end of the LC array 308 is connected to one end of the inductor 307 and the inductor 309, the other end of the LC array 308 is grounded, and the inductor 309 is used as the load inductor of the first stage amplifying circuit, and the other end of the load inductor 309 is connected to the first stage.
  • the collector or drain (not shown) of the transistor 312 of the amplifying circuit is connected to not only realize the load function but also suppress spurious.
  • the inductor 307 is used as an inter-stage isolation inductor, and the other end thereof is connected to the second-stage load.
  • the second-stage load is the same as the first-stage load. For simplicity of explanation, only the first-stage load is shown in FIG.
  • the N-1th stage load (the load of the N-1th stage amplifying circuit) is composed of an inductor 304, an LC array 305, and an inductor 306.
  • One end of the LC array 305 is connected to one end of the inductor 304 and the inductor 306, the other end of the LC array 308 is grounded, and the inductor 306 is used as the load inductance of the N-1 stage amplifying circuit, and the other end of the load inductor 306 is The collector or drain (not shown) of the transistor 311 of the N-1 stage amplifying circuit is connected, and not only the load function but also the spurious can be suppressed.
  • Inductor 304 acts as an inter-stage isolation inductor with the other end connected to the Nth stage load.
  • the inductance of inductor 304 and inductor 307 is typically large in order to achieve isolation from stray.
  • the Nth stage load (ie, the load of the Nth stage amplifying circuit) is composed of an inductor 303 and an LC array 302.
  • One end of the LC array 302 is connected to one end of the inductor 303 and the voltage source 301 (voltage 104 in FIG. 1), the other end of the LC array 302 is grounded, and the inductor 303 is used as a load inductor of the Nth stage amplifying circuit.
  • the other end of the inductor 303 is connected to the collector or the drain (not shown) of the transistor 310 of the Nth stage amplifying circuit, and not only can the load function be realized, but also the spur can be suppressed.
  • the spur suppression unit 105 is composed of a load cascade of N amplification circuits, and the isolation of the spurs in the amplification unit is realized by connecting the isolation inductance in each stage load to the next-stage load;
  • the load inductances in each stage of the load are respectively connected to the collectors or drains of the transistors in the corresponding amplifying circuit, thereby realizing the suppression of the spurs of the transistors in each stage of the amplifying circuit.
  • the voltage source 301 supplies a supply voltage to the corresponding amplifying circuit through each stage of the load, and the spurious suppression unit 105 filters out the interference of the spurious radio frequency signal for each stage of the amplifying circuit.
  • the radio frequency signal is transmitted to the amplifying unit, and a capacitor is disposed between each amplifying circuit of the amplifying unit, and the radio frequency signal amplified by the upper amplifying circuit is transmitted to the next-stage amplifying circuit through the capacitor, and finally passes through the last stage.
  • the amplifying circuit externally amplifies the RF signal Output.
  • each stage of the load is composed of a load inductor, an LC array 400, and each stage of the load is connected by an isolation inductor.
  • the LC array 400 is composed of M (M is a positive integer, the same below) LC series resonant circuits are connected in parallel.
  • the LC series resonant circuit consists of a capacitor connected in series with the inductor. Referring to the dotted line frame in FIG.
  • the capacitor 402 and the inductor 403 are connected in series to form a first-stage series resonant circuit
  • the capacitor 404 and the inductor 405 form a second-stage series resonant circuit
  • the capacitor 406 and the inductor 407 form an M-th series resonant circuit.
  • the LC array can have any number of stages, and the LC array 400 is composed of a first-stage series resonant circuit, a second-stage series resonant circuit, and an M-th series resonant circuit connected in parallel.
  • One end 409 of the LC array 400 is connected to one end of the load inductor 401 and the isolation inductor 408, the other end 410 of the LC array 400 is grounded, and the other end of the load inductor 401 is connected to the collector or drain of the transistor 411 in the amplifier circuit ( Connected, the emitter or source of transistor 411 is grounded.
  • the isolation inductor 408 is an inter-stage isolation inductor, the isolation inductor 408 can be regarded as a high impedance, and the load inductor 401 and the LC array 400 generate M resonance points, and the resonance frequencies corresponding to the M resonance points are f1, f2, ..., fM, respectively.
  • the impedance to ground of transistor 411 appears as a low impedance at these M frequencies, thereby suppressing the spurs of transistor 411 at these M frequencies.
  • the frequencies f1, f2, ... fM are set lower than the operating frequency, and therefore, the LC array 400 cooperates with the load inductor 401 to suppress spurs below the operating frequency.
  • the load inductance in each stage of the load and the LC array generate multiple resonance points below the operating frequency, and the number of resonance points generated in each stage of the load and the resonance frequency are independent of each other, and can be flexibly configured to suppress Spurious at different frequencies.
  • FIG. 5 is a circuit schematic of a low pass matching network in one embodiment of a radio frequency power amplifier.
  • the low-pass matching network 500 (labeled 114 in FIG. 1) is a multi-level matching network composed of N (N is a positive integer, the same below) matching network cascade.
  • the matching network of each stage is composed of a first inductor, a first capacitor, a second inductor, and a second capacitor.
  • the first inductor and the first capacitor are connected in parallel to form an LC parallel resonant circuit, and the second inductor and the second capacitor are connected in series to form an LC series connection.
  • the resonant circuit In the resonant circuit, one end of the LC series resonant circuit is connected to the LC parallel resonant circuit, and the other end of the LC series resonant circuit is grounded.
  • the resonant frequency f1 of the LC parallel resonant circuit is set higher than the operating frequency
  • the resonant frequency f2 of the LC series resonant circuit is set to be higher than the operating frequency.
  • the first inductor is connected in parallel with the first capacitor It appears as a high resistance at the resonance frequency f1, and harmonics and spurs at the resonance frequency f1 can be suppressed by the voltage division.
  • each stage matching network the ground impedance after the second inductor and the second capacitor are connected in series exhibits a low resistance at the resonance frequency f2, and harmonics and spurs at the resonance frequency f2 can be suppressed by the shunting action.
  • the LC parallel resonant circuit behaves as inductive at the operating frequency, and the LC series resonant circuit appears capacitive at the operating frequency, so each stage matching network is an L-C low pass matching network at the operating frequency. Specifically, as shown in FIG.
  • the first stage matching network is composed of the inductor 501, the inductor 502, the capacitor 503, and the inductor 504, and the second stage matching network is composed of the inductor 505, the inductor 506, the capacitor 507, and the inductor 508.
  • the inductor 510, the capacitor 511, and the inductor 512 form an Nth-level matching network.
  • the inductor 501 and the inductor 502 are connected in parallel to form an LC parallel resonant circuit, and the inductor 502 and the capacitor 503 are connected in series to form an LC series resonant circuit.
  • the second-stage matching network ...
  • the N-th matching network, the inductor 505 and the inductor 506, the capacitor 507 and the inductors 508, 509 and the inductor 510, the capacitor 511 and the inductor 512 respectively constitute an LC parallel resonant circuit and an LC series connection.
  • the resonant circuit, and the working principle of each level matching network have been explained above, and will not be described herein.
  • the low-pass matching network of the RF power amplifier In the low-pass matching network of the RF power amplifier, one end of the LC parallel resonant circuit of each stage matching network is respectively connected to one end of the LC series resonant circuit of the matching network of the current stage and the LC parallel resonant circuit of the matching network of the next stage, And the other end of the LC series resonant circuit of each stage matching network is grounded.
  • the low-pass matching network can filter the harmonics and spurs in the RF signal amplified by the amplification unit to ensure the stability of the output RF signal. Since each level matching network will generate 2 resonance points, the low-pass matching network can generate 2N (N is a positive integer, the same below) resonance points, and the 2N resonance points can be independently configured to achieve low-pass.
  • the impedance matching function also achieves the effect of suppressing harmonics and spurs.
  • the RF power amplifier provided by the present invention may generate a harmonic spur component under the coupling action, and the first power source 106 and the second power source may be used.
  • the power sources 107 are connected together, and by suppressing the harmonic suppression unit 108 by the first power source 106 and the second power source 107, the suppression of harmonic spurs generated during the power supply of the first power source 106 and the second power source 107 is achieved.
  • FIG. 6 another embodiment of the radio frequency power amplifier shown in FIG. 6 can be referred to. In this embodiment, the suppression of the first power source 606 (ie, the first power source 106 in FIG. 1) and the second power source 607 (ie, FIG.
  • the harmonic suppression unit 608 ie, the harmonic suppression unit 108 in FIG. 1). Harmonics and spurs in the second power source 107), and supply power to the control circuit 601 and the LDO circuit 603, respectively
  • the voltage is controlled so that the control voltage 602 generated by the control circuit can control the LDO circuit 603 to output a different voltage 604.
  • the voltage 604 can effectively suppress the spur generated by the voltage 604 through the spurious suppression unit 605, and provide stable and interference-free for the amplifying unit.
  • the power supply voltage, the radio frequency signal is amplified by the amplifying unit (composed of the first stage amplifying circuit 611 to the Nth stage amplifying circuit 612), and the harmonics and spurious filtering are performed through the low pass matching network 614, and finally the amplified
  • the RF signal is output to the load (antenna). Since the structure of the RF power amplifier in FIG. 6 is only connected to the second power source 607 in comparison with the RF power amplifier structure in FIG. 1, the structure and principle of the RF power amplifier are not performed. A detailed description.
  • the radio frequency power amplifier provided by the invention combines the first power source and the second power source path to share the harmonic suppression unit, and the harmonic suppression unit adopts the LC array to suppress the harmonic of the first power source and the second power source at the resonance frequency.
  • the spurs of the amplifying unit are suppressed by the spur suppression unit by employing a plurality of loads composed of load inductors, LC arrays, and cascading each stage load through the isolation inductors to form a spur suppression unit.
  • a low-pass matching network at the output of the present RF power amplifier, it is possible to suppress harmonics and spurs of the RF signal amplified by the amplification unit at different frequencies.
  • the RF power amplifier simplifies the design complexity of the RF power amplifier and reduces the cost of the related design by connecting the LC array on the power path and using the low-pass matching network to effectively suppress harmonics and spurs.
  • the above RF power amplifier capable of suppressing harmonics and spurs can be used in a chip.
  • the specific structure and connection mode of the RF power amplifier used in the chip will not be specifically described herein.
  • the radio frequency power amplifier provided by the present invention capable of suppressing harmonics and spurs can also be used in a communication terminal as an important component of the radio frequency circuit.
  • the term "communication terminal” as used herein refers to a computer device that can be used in a mobile environment and supports various communication systems such as GSM, EDGE, TD_SCDMA, TDD_LTE, and FDD_LTE, including but not limited to mobile phones, notebook computers, tablet computers, and on-board computers.
  • the RF power amplifier is also suitable for other multi-mode technology applications, such as communication base stations compatible with a variety of communication systems, etc., which will not be detailed here.

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Abstract

一种抑制谐波与杂散的射频功率放大器、芯片及通信终端。该射频功率放大器包括电源（106、107）、LDO电路（103）、谐波抑制单元（108）、杂散抑制单元（105）、放大单元、低通匹配网络（114）。一方面，通过使电源（107）连接谐波抑制单元（108），抑制电源（107）在谐振频率处的谐波与杂散。并且，通过杂散抑制单元（105）降低放大单元在谐振频率处的增益，从而降低输出杂散。另一方面，通过在本射频功率放大器的输出端嵌入低通匹配网络（114），有效抑制经放大单元放大的射频信号在不同频率处的谐波与杂散。

Description

一种抑制谐波与杂散的射频功率放大器、芯片及通信终端 技术领域
本发明涉及一种射频功率放大器，尤其涉及一种可以抑制谐波与杂散的射频功率放大器，同时也涉及包括该射频功率放大器的芯片及通信终端，属于集成电路技术领域。
背景技术
随着无线通信技术的飞速发展，对无线收发器的线性性能要求逐步提高。射频功率放大器作为发射机中的最后一级，很大程度上影响了整个收发机的线性性能。通常，射频功率放大器的最后一级采用A类或B类功率放大器。由于非线性失真的影响，当信号增加到一定程度时，射频功率放大器因工作在非线性区而产生一系列谐波与杂散，很大程度上影响了射频功率放大器的线性性能，所以抑制谐波与杂散成为提高射频功率放大器线性度的重要措施。
在申请号为201510057384.5的中国专利申请中，公开了一种改善射频功率放大器谐波性能的电路结构。该电路结构包括射频功率放大管、二次谐波抑制网络、三次谐波抑制网络、高次谐波抑制网络、第一匹配电感、第二匹配电感和隔直电容；其中，第一匹配电感、第二匹配电感、三次谐波抑制网络和高次谐波抑制网络构成功率放大器的低通输出匹配网络并连接于功放管的集电极处；二次谐波抑制网络连接于功放管的集电极，独立于输出匹配网络且抑制频率可调节，三次和高次谐波抑制网络包含于输出匹配网络中且高次谐波抑制频率可调节。该电路结构有效地抑制了射频功率放大器产生的谐波分量，改善了功率放大器的性能。
但是，发射机中的射频功率放大器还有可能产生频带外的杂散输出，杂散输出位于接收机频带内，如果不能很好地被隔离，可能会被耦合到接收机前端的低噪声放大器输入端，形成干扰，或者也会对其他相邻信道形成干扰。所以，需要对射频功率放大器进行进一步改进，使其不仅能抑制谐波，还能限制频带外的寄生输出。
发明内容
本发明所要解决的首要技术问题在于提供一种可以抑制谐波与杂散的射频功率放大器。
本发明所要解决的另一技术问题在于提供一种包括上述射频功率放大器的芯片及通信终端。
为了实现上述发明目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种抑制谐波与杂散的射频功率放大器，它包括电源、LDO电路、谐波抑制单元、杂散抑制单元、放大单元、低通匹配网络；其中，
所述电源与所述谐波抑制单元连接，在所述LDO电路与所述放大单元之间设置所述杂散抑制单元；
在所述放大单元的输出端设置所述低通匹配网络，通过所述低通匹配网络产生多个谐振频率，抑制经所述放大单元放大的射频信号在所述谐振频率处的谐波与杂散。
其中较优地，所述电源包括第一电源和第二电源，所述第一电源与所述第二电源共用所述谐波抑制单元。
其中较优地，所述谐波抑制单元的一端分别与所述电源连接，另一端接地；通过所述谐波抑制单元产生多个谐振频率，抑制所述电源在所述谐振频率处的谐波与杂散。
其中较优地，所述谐波抑制单元为多个LC串联谐振电路并联组成的LC阵列，每个LC串联谐振电路由电容与电感串联组成。
其中较优地，所述杂散抑制单元由多个负载级联组成，每一级负载通过隔离电感与下一级负载连接，实现对杂散的隔离。
其中较优地，所述每一级负载包括负载电感与LC阵列，所述LC阵列的一端分别与所述负载电感和所述隔离电感连接，另一端接地；
所述负载电感的另一端与放大单元中对应的晶体管的集电极或漏极连接，所述晶体管的发射极或源极接地；
通过所述每一级负载产生低于工作频率的多个谐振点以及与所述谐振点对应的谐振频率，抑制所述晶体管在所述谐振频率处的杂散。
其中较优地，所述每一级负载中产生的谐振点的数目以及谐振频率相互独立，通过灵活配置以抑制所述晶体管在不同频率处的杂散。
其中较优地，所述低通匹配网络为多个匹配网络级联组成的多级匹 配网络，每一级匹配网络由第一电感、第一电容、第二电感、第二电容组成；
所述第一电感与所述第一电容并联组成LC并联谐振电路，所述第二电感与所述第二电容串联组成LC串联谐振电路；
所述LC串联谐振电路的一端分别与本级匹配网络的所述LC并联谐振电路以及下一级匹配网络的所述LC并联谐振电路连接，所述LC串联谐振电路的另一端接地。
其中较优地，在所述每一级匹配网络中，所述LC并联谐振电路的谐振频率高于工作频率，所述LC串联谐振电路的谐振频率高于工作频率，通过电压分压作用、电流分流作用抑制射频信号在所述谐振频率处的谐波与杂散。
其中较优地，所述放大单元由至少一级放大电路级联组成；
每一级放大电路由晶体管组成，各级放大电路之间通过电容连接；
所述每一级放大电路分别与所述杂散抑制单元连接。
根据本发明实施例的第二方面，提供一种芯片，包括有上述任意一项所述的射频功率放大器。
根据本发明实施例的第三方面，提供一种通信终端，包括有上述任意一项所述的射频功率放大器。
本发明所提供的射频功率放大器，一方面通过使第一电源与第二电源共用谐波抑制单元，实现抑制第一电源与第二电源在谐振频率处的谐波与杂散，并且通过杂散抑制单元降低放大单元在谐振频率处的增益，从而降低输出杂散。另一方面，通过在射频功率放大器的输出端嵌入低通匹配网络，抑制经放大单元放大的射频信号在不同频率处的谐波与杂散。同时，由于本射频功率放大器主要是通过在电源通路上连接LC阵列以及运用低通匹配网络实现对谐波以及杂散的有效抑制，所以简化了射频功率放大器的设计复杂度，降低了相关设计实现的成本。
附图说明
图1为本发明所提供的一种射频功率放大器的电路原理图；
图2为本发明所提供的射频功率放大器中，谐波抑制单元的原理图；
图3为本发明所提供的射频功率放大器中，杂散抑制单元与放大 单元的连接示意图；
图4为本发明所提供的射频功率放大器中，杂散抑制单元的每一级负载与对应放大电路的连接示意图；
图5为本发明所提供的射频功率放大器中，低通匹配网络的电路原理图；
图6为本发明所提供的另一种射频功率放大器的电路原理图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
首先需要说明的是，在本发明的各个实施例中，所涉及的通信终端指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，该射频功率放大器也适用于其他功率放大电路应用的场合，例如兼容多种通信制式的通信基站等。
图1为本发明所提供的一种可以抑制谐波与杂散的射频功率放大器的电路原理图。如图1所示，该射频功率放大器包括控制电路101、LDO(low dropout regulator，低压差线性稳压器)电路103、杂散抑制单元105、谐波抑制单元108、放大单元、低通匹配网络114。其中，第一电源106为控制电路101提供供电电压，使控制电路101产生控制电压102，通过控制电压102以及第二电源107控制LDO电路103，以便根据不同的功率等级输出不同的电压104。通过在第二电源107与大地之间设置谐波抑制单元108，有效抑制第二电源107供电过程中产生的谐波杂散分量，保证为LDO电路103提供稳定的供电电压，从而抑制LDO电路103输出的电压104中的谐波杂散分量。通过在电压104与放大单元之间设置杂散抑制单元105，可以让放大单元在谐振频率处增益降低，从而降低输出杂散(杂散主要是由放大单元产生的，不是LDO电路产生的)。经过放大后的射频信号最终通过低通匹配网络114输出给负载(例如天线)。通过低通匹配网络114不仅能够实现阻抗匹配，而且还能抑制输出的射频信号中的谐波以及杂散，使射频信号落入到另外一个系统的接收频段内也不会造成干扰。
在本发明的一个实施例中，上述放大单元可以由一个或一个以上的 晶体管(包括但不限于场效应管或双极晶体管，下同)组成，也可以是由多个放大电路级联组成的多级放大电路。这些晶体管可以是同类型的晶体管，也可以是不同类型的晶体管。如图1所示，多级放大电路由第一级放大电路111与第N(N为正整数)级放大电路112级联组成，图1中为了简化起见，只标示出了第一级放大电路111与最后一级放大电路112，在第一级放大电路111与最后一级放大电路112之间可以有多个放大电路，通过将多个放大电路分别与杂散抑制单元105连接，可以有效抑制放大单元产生的杂散。
在本发明的一个实施例中，LDO电路103可以为任何能够根据不同的功率等级输出不同电压的低压差线性稳压器。通过低压差线性稳压器，保证每个晶体管的各个端口间电压差不超过自身工艺标称电压值，防止随着电源电压的升高，使晶体管端电压差超过其自身工艺标称的耐压值，使器件面临烧坏的危险。
图2为本射频功率放大器的一个实施例中，谐波抑制单元108的电路原理图。如图2所示，该谐波抑制单元108为M(M为正整数，下同)个LC串联谐振电路并联组成的LC阵列。其中，LC串联谐振电路由电容与电感串联组成。参见图2中的虚线框处，电容202与电感203串联组成第一级串联谐振电路，电容204与电感205组成第二级串联谐振电路，依此类推，电容206与电感207组成第M级串联谐振电路。LC阵列可以有任意级数，由第一级串联谐振电路、第二级串联谐振电路以及第M级串联谐振电路并联在一起组成了LC阵列。将本射频功率放大器的谐波抑制单元108的一端201与第二电源107连接，谐波抑制单元108的另一端208接地。由于电容202与电感203产生谐振频率f1，电容204与电感205产生谐振频率f2，电容206与207产生谐振频率fM，第二电源107对地阻抗在频率f1、频率f2以及频率fM处表现为低阻，从而能够抑制第二电源107在频率f1、频率f2以及频率fM处的谐波以及杂散。其中，频率f1、频率f2以及频率fM可以设定为任意不同频率(高于工作频率或者低于工作频率)。通过在第二电源107与大地之间嵌入谐波抑制单元108，抑制了第二电源供电过程中在不同谐振频率处的谐波以及杂散。
图3为本射频功率放大器的一个实施例中，杂散抑制单元105与放 大单元连接的示意图。如图3中的虚线框处所示，第一级负载(即第一级放大电路的负载)由电感307、LC阵列308、电感309组成。其中，LC阵列308的一端分别与电感307和电感309的一端连接，LC阵列308的另一端接地，电感309作为第一级放大电路的负载电感，通过将负载电感309的另一端与第一级放大电路的晶体管312的集电极或漏极(图中未示出)连接，不仅能实现负载功能，同时还能够抑制杂散。电感307作为级间隔离电感，它的另一端与第二级负载连接，第二级负载与第一级负载相同，为简化说明，图3中仅示出了第一级负载，第N－1级负载以及第N(N为正整数，下同)级负载。第N－1级负载(第N－1级放大电路的负载)由电感304、LC阵列305、电感306组成。其中，LC阵列305的一端分别与电感304和电感306的一端连接，LC阵列308的另一端接地，电感306作为第N－1级放大电路的负载电感，通过将负载电感306的另一端与第N－1级放大电路的晶体管311的集电极或漏极(图中未示出)连接，同样不仅能实现负载功能，同时还能够抑制杂散。电感304作为级间隔离电感，它的另一端与第N级负载连接。电感304与电感307的电感值通常较大，以便实现对杂散的隔离。第N级负载(即第N级放大电路的负载)由电感303、LC阵列302组成。其中，LC阵列302的一端分别与电感303的一端以及电压源301(图1中的电压104)连接，LC阵列302的另一端接地，电感303作为第N级放大电路的负载电感，通过将负载电感303的另一端与第N级放大电路的晶体管310的集电极或漏极(图中未示出)连接，同样不仅能实现负载功能，同时还能够抑制杂散。综上所述，杂散抑制单元105由N个放大电路的负载级联组成，通过将每一级负载中的隔离电感与下一级负载相连，实现对放大单元中杂散的隔离；并且，将每一级负载中的负载电感分别与对应的放大电路中的晶体管的集电极或漏极对应连接，实现对每一级放大电路中的晶体管的杂散的抑制作用。电压源301分别通过每一级负载为对应的放大电路提供供电电压，通过杂散抑制单元105为每一级放大电路滤去了杂散对射频信号的干扰。射频信号传输到放大单元中，在放大单元的每一级放大电路之间设置电容，通过电容使经上一级放大电路放大后的射频信号传输到下一级放大电路中，最终通过最后一级放大电路将放大后的射频信号对外进行 输出。
图4为杂散抑制单元105的每一级负载与对应放大电路的连接示意图。如图4所示，每一级负载由负载电感、LC阵列400组成，并且每一级负载之间通过隔离电感相连。其中，LC阵列400为M(M为正整数，下同)个LC串联谐振电路并联组成。LC串联谐振电路由电容与电感串联组成。参见图4中的虚线框处，电容402与电感403串联组成第一级串联谐振电路，电容404与电感405组成第二级串联谐振电路，电容406与电感407组成第M级串联谐振电路。LC阵列可以有任意级数，由第一级串联谐振电路、第二级串联谐振电路以及第M级串联谐振电路并联在一起组成了LC阵列400。将LC阵列400的一端409分别与负载电感401和隔离电感408的一端连接，LC阵列400的另一端410接地，并且负载电感401的另一端与放大电路中的晶体管411的集电极或漏极(图中未示出)连接，晶体管411的发射极或源极接地。由于隔离电感408为级间隔离电感，可以将隔离电感408视为高阻，负载电感401与LC阵列400产生M个谐振点，M个谐振点对应的谐振频率分别为f1、f2……fM。晶体管411的对地阻抗在这M个频率处表现为低阻，从而抑制晶体管411在这M个频率处的杂散。为了兼顾工作频带的性能，频率f1、f2…fM设定为低于工作频率，因此，LC阵列400与负载电感401配合可以抑制低于工作频率处的杂散。综上所述，每一级负载中的负载电感与LC阵列产生低于工作频率的多个谐振点，并且每一级负载中产生的谐振点的数目以及谐振频率相互独立，可以灵活配置以抑制不同频率处的杂散。
图5为本射频功率放大器的一个实施例中，低通匹配网络的电路原理图。如图5所示，该低通匹配网络500(在图1中标号为114)由N(N为正整数，下同)个匹配网络级联组成的多级匹配网络。其中，每一级匹配网络由第一电感、第一电容、第二电感、第二电容组成，第一电感与第一电容并联组成LC并联谐振电路，第二电感与第二电容串联组成LC串联谐振电路，LC串联谐振电路的一端与LC并联谐振电路连接，LC串联谐振电路的另一端接地。在每一级匹配网络中，设定LC并联谐振电路的谐振频率f1高于工作频率，设定LC串联谐振电路的谐振频率f2高于工作频率。那么，在LC并联谐振电路中，第一电感与第一电容并联在一 起在谐振频率f1处表现为高阻，通过电压分压作用可以抑制谐振频率f1处的谐波以及杂散。在LC串联谐振电路中，第二电感与第二电容串联在一起后的对地阻抗在谐振频率f2处表现为低阻，通过分流作用可以抑制谐振频率f2处的谐波以及杂散。在每一级匹配网络中，LC并联谐振电路在工作频率处表现为感性，LC串联谐振电路在工作频率处表现为容性，因此每一级匹配网络在工作频率处为L-C低通匹配网络。具体地说，如图5所示，由电感501、电感502、电容503、电感504组成第一级匹配网络，由电感505、电感506、电容507、电感508组成第二级匹配网络，由电感509、电感510、电容511、电感512组成第N级匹配网络。其中，电感501与电感502并联组成LC并联谐振电路，电感502与电容503串联组成LC串联谐振电路。在第二级匹配网络、……第N级匹配网络中，同样由电感505与电感506、电容507与电感508、509与电感510、电容511与电感512分别组成了LC并联谐振电路、LC串联谐振电路，并且每一级匹配网络的工作原理已经在上文中说明，在此不再赘述。
在本射频功率放大器的低通匹配网络中，每一级匹配网络的LC并联谐振电路的一端分别与本级匹配网络的LC串联谐振电路的一端以及下一级匹配网络的LC并联谐振电路相连，并且每一级匹配网络的LC串联谐振电路的另一端接地。通过低通匹配网络可以将经放大单元放大的射频信号中的谐波以及杂散滤除，保证输出的射频信号的稳定性。由于每一级匹配网络会产生2个谐振点，所以低通匹配网络总共可以产生2N(N为正整数，下同)个谐振点，并且这2N个谐振点可以相互独立配置，在实现低通阻抗匹配功能的同时，还实现了抑制谐波与杂散的作用。
需要说明的是，本发明所提供的射频功率放大器为了避免第一电源106为控制电路101提供供电电压过程中，可能在耦合作用下产生谐波杂散分量，可以将第一电源106与第二电源107连接在一起，通过使第一电源106与第二电源107共用谐波抑制单元108，实现对第一电源106与第二电源107供电过程中产生的谐波杂散分量的抑制。对此，可以参阅图6所示的射频功率放大器的另一实施例。在该实施例中，通过谐波抑制单元608(即图1中的谐波抑制单元108)实现抑制第一电源606(即图1中的第一电源106)与第二电源607(即图1中的第二电源107)中的谐波与杂散，并且为控制电路601以及LDO电路603分别提供供电电 压，使控制电路产生的控制电压602能够控制LDO电路603输出不同的电压604，该电压604通过杂散抑制单元605，实现对电压604产生的杂散的有效抑制，为放大单元提供稳定无干扰的供电电压，射频信号通过放大单元(由第一级放大电路611到第N级放大电路612组成)进行放大，并且通过低通匹配网络614进行谐波与杂散的滤除，最终将放大的射频信号输出给负载(天线)。由于图6中的射频功率放大器的结构与图1中的射频功率放大器结构相比，只是将第一电源606与第二电源607连接在一起，所以对该射频功率放大器的结构及原理不再进行详细描述。
本发明所提供的射频功率放大器，一方面通过使第一电源与第二电源通路共用谐波抑制单元，谐波抑制单元采用LC阵列，实现抑制第一电源与第二电源在谐振频率处的谐波与杂散。通过采用多个由负载电感、LC阵列组成的负载，并且将每一级负载通过隔离电感级联组成杂散抑制单元，利用杂散抑制单元抑制放大单元的杂散。另一方面，通过在本射频功率放大器的输出端嵌入低通匹配网络，从而实现抑制经放大单元放大的射频信号在不同频率处的谐波与杂散。同时，本射频功率放大器通过在电源通路上连接LC阵列以及运用低通匹配网络实现对谐波以及杂散的有效抑制，简化了射频功率放大器的设计复杂度，降低了相关设计实现的成本。
上述可以抑制谐波与杂散的射频功率放大器可以用在芯片中。对于该芯片中使用的射频功率放大器的具体结构和连接方式，在此就不再具体说明了。
另外，本发明所提供的可以抑制谐波与杂散的射频功率放大器还可以被用在通信终端中，作为射频电路的重要组成部分。这里所说的通信终端指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括但不限于移动电话、笔记本电脑、平板电脑、车载电脑等。此外，该射频功率放大器也适用于其他多模技术应用的场合，例如兼容多种通信制式的通信基站等，在此就不一一详述了。
以上对本发明所提供的抑制谐波与杂散的射频功率放大器、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质精神的前提下对它所做的任何显而易见的改动，都将 属于本发明专利权的保护范围。

Claims (12)

  1. 一种抑制谐波与杂散的射频功率放大器，其特征在于包括电源、LDO电路、谐波抑制单元、杂散抑制单元、放大单元、低通匹配网络；其中，
    所述电源与所述谐波抑制单元连接，在所述LDO电路与所述放大单元之间设置所述杂散抑制单元；
    在所述放大单元的输出端设置所述低通匹配网络，通过所述低通匹配网络产生多个谐振频率，抑制经所述放大单元放大的射频信号在所述谐振频率处的谐波与杂散。
  2. 如权利要求1所述的射频功率放大器，其特征在于：
    所述电源包括第一电源和第二电源，所述第一电源与所述第二电源共用所述谐波抑制单元。
  3. 如权利要求1或2所述的射频功率放大器，其特征在于：
    所述谐波抑制单元的一端分别与所述电源连接，另一端接地；通过所述谐波抑制单元产生多个谐振频率，抑制所述电源在所述谐振频率处的谐波与杂散。
  4. 如权利要求3所述的射频功率放大器，其特征在于：
    所述谐波抑制单元为多个LC串联谐振电路并联组成的LC阵列，每个LC串联谐振电路由电容与电感串联组成。
  5. 如权利要求1或2所述的射频功率放大器，其特征在于：
    所述杂散抑制单元由多个负载级联组成，每一级负载通过隔离电感与下一级负载连接，实现对杂散的隔离。
  6. 如权利要求5所述的射频功率放大器，其特征在于：
    所述每一级负载包括负载电感与LC阵列，所述LC阵列的一端分别与所述负载电感和所述隔离电感连接，另一端接地；
    所述负载电感的另一端与放大单元中对应的晶体管的集电极或漏极连接，所述晶体管的发射极或源极接地；
    通过所述每一级负载产生低于工作频率的多个谐振点以及与所述谐振点对应的谐振频率，抑制所述晶体管在所述谐振频率处的杂散。
  7. 如权利要求6所述的射频功率放大器，其特征在于：
    所述每一级负载中产生的谐振点的数目以及谐振频率相互独立，通过灵活配置以抑制所述晶体管在不同频率处的杂散。
  8. 如权利要求1或2所述的射频功率放大器，其特征在于：
    所述低通匹配网络为多个匹配网络级联组成的多级匹配网络，每一级匹配网络由第一电感、第一电容、第二电感、第二电容组成；
    所述第一电感与所述第一电容并联组成LC并联谐振电路，所述第二电感与所述第二电容串联组成LC串联谐振电路；
    所述LC串联谐振电路的一端分别与本级匹配网络的所述LC并联谐振电路以及下一级匹配网络的所述LC并联谐振电路连接，所述LC串联谐振电路的另一端接地。
  9. 如权利要求8所述的射频功率放大器，其特征在于：
    在所述每一级匹配网络中，所述LC并联谐振电路的谐振频率高于工作频率，所述LC串联谐振电路的谐振频率高于工作频率，通过电压分压作用、电流分流作用抑制射频信号在所述谐振频率处的谐波与杂散。
  10. 如权利要求1或2所述的射频功率放大器，其特征在于：
    所述放大单元由至少一级放大电路级联组成；
    每一级放大电路由晶体管组成，各级放大电路之间通过电容连接；
    所述每一级放大电路分别与所述杂散抑制单元连接。
  11. 一种芯片，其特征在于包括有权利要求1～10中任意一项所述的射频功率放大器。
  12. 一种通信终端，其特征在于包括有权利要求1～10中任意一项所述的射频功率放大器。
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US20200186099A1 (en) 2020-06-11

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