WO2018040864A1 - Semiconductor device and method for manufacturing same - Google Patents

Abstract

A semiconductor device and a method for manufacturing same. The method comprises: step 1, providing a semiconductor substrate (100), forming a source, a drain, and a gate (101) on the semiconductor substrate (100), and forming a drift region on the semiconductor substrate (100) between the gate (101) and the drain; step 2, forming a first dielectric layer (1031) to cover the surface of the semiconductor substrate (100) as well as the source, the drain, and the gate (101); and step 3, forming a first field plate layer (1041) on the first dielectric layer (1031), the first field plate layer (1041) being located at least in part above the drift region and adjacent to one side of the gate (101).

Description

Semiconductor device and method of manufacturing same Technical field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method of fabricating the same.

Background technique

Conventional high-voltage device structures generally extend the polysilicon to the drain by adjusting the polysilicon length of the gate to act as a field plate. The field plate depletes the drift region to form a depletion layer, thereby increasing the width of the lateral depletion layer and thereby increasing Withstand voltage (ie breakdown voltage). In addition, a field plate oxide layer is disposed under the field plate to form a field plate structure, and the field plate oxide layer generally introduces an additional oxide layer between the drain and the gate in the drift region. The negative effects limit the compatibility of the process and the characteristics of the components. It is difficult to integrate low-voltage to high-voltage devices in a process platform, especially advanced process platforms, because small-sized devices in low-voltage devices have very high effective channel width (channel Width). Sensitive, how to control the effective channel width is a challenge for advanced process platforms. However, the addition of high-voltage devices to the platform requires the introduction of additional oxide layers as field oxide layers for high-voltage devices. Additional oxide layer formation methods often require additional Oxide layer growth and rinsing processes cause irreversible changes in the effective channel width of the active region, which in turn affects compatibility between process platforms.

If an additional oxide layer is not introduced as the field oxide layer of the high voltage device, a parasitic oxide layer (eg, double gate field oxide layer, STI, etc.) is used to implement the high voltage device, although the effective channel width can be maintained, The parasitic oxide layer limits the thickness and shape of the oxide layer, causing the path of current flowing through the drift region to bend and lengthen, directly affecting the performance of the high voltage device and reducing the performance of the high voltage device.

It is a common method to achieve the desired high voltage device by fixing the oxide thickness of the field plate and adjusting the length of the polysilicon, but thus increasing the gate charge (Qgd). Since the field plate and the gate polysilicon are inseparable, the longer the higher voltage device field plate, the larger the gate charge (Qgd), which limits the final characteristics of the high voltage device.

Summary of the invention

A series of simplified forms of concepts are introduced in the Summary of the Invention section, which will be described in further detail in the Detailed Description section. The inventive content of the present invention is not meant to be an attempt to define The key features and essential technical features of the claimed technical solution are not meant to be an attempt to determine the scope of protection of the claimed technical solution.

In view of the deficiencies of the prior art, the present invention provides a semiconductor device and a method of fabricating the same.

A method of fabricating a semiconductor device, comprising:

Step 1: providing a semiconductor substrate, forming a source, a drain, and a gate on the semiconductor substrate, and forming a drift region in the semiconductor substrate between the gate and the drain,

Step two, forming a first dielectric layer to cover a surface of the semiconductor substrate and a source, a drain, and a gate,

Step 3, forming a first field plate layer on the first dielectric layer, and the first field plate layer is at least partially located above the drift region and adjacent to the gate side.

A semiconductor device having a separate planar field plate structure, comprising:

a semiconductor substrate on which a source, a drain and a gate are formed, and a drift region is formed in a semiconductor substrate between the gate and the drain;

a first dielectric layer covering a surface of the semiconductor substrate and a source, a drain, and a gate;

A first field plate layer is formed on the first dielectric layer, the first field plate layer being at least partially located above the drift region and adjacent to the gate side.

DRAWINGS

The following drawings of the invention are hereby incorporated by reference in their entirety in their entirety. The embodiments of the invention and the description thereof are shown in the drawings

In the figure:

1A is a schematic view showing a structure obtained by an implementation of a method of fabricating a semiconductor device having a separate planar field plate structure in an embodiment;

1B is a schematic view showing a structure obtained by an implementation of a method of fabricating a semiconductor device having a separate planar field plate structure in another embodiment;

1C is a schematic view showing a structure obtained by an implementation of a method of fabricating a semiconductor device having a separate planar field plate structure in still another embodiment;

2 shows an SEM (Scanning Electron Microscope) diagram of a semiconductor device having a separate planar field plate structure in one embodiment;

3 is a flow chart showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

detailed description

In the following description, numerous specific details are set forth in the However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some of the technical features well known in the art have not been described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. In the drawings, the size and relative dimensions of the layers and regions may be exaggerated for clarity. The same reference numbers indicate the same elements throughout.

It will be understood that when an element or layer is referred to as "on", "adjacent", "connected to" or "coupled to" another element or layer, it may be directly on the other element or layer, Adjacent, connected or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers. It should be understood that the terms, components, regions, layers, and/or portions may not be limited by the terms of the first, second, third, etc. The terms are only used to distinguish one element, component, region, layer, Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section.

Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used herein for convenience of description. The relationship of one element or feature shown in the figures to the other elements or features is thus described. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned "on" or "below" or "below" or "under" the element or feature is to be "on" the other element or feature. Thus, the exemplary terms "below" and "include" can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing the particular embodiments and embodiments The singular forms "a", "the", and "the" The term "composition" and/or "comprising", when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more Features, integers, steps, operations, components, components And/or the presence or addition of a group. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations of schematic representations of the preferred embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown can be expected as a result, for example, of manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the specific shapes of the regions illustrated herein, but rather include variations in the shape, for example. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implanted concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. The regions shown in the figures are, therefore, are not intended to limit the scope of the invention.

In order to thoroughly understand the present invention, a detailed manufacturing method will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but the present invention may have other embodiments in addition to the detailed description.

In order to solve the problems existing in the prior art, the present invention provides a method of fabricating a semiconductor device, as shown in FIG. 3, which includes the following main steps:

Step S1, providing a semiconductor substrate, forming a source, a drain, and a gate on the semiconductor substrate, and forming a drift region in the semiconductor substrate between the gate and the drain;

Step S2, forming a first dielectric layer to cover a surface of the semiconductor substrate and a source, a drain, and a gate;

Step S3, forming a first field plate layer on the first dielectric layer, and the first field plate layer is at least partially located above the drift region and adjacent to the gate side.

According to the above manufacturing method of the present invention, in the process of depositing the dielectric layer, the steps of depositing the dielectric layer and forming the field plate layer are alternately performed to form a separate planar field plate including one, two or more field plate layers. structure. Since no additional oxide layer is introduced, the front-end process does not change, and the compatibility between process platforms is achieved. The field plate is added during the deposition process of the latter dielectric layer, and the process structure of the multi-layer separated planar field plate structure is realized, and the oxide layer under the field plate can be freely adjusted.

Hereinafter, a method of fabricating a semiconductor device in an embodiment will be described in detail with reference to FIGS. 1A and 1B, wherein FIG. 1A shows an implementation of a method of fabricating a semiconductor device having a separate planar field plate structure in an embodiment. Schematic diagram of the structure; FIG. 1B is a schematic view showing the structure obtained by the implementation of the method of fabricating the semiconductor device having the separated planar field plate structure in one embodiment.

As an example, a method of fabricating a semiconductor device includes the following steps:

First, as shown in FIG. 1A, a semiconductor substrate 100 is provided.

Specifically, the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and silicon germanium stacked on the insulator. (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 100 is selected from single crystal silicon.

The semiconductor substrate 100 may also be a P-type semiconductor substrate or an N-type semiconductor substrate. For example, an N-type high voltage device may select a P-type semiconductor substrate, and a P-type high voltage device may select an N-type semiconductor substrate. .

Illustratively, a shallow trench isolation structure (STI) is formed in the semiconductor substrate to define an active region.

Illustratively, a drift region (not shown) is formed in the semiconductor substrate 100.

The drift region can be formed using a suitable method depending on the type of the device. For example, if an N-type high voltage device is prepared, the semiconductor substrate 100 is doped with N-type ions to form an N-type drift region in the substrate. When a P-type high voltage device is prepared, the semiconductor substrate 100 is subjected to P-type ion doping to form a P-type drift region.

Doping is generally achieved by means of implantation. The higher the doping concentration required, the correspondingly the implant dose during the injection should also be higher. In general, the drift region has a low doping concentration, which is equivalent to forming a high resistance layer between the source and the drain, which can increase the breakdown voltage and reduce the parasitic capacitance between the source and the drain. Conducive to improve the frequency characteristics. For example, in one embodiment, the implanted impurity is phosphorus, and the implantation dose of the drift region may be 1.0 x 10 ¹² to 1.0 x 10 ¹³ cm ^-2 .

In one example, a body region may also be formed in the semiconductor substrate 100, the body region being located outside the drift region and spaced apart from the drift region, generally between the body region and the drift region, a channel region of the device, wherein The body region and the drift region have opposite conductivity types, that is, when the drift region is N-type, the body region is P-type, or when the drift region is P-type, the body region is N-type, and the drift region and the channel region are It also has the opposite conductivity type.

Other well regions and the like may also be formed in the semiconductor substrate 100, and will not be described herein.

Further, as shown in FIG. 1A and FIG. 1B, a gate electrode 101 covering a channel region is formed on the semiconductor substrate 100, and the gate electrode includes a gate dielectric layer on the surface of the semiconductor substrate 100 and is located on the gate. The gate layer on the very dielectric layer.

In one example, the method of forming the gate electrode 101 may include the steps of sequentially forming a gate dielectric layer and a gate layer on the semiconductor substrate 100, patterning the gate dielectric layer and the gate layer to form a gate Extreme 101. In an embodiment, the gate dielectric layer can comprise a conventional dielectric material such as There are oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). The gate layer is composed of a polysilicon material, and a metal, a metal nitride, a metal silicide or the like can also be generally used as the material of the gate layer. Preferred methods for forming the gate layer include chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), and plasma chemical vapor deposition (PECVD). A similar method such as sputtering and physical vapor deposition (PVD) can also be used. The thickness of the gate layer may be a suitable thickness depending on the size of the device, and is not specifically limited herein.

Subsequently, a spacer (not shown) may also be selectively formed on the sidewall of the gate electrode 101. The spacer may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an embodiment of the present embodiment, the spacer is composed of silicon oxide and silicon nitride, and the specific process is: forming a first silicon oxide layer, a first silicon nitride layer, and a second oxide on the semiconductor substrate. The silicon layer is then etched to form spacers.

Illustratively, ion implantation is performed to form a body region lead-out region of the same conductivity type as the body region in the body region, for example, the body region is P-type, and the body region lead-out region may also be P-type, and its impurity doping The impurity concentration is greater than the impurity doping concentration of the body region, for example, the body region lead-out region is heavily doped with a P-type impurity.

Subsequently, source-drain ion implantation is performed to form a source and a drain (not shown) in the semiconductor substrate 100 on both sides of the gate electrode 101, wherein the drain is formed in the drift region, the drain The pole has the same conductivity type as the drift region, for example, the drift region is an N-type drift region, and the drain and the source may be an N-type source and drain, which may also be an N-type Doped ion heavily doped source and drain.

Next, a separate planar field plate structure is formed on the outer side of the gate electrode 101, wherein the method for forming the separate planar field plate structure comprises:

A first dielectric layer 1031 is deposited to cover the gate 101 and a surface of the semiconductor substrate 100 (including a surface of a source and a drain).

A first field plate layer 1041 is formed on the first dielectric layer 1031, and the first field plate layer 1041 is at least partially located above the drift region and adjacent to the gate 101 side.

In one example, before the deposition of the first dielectric layer 1031, a contact hole etch stop layer 102 may be selectively formed to cover the gate electrode 101 and the surface of the semiconductor substrate 100, the material of the contact hole etch stop layer 102. It may be one or more of materials such as SiCN, SiN, SiC, SiOF, SiON, and the like.

Subsequently, a separate planar field plate structure is formed on the outside of the gate electrode 101.

In one embodiment, as shown in FIG. 1A, a sub-layer layer structure may be formed. The off-plane field plate structure includes steps S11 to S12:

Step S11, depositing a first dielectric layer 1031 to cover the surface of the semiconductor substrate 100 and the source, drain and gate 101;

Step S12, forming a first field plate layer 1041 on the first dielectric layer 1031, and the first field plate layer 1041 is at least partially located above the drift region and near the side of the gate electrode 101, exemplary The first field plate layer 1041 is partially located above the gate electrode 101, and the first field plate layer 1041 includes a portion on the gate and a portion on the drift region, in another example. The first field plate layer 1041 may also all be located above the drift region.

Thereafter, after forming the separated planar field plate structure, a third dielectric layer may be deposited to cover the surface of the first dielectric layer 1031 and the first field plate layer 1041 to planarize the third dielectric layer. Wherein the third dielectric layer and the first dielectric layer are the same material.

The total thickness of the third dielectric layer formed by the deposition may range from 10,000 to 20,000 angstroms, for example, 12,000 angstroms, 14,000 angstroms, 16,000 angstroms, 18,000 angstroms, etc., and the above thickness ranges are only exemplified, and are specifically set according to the needs of the device process. The third dielectric layer is then planarized to a target thickness, which can be achieved using chemical mechanical polishing.

In one embodiment, as shown in FIG. 1B, a separate planar field plate structure including a two-layer field plate layer structure may be formed. Specifically, the step of forming a separate planar field plate structure as shown in FIG. 1B includes the step A1. To A4:

Step A1, depositing a first dielectric layer 1031 to cover the surface of the semiconductor substrate 100 and the source, drain and gate 101;

Step A2, forming a first field plate layer 1041 on the first dielectric layer 1031, and the first field plate layer 1041 is at least partially located above the drift region and adjacent to the side of the gate 101, exemplary The first field plate layer 1041 is partially located above the gate electrode 101, and the first field plate layer 1041 includes a portion on the gate and a portion on the drift region, in another example. The first field plate layer 1041 may also be located above the drift region;

Step A3, as shown in FIG. 1B, a second dielectric layer 1032 is deposited to cover the surface of the first dielectric layer 1031 and the first field plate layer 1041;

Step A4, forming a second field plate layer 1042 on the second dielectric layer 1032, and the second field plate layer 1042 is located above the drift region and adjacent to the first field plate layer side.

Illustratively, the second field plate layer 1042 is located outside the first field plate layer, and a portion of the second field plate layer 1042 overlaps with a portion of the first field plate layer 1041, in one example, All of the second field plate layers are located above the drift region, and in another example, the second field plate There is no overlapping portion of layer 1042 and the first field plate layer 1041.

Further, the step A3 and the step A4 are performed alternately cyclically more than once, and the second field plate layer formed in the latter step is close to the side of the second field plate layer formed by the adjacent previous step, that is, after The formed second field plate layer is adjacent to the side of the adjacent previously formed second field plate layer to further obtain a multilayer separated planar field plate structure of more than two field plate layers.

Further, the upper and lower adjacent layers of the field plate layer are completely staggered or partially overlapped in the vertical direction.

Further, the second dielectric layer is thicker than the first dielectric layer, and the second dielectric layer formed in the latter step is thicker than the second dielectric layer formed in the adjacent previous step.

Referring to FIG. 1C, in another example, the step of forming a separate planar field plate structure includes steps B1 through B4:

Step B1, depositing a first dielectric layer 1031 to cover the surface of the semiconductor substrate 100 and the source, drain and gate electrodes 101;

Step B2, forming a first field plate layer 1041 on the first dielectric layer, and the first field plate layer 1041 is at least partially located above the drift region and adjacent to the side of the gate 101, exemplarily The first field plate layer 1041 is partially located above the gate electrode 101, and the first field plate layer 1041 includes a portion on the gate electrode 101 and a portion on the drift region, in another example. The first field plate layer 1041 may also be located above the drift region;

Step B3, thinning the first dielectric layer 1031 to cover an area other than the field plate layer. For the first step B3, the area where the first dielectric layer 1031 is not covered by the first field plate layer 1041 is thinned. The thinning can be performed by any common etching method, and the thickness after the specific thinning can be reasonably selected according to the actual process;

Step B4, forming a second field plate layer 1042 separated from the previous layer of the field plate layer on the thinned first dielectric layer 1031, and the second field plate layer 1042 is located above the drift region.

The step B3 and the step B4 are performed alternately or more cyclically. A stepped planar field plate structure having a plurality of field plate layers may be formed through steps B1 to B4, wherein a thickness of the dielectric layer below the field plate layer formed later is smaller than a thickness of the dielectric layer below the previously formed field plate layer .

In another example, the step of forming a separate planar field plate structure includes steps C1 through C4:

Step C1, depositing a first dielectric layer to cover a surface of the semiconductor substrate and a source, a drain, and a gate;

Step C2, forming a first field plate layer on the first dielectric layer, and the first field plate layer is at least partially located above the drift region and adjacent to the gate side, exemplarily, the a first field layer portion is located above the gate, the first field plate layer including a portion on the gate and a portion located on the drift region, in another example, the first field plate layer may also all be located above the drift region;

Step C3, etching the dielectric layer covered with the field plate layer until the semiconductor substrate is exposed, and etching the dielectric layer by any suitable etching method well known to those skilled in the art, including but not limited to dry etching Etching or wet etching;

Step C4, forming a second dielectric layer to cover the surface of the semiconductor substrate and the exposed field plate layer surface, forming a second field plate layer on the second dielectric layer, and the second field plate layer is located The drift region is above and adjacent to the first field plate layer side.

The step C3 and the step C4 are performed alternately and cyclically more than once, and the second field plate layer formed in the latter step is close to the side of the second field plate layer formed by the adjacent previous step, and the dielectric layer can be deposited by each time. The thickness of the dielectric layer (including the first dielectric layer or the second dielectric layer) is adjusted to adjust the thickness of the dielectric layer below the field plate layer.

It is worth mentioning that in the step of forming a separate planar field plate structure in the present specification and claims, the field plate layer may represent the first field plate layer or the second field plate layer, which may be implemented according to actual implementation. Steps to determine.

The first dielectric layer 1031 and the second dielectric layer 1032 may be a silicon oxide layer, including doped or not formed by a thermal CVD fabrication process or a high density plasma (HDP) fabrication process. A layer of material of doped silicon oxide, such as undoped silicon glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the first dielectric layer 1031 may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped. Tetraethoxysilane (BTEOS).

Further, the thickness of the first dielectric layer 1031 and the second dielectric layer 1032 deposited each time may be different or the same, and may be appropriately set according to the needs of a specific actual device. Illustratively, the thickness of the first dielectric layer 1031 and the second dielectric layer 1032 deposited each time may range from 200 angstroms to 4000 angstroms.

The first dielectric layer 1031 and the second dielectric layer 1032 are insulating interlayer dielectric layers conventionally used in devices. In the prior art, a first deposition process is used to form an interlayer dielectric layer covering the semiconductor substrate, and is performed. Flattening results in a flat surface. In one embodiment, the field plate layer is added when depositing the first dielectric layer 1031 and the second dielectric layer 1032 a plurality of times, so that the first dielectric layer 1031 and the second dielectric layer 1032 can also directly form a separate planar field. The field plate oxide layer of the plate structure, and compared with the prior art, there is no need to perform an additional field plate oxide layer formation step, thereby avoiding the need for additional oxide layer growth and rinsing process due to the formation of an additional field plate oxide layer. Active trench The problem of irreversible change in the width of the track, in turn, achieves the advantages of compatibility between process platforms.

In one example, the step of forming the first field plate layer 1041 further includes the steps of: depositing the first field plate layer 1041 on the surface of the first dielectric layer 1031, and forming the first field plate layer 1041 Patterning is performed to obtain the final desired pattern of the first field layer 1041, as shown in FIGS. 1A, 1B, and 2.

Illustratively, the thickness of the first field plate layer 1041 may range from 800 to 2500 angstroms, which is only an example, and other suitable thickness ranges are also applicable.

Similarly, the second field plate layer 1042 can be formed using the same method as the first field plate layer 1041.

In one example, the material of the first field plate layer 1041 and the second field plate layer 1042 may be a semiconductor material, and the semiconductor material may be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or other III- The binary or ternary compound of the group V, for example, the material of the field plate layer 104 may be polysilicon.

The polysilicon layer may be formed using a conventional technique such as chemical vapor deposition. For example, the polysilicon formation method may be a low pressure chemical vapor deposition (LPCVD) process. The process conditions for forming the polycrystalline silicon include: the reaction gas is silane (SiH ₄ ), the flow rate of the silane may be 100-200 cubic centimeters per minute (sccm), such as 150 sccm; and the temperature in the reaction chamber may range from 700 to 750. Celsius; the pressure in the reaction chamber may be 250-350 mmHg, such as 300 mTorr; the reaction gas may further include a buffer gas, which may be helium or nitrogen, and the helium and nitrogen The flow rate can range from 5 to 20 liters per minute (slm), such as 8 slm, 10 slm, or 15 slm.

After each deposition of the polysilicon field plate layer, a patterned photoresist layer may be formed by using a photolithography process to cover a portion of the polysilicon field plate layer, and then the patterned photoresist layer is used as a mask to expose the exposed layer. The polysilicon field plate layer is etched to form a desired field plate layer pattern in the target area. After the dielectric layer deposition and the field plate layer forming step are performed in a plurality of alternate cycles, the separated planar field plate structure is also correspondingly a polysilicon field plate, which may include one, two or more layers of polysilicon.

In one example, the materials of the first field plate layer 1041 and the second field plate layer 1042 may also include a metal silicide. The metal silicide can be formed using any method commonly used in the art including, but not limited to, a salicide. For example, a metal layer (not shown) is deposited on the surface of the aforementioned polysilicon field plate layer formed by each deposition. The material of the metal layer may be selected from one or more of Co, Ni, Ti, TiN, W, and WSix. The substrate is then heated to cause silicidation of the metal layer and the underlying polysilicon layer, and the metal silicide layer region is thus formed. An etchant that erodes the metal layer but does not erode the metal silicide layer region is then used to remove the unreacted metal layer to form a metal silicide material field plate layer. And performing multiple layers of alternating dielectric layer deposition and After the field plate layer forming step, the formed separate planar field plate structure is also correspondingly a metal silicide field plate, which may include one, two or more layers of metal silicide.

In one example, the materials of the first field plate layer 1041 and the second field plate layer 1042 include a metal material including Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al. One or more of the materials, in the embodiment, the material of the field plate layer 104 may be Al. It can be formed by low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD) or other advanced deposition techniques.

Wherein, a metal field plate layer may be deposited on the surface of each deposited dielectric layer, and a patterned photoresist layer may be formed by using a photolithography process to cover a portion of the metal field plate layer, and then patterned photoresist The layer is a mask that etches the exposed metal field plate layer to form a desired field plate layer pattern in the target area. After a plurality of alternating cycles of performing dielectric layer deposition and field plate layer formation steps, the formed separated planar field plate structure is correspondingly a metal field plate, which may include one, two or more layers of metal field plate layers. The use of a metal material as the field plate layer reduces the gate charge (Qgd) and improves the performance of the device compared to the prior art polysilicon field plate structure.

Illustratively, as shown in FIGS. 1A, 1B, and 2, wherein a separate planar field plate structure is formed over the drift region, the surface of the semiconductor substrate between the gate and the drain Above, that is, above the horizontal plane between the gate and the drain. This does not block the current path between the gate and the drain, thus shortening the drift region current path and improving device performance. In the prior art, the buried field plate structure is generally that the oxide layer of the field plate is partially located in the drift region, thereby blocking the current path between the gate and the drain, so that the current flow needs to bypass the field plate region, so The drift zone current path is increased, which affects the performance of the device. Further, the field plate layer located in the lower layer of the separate planar field plate structure is closer to the gate electrode 101 than the field plate layer located in the upper layer.

Further, the thickness of the dielectric layer under the field plate layer of the lower layer in the separate planar field plate structure is smaller than the thickness of the dielectric layer under the field plate layer of the upper layer, and can be controlled by each deposition The thickness of the dielectric layer is free to adjust the total thickness of the dielectric layer under each layer of the field plate layer, that is, to achieve free adjustment of the thickness of the field oxide layer.

Subsequently, after forming the separate planar field plate structure, depositing and planarizing the third dielectric layer 1033 on the semiconductor substrate, the third dielectric layer covering the surface of the second dielectric layer and the second field plate Floor. Wherein the third dielectric layer, the second dielectric layer and the first dielectric layer are the same material. After the step, the total thickness of the third dielectric layer 1033 formed by the deposition may range from 10,000 to 20,000 angstroms, for example, 12,000 angstroms, 14,000 angstroms, 16,000 angstroms, 18,000 angstroms, etc., and the thickness ranges are merely exemplified, depending on the device. The process needs to be properly set, and then The three dielectric layers 1033 are planarized to a target thickness, which can be achieved using chemical mechanical polishing.

Finally, a plurality of contact holes are formed in the third dielectric layer 1033, and a patterned metal layer is formed on the surface of the third dielectric layer 1033. The contact holes are electrically connected to the source, drain, gate, body lead-out regions, and each layer of the field plate structure of the separate planar field plate structure. Wherein, the contact hole electrically connected to the gate and the separated planar field plate structure is further electrically connected to the same metal layer on the dielectric layer to realize electrical connection between the gate and the separated planar field plate structure. The source, drain, gate, body lead-out regions, and each of the field plate layers of the separate planar field plate structure may also be extracted by a metal interconnect structure composed of a plurality of metal layers and contact holes. The material of the contact hole and the metal layer in the interconnect structure may be a metal material such as aluminum or copper.

It is worth mentioning that the above manufacturing method of the semiconductor device can be applied to the preparation of any device that requires preparation of a field plate, such as a high voltage device. The high voltage device can be a high voltage device commonly used in the field of semiconductor technology, such as DMOS (Double Diffused MOSFET, double diffused metal oxide semiconductor field effect transistor). There are two main types of DMOS: vertical double diffused metal oxide semiconductor field effect transistor VDMOSFET (vertical double-diffused MOSFET, VDMOS for short) and lateral double-diffused MOSFET (LDMOS).

In summary, in the above manufacturing method, the steps of depositing the dielectric layer and forming the field plate layer are alternately performed during the process of depositing the dielectric layer to form a separate planar field including one, two or more field plate layers. Board structure. Since no additional oxide layer is introduced, the front-end process does not change, and the compatibility between process platforms is achieved. The field plate is added during the deposition process of the latter dielectric layer, and the process structure of the multi-layer separated planar field plate structure is realized, and the oxide layer under the field plate can be freely adjusted. Moreover, the separate planar field plate structure formed by the above manufacturing method shortens the drift region current path and improves the performance of the device.

It is also necessary to provide a semiconductor device which can be a semiconductor device which is obtained by the method of the foregoing embodiment.

In one embodiment, as shown in FIG. 1A, the semiconductor device includes:

a semiconductor substrate 100 having a source, a drain, and a gate 101 formed on the semiconductor substrate 100, and a drift region formed in the semiconductor substrate 100 between the gate 101 and the drain;

a first dielectric layer 1031 covering a surface of the semiconductor substrate 100 and a source, a drain, and a gate 101;

a first field plate layer 1041 formed on the first dielectric layer 1031, the first field plate layer being at least partially located above the drift region and adjacent to the side of the gate electrode 101, exemplarily, the First A plate layer 1041 is partially located above the gate 101, the first field plate layer 1041 includes a portion on the gate and a portion on the drift region, and in another example, the first The field plate layer 1041 may also all be located above the drift region;

Provided on the separate planar field plate structure and the semiconductor substrate with a third dielectric layer covering the surface of the first dielectric layer 1031 and the first field plate layer 1041, wherein the third dielectric layer and the first medium Layer 1031 is the same material and the third dielectric layer has a flat surface.

In another embodiment, as shown in FIG. 1B and FIG. 2, the semiconductor device includes:

a semiconductor substrate 100 having a source, a drain, and a gate 101 formed on the semiconductor substrate 100, and a drift region formed in the semiconductor substrate between the gate 101 and the drain;

a first dielectric layer 1031 covering a surface of the semiconductor substrate 100 and a source, a drain, and a gate 101;

a first field plate layer 1041 formed on the first dielectric layer 1031, the first field plate layer being at least partially located above the drift region and adjacent to the side of the gate electrode 101, exemplarily, the A first field plate layer 1041 is partially located above the gate electrode 101, the first field plate layer 1041 includes a portion on the gate and a portion on the drift region, and in another example, the first A plate layer 1041 may also be located entirely above the drift zone;

a second dielectric layer 1032 covering the surface of the first dielectric layer 1031 and the first field plate layer 1041;

a second field plate layer 1042 formed on the second dielectric layer 1032, and the second field plate layer 1042 is at least partially located above the drift region and adjacent to the first field plate layer side, exemplary The second field plate layer 1042 is located outside the first field plate layer, and a portion of the second field plate layer 1042 overlaps with a portion of the first field plate layer 1041. In one example, all The second field plate layer is located above the drift region, and in another example, the second field plate layer 1042 and the first field plate layer 1041 do not have overlapping portions.

Wherein, the second dielectric layer 1032 and the second field plate layer 1042 are alternately stacked one layer or more, and the second field plate layer of the upper layer is adjacent to the second field plate layer side of the lower layer adjacent thereto.

Further, the upper and lower adjacent layers of the field plate layer are completely staggered or partially overlapped in the vertical direction.

Further, the second dielectric layer is thicker than the first dielectric layer, and the second dielectric layer of the upper layer is thicker than the second dielectric layer of the lower layer adjacent thereto.

Further, a drift region (not shown) is formed in the semiconductor substrate, the drift region is located outside the gate electrode 101, and a drain is formed in the drift region, the drain and the drain The drift regions have the same conductivity type, and the drift regions have opposite conductivity types to the channel regions. Show Illustratively, the split planar field plate structure is formed over the drift region above the semiconductor substrate between the gate and the drain.

Specifically, the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), and silicon germanium stacked on the insulator. (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate 100 is selected from single crystal silicon.

The semiconductor substrate 100 may also be a P-type semiconductor substrate or an N-type semiconductor substrate. For example, an N-type high voltage device may select a P-type semiconductor substrate, and a P-type high voltage device may select an N-type semiconductor substrate. .

Illustratively, a drift region (not shown) is formed in the semiconductor substrate 100.

The drift region can be formed using a suitable method depending on the type of the device. For example, if an N-type high voltage device is prepared, the semiconductor substrate 100 is doped with N-type ions to form an N-type drift region in the substrate. When a P-type high voltage device is prepared, the semiconductor substrate 100 is subjected to P-type ion doping to form a P-type drift region.

In one example, a body region is formed in the semiconductor substrate 100, and the body region is located outside the drift region and spaced apart from the drift region, and is generally a channel region of the device between the body region and the drift region, wherein The body region and the drift region have opposite conductivity types, that is, when the drift region is N-type, the body region is P-type, or when the drift region is P-type, the body region is N-type, and the drift region and the channel region are also Has the opposite conductivity type.

Other well regions and the like may be formed in the semiconductor substrate 100, and will not be described herein.

Further, as shown in FIG. 1B, a gate electrode 101 covering a channel region is formed on the semiconductor substrate 100.

In one example, the gate includes a gate dielectric layer on a surface of the semiconductor substrate 100 and a gate layer on the gate dielectric layer. The gate dielectric layer can comprise a conventional dielectric material such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). The gate layer is composed of a polysilicon material, and a metal, a metal nitride, a metal silicide or the like can also be generally used as the material of the gate layer.

A spacer (not shown) may also be selectively disposed on the sidewall of the gate 101. The spacer may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an embodiment of the embodiment, the spacer is composed of silicon oxide and silicon nitride.

A source and a drain (not shown) are formed in the semiconductor substrate 100 on both sides of the gate electrode 101, wherein the drain is formed in the drift region, and the drain has the same as the drift region The type of conductivity.

A separate planar field plate structure is formed on the outer side of the gate electrode 101. The separate planar field plate structure comprises a plurality of layers of dielectric layers and field plate layers alternately stacked from bottom to top, wherein one layer and two layers may be included. The dielectric layer and the field plate layer which are alternately laminated in layers or layers are not specifically limited herein.

In one example, a contact hole etch stop layer 102 may also be selectively disposed under the separate planar field plate structure to cover the gate 101 and the surface of the semiconductor substrate 100. The material of the contact hole etch stop layer 102 may be one or more of materials such as SiO ₂ , SiCN, SiN, SiC, SiOF, SiON, and the like. The contact hole etch stop layer 102 can also be used as part of the field oxide layer.

The first dielectric layer 1031 and the second dielectric layer 1032 may be a silicon oxide layer, including doped or undoped formed by a thermal CVD fabrication process or a high density plasma (HDP) fabrication process. A layer of material of silicon oxide, such as undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the first dielectric layer 1031 and the second dielectric layer 1032 may also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane ( PTEOS) or boron-doped tetraethoxysilane (BTEOS).

Further, the thickness of each dielectric layer may be different or the same, and may be appropriately set according to the needs of a specific actual device. Illustratively, the thickness of each of the first dielectric layer 1031 and the second dielectric layer 1032 may be controlled to range from 200 angstroms to 4000 angstroms.

The first dielectric layer 1031 and the second dielectric layer 1032, which are conventionally used as an insulating interlayer dielectric layer, can also be directly used as a field oxide layer of a separate planar field plate structure, and are related to the prior art. Compared, there is no need to perform an additional field plate oxide layer formation step, thereby avoiding the problem of irreversible change of the effective channel width of the active region due to the formation of an additional field plate oxide layer, thereby achieving compatibility between process platforms. advantage.

In one example, the material of the first field plate layer 1041 and the second field plate layer 1042 may be a semiconductor material, which may be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP, AsGa or other III. a binary or ternary compound of the -V group. For example, the material of the first field plate layer 1041 and the second field plate layer 1042 may be polysilicon.

The thickness of the first field plate layer 1041 and the second field plate layer 1042 may range from 800 to 2500 angstroms. This thickness range is only an example, and other suitable thickness ranges are also applicable.

After the dielectric layer deposition and the field plate layer forming step are performed in a plurality of alternate cycles, the separated planar field plate structure is also correspondingly a polysilicon field plate, which may include one, two or more layers of polysilicon.

In one example, the materials of the first field plate layer 1041 and the second field plate layer 1042 may also include a metal silicide, which may be formed using any method commonly used in the art, including It is not limited to a salicide, for example, a metal layer (not shown) is deposited on the surface of the aforementioned polysilicon field plate layer formed by each deposition, and the material of the metal layer may be selected from Co, Ni. One or more of Ti, TiN, W, and WSix. The substrate is then heated to cause silicidation of the metal layer and the underlying polysilicon layer, and the metal silicide layer region is thus formed. An etchant that erodes the metal layer but does not erode the metal silicide layer region is then used to remove the unreacted metal layer to form a metal silicide material field plate layer. After a plurality of alternating cycles of performing dielectric layer deposition and field plate layer formation steps, the formed separate planar field plate structure is correspondingly a metal silicide field plate, which may include one, two or more layers of metal silicidation. Things.

In one example, the materials of the first field plate layer 1041 and the second field plate layer 1042 include a metal material including Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al. In one or more of the embodiments, in the embodiment, the materials of the first field plate layer 1041 and the second field plate layer 1042 may be Al.

Wherein, a metal field plate layer may be deposited on the surface of each deposited dielectric layer, and a patterned photoresist layer may be formed by using a photolithography process to cover part of the metal field plate layer and then expose the exposed metal field plate layer. Etching is performed to form a desired field plate layer pattern in the target area. After a plurality of alternating cycles of performing dielectric layer deposition and field plate layer formation steps, the formed separated planar field plate structure is correspondingly a metal field plate, which may include one, two or more layers of metal field plate layers. . The use of a metal material as the field plate layer reduces the gate charge (Qgd) and improves the performance of the device compared to the prior art polysilicon field plate structure.

Illustratively, as shown in FIG. 1B and FIG. 2, wherein a separate planar field plate structure is formed over the drift region, above the surface of the semiconductor substrate between the gate and the drain, That is, above the horizontal plane between the gate and the drain, this does not block the current path between the gate and the drain, thus shortening the drift region current path and improving the performance of the device. In the prior art, the buried field plate structure is generally that the oxide layer of the field plate is partially located in the drift region, thereby blocking the current path between the gate and the drain, so that the current flow needs to bypass the field plate region, so The drift zone current path is increased, which affects the performance of the device.

Further, in the separate planar field plate structure, the field plate layer located in the lower layer is closer to the gate electrode than the field plate layer located in the upper layer.

Further, the thickness of the dielectric layer under the field plate layer of the lower layer in the separate planar field plate structure is smaller than the thickness of the dielectric layer under the field plate layer of the upper layer, and can be controlled by each deposition The thickness of the dielectric layer is free to adjust the total thickness of the dielectric layer under each layer of the field plate layer, that is, to achieve free adjustment of the thickness of the field oxide layer.

In one example, a third dielectric layer 1033 is disposed over the separate planar field plate structure and the semiconductor substrate, covering a surface of the second dielectric layer 1032 and a second field plate layer 1042, wherein the third dielectric layer 1033 and the second dielectric layer 1032 and the first dielectric layer 1031 are the same material, and the third dielectric layer 1033 has a flat surface.

Finally, a plurality of contact holes are formed in the third dielectric layer 1033. The contact holes are electrically connected to the source, the drain, the gate, the body lead-out area, and each of the field plate layers of the separate planar field plate structure, wherein the gate and the separated planar field plate structure are electrically connected The contact holes are further electrically connected to the same metal layer on the dielectric layer to effect electrical connection of the gate and the separate planar field plate structure. The source, drain, gate, body lead-out regions, and each of the field plate layers of the separate planar field plate structure may also be extracted by a metal interconnect structure composed of a plurality of metal layers and contact holes. The material of the contact hole and the metal layer in the interconnect structure may be a metal material such as aluminum or copper.

The above semiconductor device may be any device including a field plate, and may be a high voltage device, wherein the high voltage device may be a high voltage device commonly used in the field of semiconductor technology, such as DMOS (Double Diffused MOSFET, double diffused metal oxide semiconductor field effect transistor). There are two main types of DMOS: vertical double-diffused MOSFET (VDMOS) and lateral double-diffused MOSFET (LDMOS).

In summary, the above semiconductor device includes a separate planar field plate structure of one, two or more field plate layers, shortening the drift region current path, improving the performance of the device, and using the foregoing embodiments for the semiconductor device. The method is prepared and therefore has the same advantages.

The present invention has been described by the above-described embodiments, but it should be understood that the above-described embodiments are only for the purpose of illustration and description. Further, those skilled in the art can understand that the present invention is not limited to the above embodiments, and various modifications and changes can be made according to the teachings of the present invention. These modifications and modifications are all claimed in the present invention. Within the scope. The scope of the invention is defined by the appended claims and their equivalents.

Claims (22)

A method of fabricating a semiconductor device, comprising: Step 1: providing a semiconductor substrate, forming a source, a drain, and a gate on the semiconductor substrate, and forming a drift region in the semiconductor substrate between the gate and the drain, Step two, forming a first dielectric layer to cover a surface of the semiconductor substrate and a source, a drain, and a gate; Step 3, forming a first field plate layer on the first dielectric layer, the first field plate layer being at least partially located above the drift region and the portion being disposed adjacent to the gate. The method of claim 1 wherein said first field plate layers are all located above said drift region. The method of claim 1 wherein said first field plate layer portion is above said gate. The method of claim 1 further comprising the step of: after said step three: Step four, forming a second dielectric layer to cover the surface of the first dielectric layer and the first field plate layer; Step 5, forming a second field plate layer on the second dielectric layer, the second field plate layer being located above the drift region and adjacent to an outer side of the first field plate layer. The method of claim 4, further comprising performing said step four and said step five in an alternating cycle, and wherein said second dielectric layer formed in said step four is overlaid in a previous step four The second medium layer and the second field layer are formed, and the second field layer formed in the step 5 is adjacent to the outer side of the second field layer formed in the previous step 5. The method of claim 5 wherein the upper and lower adjacent layers of the field plate layer are completely staggered or partially overlapped in the vertical direction. The method according to claim 5, wherein said second dielectric layer is thicker than said first dielectric layer, and said second dielectric layer formed in a subsequent step is formed by said adjacent previous step Two dielectric layers are thick. The method of claim 1 further comprising the step of: after said step three: Step 4, thinning the first dielectric layer covered with a region other than the field plate layer, and Step 5, forming a second field plate layer on the thinned first dielectric layer, the second field plate layer being located above the drift region and separated from the previous layer field plate layer. The method of claim 8 wherein said step four and said step are performed more than once in an alternating cycle. The method of claim 1 further comprising the step of: after said step three: Step four, etching the dielectric layer covered with the field plate layer until the semiconductor substrate is exposed; Step 5, forming a second dielectric layer to cover the surface of the semiconductor substrate and the exposed surface of the field plate layer, forming a second field plate layer on the second dielectric layer, and the second field layer is located Above the drift zone and adjacent to the outside of the first field plate layer. The method of claim 10, further comprising: performing said step four and said step five or more times in an alternating cycle, and wherein said second field layer formed in said step five is in close proximity The outer side of the second field layer formed in the previous step five. The method according to claim 1, wherein the material of the first field plate layer is at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al or a polysilicon semiconductor. Or metal silicide. The method of claim 1, wherein after the step three, the method further comprises: Depositing a third dielectric layer to cover a surface of the first dielectric layer and the first field plate layer, The third dielectric layer is planarized, wherein the third dielectric layer and the first dielectric layer are the same material. A semiconductor device comprising: a semiconductor substrate having a source, a drain and a gate formed on the semiconductor substrate, and a drift region formed in the semiconductor substrate between the gate and the drain; a first dielectric layer covering a surface of the semiconductor substrate and the source, the drain, and the gate; A first field plate layer is formed on the first dielectric layer, the first field plate layer being at least partially above the drift region and the portion being adjacent to the gate. The semiconductor device of claim 14 wherein said first field plate layers are all located above said drift region. The semiconductor device of claim 14 wherein said first field plate layer portion is above said gate. The semiconductor device of claim 14 further comprising: a second dielectric layer covering a surface of the first dielectric layer and the first field plate layer; A second field plate layer is formed on the second dielectric layer, and the second field plate layer is at least partially located above the drift region and adjacent to an outer side of the first field plate layer. A semiconductor device according to claim 14, wherein said semiconductor device comprises a plurality of second dielectric layers and a second field plate layer, each of said second dielectric layers covering a lower second dielectric layer surface and a second The field plate layer, each layer of the second field plate layer is formed on the lower dielectric layer and adjacent to the outer side of the lower field plate layer. A semiconductor device having a split planar field plate structure according to claim 18, wherein the upper and lower adjacent field plate layers are completely shifted or partially overlapped in the vertical direction. A semiconductor device having a split planar field plate structure according to claim 18, wherein said second dielectric layer has a thickness thicker than said first dielectric layer, and said second dielectric layer has a thickness of said upper dielectric layer It is thicker than the second dielectric layer of the lower layer adjacent thereto. A semiconductor device having a split planar field plate structure according to claim 18, wherein said first field plate layer is made of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and At least one of Al or a polysilicon semiconductor or a metal silicide. A semiconductor device having a separate planar field plate structure according to claim 18, further comprising: And a third dielectric layer covering the surface of the first dielectric layer and the first field plate layer, wherein the material of the third dielectric layer is the same as the material of the first dielectric layer.

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