WO2017217129A1 - Bonded wafer manufacturing method - Google Patents
Bonded wafer manufacturing method Download PDFInfo
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- WO2017217129A1 WO2017217129A1 PCT/JP2017/017184 JP2017017184W WO2017217129A1 WO 2017217129 A1 WO2017217129 A1 WO 2017217129A1 JP 2017017184 W JP2017017184 W JP 2017017184W WO 2017217129 A1 WO2017217129 A1 WO 2017217129A1
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- wafer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000010438 heat treatment Methods 0.000 claims abstract description 121
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 239000007789 gas Substances 0.000 claims abstract description 11
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims abstract description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims abstract description 5
- -1 hydrogen ions Chemical class 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 12
- 238000004299 exfoliation Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 1
- 230000003746 surface roughness Effects 0.000 abstract description 37
- 238000000926 separation method Methods 0.000 abstract description 13
- 238000009413 insulation Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 158
- 206010040844 Skin exfoliation Diseases 0.000 description 43
- 239000010408 film Substances 0.000 description 18
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000005498 polishing Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Definitions
- the present invention relates to a method for manufacturing a bonded wafer.
- an oxide film is formed on at least one of two silicon wafers, and hydrogen ions or rare ions are formed from the upper surface of one silicon wafer (bond wafer).
- Gas ions such as gas ions are implanted to form a microbubble layer (encapsulation layer) inside the bond wafer.
- the ion-implanted surface is brought into close contact with the other silicon wafer (base wafer) through an oxide film, and then a heat treatment (peeling heat treatment) is applied to form one wafer (bond wafer) with the microbubble layer as a cleavage plane.
- the thin film is peeled off, and further heat treatment (bonding heat treatment) is applied to firmly bond to form an SOI wafer (see Patent Document 1).
- bonding heat treatment bonding heat treatment
- an SOI wafer having an SOI layer with a highly uniform cleaved surface (peeling surface) and high film thickness uniformity can be obtained relatively easily.
- polishing (removal allowance: about 100 nm) called “polishing polish” has been performed in the final step after the bonding heat treatment.
- the thin film (SOI layer) of the bonded wafer is polished including a machining element, the amount of polishing is not uniform in the plane. Therefore, the thin film is achieved by implantation and peeling of hydrogen ions and the like. There arises a problem that the thickness uniformity deteriorates.
- Patent Document 2 pays attention to the short period roughness and long period roughness of the surface roughness, and in the flattening heat treatment, rapid heating / rapid cooling apparatus (RTA apparatus) and heater heating type heat treatment furnace (batch type furnace) are used.
- RTA apparatus rapid heating / rapid cooling apparatus
- heater heating type heat treatment furnace batch type furnace
- Patent Document 3 in order to avoid OSF (oxidation-induced stacking fault) that is likely to occur when the peeled surface is directly oxidized, planarization heat treatment in an inert gas, hydrogen gas, or mixed gas atmosphere thereof is performed. By performing sacrificial oxidation treatment later, planarization of the peeled surface and avoidance of OSF are achieved at the same time. Further, it has been proposed to further reduce the long-period component of the surface roughness by carrying out polishing with a machining allowance of 70 nm or less before sacrificial oxidation.
- Patent Document 4 when bonding heat treatment for increasing the bonding strength of a bonded wafer after peeling is performed in an oxidizing atmosphere, 950 ° C. is used as the bonding heat treatment in order to surely avoid OSF that tends to occur on the peeling surface. It is disclosed that the heat treatment is performed at a temperature of 1000 ° C. or higher in an inert gas atmosphere containing 5% or less of oxygen after performing the oxidation heat treatment at a temperature below.
- Patent Document 2 When only high-temperature heat treatment is performed without polishing as the release surface flattening treatment, the higher the heat treatment temperature, the higher the flatness. According to Patent Document 2, it is said that it is more effective to set a temperature range of 1200 to 1350 ° C. as the heat treatment temperature by the RTA apparatus for improving the short period component, and the long period component is improved. Similarly, it is said that it is more effective to set the heat treatment temperature in the batch furnace to 1200 to 1350 ° C. And in an Example, the heat processing of 1200 degreeC or more is performed in all the heat processing. Similarly, Patent Document 3 discloses only a heat treatment temperature of 1200 ° C. as Ar annealing for planarization heat treatment.
- a heat treatment temperature of 1200 ° C. or higher is necessary in order to obtain a surface roughness that can be sufficiently applied to a device process by planarization treatment only by heat treatment. Even in mass production, a temperature of 1200 ° C. or higher was adopted.
- the surface roughness of the release surface after the release heat treatment can be reduced, it can be processed in a subsequent process so as not to apply a load to the planarization heat treatment for reducing the surface roughness.
- a bonded wafer having a small surface roughness of the peeled surface can be processed at a low temperature, the occurrence of slip dislocation is reduced, and the increase in particles is also reduced.
- processing at a higher temperature is required to reduce the surface roughness. Therefore, it is necessary to take measures against slip, particles and the like.
- the surface roughness of the peeled surface after the peeling heat treatment is large, there are many defects due to peeling of the bonded wafer, and sacrificial oxidation with a thicker oxide film is required to eliminate the defects.
- the present invention has been made in view of the above circumstances. For example, by reducing the surface roughness of a peeled surface after peeling of a bonded wafer such as an SOI wafer, a final planarization heat treatment is performed at a lower temperature. It aims at providing the manufacturing method of the bonded wafer which can reduce the surface roughness of the surface of a bonded wafer.
- At least one kind of gas ion of hydrogen ion or rare gas ion is ion-implanted from the surface of a bond wafer made of a silicon single crystal wafer, and an ion implantation layer is formed inside the bond wafer.
- the bond wafer is peeled off and pasted by the ion-implanted layer by performing a peeling heat treatment.
- the bonded interface between the bonded wafer and the base wafer is bonded until the peeling heat treatment is performed.
- the bonded body is bonded with the contribution of water molecules. Hold the wafer and the base wafer at room temperature for 12 hours or more, and the peeling heat treatment raises the bonded wafer and base wafer bonded together in a heat treatment furnace set at a constant temperature of 400 ° C. or more and 500 ° C. or less.
- a method for producing a bonded wafer that is directly charged without a temperature step and heat-treated at the constant temperature, or heated to a predetermined temperature within + 50 ° C. from the constant temperature and then heat-treated at the predetermined temperature.
- the surface roughness of the peeled surface after peeling of the bonded wafer such as an SOI wafer can be reduced, so that the final surface can be obtained by planarizing heat treatment at a lower temperature. It is possible to reduce the surface roughness of the surface of the bonded wafer (surface of the SOI layer).
- the bonding strength between the bond wafer and the base wafer when being put into the heat treatment furnace can be increased, thereby suppressing the generation of voids. .
- the temperature at the time of taking out the bonded wafer from the heat treatment furnace after the heat treatment at the constant temperature or the predetermined temperature is the same as the temperature at the time of the peeling heat treatment.
- the temperature lowering step can be omitted, which is efficient and the manufacturing cost can be reduced.
- the holding time at the room temperature is 48 hours or more.
- the bonding strength between the bond wafer and the base wafer can be further increased.
- a heat treatment for flattening the peeled surface of the bonded wafer from which the bond wafer has been peeled is performed, and the temperature of the flattening heat treatment is performed within a temperature range of 1100 ° C. to 1175 ° C. Is preferred.
- the flattening heat treatment is performed in such a temperature range, the probability of occurrence of slip dislocation is reduced, so that the product yield is improved, and as a result, the manufacturing cost can be reduced.
- the present invention by bonding the bond wafer and the base wafer before bonding the bond wafer and the base wafer, sufficient water molecules can be left on the surface of the bond wafer and the base wafer.
- the bond wafer and the base wafer are bonded together, the bonded interface of the bonded wafers can be brought into a bonded state due to the contribution of water molecules.
- the manufacturing method of the bonded wafer of this invention since the surface roughness of the peeling surface after peeling of bonded wafers, such as an SOI wafer, can be reduced, it is final by planarization heat processing at lower temperature. It is possible to reduce the surface roughness of the surface of the bonded wafer (surface of the SOI layer). In addition, by holding the bonded wafer at room temperature for 12 hours or more, the bonding strength between the bond wafer and the base wafer when being put into the heat treatment furnace can be increased, thereby suppressing the generation of voids. .
- the present invention will be described more specifically.
- a bonded wafer such as an SOI wafer or a direct bond wafer that does not pass through an insulating film
- the final surface is processed by a planarization heat treatment at a lower temperature.
- a method for manufacturing a bonded wafer that can reduce the surface roughness of the surface of the bonded wafer (the surface of the SOI layer).
- a wafer bonded to a heat treatment furnace maintained at a low temperature of about 350 ° C. is loaded as described in, for example, Japanese Patent Application Laid-Open No. 2003-347526. And holding for a predetermined time, and then raising the temperature to 500 ° C. or higher and holding it for a predetermined time.
- the diffusion of ion-implanted hydrogen slightly progresses until the temperature reaches 500 ° C. at which peeling occurs, and the hydrogen concentration distribution in the implanted layer widens.
- peeling occurs in this state, the width of the peeling region (width in the depth direction) becomes wide, and as a result, the surface roughness of the peeling surface increases.
- the present inventors either directly input the temperature at which separation is possible without a heating step, or after raising the temperature from a certain temperature to a predetermined temperature within + 50 ° C. It has been found that the surface roughness of the peeled surface after peeling can be reduced by heat treatment at a predetermined temperature. However, when it is charged into the heat treatment furnace at a higher temperature than in the prior art, if the bonding force at the time of charging is weak, complete peeling cannot be obtained and voids are generated. As a countermeasure, the present inventors have bonded the bonded wafer and the base wafer at room temperature until the bonded interface is bonded by the contribution of water molecules until the separation heat treatment is performed. The inventors have found that the above problems can be solved by increasing the bonding strength between the bond wafer and the base wafer when being put into a heat treatment furnace by holding for a long time, and the present invention has been completed.
- FIG. 1 is a schematic view showing an example of a method for producing a bonded wafer according to the present invention.
- the bond wafer 1 and the base wafer 2 (FIGS. 1A and 1C).
- an insulating film (for example, an oxide film) 3 to be a buried oxide film layer is formed only on the bonding surface of the bond wafer 1, but the insulating film 3 is formed only on the base wafer 2. It may be formed on both wafers. Further, both wafers may be bonded directly without forming an insulating film.
- the insulating film formed at this time for example, a thermal oxide film, a CVD oxide film, or the like can be formed.
- the insulating film may be formed only on the bonding surface, or may be formed on the entire wafer including the back surface.
- At least one kind of gas ion of hydrogen ion and rare gas ion is ion-implanted from the surface of the insulating film 3 of the bond wafer 1 to form an ion-implanted layer 4 inside the bond wafer 1 (FIG. 1B).
- ion implantation conditions such as implantation energy, implantation dose, and implantation temperature can be appropriately selected so that a thin film having a predetermined thickness can be obtained.
- the bond wafer 1 and the base wafer 2 it is preferable to clean the bond wafer 1 and the base wafer 2 before bonding the bond wafer 1 and the base wafer 2 together.
- the present invention by bonding the bond wafer and the base wafer before bonding the bond wafer and the base wafer, sufficient water molecules can be left on the surface of the bond wafer and the base wafer.
- the bonded interface of the bonded wafers can be brought into a bonded state due to the contribution of water molecules.
- the cleaning liquid used for this cleaning is not particularly limited, and examples thereof include a mixed solution of ammonia water and hydrogen peroxide water.
- the bonded wafer is bonded at the room temperature in the state where the bonded interface of the bonded wafers is bonded by the contribution of water molecules until the peeling heat treatment described later is performed. Hold for at least 12 hours (FIG. 1 (e)).
- the heat treatment of peeling is not performed, and the bonded wafer is left for a while to align the direction of water molecules at the bonding interface, thereby increasing the strength of the bonding interface. Can do.
- the holding time at room temperature is less than 12 hours, the bonding strength between the bond wafer and the base wafer cannot be sufficiently increased.
- the time for holding at room temperature may be 12 hours or more, and preferably 48 hours or more. By holding at room temperature for 48 hours or more, the bonding strength between the bond wafer and the base wafer can be further increased.
- the bonding strength is increased up to about 100 hours, but when the time exceeds 100 hours, no further increase in the bonding strength is observed, so the upper limit is set from the viewpoint of productivity. 100 hours is preferable.
- the holding time at room temperature can be adjusted within a range in which the yield can be secured according to the product specifications.
- the bonded wafer is subjected to a heat treatment (peeling heat treatment) for generating a microbubble layer in the ion implantation layer 4, and the bond wafer 1 is peeled off by the ion implantation layer 4 (microbubble layer).
- a bonded wafer 6 having a thin film (SOI layer) 5 formed thereon via an insulating film 3 is obtained (FIG. 1 (f)).
- the temperature at the time of taking out the bonded wafer from the heat treatment furnace after the heat treatment at a constant temperature or a predetermined temperature is the same as the temperature at the peeling heat treatment. If the temperature at the time of taking out the bonded wafer from the heat treatment furnace is the same as the temperature at the time of the peeling heat treatment, the temperature lowering step can be omitted, which is efficient and the manufacturing cost can be reduced.
- Bonded heat treatment for increasing the bond strength at the bonding interface, and planarization heat treatment for flattening the peeled surface of the bonded wafer from which the bond wafer has been peeled off, if necessary, for the bonded wafer produced as described above. Then, heat treatment such as sacrificial oxidation treatment for adjusting the thickness of the thin film can be performed.
- the planarization heat treatment it is preferable to perform the planarization heat treatment within a temperature range of 1100 ° C. to 1175 ° C. If the planarization heat treatment is performed in such a temperature range, the probability of occurrence of slip dislocation is reduced, so that the product yield is improved, and as a result, the manufacturing cost can be reduced.
- the surface roughness of the peeling surface after peeling of bonded wafers can be reduced, it is at lower temperature.
- the surface roughness of the final bonded wafer surface (the surface of the SOI layer) can be reduced by the planarization heat treatment.
- Example 1 First, a plurality of wafers shown in Table 1 are used as bond wafers and base wafers made of silicon single crystal, and an SOI wafer is manufactured by performing cleaning, bonding, room temperature holding, and peeling heat treatment under the conditions shown in Table 1. did.
- the room temperature holding time was 12 hours.
- the peeling heat treatment was performed at a constant temperature of 450 ° C. and the heat treatment time was 3 hours.
- the obtained SOI wafer is further subjected to sacrificial oxidation treatment that also serves as bonding heat treatment, planarization heat treatment, and sacrificial oxidation treatment for adjusting the film thickness of the SOI layer, and bonded SOI with a SOI layer thickness of 90 nm.
- a wafer was produced.
- the planarization heat treatment was performed separately for 2 hours on the obtained SOI wafer under the temperature conditions of 1100 ° C., 1150 ° C., and 1175 ° C.
- the surface roughness (1 ⁇ m square RMS) of the SOI layer (final SOI layer) of the obtained bonded SOI wafer was measured with an AFM (atomic force microscope) and shown in Table 2. Note that, when the surface roughness of the peeled surface immediately after peeling is measured, there is a large variation due to the measurement point and it is difficult to compare, so here, the surface surface of the final SOI layer (that is, after performing the planarization heat treatment) Roughness was measured and compared.
- Example 2 A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 48 hours. Further, the peeling heat treatment was performed by raising the temperature from a constant temperature of 450 ° C. to a predetermined temperature of 500 ° C. (+ 50 ° C.) (temperature raising rate: 10 ° C./min) and a heat treatment time of 0.5 hours. Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
- Example 3 A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 96 hours. Further, the peeling heat treatment was performed by raising the temperature from a constant temperature of 400 ° C. to a predetermined temperature (+ 50 ° C.) of 450 ° C. (heating rate of 10 ° C./min) and a heat treatment time of 3 hours. Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
- Example 1 A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 1 hour. The peeling heat treatment was performed at a constant temperature of 450 ° C. and the heat treatment time was 3 hours. Further, as shown in Table 2, the planarization heat treatment was obtained under the temperature conditions of 1100 ° C., 1150 ° C., 1175 ° C., and 1200 ° C. with the heat treatment time being 2 hours, 2 hours, 2 hours, and 1 hour, respectively. Separately for SOI wafers. Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
- Example 2 A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 96 hours, and the peeling heat treatment was performed by raising the temperature from a constant temperature of 350 ° C. to a predetermined temperature of 500 ° C. (+ 150 ° C.) (heating rate 10 ° C./min), and the heat treatment time was 0.5 hours. Went as. Further, as shown in Table 2, the planarization heat treatment was obtained under the temperature conditions of 1100 ° C., 1150 ° C., 1175 ° C., and 1200 ° C. with the heat treatment time being 2 hours, 2 hours, 2 hours, and 1 hour, respectively. Separately for SOI wafers. Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
- Comparative Example 1 in which the room temperature retention time was less than 12 hours (1 hour) and Comparative Example 2 in which the temperature was raised from a certain temperature to a predetermined temperature exceeding + 50 ° C. (+ 150 ° C.), a relatively high temperature of 1100 to 1175 ° C. In the low-temperature planarization heat treatment, the surface roughness of the final SOI layer surface was worse than that in Examples 1 to 3. Further, Comparative Example 1 in which the room temperature holding time was 1 hour had a higher void generation rate than Example 1 in which the room temperature holding time was 12 hours.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
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Abstract
The present invention is a bonded wafer manufacturing method comprising: injecting at least one type of gas ions selected from hydrogen ions and rare gas ions into a surface of a wafer for bonding that is formed of a silicon single crystal wafer, so as to form an ion implantation layer inside the wafer for bonding; bonding a surface of a base wafer to the surface of the wafer for bonding, into which the ions have been injected, such that the surfaces are bonded directly or with an insulation film interposed therebetween; and then, performing separation heat treatment so as to separate, at the ion implantation layer, the wafer for bonding, thereby manufacturing a bonded wafer. In the bonded wafer manufacturing method: after the wafer for bonding and the base wafer are bonded to each other, until the separation heat treatment is performed, the wafer for bonding and the base wafer that are bonded to each other, are kept at a room temperature for 12 hours or longer in a state where the wafer for bonding and the base wafer that are bonded to each other, are joined to each other at the bonding interface therebetween due to water molecules; and, in the separation heat treatment, the wafer for bonding and the base wafer that are bonded to each other, are fed directly without a temperature increase step into a heat treating furnace of which the in-furnace temperature is set at a fixed temperature of 400-500ºC, and are subjected to heat treatment at the fixed temperature, or, after increase of the temperature from the fixed temperature to a predetermined temperature higher than the fixed temperature by not more than 50ºC, are subjected to heat treatment at the predetermined temperature. Accordingly, a bonded wafer manufacturing method is provided which allows reduction in the surface roughness of a separation surface, of a bonded wafer such as an SOI wafer, obtained after separation, whereby the surface roughness of the surface of the final bonded wafer can be reduced by flattening heat treatment performed at a lower temperature.
Description
本発明は、貼り合わせウェーハの製造方法に関する。
The present invention relates to a method for manufacturing a bonded wafer.
近年、貼り合わせウェーハの製造方法として、イオン注入したウェーハを他のウェーハと接合して剥離することで貼り合わせウェーハを製造する方法(イオン注入剥離法:スマートカット法(登録商標)とも呼ばれる技術)が新たに注目され始めている。
In recent years, as a method of manufacturing a bonded wafer, a method of manufacturing a bonded wafer by bonding an ion-implanted wafer to another wafer and peeling the wafer (ion-implantation peeling method: a technique called Smart Cut Method (registered trademark)) Has begun to attract new attention.
このようなイオン注入剥離法によりSOIウェーハを製造する方法としては、2枚のシリコンウェーハのうち、少なくとも一方に酸化膜を形成するとともに、一方のシリコンウェーハ(ボンドウェーハ)の上面から水素イオンや希ガスイオン等のガスイオンを注入し、該ボンドウェーハ内部に微小気泡層(封入層)を形成させる。そして、イオン注入した側の面を酸化膜を介して他方のシリコンウェーハ(ベースウェーハ)と密着させ、その後熱処理(剥離熱処理)を加えて微小気泡層を劈開面として一方のウェーハ(ボンドウェーハ)を薄膜状に剥離し、さらに熱処理(結合熱処理)を加えて強固に結合してSOIウェーハとする(特許文献1参照)。この方法では、劈開面(剥離面)が良好な鏡面で、膜厚の均一性が高いSOI層を有するSOIウェーハが比較的容易に得られる。
As a method of manufacturing an SOI wafer by such an ion implantation separation method, an oxide film is formed on at least one of two silicon wafers, and hydrogen ions or rare ions are formed from the upper surface of one silicon wafer (bond wafer). Gas ions such as gas ions are implanted to form a microbubble layer (encapsulation layer) inside the bond wafer. Then, the ion-implanted surface is brought into close contact with the other silicon wafer (base wafer) through an oxide film, and then a heat treatment (peeling heat treatment) is applied to form one wafer (bond wafer) with the microbubble layer as a cleavage plane. The thin film is peeled off, and further heat treatment (bonding heat treatment) is applied to firmly bond to form an SOI wafer (see Patent Document 1). In this method, an SOI wafer having an SOI layer with a highly uniform cleaved surface (peeling surface) and high film thickness uniformity can be obtained relatively easily.
しかし、イオン注入剥離法により貼り合わせウェーハを作製する場合においては、剥離後の貼り合わせウェーハ表面にイオン注入によるダメージ層が存在し、また通常の製品レベルのシリコンウェーハの鏡面に比べて表面粗さが大きなものとなる。従って、イオン注入剥離法による製造では、このようなダメージ層及び表面粗さを除去することが必要になる。
However, when a bonded wafer is manufactured by the ion implantation separation method, a damage layer due to ion implantation exists on the surface of the bonded wafer after separation, and the surface roughness is higher than the mirror surface of a normal product level silicon wafer. Will be big. Therefore, it is necessary to remove such a damaged layer and surface roughness in the production by the ion implantation separation method.
従来、このダメージ層等を除去するために、結合熱処理後の最終工程において、タッチポリッシュと呼ばれる研磨代の極めて少ない鏡面研磨(取り代:100nm程度)が行われていた。
Conventionally, in order to remove the damaged layer and the like, mirror polishing (removal allowance: about 100 nm) called “polishing polish” has been performed in the final step after the bonding heat treatment.
ところが、貼り合わせウェーハの薄膜(SOI層)に機械加工的要素を含む研磨を施すと、研磨の取り代が面内で均一でないために、水素イオン等の注入、剥離によって達成された薄膜の膜厚均一性が悪化してしまうという問題が生じる。
However, if the thin film (SOI layer) of the bonded wafer is polished including a machining element, the amount of polishing is not uniform in the plane. Therefore, the thin film is achieved by implantation and peeling of hydrogen ions and the like. There arises a problem that the thickness uniformity deteriorates.
このような問題点を解決する方法として、前記タッチポリッシュの代わりに高温熱処理を行って表面粗さを改善する平坦化熱処理が行われるようになってきている。
As a method for solving such a problem, a flattening heat treatment for improving the surface roughness by performing a high-temperature heat treatment instead of the touch polish has been performed.
特に、特許文献2では、表面粗さの短周期粗さと長周期粗さに注目し、平坦化熱処理において、急速加熱・急速冷却装置(RTA装置)とヒータ加熱式熱処理炉(バッチ式炉)による2段階の熱処理を行うことによって、表面粗さの短周期粗さと長周期粗さの両者を低減する方法が提案されている。
In particular, Patent Document 2 pays attention to the short period roughness and long period roughness of the surface roughness, and in the flattening heat treatment, rapid heating / rapid cooling apparatus (RTA apparatus) and heater heating type heat treatment furnace (batch type furnace) are used. There has been proposed a method of reducing both the short period roughness and the long period roughness of the surface roughness by performing a two-step heat treatment.
また、特許文献3では、剥離面を直接酸化する際に発生しやすいOSF(酸化誘起積層欠陥)を回避するため、不活性ガス、水素ガス、あるいはこれらの混合ガス雰囲気下での平坦化熱処理の後に犠牲酸化処理を行うことにより、剥離面の平坦化とOSFの回避を同時に達成している。また、犠牲酸化の前に70nm以下の取り代の研磨を実施することで、表面粗さの長周期成分を一層低減することを提案している。
Further, in Patent Document 3, in order to avoid OSF (oxidation-induced stacking fault) that is likely to occur when the peeled surface is directly oxidized, planarization heat treatment in an inert gas, hydrogen gas, or mixed gas atmosphere thereof is performed. By performing sacrificial oxidation treatment later, planarization of the peeled surface and avoidance of OSF are achieved at the same time. Further, it has been proposed to further reduce the long-period component of the surface roughness by carrying out polishing with a machining allowance of 70 nm or less before sacrificial oxidation.
また、特許文献4では、剥離後の貼り合わせウェーハの結合強度を高めるための結合熱処理を酸化性雰囲気で行う際、剥離面に発生しやすいOSFを確実に回避するため、結合熱処理として、950℃未満の温度で酸化熱処理を行った後に、5%以下の酸素を含む不活性ガス雰囲気で、1000℃以上の温度で熱処理を行うことが開示されている。
Further, in Patent Document 4, when bonding heat treatment for increasing the bonding strength of a bonded wafer after peeling is performed in an oxidizing atmosphere, 950 ° C. is used as the bonding heat treatment in order to surely avoid OSF that tends to occur on the peeling surface. It is disclosed that the heat treatment is performed at a temperature of 1000 ° C. or higher in an inert gas atmosphere containing 5% or less of oxygen after performing the oxidation heat treatment at a temperature below.
剥離面の平坦化処理として研磨を行うことなく高温の熱処理のみを行う場合、熱処理温度が高い方が平坦度を高めることができる。特許文献2によれば、短周期成分を改善するためのRTA装置による熱処理温度としては、1200~1350℃の温度範囲とするのがより効果的であるとしており、また、長周期成分を改善するためのバッチ式炉による熱処理温度としても同様に、1200~1350℃の温度範囲とするのがより効果的であるとしている。そして、実施例においては、いずれの熱処理も1200℃以上の熱処理が行われている。また、特許文献3でも同様に、平坦化熱処理のArアニールとして、1200℃の熱処理温度のみが開示されている。
When only high-temperature heat treatment is performed without polishing as the release surface flattening treatment, the higher the heat treatment temperature, the higher the flatness. According to Patent Document 2, it is said that it is more effective to set a temperature range of 1200 to 1350 ° C. as the heat treatment temperature by the RTA apparatus for improving the short period component, and the long period component is improved. Similarly, it is said that it is more effective to set the heat treatment temperature in the batch furnace to 1200 to 1350 ° C. And in an Example, the heat processing of 1200 degreeC or more is performed in all the heat processing. Similarly, Patent Document 3 discloses only a heat treatment temperature of 1200 ° C. as Ar annealing for planarization heat treatment.
これらの記載からも明らかなように、熱処理のみの平坦化処理でデバイスプロセスに十分に適用できる表面粗さを得るためには、1200℃以上の熱処理温度が必要であるとされており、実際の量産でも1200℃以上の温度が採用されていた。
As is clear from these descriptions, it is said that a heat treatment temperature of 1200 ° C. or higher is necessary in order to obtain a surface roughness that can be sufficiently applied to a device process by planarization treatment only by heat treatment. Even in mass production, a temperature of 1200 ° C. or higher was adopted.
しかしながら、1200℃以上の温度で熱処理を行うとスリップ転位が発生する確率が高まるため、製品歩留まりの低下をもたらし、結果として製造コストの増加を招いていた。
However, if the heat treatment is performed at a temperature of 1200 ° C. or higher, the probability of occurrence of slip dislocation increases, resulting in a decrease in product yield, resulting in an increase in manufacturing cost.
そこで、剥離熱処理後の剥離面の表面粗さを小さくできれば、その後の工程で、表面粗さを低減させるための平坦化熱処理に負荷をかけないように処理できる。
Therefore, if the surface roughness of the release surface after the release heat treatment can be reduced, it can be processed in a subsequent process so as not to apply a load to the planarization heat treatment for reducing the surface roughness.
例えばArアニールによるマイグレーションを利用する場合、剥離面の表面粗さの小さな貼り合わせウェーハは低温で処理することが可能となり、スリップ転位の発生は少なくなり、パーティクルの増加も少なくなる。しかし、剥離面の表面粗さの大きな貼り合わせウェーハでは、表面粗さを小さくするため、より高温での処理が必要となる。従って、スリップ、パーティクル等の対策が必要となる。また、剥離熱処理後の剥離面の表面粗さが大きい場合、その貼り合わせウェーハの剥離起因の欠陥が多く存在し、その欠陥を消滅させるためより厚い酸化膜厚の犠牲酸化が必要となる。
For example, when using migration by Ar annealing, a bonded wafer having a small surface roughness of the peeled surface can be processed at a low temperature, the occurrence of slip dislocation is reduced, and the increase in particles is also reduced. However, in a bonded wafer having a peeled surface with a large surface roughness, processing at a higher temperature is required to reduce the surface roughness. Therefore, it is necessary to take measures against slip, particles and the like. In addition, when the surface roughness of the peeled surface after the peeling heat treatment is large, there are many defects due to peeling of the bonded wafer, and sacrificial oxidation with a thicker oxide film is required to eliminate the defects.
本発明は、上記事情に鑑みなされたもので、例えばSOIウェーハのような貼り合わせウェーハの剥離後の剥離面の表面粗さを低減させることで、より低い温度での平坦化熱処理により最終的な貼り合わせウェーハの表面の表面粗さを低下させることができる貼り合わせウェーハの製造方法を提供することを目的とする。
The present invention has been made in view of the above circumstances. For example, by reducing the surface roughness of a peeled surface after peeling of a bonded wafer such as an SOI wafer, a final planarization heat treatment is performed at a lower temperature. It aims at providing the manufacturing method of the bonded wafer which can reduce the surface roughness of the surface of a bonded wafer.
上記課題を解決するために、本発明では、シリコン単結晶ウェーハからなるボンドウェーハの表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入して前記ボンドウェーハの内部にイオン注入層を形成し、前記ボンドウェーハのイオン注入した表面とベースウェーハの表面とを直接又は絶縁膜を介して貼り合わせた後、剥離熱処理を行うことによって前記イオン注入層で前記ボンドウェーハを剥離させて貼り合わせウェーハを製造する貼り合わせウェーハの製造方法において、前記ボンドウェーハと前記ベースウェーハとを貼り合わせた後、前記剥離熱処理を行うまで、貼り合わせた前記ボンドウェーハと前記ベースウェーハとの貼り合わせ界面が水分子の寄与によって結合している状態で前記貼り合わせたボンドウェーハとベースウェーハを室温で12時間以上保持し、前記剥離熱処理は、炉内温度が400℃以上500℃以下の一定温度に設定された熱処理炉内に前記貼り合わせたボンドウェーハとベースウェーハを昇温工程なしで直接投入し、前記一定温度で熱処理するか、又は、前記一定温度から+50℃以内の所定温度に昇温したのち該所定温度で熱処理する貼り合わせウェーハの製造方法を提供する。
In order to solve the above problems, in the present invention, at least one kind of gas ion of hydrogen ion or rare gas ion is ion-implanted from the surface of a bond wafer made of a silicon single crystal wafer, and an ion implantation layer is formed inside the bond wafer. After bonding the ion-implanted surface of the bond wafer and the surface of the base wafer directly or through an insulating film, the bond wafer is peeled off and pasted by the ion-implanted layer by performing a peeling heat treatment. In the bonded wafer manufacturing method for manufacturing a bonded wafer, after bonding the bond wafer and the base wafer, the bonded interface between the bonded wafer and the base wafer is bonded until the peeling heat treatment is performed. The bonded body is bonded with the contribution of water molecules. Hold the wafer and the base wafer at room temperature for 12 hours or more, and the peeling heat treatment raises the bonded wafer and base wafer bonded together in a heat treatment furnace set at a constant temperature of 400 ° C. or more and 500 ° C. or less. Provided is a method for producing a bonded wafer that is directly charged without a temperature step and heat-treated at the constant temperature, or heated to a predetermined temperature within + 50 ° C. from the constant temperature and then heat-treated at the predetermined temperature.
このような貼り合わせウェーハの製造方法であれば、例えばSOIウェーハのような貼り合わせウェーハの剥離後の剥離面の表面粗さを低減させることができるので、より低い温度での平坦化熱処理により最終的な貼り合わせウェーハの表面(SOI層の表面)の表面粗さを低下させることができる。また、貼り合わせたウェーハを室温で12時間以上保持することによって、熱処理炉に投入する際のボンドウェーハとベースウェーハとの貼り合わせ強度を高めておくことができ、これによりボイドの発生を抑制できる。
With such a bonded wafer manufacturing method, for example, the surface roughness of the peeled surface after peeling of the bonded wafer such as an SOI wafer can be reduced, so that the final surface can be obtained by planarizing heat treatment at a lower temperature. It is possible to reduce the surface roughness of the surface of the bonded wafer (surface of the SOI layer). In addition, by holding the bonded wafer at room temperature for 12 hours or more, the bonding strength between the bond wafer and the base wafer when being put into the heat treatment furnace can be increased, thereby suppressing the generation of voids. .
このとき、前記一定温度又は前記所定温度で熱処理した後に、前記熱処理炉から前記貼り合わせウェーハを取り出す際の温度を、前記剥離熱処理の際の温度と同一温度とすることが好ましい。
At this time, it is preferable that the temperature at the time of taking out the bonded wafer from the heat treatment furnace after the heat treatment at the constant temperature or the predetermined temperature is the same as the temperature at the time of the peeling heat treatment.
熱処理炉から貼り合わせウェーハを取り出す際の温度を、剥離熱処理の際の温度と同一温度とすれば、降温工程を省略することができるので効率的であり、製造コストを低減させることができる。
If the temperature at the time of taking out the bonded wafer from the heat treatment furnace is the same as the temperature at the time of the peeling heat treatment, the temperature lowering step can be omitted, which is efficient and the manufacturing cost can be reduced.
またこのとき、前記室温で保持する時間を48時間以上とすることが好ましい。
Further, at this time, it is preferable that the holding time at the room temperature is 48 hours or more.
このようにすれば、ボンドウェーハとベースウェーハとの貼り合わせ強度をより一層高めることができる。
In this way, the bonding strength between the bond wafer and the base wafer can be further increased.
またこのとき、前記剥離熱処理の後に、前記ボンドウェーハを剥離した貼り合わせウェーハの剥離面を平坦化する熱処理を行い、該平坦化する熱処理の温度を1100℃~1175℃の温度範囲内で行うことが好ましい。
At this time, after the peeling heat treatment, a heat treatment for flattening the peeled surface of the bonded wafer from which the bond wafer has been peeled is performed, and the temperature of the flattening heat treatment is performed within a temperature range of 1100 ° C. to 1175 ° C. Is preferred.
このような温度範囲で平坦化熱処理を行えば、スリップ転位が発生する確率が低下するため、製品歩留まりが向上し、結果として製造コストを低下させることができる。
If the flattening heat treatment is performed in such a temperature range, the probability of occurrence of slip dislocation is reduced, so that the product yield is improved, and as a result, the manufacturing cost can be reduced.
またこのとき、前記ボンドウェーハと前記ベースウェーハとを貼り合わせる前に、前記ボンドウェーハ及び前記ベースウェーハを洗浄することが好ましい。
At this time, it is preferable to clean the bond wafer and the base wafer before bonding the bond wafer and the base wafer together.
このように、本発明では、ボンドウェーハとベースウェーハとを貼り合わせる前に、ボンドウェーハ及びベースウェーハを洗浄することで、ボンドウェーハ及びベースウェーハの表面に水分子を十分に残すことができ、また、ボンドウェーハとベースウェーハとを貼り合わせた際に、貼り合わせたウェーハの貼り合わせ界面が水分子の寄与によって結合している状態とすることができる。
As described above, in the present invention, by bonding the bond wafer and the base wafer before bonding the bond wafer and the base wafer, sufficient water molecules can be left on the surface of the bond wafer and the base wafer. When the bond wafer and the base wafer are bonded together, the bonded interface of the bonded wafers can be brought into a bonded state due to the contribution of water molecules.
本発明の貼り合わせウェーハの製造方法であれば、例えばSOIウェーハのような貼り合わせウェーハの剥離後の剥離面の表面粗さを低減させることができるので、より低い温度での平坦化熱処理により最終的な貼り合わせウェーハの表面(SOI層の表面)の表面粗さを低下させることができる。また、貼り合わせたウェーハを室温で12時間以上保持することによって、熱処理炉に投入する際のボンドウェーハとベースウェーハとの貼り合わせ強度を高めておくことができ、これによりボイドの発生を抑制できる。
If it is the manufacturing method of the bonded wafer of this invention, since the surface roughness of the peeling surface after peeling of bonded wafers, such as an SOI wafer, can be reduced, it is final by planarization heat processing at lower temperature. It is possible to reduce the surface roughness of the surface of the bonded wafer (surface of the SOI layer). In addition, by holding the bonded wafer at room temperature for 12 hours or more, the bonding strength between the bond wafer and the base wafer when being put into the heat treatment furnace can be increased, thereby suppressing the generation of voids. .
以下、本発明について、より具体的に説明する。
上述のように、例えばSOIウェーハあるいは絶縁膜を介さないダイレクトボンドウェーハのような貼り合わせウェーハの剥離後の剥離面の表面粗さを低減させることで、より低い温度での平坦化熱処理により最終的な貼り合わせウェーハの表面(SOI層の表面)の表面粗さを低下させることができる貼り合わせウェーハの製造方法が求められていた。 Hereinafter, the present invention will be described more specifically.
As described above, for example, by reducing the surface roughness of the peeled surface after peeling of a bonded wafer such as an SOI wafer or a direct bond wafer that does not pass through an insulating film, the final surface is processed by a planarization heat treatment at a lower temperature. There has been a demand for a method for manufacturing a bonded wafer that can reduce the surface roughness of the surface of the bonded wafer (the surface of the SOI layer).
上述のように、例えばSOIウェーハあるいは絶縁膜を介さないダイレクトボンドウェーハのような貼り合わせウェーハの剥離後の剥離面の表面粗さを低減させることで、より低い温度での平坦化熱処理により最終的な貼り合わせウェーハの表面(SOI層の表面)の表面粗さを低下させることができる貼り合わせウェーハの製造方法が求められていた。 Hereinafter, the present invention will be described more specifically.
As described above, for example, by reducing the surface roughness of the peeled surface after peeling of a bonded wafer such as an SOI wafer or a direct bond wafer that does not pass through an insulating film, the final surface is processed by a planarization heat treatment at a lower temperature. There has been a demand for a method for manufacturing a bonded wafer that can reduce the surface roughness of the surface of the bonded wafer (the surface of the SOI layer).
通常、イオン注入剥離法で剥離熱処理を行う際には、例えば特開2003-347526号等に記載されているように、350℃程度の低温に保持された熱処理炉に貼り合わせたウェーハを投入して一定時間保持した後、500℃以上の温度に昇温して所定時間保持する方法が行われる。しかしながら、このような熱処理を行うと、剥離が生じる500℃に達するまでの間に、イオン注入された水素の拡散がわずかながら進行し、注入層の水素濃度分布が広がってしまう。その状態で剥離が生じると、剥離領域の幅(深さ方向の幅)が広くなり、結果として剥離面の表面粗さは大きくなる。
Normally, when performing a heat treatment for separation by an ion implantation separation method, a wafer bonded to a heat treatment furnace maintained at a low temperature of about 350 ° C. is loaded as described in, for example, Japanese Patent Application Laid-Open No. 2003-347526. And holding for a predetermined time, and then raising the temperature to 500 ° C. or higher and holding it for a predetermined time. However, when such heat treatment is performed, the diffusion of ion-implanted hydrogen slightly progresses until the temperature reaches 500 ° C. at which peeling occurs, and the hydrogen concentration distribution in the implanted layer widens. When peeling occurs in this state, the width of the peeling region (width in the depth direction) becomes wide, and as a result, the surface roughness of the peeling surface increases.
そこで、本発明者らは、水素の拡散を抑えるために、剥離が可能な温度に、昇温工程なしで直接投入するか、又は、一定温度から+50℃以内の所定温度に昇温したのちこの所定温度で熱処理することにより、剥離後の剥離面の表面粗さを低減することができることを見出した。ただし、このように従来よりも高温で熱処理炉に投入する場合、投入時の結合力が弱いと完全な剥離が得られずに、ボイドの発生を伴ってしまう。本発明者らは、その対策として、ボンドウェーハとベースウェーハとを貼り合わせた後、剥離熱処理を行うまで、貼り合わせ界面が水分子の寄与によって結合している状態で貼り合わせたウェーハを室温で長時間保持することによって、熱処理炉に投入する際のボンドウェーハとベースウェーハとの貼り合わせ強度を高めておくことにより、上記課題を解決できることを見出し、本発明を完成させた。
Therefore, in order to suppress the diffusion of hydrogen, the present inventors either directly input the temperature at which separation is possible without a heating step, or after raising the temperature from a certain temperature to a predetermined temperature within + 50 ° C. It has been found that the surface roughness of the peeled surface after peeling can be reduced by heat treatment at a predetermined temperature. However, when it is charged into the heat treatment furnace at a higher temperature than in the prior art, if the bonding force at the time of charging is weak, complete peeling cannot be obtained and voids are generated. As a countermeasure, the present inventors have bonded the bonded wafer and the base wafer at room temperature until the bonded interface is bonded by the contribution of water molecules until the separation heat treatment is performed. The inventors have found that the above problems can be solved by increasing the bonding strength between the bond wafer and the base wafer when being put into a heat treatment furnace by holding for a long time, and the present invention has been completed.
以下、本発明について、図面を参照しながら詳細に説明するが、本発明はこれらに限定されるものではない。
Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.
図1は、本発明の貼り合わせウェーハの製造方法の一例を示す概略図である。
図1の貼り合わせウェーハの製造方法では、まず、ボンドウェーハ1とベースウェーハ2として例えばシリコン単結晶ウェーハ2枚を準備する(図1(a),(c))。
ここで、図1では、ボンドウェーハ1の貼り合わせ面にだけ埋め込み酸化膜層となる絶縁膜(例えば、酸化膜)3が形成されているが、絶縁膜3はベースウェーハ2にだけ形成されていてもよいし、両ウェーハに形成されていてもよい。また、両ウェーハともに絶縁膜を形成することなく、直接貼り合わせてもよい。
このとき形成させる絶縁膜としては、例えば熱酸化膜、CVD酸化膜等を形成させることができる。なお、絶縁膜は、貼り合わせ面のみに形成されていてもよいし、裏面も含めたウェーハの全体に形成されていてもよい。 FIG. 1 is a schematic view showing an example of a method for producing a bonded wafer according to the present invention.
In the bonded wafer manufacturing method of FIG. 1, first, for example, two silicon single crystal wafers are prepared as thebond wafer 1 and the base wafer 2 (FIGS. 1A and 1C).
Here, in FIG. 1, an insulating film (for example, an oxide film) 3 to be a buried oxide film layer is formed only on the bonding surface of thebond wafer 1, but the insulating film 3 is formed only on the base wafer 2. It may be formed on both wafers. Further, both wafers may be bonded directly without forming an insulating film.
As the insulating film formed at this time, for example, a thermal oxide film, a CVD oxide film, or the like can be formed. The insulating film may be formed only on the bonding surface, or may be formed on the entire wafer including the back surface.
図1の貼り合わせウェーハの製造方法では、まず、ボンドウェーハ1とベースウェーハ2として例えばシリコン単結晶ウェーハ2枚を準備する(図1(a),(c))。
ここで、図1では、ボンドウェーハ1の貼り合わせ面にだけ埋め込み酸化膜層となる絶縁膜(例えば、酸化膜)3が形成されているが、絶縁膜3はベースウェーハ2にだけ形成されていてもよいし、両ウェーハに形成されていてもよい。また、両ウェーハともに絶縁膜を形成することなく、直接貼り合わせてもよい。
このとき形成させる絶縁膜としては、例えば熱酸化膜、CVD酸化膜等を形成させることができる。なお、絶縁膜は、貼り合わせ面のみに形成されていてもよいし、裏面も含めたウェーハの全体に形成されていてもよい。 FIG. 1 is a schematic view showing an example of a method for producing a bonded wafer according to the present invention.
In the bonded wafer manufacturing method of FIG. 1, first, for example, two silicon single crystal wafers are prepared as the
Here, in FIG. 1, an insulating film (for example, an oxide film) 3 to be a buried oxide film layer is formed only on the bonding surface of the
As the insulating film formed at this time, for example, a thermal oxide film, a CVD oxide film, or the like can be formed. The insulating film may be formed only on the bonding surface, or may be formed on the entire wafer including the back surface.
次に、ボンドウェーハ1の絶縁膜3の表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入してボンドウェーハ1の内部にイオン注入層4を形成する(図1(b))。この際、注入エネルギー、注入線量、注入温度等のイオン注入条件は、所定の厚さの薄膜を得ることができるように適宜選択することができる。
Next, at least one kind of gas ion of hydrogen ion and rare gas ion is ion-implanted from the surface of the insulating film 3 of the bond wafer 1 to form an ion-implanted layer 4 inside the bond wafer 1 (FIG. 1B). ). At this time, ion implantation conditions such as implantation energy, implantation dose, and implantation temperature can be appropriately selected so that a thin film having a predetermined thickness can be obtained.
次に、ボンドウェーハ1のイオン注入された側の表面とベースウェーハ2の表面とを密着させて、18~30℃程度の室温で貼り合わせる(図1(d))。
Next, the ion-implanted surface of the bond wafer 1 and the surface of the base wafer 2 are brought into close contact with each other and bonded at a room temperature of about 18 to 30 ° C. (FIG. 1 (d)).
この際、貼り合わせを行う表面の少なくとも一方にプラズマ処理を施しておくことが好ましい。これによって、後述する室温での保持による貼り合わせ強度の向上効果をより一層高めることができる。
At this time, it is preferable to perform plasma treatment on at least one of the surfaces to be bonded. Thereby, the improvement effect of the bonding strength by holding | maintenance at room temperature mentioned later can be heightened further.
また、ボンドウェーハ1とベースウェーハ2とを貼り合わせる前に、ボンドウェーハ1及びベースウェーハ2を洗浄することが好ましい。このように、本発明では、ボンドウェーハとベースウェーハとを貼り合わせる前に、ボンドウェーハ及びベースウェーハを洗浄することで、ボンドウェーハ及びベースウェーハの表面に水分子を十分に残すことができ、また、ボンドウェーハとベースウェーハとを貼り合わせた際に、貼り合わせたウェーハの貼り合わせ界面が水分子の寄与によって結合している状態とすることができる。この洗浄に用いる洗浄液としては、特に限定されないが、例えばアンモニア水と過酸化水素水との混合溶液を挙げることができる。
Further, it is preferable to clean the bond wafer 1 and the base wafer 2 before bonding the bond wafer 1 and the base wafer 2 together. As described above, in the present invention, by bonding the bond wafer and the base wafer before bonding the bond wafer and the base wafer, sufficient water molecules can be left on the surface of the bond wafer and the base wafer. When the bond wafer and the base wafer are bonded together, the bonded interface of the bonded wafers can be brought into a bonded state due to the contribution of water molecules. The cleaning liquid used for this cleaning is not particularly limited, and examples thereof include a mixed solution of ammonia water and hydrogen peroxide water.
ボンドウェーハ1とベースウェーハ2とを貼り合わせた後、この貼り合わせたウェーハを、後述の剥離熱処理を行うまで、貼り合わせたウェーハの貼り合わせ界面が水分子の寄与によって結合している状態で室温で12時間以上保持する(図1(e))。ボンドウェーハとベースウェーハとを貼り合わせた後、直ちに剥離熱処理を行わず、貼り合わせた状態でしばらく放置することで、貼り合わせ界面の水分子の方向を整列させ、貼り合わせ界面の強度を高めることができる。室温で保持する時間が12時間未満では、ボンドウェーハとベースウェーハとの貼り合わせ強度を十分に高めることができない。
After the bond wafer 1 and the base wafer 2 are bonded together, the bonded wafer is bonded at the room temperature in the state where the bonded interface of the bonded wafers is bonded by the contribution of water molecules until the peeling heat treatment described later is performed. Hold for at least 12 hours (FIG. 1 (e)). Immediately after bonding the bond wafer and the base wafer, the heat treatment of peeling is not performed, and the bonded wafer is left for a while to align the direction of water molecules at the bonding interface, thereby increasing the strength of the bonding interface. Can do. When the holding time at room temperature is less than 12 hours, the bonding strength between the bond wafer and the base wafer cannot be sufficiently increased.
室温で保持する時間としては、12時間以上であればよく、好ましくは48時間以上である。室温で48時間以上保持することで、ボンドウェーハとベースウェーハとの貼り合わせ強度をより一層高めることができる。また、室温で保持する時間の上限としては、100時間程度までは貼り合わせ強度が上がるが、100時間を超えると貼り合わせ強度のこれ以上の上昇が見られなくなるため、生産性の観点から上限を100時間とすることが好ましい。室温で保持する時間は、製品仕様に合わせて、歩留まりが確保できる範囲で調整することができる。
The time for holding at room temperature may be 12 hours or more, and preferably 48 hours or more. By holding at room temperature for 48 hours or more, the bonding strength between the bond wafer and the base wafer can be further increased. In addition, as the upper limit of the time for holding at room temperature, the bonding strength is increased up to about 100 hours, but when the time exceeds 100 hours, no further increase in the bonding strength is observed, so the upper limit is set from the viewpoint of productivity. 100 hours is preferable. The holding time at room temperature can be adjusted within a range in which the yield can be secured according to the product specifications.
その後、貼り合わせたウェーハに対して、イオン注入層4に微小気泡層を発生させる熱処理(剥離熱処理)を施し、イオン注入層4(微小気泡層)でボンドウェーハ1を剥離させて、ベースウェーハ2上に絶縁膜3を介して薄膜(SOI層)5が形成された貼り合わせウェーハ6を得る(図1(f))。
Thereafter, the bonded wafer is subjected to a heat treatment (peeling heat treatment) for generating a microbubble layer in the ion implantation layer 4, and the bond wafer 1 is peeled off by the ion implantation layer 4 (microbubble layer). A bonded wafer 6 having a thin film (SOI layer) 5 formed thereon via an insulating film 3 is obtained (FIG. 1 (f)).
この剥離熱処理は、炉内温度が400℃以上500℃以下の一定温度に設定された熱処理炉内に貼り合わせたボンドウェーハとベースウェーハを昇温工程なしで直接投入し、一定温度で熱処理するか、又は、一定温度から+50℃以内(通常、0℃を超え+50℃以内)の所定温度に昇温したのちこの所定温度で熱処理することで行われる。このような熱処理条件で剥離熱処理を行うことで、剥離面の表面粗さを低減することができる。
In this exfoliation heat treatment, whether or not the bonded wafer and the base wafer bonded together in a heat treatment furnace whose temperature in the furnace is set to a constant temperature of 400 ° C. or more and 500 ° C. or less is directly put in without a heating step, and the heat treatment is performed at a constant temperature. Alternatively, the temperature is raised to a predetermined temperature within a range of + 50 ° C. (usually over 0 ° C. and within + 50 ° C.) from a certain temperature, and then heat treatment is performed at this predetermined temperature. By performing the peeling heat treatment under such heat treatment conditions, the surface roughness of the peeling surface can be reduced.
ここで、一定温度又は所定温度で熱処理した後に、熱処理炉から貼り合わせウェーハを取り出す際の温度を、剥離熱処理の際の温度と同一温度とすることが好ましい。熱処理炉から貼り合わせウェーハを取り出す際の温度を、剥離熱処理の際の温度と同一温度とすれば、降温工程を省略することができるので効率的であり、製造コストを低減させることができる。
Here, it is preferable that the temperature at the time of taking out the bonded wafer from the heat treatment furnace after the heat treatment at a constant temperature or a predetermined temperature is the same as the temperature at the peeling heat treatment. If the temperature at the time of taking out the bonded wafer from the heat treatment furnace is the same as the temperature at the time of the peeling heat treatment, the temperature lowering step can be omitted, which is efficient and the manufacturing cost can be reduced.
上記のように作製した貼り合わせウェーハに対し、必要に応じて、貼り合わせ界面の結合強度を高めるための結合熱処理、ボンドウェーハを剥離した貼り合わせウェーハの剥離面を平坦化するための平坦化熱処理、薄膜の膜厚を調整するための犠牲酸化処理等のような熱処理を行うことができる。
Bonded heat treatment for increasing the bond strength at the bonding interface, and planarization heat treatment for flattening the peeled surface of the bonded wafer from which the bond wafer has been peeled off, if necessary, for the bonded wafer produced as described above. Then, heat treatment such as sacrificial oxidation treatment for adjusting the thickness of the thin film can be performed.
特に、本発明では、平坦化熱処理の温度を1100℃~1175℃の温度範囲内で行うことが好ましい。このような温度範囲で平坦化熱処理を行えば、スリップ転位が発生する確率が低下するため、製品歩留まりが向上し、結果として製造コストを低下させることができる。
In particular, in the present invention, it is preferable to perform the planarization heat treatment within a temperature range of 1100 ° C. to 1175 ° C. If the planarization heat treatment is performed in such a temperature range, the probability of occurrence of slip dislocation is reduced, so that the product yield is improved, and as a result, the manufacturing cost can be reduced.
以上説明したような本発明の貼り合わせウェーハの製造方法であれば、例えばSOIウェーハのような貼り合わせウェーハの剥離後の剥離面の表面粗さを低減させることができるので、より低い温度での平坦化熱処理により最終的な貼り合わせウェーハの表面(SOI層の表面)の表面粗さを低下させることができる。
If it is the manufacturing method of the bonded wafer of this invention which was demonstrated above, since the surface roughness of the peeling surface after peeling of bonded wafers, such as an SOI wafer, can be reduced, it is at lower temperature. The surface roughness of the final bonded wafer surface (the surface of the SOI layer) can be reduced by the planarization heat treatment.
以下、実施例及び比較例を用いて本発明を具体的に説明するが、本発明はこれらに限定されるものではない。
Hereinafter, the present invention will be specifically described using examples and comparative examples, but the present invention is not limited thereto.
(実施例1)
まず、シリコン単結晶からなるボンドウェーハ及びベースウェーハとしてそれぞれ表1に記載のウェーハを複数枚用い、表1に記載の条件で洗浄、貼り合わせ、室温保持、及び剥離熱処理を行ってSOIウェーハを作製した。なお、室温保持時間は12時間とした。また、剥離熱処理は、450℃の一定温度で、熱処理時間を3時間として行った。 Example 1
First, a plurality of wafers shown in Table 1 are used as bond wafers and base wafers made of silicon single crystal, and an SOI wafer is manufactured by performing cleaning, bonding, room temperature holding, and peeling heat treatment under the conditions shown in Table 1. did. The room temperature holding time was 12 hours. The peeling heat treatment was performed at a constant temperature of 450 ° C. and the heat treatment time was 3 hours.
まず、シリコン単結晶からなるボンドウェーハ及びベースウェーハとしてそれぞれ表1に記載のウェーハを複数枚用い、表1に記載の条件で洗浄、貼り合わせ、室温保持、及び剥離熱処理を行ってSOIウェーハを作製した。なお、室温保持時間は12時間とした。また、剥離熱処理は、450℃の一定温度で、熱処理時間を3時間として行った。 Example 1
First, a plurality of wafers shown in Table 1 are used as bond wafers and base wafers made of silicon single crystal, and an SOI wafer is manufactured by performing cleaning, bonding, room temperature holding, and peeling heat treatment under the conditions shown in Table 1. did. The room temperature holding time was 12 hours. The peeling heat treatment was performed at a constant temperature of 450 ° C. and the heat treatment time was 3 hours.
得られたSOIウェーハに対し、さらに、結合熱処理を兼ねた犠牲酸化処理、平坦化熱処理、SOI層の膜厚調整のための犠牲酸化処理を行って、SOI層の膜厚が90nmの貼り合わせSOIウェーハを作製した。なお、平坦化熱処理は、表2に示すように、1100℃、1150℃、1175℃の温度条件で、得られたSOIウェーハに対し別個に2時間行った。
The obtained SOI wafer is further subjected to sacrificial oxidation treatment that also serves as bonding heat treatment, planarization heat treatment, and sacrificial oxidation treatment for adjusting the film thickness of the SOI layer, and bonded SOI with a SOI layer thickness of 90 nm. A wafer was produced. In addition, as shown in Table 2, the planarization heat treatment was performed separately for 2 hours on the obtained SOI wafer under the temperature conditions of 1100 ° C., 1150 ° C., and 1175 ° C.
得られた貼り合わせSOIウェーハのSOI層(最終的なSOI層)の表面の表面粗さ(1μm角のRMS)をAFM(原子間力顕微鏡)で測定し、表2に示した。なお、剥離直後の剥離面の表面粗さを測定すると、測定ポイントによるバラツキが大きく、比較が困難なので、ここでは、最終的なSOI層(即ち、平坦化熱処理を行った後)の表面の表面粗さを測定し、比較した。
The surface roughness (1 μm square RMS) of the SOI layer (final SOI layer) of the obtained bonded SOI wafer was measured with an AFM (atomic force microscope) and shown in Table 2. Note that, when the surface roughness of the peeled surface immediately after peeling is measured, there is a large variation due to the measurement point and it is difficult to compare, so here, the surface surface of the final SOI layer (that is, after performing the planarization heat treatment) Roughness was measured and compared.
(実施例2)
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は48時間とした。また、剥離熱処理は、450℃の一定温度から500℃の所定温度(+50℃)まで昇温し(昇温速度10℃/min)、熱処理時間を0.5時間として行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Example 2)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 48 hours. Further, the peeling heat treatment was performed by raising the temperature from a constant temperature of 450 ° C. to a predetermined temperature of 500 ° C. (+ 50 ° C.) (temperature raising rate: 10 ° C./min) and a heat treatment time of 0.5 hours.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は48時間とした。また、剥離熱処理は、450℃の一定温度から500℃の所定温度(+50℃)まで昇温し(昇温速度10℃/min)、熱処理時間を0.5時間として行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Example 2)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 48 hours. Further, the peeling heat treatment was performed by raising the temperature from a constant temperature of 450 ° C. to a predetermined temperature of 500 ° C. (+ 50 ° C.) (temperature raising rate: 10 ° C./min) and a heat treatment time of 0.5 hours.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
(実施例3)
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は96時間とした。また、剥離熱処理は、400℃の一定温度から450℃の所定温度(+50℃)まで昇温し(昇温速度10℃/min)、熱処理時間を3時間として行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Example 3)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 96 hours. Further, the peeling heat treatment was performed by raising the temperature from a constant temperature of 400 ° C. to a predetermined temperature (+ 50 ° C.) of 450 ° C. (heating rate of 10 ° C./min) and a heat treatment time of 3 hours.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は96時間とした。また、剥離熱処理は、400℃の一定温度から450℃の所定温度(+50℃)まで昇温し(昇温速度10℃/min)、熱処理時間を3時間として行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Example 3)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 96 hours. Further, the peeling heat treatment was performed by raising the temperature from a constant temperature of 400 ° C. to a predetermined temperature (+ 50 ° C.) of 450 ° C. (heating rate of 10 ° C./min) and a heat treatment time of 3 hours.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
(比較例1)
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は1時間とした。また、剥離熱処理は、450℃の一定温度で、熱処理時間を3時間として行った。さらに、平坦化熱処理は、表2に示すように、1100℃、1150℃、1175℃、1200℃の温度条件で、熱処理時間をそれぞれ2時間、2時間、2時間、1時間として、得られたSOIウェーハに対し別個に行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Comparative Example 1)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 1 hour. The peeling heat treatment was performed at a constant temperature of 450 ° C. and the heat treatment time was 3 hours. Further, as shown in Table 2, the planarization heat treatment was obtained under the temperature conditions of 1100 ° C., 1150 ° C., 1175 ° C., and 1200 ° C. with the heat treatment time being 2 hours, 2 hours, 2 hours, and 1 hour, respectively. Separately for SOI wafers.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は1時間とした。また、剥離熱処理は、450℃の一定温度で、熱処理時間を3時間として行った。さらに、平坦化熱処理は、表2に示すように、1100℃、1150℃、1175℃、1200℃の温度条件で、熱処理時間をそれぞれ2時間、2時間、2時間、1時間として、得られたSOIウェーハに対し別個に行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Comparative Example 1)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 1 hour. The peeling heat treatment was performed at a constant temperature of 450 ° C. and the heat treatment time was 3 hours. Further, as shown in Table 2, the planarization heat treatment was obtained under the temperature conditions of 1100 ° C., 1150 ° C., 1175 ° C., and 1200 ° C. with the heat treatment time being 2 hours, 2 hours, 2 hours, and 1 hour, respectively. Separately for SOI wafers.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
(比較例2)
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は96時間とし、剥離熱処理は、350℃の一定温度から500℃の所定温度(+150℃)まで昇温し(昇温速度10℃/min)、熱処理時間は0.5時間として行った。さらに、平坦化熱処理は、表2に示すように、1100℃、1150℃、1175℃、1200℃の温度条件で、熱処理時間をそれぞれ2時間、2時間、2時間、1時間として、得られたSOIウェーハに対し別個に行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Comparative Example 2)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 96 hours, and the peeling heat treatment was performed by raising the temperature from a constant temperature of 350 ° C. to a predetermined temperature of 500 ° C. (+ 150 ° C.) (heating rate 10 ° C./min), and the heat treatment time was 0.5 hours. Went as. Further, as shown in Table 2, the planarization heat treatment was obtained under the temperature conditions of 1100 ° C., 1150 ° C., 1175 ° C., and 1200 ° C. with the heat treatment time being 2 hours, 2 hours, 2 hours, and 1 hour, respectively. Separately for SOI wafers.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
実施例1と同様にして貼り合わせSOIウェーハの作製を行った。ただし、室温保持時間は96時間とし、剥離熱処理は、350℃の一定温度から500℃の所定温度(+150℃)まで昇温し(昇温速度10℃/min)、熱処理時間は0.5時間として行った。さらに、平坦化熱処理は、表2に示すように、1100℃、1150℃、1175℃、1200℃の温度条件で、熱処理時間をそれぞれ2時間、2時間、2時間、1時間として、得られたSOIウェーハに対し別個に行った。
また、実施例1と同様にして、最終的なSOI層の表面の表面粗さの測定を行い、結果を表2に示した。 (Comparative Example 2)
A bonded SOI wafer was prepared in the same manner as in Example 1. However, the room temperature holding time was 96 hours, and the peeling heat treatment was performed by raising the temperature from a constant temperature of 350 ° C. to a predetermined temperature of 500 ° C. (+ 150 ° C.) (heating rate 10 ° C./min), and the heat treatment time was 0.5 hours. Went as. Further, as shown in Table 2, the planarization heat treatment was obtained under the temperature conditions of 1100 ° C., 1150 ° C., 1175 ° C., and 1200 ° C. with the heat treatment time being 2 hours, 2 hours, 2 hours, and 1 hour, respectively. Separately for SOI wafers.
Further, the surface roughness of the surface of the final SOI layer was measured in the same manner as in Example 1, and the results are shown in Table 2.
(結果)
表2に示されるように、本発明の貼り合わせウェーハの製造方法で貼り合わせSOIウェーハを製造した実施例1~3では、1100~1175℃の比較的低温の平坦化熱処理により、比較例2の従来法(平坦化熱処理温度:1200℃)における表面粗さと同等以上の良好な表面粗さが得られることが分かった。
また、実施例1~3における平坦化熱処理は1175℃以下で行われているため、1200℃の場合に比べて熱処理によるスリップ転位の発生が抑制されていることも確認できた。 (result)
As shown in Table 2, in Examples 1 to 3 in which bonded SOI wafers were manufactured by the method for manufacturing a bonded wafer of the present invention, a relatively low temperature flattening heat treatment at 1100 to 1175 ° C. was performed. It was found that a good surface roughness equal to or better than the surface roughness in the conventional method (planarization heat treatment temperature: 1200 ° C.) can be obtained.
Further, since the flattening heat treatment in Examples 1 to 3 was performed at 1175 ° C. or lower, it was confirmed that the occurrence of slip dislocation due to the heat treatment was suppressed as compared with the case of 1200 ° C.
表2に示されるように、本発明の貼り合わせウェーハの製造方法で貼り合わせSOIウェーハを製造した実施例1~3では、1100~1175℃の比較的低温の平坦化熱処理により、比較例2の従来法(平坦化熱処理温度:1200℃)における表面粗さと同等以上の良好な表面粗さが得られることが分かった。
また、実施例1~3における平坦化熱処理は1175℃以下で行われているため、1200℃の場合に比べて熱処理によるスリップ転位の発生が抑制されていることも確認できた。 (result)
As shown in Table 2, in Examples 1 to 3 in which bonded SOI wafers were manufactured by the method for manufacturing a bonded wafer of the present invention, a relatively low temperature flattening heat treatment at 1100 to 1175 ° C. was performed. It was found that a good surface roughness equal to or better than the surface roughness in the conventional method (planarization heat treatment temperature: 1200 ° C.) can be obtained.
Further, since the flattening heat treatment in Examples 1 to 3 was performed at 1175 ° C. or lower, it was confirmed that the occurrence of slip dislocation due to the heat treatment was suppressed as compared with the case of 1200 ° C.
一方、室温保持時間が12時間未満(1時間)であった比較例1や一定温度から+50℃を超えた所定温度(+150℃)まで昇温した比較例2では、1100~1175℃の比較的低温の平坦化熱処理では、最終的なSOI層の表面の表面粗さは実施例1~3と比べて悪かった。また、室温保持時間が1時間であった比較例1は、室温保持時間が12時間であった実施例1に比べてボイドの発生率が高かった。
On the other hand, in Comparative Example 1 in which the room temperature retention time was less than 12 hours (1 hour) and Comparative Example 2 in which the temperature was raised from a certain temperature to a predetermined temperature exceeding + 50 ° C. (+ 150 ° C.), a relatively high temperature of 1100 to 1175 ° C. In the low-temperature planarization heat treatment, the surface roughness of the final SOI layer surface was worse than that in Examples 1 to 3. Further, Comparative Example 1 in which the room temperature holding time was 1 hour had a higher void generation rate than Example 1 in which the room temperature holding time was 12 hours.
なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。
Note that the present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
Claims (5)
- シリコン単結晶ウェーハからなるボンドウェーハの表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入して前記ボンドウェーハの内部にイオン注入層を形成し、前記ボンドウェーハのイオン注入した表面とベースウェーハの表面とを直接又は絶縁膜を介して貼り合わせた後、剥離熱処理を行うことによって前記イオン注入層で前記ボンドウェーハを剥離させて貼り合わせウェーハを製造する貼り合わせウェーハの製造方法において、
前記ボンドウェーハと前記ベースウェーハとを貼り合わせた後、前記剥離熱処理を行うまで、貼り合わせた前記ボンドウェーハと前記ベースウェーハとの貼り合わせ界面が水分子の寄与によって結合している状態で前記貼り合わせたボンドウェーハとベースウェーハを室温で12時間以上保持し、
前記剥離熱処理は、炉内温度が400℃以上500℃以下の一定温度に設定された熱処理炉内に前記貼り合わせたボンドウェーハとベースウェーハを昇温工程なしで直接投入し、前記一定温度で熱処理するか、又は、前記一定温度から+50℃以内の所定温度に昇温したのち該所定温度で熱処理することを特徴とする貼り合わせウェーハの製造方法。 A surface of a bond wafer made of a silicon single crystal wafer is ion-implanted with at least one gas ion of hydrogen ions and rare gas ions to form an ion implantation layer inside the bond wafer, and the ion-implanted surface of the bond wafer In the method for manufacturing a bonded wafer, the bonded wafer is manufactured by peeling the bond wafer with the ion implantation layer by performing a peeling heat treatment after bonding the substrate and the surface of the base wafer directly or through an insulating film. ,
After bonding the bond wafer and the base wafer, the bonding interface between the bonded bond wafer and the base wafer is bonded with the contribution of water molecules until the peeling heat treatment is performed. Hold the combined bond wafer and base wafer for more than 12 hours at room temperature,
In the exfoliation heat treatment, the bonded wafer and base wafer are directly put into a heat treatment furnace set at a constant temperature of 400 ° C. or more and 500 ° C. or less without a heating step, and the heat treatment is performed at the constant temperature. Or a method of manufacturing a bonded wafer, wherein the temperature is raised to a predetermined temperature within + 50 ° C. from the constant temperature and then heat-treated at the predetermined temperature. - 前記一定温度又は前記所定温度で熱処理した後に、前記熱処理炉から前記貼り合わせウェーハを取り出す際の温度を、前記剥離熱処理の際の温度と同一温度とすることを特徴とする請求項1に記載の貼り合わせウェーハの製造方法。 The temperature at the time of taking out the bonded wafer from the heat treatment furnace after the heat treatment at the constant temperature or the predetermined temperature is the same as the temperature at the time of the peeling heat treatment. Manufacturing method of bonded wafer.
- 前記室温で保持する時間を48時間以上とすることを特徴とする請求項1又は請求項2に記載の貼り合わせウェーハの製造方法。 The method for producing a bonded wafer according to claim 1 or 2, wherein the time for holding at room temperature is 48 hours or more.
- 前記剥離熱処理の後に、前記ボンドウェーハを剥離した貼り合わせウェーハの剥離面を平坦化する熱処理を行い、該平坦化する熱処理の温度を1100℃~1175℃の温度範囲内で行うことを特徴とする請求項1から請求項3のいずれか一項に記載の貼り合わせウェーハの製造方法。 After the peeling heat treatment, a heat treatment for flattening the peeled surface of the bonded wafer from which the bond wafer has been peeled is performed, and the temperature of the flattening heat treatment is within a temperature range of 1100 ° C. to 1175 ° C. The manufacturing method of the bonded wafer as described in any one of Claims 1-3.
- 前記ボンドウェーハと前記ベースウェーハとを貼り合わせる前に、前記ボンドウェーハ及び前記ベースウェーハを洗浄することを特徴とする請求項1から請求項4のいずれか一項に記載の貼り合わせウェーハの製造方法。 The method for producing a bonded wafer according to any one of claims 1 to 4, wherein the bond wafer and the base wafer are cleaned before the bond wafer and the base wafer are bonded together. .
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WO2003009386A1 (en) * | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Method for producing bonding wafer |
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JP2012169449A (en) * | 2011-02-14 | 2012-09-06 | Shin Etsu Handotai Co Ltd | Manufacturing method of bonding wafer |
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JPH05211128A (en) * | 1991-09-18 | 1993-08-20 | Commiss Energ Atom | Manufacture of thin film of semiconductor material |
WO2001028000A1 (en) * | 1999-10-14 | 2001-04-19 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing soi wafer, and soi wafer |
WO2003009386A1 (en) * | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Method for producing bonding wafer |
JP2009295667A (en) * | 2008-06-03 | 2009-12-17 | Shin Etsu Handotai Co Ltd | Method for manufacturing laminated wafer |
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