WO2017123273A1

WO2017123273A1 - Informationally efficient error correction coding

Info

Publication number: WO2017123273A1
Application number: PCT/US2016/031781
Authority: WO
Inventors: Tao Xu; Ajit Nimbalker
Original assignee: Intel IP Corporation
Priority date: 2016-01-14
Filing date: 2016-05-11
Publication date: 2017-07-20
Also published as: TWI695589B; CN108432167B; CN108432167A; TW201733276A

Abstract

A set of information bits to be transmitted are encoded according to a parity-check block to produce a first codeword, the first codeword representing a set of parity-check nodes based on the set of information bits and on a set of parity-check bits. Parity-check bits are selected to be deprioritized from the first codeword based on selection criteria that deprioritizes those parity-check bits that are associated with relatively greater quantities of the parity-check nodes. An output data set is produced for transmission based on the first codeword, with the selected parity-check bits deprioritized.

Description

INFORMATIONAL!^ EFFICIENT ERROR CORRECTION CODING

PRIORITY CLAIM

[0001] This Application claims the benefit of U.S. Provisional Application No. 62/278,742, filed January 14, 2016, and entitled "LDPC PUNCTURING PATTERN SELECTION," the disclosure of which is incorporated by reference herein.

TECHNICAL FIELD

[0002] Embodiments pertain to wireless communications. Some embodiments relate to wireless networks including 3 GPP (Third Generation Partnership Project) networks, 3 GPP LTE (Long Term Evolution) networks, 3 GPP LTE-A (LTE

Advanced) networks, and 5G networks. Other embodiments relate to Wi-Fi Alliance wireless networks. Further embodiments are more generally applicable outside the purview of LTE and Wi-Fi networks.

BACKGROUND

[0003] In communication systems, particularly wireless systems, the

communication channel between the transmitter and receiver is subject to noise, which may interfere with the integrity of data being communicated. For instance, signal interference may cause errors in communicated bits of information. One approach for dealing with this problem is the use of error-correction coding. Error correction is the addition of redundant information to a message transmission that enables the receiver to detect of errors and reconstruct the intended, error-free, data.

[0004] Low-density parity-check (LDPC) codes are forward error-correction codes, first proposed in the early- 1960s. At the time, their potential remained undiscovered due to the limitations of computer systems needed to perform simulations. LDPC codes remained neglected by researchers for decades until the mid-1990s, when it was discovered that LDPC codes have the ability to outperform other existing forward error-correction schemes.

[0005] As with any forward error-correction coding, the informational redundancy introduced with the use of LDPC codes represents an engineering trade-off between data-communication rate on the one hand, and communication system robustness on the other. The ratio of information to be communicated to total message size is referred to as the coding rate. In order to accommodate ever-increasing demands for data-communication speed, solutions are needed to increase the coding rate with a negligible impact on the robustness provided by the error-correction coding overhead.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. Some embodiments are illustrated by way of example, and not limitation, in the following figures of the accompanying drawings.

[0007] FIG. 1 is a functional diagram of a 3 GPP network in accordance with some embodiments.

[0008] FIG. 2 is a block diagram of a User Equipment (UE) in accordance with some embodiments.

[0009] FIG. 3 is a block diagram of an Evolved Node-B (eNB) in accordance with some embodiments.

[0010] FIG. 4 is a diagram illustrating an example parity-check matrix according to an example embodiment.

[0011] FIGs. 5 A-5C illustrate simplified examples of permuted identity matrices for use as submatrices in the parity-check matrix of the type exemplified in FIG. 4.

[0012] FIG. 6 illustrates a system for performing LDPC encoding and optimization according to some embodiments.

[0013] FIG. 7 is a diagram illustrating an example of the operation of the system of

FIG. 6 according to some embodiments.

[0014] FIG. 8 is a flow diagram illustrating a process for puncturing parity-check bits according to some embodiments.

[0015] FIG. 9 is a diagram illustrating permutation operations for the systematic and parity-check bits according to some embodiments.

[0016] FIG. 10 illustrates a system for performing LDPC receive-side decoding according to some embodiments.

[0017] FIG. 11 is a diagram illustrating an example of the operation of the system of FIG. 10 according to an embodiment. [0018] FIG. 12 is a diagram illustrating operation in a layered iterative decoding scheme according to some embodiments.

DETAILED DESCRIPTION

[0019] The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. A number of examples are described in the context of 3 GPP communication systems and components thereof. It will be understood that principles of the embodiments are applicable in other types of communication systems, such as Wi-Fi or Wi-Max networks, Bluetooth or other personal-area networks, Zigbee or other home-area networks, wireless mesh networks, and the like, without limitation, unless expressly limited by a corresponding claim. Given the benefit of the present disclosure, persons skilled in the relevant technologies will be able to engineer suitable variations to implement principles of the embodiments in other types of communication systems. Various diverse embodiments may incorporate structural, logical, electrical, process, and other differences. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all presently-known, and after-arising, equivalents of those claims.

[0020] FIG. 1 is a functional diagram of a 3 GPP network in accordance with some embodiments. The network comprises a radio access network (RAN) (e.g., as depicted, the E-UTRAN or evolved universal terrestrial radio access network) 101 and the core network 120 (e.g., shown as an evolved packet core (EPC)) coupled together through an S I interface 115. For convenience and brevity sake, only a portion of the core network 120, as well as the RAN 101, is shown.

[0021] The core network 120 includes a mobility management entity (MME) 122, a serving gateway (serving GW) 124, and packet data network gateway (PDN GW) 126. The RAN 101 includes Evolved Node-B's (eNB) 104 (which may operate as base stations) for communicating with User Equipment (UE) 102. The eNBs 104 may include macro eNBs and low power (LP) eNBs. In accordance with some embodiments, the eNB 104 may transmit a downlink control message to the UE 102 to indicate an allocation of physical uplink control channel (PUCCH) channel resources. The UE 102 may receive the downlink control message from the eNB 104, and may transmit an uplink control message to the eNB 104 in at least a portion of the PUCCH channel resources. These embodiments will be described in more detail below.

[0022] The MME 122 is similar in function to the control plane of legacy Serving GPRS Support Nodes (SGSN). The MME 122 manages mobility aspects in access such as gateway selection and tracking area list management. The serving GW 124 terminates the interface toward the RAN 101, and routes data packets between the RAN 101 and the core network 120. In addition, it may be a local mobility anchor point for inter-eNB handovers and also may provide an anchor for inter-3GPP mobility. Other responsibilities may include lawful intercept, charging, and some policy enforcement. The serving GW 124 and the MME 122 may be implemented in one physical node or separate physical nodes. The PDN GW 126 terminates a SGi interface toward the packet data network (PDN). The PDN GW 126 routes data packets between the EPC 120 and the external PDN, and may be a key node for policy enforcement and charging data collection. It may also provide an anchor point for mobility with non-LTE accesses. The external PDN can be any kind of IP network, as well as an IP Multimedia Subsystem (IMS) domain. The PDN GW 126 and the serving GW 124 may be implemented in one physical node or separated physical nodes.

[0023] The eNB 104 (macro and micro) terminate the air interface protocol and may be the first point of contact for a UE 102. In some embodiments, an eNB 104 may fulfill various logical functions for the RAN 101 including but not limited to RNC (radio network controller functions) such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management. In accordance with embodiments, UE 102 may be configured to communicate with an eNB 104 over a multipath fading channel in accordance with an Orthogonal Frequency Division Multiple Access (OFDMA) communication technique. The OFDM signals may comprise a plurality of orthogonal subcarriers.

[0024] The S I interface 115 is the interface that separates the RAN 101 and the EPC 120. It is split into two parts: the Sl-U, which carries traffic data between the eNB 104 and the serving GW 124, and the SI -MME, which is a signaling interface between the eNB 104 and the MME 122. The X2 interface is the interface between eNBs 104. The X2 interface comprises two parts, the X2-C and X2-U. The X2-C is the control plane interface between the eNBs 104, while the X2-U is the user plane interface between the eNBs 104. [0025] With cellular networks, LP cells are typically used to extend coverage to indoor areas where outdoor signals do not reach well, or to add network capacity in areas with very dense phone usage, such as train stations. As used herein, the term low power (LP) eNB refers to any suitable low-power eNB for implementing a narrower cell (narrower than a macro cell) such as a femtocell, a picocell, or a micro cell. Femtocell eNBs are typically provided by a mobile network operator to its residential or enterprise customers. A femtocell is typically the size of a residential gateway or smaller and generally connects to the user's broadband line. Once plugged in, the femtocell connects to the mobile operator's mobile network and provides extra coverage in a range of typically 30 to 50 meters for residential femtocells. Thus, a LP eNB might be a femtocell eNB since it is coupled through the PDN GW 126. Similarly, a picocell is a wireless communication system typically covering a small area, such as in-building (offices, shopping malls, train stations, etc.), or more recently in-aircraft. A picocell eNB can generally connect through the X2 link to another eNB such as a macro eNB through its base station controller

(BSC) functionality. Thus, LP eNB may be implemented with a picocell eNB since it is coupled to a macro eNB via an X2 interface. Picocell eNBs or other LP eNBs may incorporate some or all functionality of a macro eNB. In some cases, this may be referred to as an access point base station or enterprise femtocell.

[0026] In some embodiments, a downlink resource grid may be used for downlink transmissions from an eNB 104 to a UE 102, while uplink transmission from the UE 102 to the eNB 104 may utilize similar techniques. The grid may be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. Such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. Each column and each row of the resource grid correspond to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one slot in a radio frame. The smallest time- frequency unit in a resource grid is denoted as a resource element (RE). Each resource grid comprises a number of resource blocks (RBs), which describe the mapping of certain physical channels to resource elements. Each resource block comprises a collection of resource elements in the frequency domain and may represent the smallest quanta of resources that currently can be allocated. There are several different physical downlink channels that are conveyed using such resource blocks. With particular relevance to this disclosure, two of these physical downlink channels are the physical downlink shared channel and the physical down link control channel.

[0027] The physical downlink shared channel (PDSCH) carries user data and higher- layer signaling to a UE 102 (FIG. 1). The physical downlink control channel (PDCCH) carries information about the transport format and resource allocations related to the PDSCH channel, among other things. It also informs the UE 102 about the transport format, resource allocation, and hybrid automatic repeat request (HARQ) information related to the uplink shared channel. Typically, downlink scheduling (e.g., assigning control and shared channel resource blocks to UE 102 within a cell) may be performed at the eNB 104 based on channel quality information fed back from the UE 102 to the eNB 104, and then the downlink resource assignment information may be sent to the UE 102 on the control channel (PDCCH) used for (assigned to) the UE 102.

[0028] The PDCCH uses CCEs (control channel elements) to convey the control information. Before being mapped to resource elements, the PDCCH complex- valued symbols are first organized into quadruplets, which are then permuted using a sub-block inter- leaver for rate matching. Each PDCCH is transmitted using one or more of these control channel elements (CCEs), where each CCE corresponds to nine sets of four physical resource elements known as resource element groups (REGs). Four QPSK symbols are mapped to each REG. The PDCCH can be transmitted using one or more CCEs, depending on the size of downlink control information (DCI) and the channel condition. There may be four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, L=l, 2, 4, or 8).

[0029] As used herein, the term circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, or other suitable hardware components that provide the described functionality. In some embodiments, the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules. In some embodiments, circuitry may include logic, at least partially operable in hardware. Embodiments described herein may be implemented into a system using any suitably configured hardware or software. [0030] FIG. 2 is a functional diagram of a User Equipment (UE) in accordance with some embodiments. The UE 200 may be suitable for use as a UE 102 as depicted in FIG. 1. In some embodiments, the UE 200 may include application circuitry 202, baseband circuitry 204, Radio Frequency (RF) circuitry 206, front-end module (FEM) circuitry 208 and multiple antennas 210A-210D, coupled together at least as shown. In some embodiments, other circuitry or arrangements may include one or more elements or components of the application circuitry 202, the baseband circuitry 204, the RF circuitry 206 or the FEM circuitry 208, and may also include other elements or components in some cases. As an example, "processing circuitry" may include one or more elements or components, some or all of which may be included in the application circuitry 202 or the baseband circuitry 204. As another example, "transceiver circuitry" may include one or more elements or components, some or all of which may be included in the RF circuitry 206 or the FEM circuitry 208. These examples are not limiting, however, as the processing circuitry or the transceiver circuitry may also include other elements or components in some cases.

[0031] The application circuitry 202 may include one or more application processors. For example, the application circuitry 202 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processors may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the system.

[0032] The baseband circuitry 204 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The baseband circuitry 204 may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry 206 and to generate baseband signals for a transmit signal path of the RF circuitry 206. Baseband processing circuity 204 may interface with the application circuitry 202 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 206. For example, in some embodiments, the baseband circuitry 204 may include a second generation (2G) baseband processor 204a, third generation (3G) baseband processor 204b, fourth generation (4G) baseband processor 204c, or other baseband processor(s) 204d for other existing generations, generations in development or to be developed in the future (e.g., fifth generation (5G), 6G, etc.). The baseband circuitry 204 (e.g., one or more of baseband processors 204a-d) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry 206. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, etc. In some embodiments, modulation/demodulation circuitry of the baseband circuitry 204 may include Fast-Fourier Transform (FFT), precoding, or constellation

mapping/demapping functionality. In some embodiments, encoding/decoding circuitry of the baseband circuitry 204 may include Low Density Parity Check (LDPC) encoder/decoder functionality, optionally along-side other techniques such as, for example, block codes, convolutional codes, turbo codes, or the like, which may be used to support legacy protocols. Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

[0033] In some embodiments, the baseband circuitry 204 may include elements of a protocol stack such as, for example, elements of an evolved universal terrestrial radio access network (EUTRAN) protocol including, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), or radio resource control (RRC) elements. A central processing unit (CPU) 204e of the baseband circuitry 204 may be configured to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP or RRC layers. In some embodiments, the baseband circuitry may include one or more audio digital signal processor(s) (DSP) 204f. The audio DSP(s) 204f may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 204 and the application circuitry 202 may be implemented together such as, for example, on a system on chip (SOC).

[0034] In some embodiments, the baseband circuitry 204 may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 204 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 204 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[0035] RF circuitry 206 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 206 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network. RF circuitry 206 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 208 and provide baseband signals to the baseband circuitry 204. RF circuitry 206 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 204 and provide RF output signals to the FEM circuitry 208 for transmission.

[0036] In some embodiments, the RF circuitry 206 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuitry 206 may include mixer circuitry 206a, amplifier circuitry 206b and filter circuitry 206c. The transmit signal path of the RF circuitry 206 may include filter circuitry 206c and mixer circuitry 206a. RF circuitry 206 may also include synthesizer circuitry 206d for synthesizing a frequency for use by the mixer circuitry 206a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 206a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 208 based on the synthesized frequency provided by synthesizer circuitry 206d. The amplifier circuitry 206b may be configured to amplify the down- converted signals and the filter circuitry 206c may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down- converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 204 for further processing. In some embodiments, the output baseband signals may be zero-frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry 206a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect. In some embodiments, the mixer circuitry 206a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 206d to generate RF output signals for the FEM circuitry 208. The baseband signals may be provided by the baseband circuitry 204 and may be filtered by filter circuitry 206c. The filter circuitry 206c may include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.

[0037] In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion or upconversion respectively. In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may be arranged for direct downconversion or direct upconversion, respectively. In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may be configured for super-heterodyne operation.

[0038] In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, the RF circuitry 206 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 204 may include a digital baseband interface to communicate with the RF circuitry 206. In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

[0039] In some embodiments, the synthesizer circuitry 206d may be a fractional-N synthesizer or a fractional N/N+l synthesizer, although the scope of the

embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 206d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider. The synthesizer circuitry 206d may be configured to synthesize an output frequency for use by the mixer circuitry 206a of the RF circuitry 206 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 206d may be a fractional N/N+l synthesizer. In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 204 or the applications processor 202 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 202.

[0040] Synthesizer circuitry 206d of the RF circuitry 206 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some embodiments, the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop. In these embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0041] In some embodiments, synthesizer circuitry 206d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be a LO frequency (fLo). In some embodiments, the RF circuitry 206 may include an IQ/polar converter.

[0042] FEM circuitry 208 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more of the antennas 210A-D, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 206 for further processing. FEM circuitry 208 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 206 for transmission by one or more of the one or more antennas 210A-D.

[0043] In some embodiments, the FEM circuitry 208 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 206). The transmit signal path of the FEM circuitry 208 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 206), and one or more filters to generate RF signals for subsequent transmission

(e.g., by one or more of the one or more antennas 210. In some embodiments, the UE 200 may include additional elements such as, for example, memory/storage, display, camera, sensor, or input/output (I/O) interface.

[0044] FIG. 3 is a functional diagram of an Evolved Node-B (eNB) in accordance with some embodiments. It should be noted that in some embodiments, the eNB 300 may be a stationary non-mobile device. The eNB 300 may be suitable for use as an eNB 104 as depicted in FIG. 1. The components of eNB 300 may be included in a single device or a plurality of devices. The eNB 300 may include physical layer circuitry 302 and a transceiver 305, one or both of which may enable transmission and reception of signals to and from the UE 200, other eNBs, other UEs or other devices using one or more antennas 301A-B. As an example, the physical layer circuitry 302 may perform various encoding and decoding functions that may include formation of baseband signals for transmission and decoding of received signals. For example, physical layer circuitry 302 may include LDPC encoder/decoder functionality, optionally along-side other techniques such as, for example, block codes, convolutional codes, turbo codes, or the like, which may be used to support legacy protocols. Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments. As another example, the transceiver 305 may perform various transmission and reception functions such as conversion of signals between a baseband range and a Radio Frequency (RF) range. Accordingly, the physical layer circuitry 302 and the transceiver 305 may be separate components or may be part of a combined component. In addition, some of the described functionality related to transmission and reception of signals may be performed by a combination that may include one, any or all of the physical layer circuitry 302, the transceiver 305, and other components or layers. The eNB 300 may also include medium access control layer (MAC) circuitry 304 for controlling access to the wireless medium. The eNB 300 may also include processing circuitry 306 and memory 308 arranged to perform the operations described herein. The eNB 300 may also include one or more interfaces 310, which may enable communication with other components, including other eNB 104 (FIG. 1), components in the EPC 120 (FIG. 1) or other network components. In addition, the interfaces 310 may enable communication with other components that may not be shown in FIG. 1 , including components external to the network. The interfaces 310 may be wired or wireless or a combination thereof.

[0045] The antennas 210A-D, 301A-B may comprise one or more directional or omnidirectional antennas, including, for example, dipole antennas, monopole antennas, patch antennas, loop antennas, microstrip antennas or other types of antennas suitable for transmission of RF signals. In some multiple- input multiple- output (MIMO) embodiments, the antennas 210A-D, 301 A-B may be effectively separated to take advantage of spatial diversity and the different channel

characteristics that may result.

[0046] In some embodiments, the UE 200 or the eNB 300 may be a mobile device and may be a portable wireless communication device, such as a personal digital assistant (PDA), a laptop or portable computer with wireless communication capability, a web tablet, a wireless telephone, a smartphone, a wireless headset, a pager, an instant messaging device, a digital camera, an access point, a television, a wearable device such as a medical device (e.g., a heart rate monitor, a blood pressure monitor, etc.), or other device that may receive or transmit information wirelessly. In some embodiments, the UE 200 or eNB 300 may be configured to operate in accordance with 3 GPP standards, although the scope of the embodiments is not limited in this respect. Mobile devices or other devices in some embodiments may be configured to operate according to other protocols or standards, including IEEE 802.11 or other IEEE standards. In some embodiments, the UE 200, eNB 300 or other device may include one or more of a keyboard, a display, a non- volatile memory port, multiple antennas, a graphics processor, an application processor, speakers, and other mobile device elements. The display may be an LCD screen including a touch screen.

[0047] Although the UE 200 and the eNB 300 are each illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including digital signal processors (DSPs), or other hardware elements. For example, some elements may comprise one or more microprocessors, DSPs, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), radio-frequency integrated circuits (RFICs) and combinations of various hardware and logic circuitry for performing at least the functions described herein. In some embodiments, the functional elements may refer to one or more processes operating on one or more processing elements.

[0048] Embodiments may be implemented in one or a combination of hardware, firmware and software. Embodiments may also be implemented as instructions stored on a computer-readable storage device, which may be read and executed by at least one processor to perform the operations described herein. A computer-readable storage device may include any no n- transitory mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a computer-readable storage device may include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash-memory devices, and other storage devices and media. Some embodiments may include one or more processors and may be configured with instructions stored on a computer-readable storage device.

[0049] It should be noted that in some embodiments, an apparatus used by the UE 200 or eNB 300 may include various components of the UE 200 or the eNB 300 as shown in FIGs. 2-3. Accordingly, techniques and operations described herein that refer to the UE 200 (or 102) may be applicable to an apparatus for a UE. In addition, techniques and operations described herein that refer to the eNB 300 (or 104) may be applicable to an apparatus for an eNB.

[0050] Some aspects of the embodiments are directed to an efficient coding scheme for forward error correction (FEC). LTE supports adaptive modulation and coding schemes with a fine-granularity supported set of resource allocations, modulation and coding schemes (MCS), packet sizes (or transport block (TB) sizes), and rate- compatible channel coding based on turbo code with circular buffer rate-matching for incremental-redundancy hybrid automatic repeat request (IR-HARQ) support. Turbo codes and LDPC codes are two kinds of capacity-achieving codes. In some embodiments, the supported set of spectral efficiencies are in the range of 0.1 bps/Hz up to 7.6 bps/Hz (for 256-QAM) with MCS levels defined corresponding to 1 dB step size roughly. This may call for rate-compatible channel coding to encode a packet (or TB) at any arbitrary coding rate according to the selected MCS level, and defining multiple redundancy versions to support HARQ operation. [0051] As an example of a current application of LDPC, the 802.11n/llac LDPC code design is based on a limited set of code rates and block sizes as shown in Table 1 below. Information block size is tabulated as a function of code word (CW) length and code rate.

Table 1

[0052] To encode and transmit a packet on the available channel resources, the standard also specifies Physical Layer Convergence Protocol (PLCP) Protocol Data Unit (PPDU) encoding rules, including mechanisms for shortening and puncturing. In a shortening-based method, a packet of small size is zero-padded to desired information block size and encoded with a parity-check matrix, and the zero-padding is removed after encoding, to achieve an effective lower coding rate. In a puncturing- based method, a packet is encoded with a parity-check matrix, and a portion of the parity bits after encoding are punctured, e.g., removed (with the relative placement of other bits kept intact) to increase the effective coding rate. Rate matching is achieved through either shortening a higher rate code or puncturing a lower rate code, for example, by selecting from among the 4 specified rate matrixes, among others.

[0053] Both turbo code and LDPC code are decoded using an iterative decoding technique. Notably, LDPC can provide improvement over turbo code in terms of implementation complexity and performance and, at present, LDPC is being considered as a potential channel coding candidate in future 3 GPP standardization efforts, commonly referred to as 5 G standard development.

[0054] Typically, to support adaptive MCS, puncturing and zero padding operations are used in conjunction with LDPC encoding. This allows the design to support parity-check matrices for only a given set of code rates and LDPC information block size. Other coding rates and block sizes can be supported using puncturing, repetition or zero padding operations. The limited set of parity-check matrices may provide an advantage in reduced implementation complexity while also allowing sufficient flexibility to adapt the scheme (similar to LTE turbo code). Since puncturing (especially of parity-check bits) in LDPC is known to achieve higher coding rates, any adverse impact on FEC performance due to puncturing should be taken into account.

[0055] Embodiments described herein recognize that selection of good puncturing patterns can provide improved performance at negligible (or even zero) increase in implementation complexity. Even in HARQ-based operations, selecting good puncturing patterns can increase the success rate of the first transmission, and in turn, lead to lower retransmission occurrences and increase the throughput.

[0056] One aspect of the embodiments is directed to a solution for preferentially selecting puncturing patterns for LDPC parity-check coding. Technical effects provided by some embodiments include improved communications data rate for a given FEC performance level and, likewise, improved FEC performance for a given data communications rate. Additionally, some embodiments may efficiently support HARQ-based operation with LDPC.

[0057] According to one type of embodiment, certain parity-check bits of a LDPC parity-check matrix corresponding to larger column weights are preferentially punctured over parity-check bits corresponding to lower column weights. In a related aspect, a decoder utilizing a layered decoding scheme is provided for fast and computationally-efficient decoding of LDPC codewords.

[0058] In an embodiment, an LDPC coding scheme utilized for the transmission of digital data is a structured LDPC code based on shifted identity matrices. An LDPC code with codeword length n = z-nb and information block k = z-kb, and a shift size or subblock size z, has a code rate r = k/n = kb/nb. An LDPC encoder encodes an information block i = (io, ii,i₂...ik-i) into a codeword c, of size n, where c = (co, ci,....Ck-i,Ck. . ..Cn-i). In systematic encoding, the first k bits of the codeword are typically the same as information bits i.e. Cj = ij, for j = 0 to k-1 or c = (io, ii,....ik- ι,ρο. . ..pn-k-i). The codeword c satisfies the parity-check equations H c^T = 0, where H is an n-k x n parity-check matrix. In this arrangement, typically, the first k columns (or kb) of the parity-check matrix may be referred to as systematic columns, and the remaining n-k columns (or nb-kb) may be referred to as parity columns. For the parity-check matrix, each column has a column weight, which denotes the number of 1 ' s in the column, and each row has a row weight, which denotes the numbers of Γ s in the row.

[0059] FIG. 4 is a diagram of an example parity-check matrix according to an example embodiment. As depicted, parity-check matrix H is composed of systematic columns 402, and parity columns 404. Each element of parity-check matrix H represents a square submatrix Pi having a size z x z (in the example depicted, z=27). These submatrices may be cyclic-permutations of the identity matrix (i.e., shifted identity matrix) where the numeric value of the element represents the amount of permutation (with 0 being a non-shifted identity matrix). The elements populated with the value "-" represents a null matrix (i.e. all zeros).

[0060] FIGs. 5A-5C illustrate simplified examples of permuted identity matrices for use as submatrices in the parity-check matrix of the type exemplified in FIG. 4. As depicted, permuted identity matrix Pi is shown for the case where z=5 for ease of illustration. The cyclic permutation matrix Pi is obtained from the z x z Identity matrix by cyclically shifting the columns to the right by i elements. FIG. 5A illustrates a non-shifted identity matrix corresponding to Po. FIG. 5B illustrates a cyclical shift of 2 corresponding to P2. FIG. 5C illustrates a cyclical shift of 4 corresponding to P₄.

[0061] In an embodiment, a code rate of 8/9 is achieved for various codeword sizes defined for different shift sizes z. In various examples, the supported shift sizes z may be 12, 24,36,48,60,72,84 and 96. Assuming a matrix prototype of dimensions 4 x 36 (i.e. ¾ = 36, and kb= 32), this corresponds respectively to codeword block sizes of z x 36 = 432, 864, 1296, 1728, 2160, 2592, 3024, and 3456.

[0062] FIG. 6 illustrates a system for performing LDPC encoding and optimization according to some embodiments. As depicted, the system may be implemented using baseband processor 204 of a UE or physical layer circuitry 302 of an eNB. The system includes LDPC encoder 602, and puncturer 604. According to various embodiments, LDPC encoder 602 and puncturer 604 may be implemented using hardware circuitry, or as a combination of hardware circuitry and software/firmware instructions stored on a tangible, non-transitory, computer-readable medium. In the latter case, the instructions, when executed on a processor circuit, cause the processor circuit to carry out data transformations as will be described in greater detail below.

[0063] FIG. 7 is a diagram illustrating an example of the operation of the system of FIG. 6 according to some embodiments. As depicted, the input to LDPC encoder 602 is information block S 702 (which contains information bits to be transmitted and, optionally, additional CRC bits). LDPC encoder 602 also reads parity-check matrix H 704. LDPC encoder 602 is configured to produce LDPC code words at a set code rate (e.g. r = k n representing the ratio of information block size to total block size). LDPC encoder 602 produces codeword 706, which includes systematic portion S indicated at 706A, and parity-check portion P indicated at 706B.

[0064] Codeword 706 is input to puncturer 604, which operates to remove (i.e., puncture) part(s) of the parity-check portion 706B to increase the code rate r. The output of puncturer 604 is punctured codeword 708, which includes systematic portion S 706A, along with a non-punctured part of parity-check portion 708B. Parity-check portion 708B has voids X indicated at 708C in selected bit positions. Although data bits are omitted in punctured parity-check portion 708B, their bit positions are noted in some fashion such that the omitted parity-check portion of voids X 708C may be reconstructed at the receiver.

[0065] In an embodiment, puncturer 604 preferentially selects puncturing patterns based on the structure of parity-check matrix H, and on the decoding algorithm to be used at the receiver (e.g. scheduling in layered-belief propagation). In general, when a particular parity-check bit is punctured the decoder at the receiver may assume that the corresponding bit is erased, and it may attempt to decode the information block by making use of the parity-check nodes corresponding to each erased bit to help recover the erased bit. The parity-check nodes may be represented as rows of the H matrix.

[0066] According to a related embodiment, preferential selection of the puncturing patterns selects bits for puncturing that correspond to those parity-check bits that participate in a greater number of parity-check equations, compared to other parity- check bits. In this embodiment, parity-check bits corresponding to parity-check columns of relatively greater weight tend to be preferentially selected for puncturing and, consequently, have a lower priority in being selected for transmission than parity-check bits corresponding to parity-check columns of relatively lower weight. In the present context, the columns of relatively greater weight have parity-check bits associated with a relatively greater quantity of parity-check nodes, and the columns of relatively lower weight have parity-check bits associated with a relatively smaller quantity of parity-check nodes. Notably, the columns of relatively greater weight, and the columns of relatively lower weight, have weights that are greater, and lower, respectively, relative to each other. Thus, the terms greater and lower are comparative, rather than absolute, terms.

[0067] Generally, LDPC decoders are based on a layered belief propagation algorithm, where one or more rows of the structured parity-check matrix are simultaneously processed. In a related embodiment, for receiving LDPC code that are punctured, the ordering of the rows in the decoder can take into account the puncturing scheme. For instance, the ordering of the rows may be such that punctured bits are recovered as early as possible in the decoding process, which tends to assist with recovery of the punctured bit values.

[0068] FIG. 8 is a flow diagram illustrating a process for puncturing parity-check bits according to some embodiments. The process may be carried out by puncturer 604, for example. At 802, a determination is made as to the quantity of bits to be punctured. This determination may be a function of the code rate for which the encoder 602 is configured, and the desired code rate. Puncturing reduces the overall size of the LDPC code block such that the effective total length to be transmitted over the communication channel is reduced. At 804, puncturer 604 initializes a null- element list having a length equal to the determined number of parity-check bits to be punctured. The following operations 806-812 populate the list with the punctured bits.

[0069] To illustrate a puncturing procedure according to some embodiments, the term effective column weight of a parity-check bit is defined as the number of parity- check nodes to which the parity-check bit connects that do not contain other as-yet unrecovered punctured bits. At 806, puncturer 604 searches the parity-check bits with highest effective column weight which, if punctured, may be recovered immediately at the current iteration without depending on other punctured bits that are not yet recovered. As discussed above, in an embodiment, parity-check bits that have greater effective column weight, and therefore participate in a greater quantity of parity-check equations, are preferentially selected for puncturing. Already- recovered punctured bits from previous iterations are considered as non-punctured bits for the current iteration. At 808, all found bits as a result of the search operation at 806 are marked. At 810, the list is populated with the found bits to replace the initial null values. In one embodiment, the list is ordered such that the parity-check bit with the largest effective column weight is listed first, followed by the bit with second largest effective column weight, and so on. If two or more parity-check bits are tied, their ordering is chosen arbitrarily.

[0070] Decision 812 determines if the list is full and, if it is not, the process loops back to operation 806 to continue the search for suitable parity-check bits to be punctured. Otherwise, if the list of bits is completed, the process advances to 814, where puncturer 604 applies column permutations to the systemic and parity-check bits to prioritize the non-punctured parity-check bits. At 816, the systematic bits and parity-check bits are concatenated to form a circular buffer to be used for transmission of the block. At 818, bits are read from the circular buffer and passed to the transceiver for transmission over the wireless medium.

[0071] In a related embodiment, incremental redundancy hybrid ARQ operation (IR-HARQ) is supported with the use of the circular buffer and the column permutations. Permutation πΐ is applied to parity-check bits to rearrange them in an order such that the bits that need to be punctured are placed at the end. Permutation πθ is applied to the systematic bits.

[0072] FIG. 9 is a diagram illustrating permutation operations for the systematic and parity-check bits according to some embodiments. For ease of illustration, only two redundancy version blocks, first transmission 902, and second transmission 904, are shown. S and P indicated at 906 and 908 respectively denote the systematic bits and parity-check bits. Permutation operations πθ 910 and πΐ 912 are applied to S and P as illustrated to produce permuted systematic bits S' at 914 and permuted parity- check bits P' at 916. The concatenation of S' 914 and P' 916 is a data structure used as the circular buffer 918 from which redundancy versions are defined.

[0073] For each transmission, the bits selected for transmission may be read out starting from the starting point in the circular buffer, and reading of bits continues sequentially until the required number of bit are read out. If the end of circular buffer is reached, the reading-out resumes from the beginning of the circular buffer. In the example depicted, first transmission 902 from circular buffer 918 begins at bit position RV0. Second transmission 904 begins at bit position RV1. Here, the abbreviation RV denotes a redundancy version that can be used to support HARQ operation. For Chase combining, only one RV may be adequate. For IR based HARQ, multiple RVs may be defined.

[0074] FIG. 10 illustrates a system for performing LDPC receive-side decoding according to some embodiments. As depicted, the system may be implemented using baseband processor 204 of a UE or physical layer circuitry 302 of an eNB. The system includes HARQ memory 1002, soft-combining unit 1004, H-matrix determining unit 1006, inverse permutation computer 1008, and decoder 1010. According to various embodiments, the components of the system may be implemented using hardware circuitry, or as a combination of hardware circuitry and software/firmware instructions stored on a tangible, non-transitory, computer- readable medium. In the latter case, the instructions, when executed on a processor circuit, cause the processor circuit to carry out data transformations as will be described in greater detail below.

[0075] The input 1012 to the system includes the received bits (in the form of log- likelihood ratios (LLRs)), that are soft-combined by soft-combining unit 1004 with any previous LLRs stored in HARQ memory 1002. Inverse permutation computer 1008 applies inverse permutations πθ^"1 and πΓ¹ to prepare the result for the LDPC decoding. H matrix determination unit operates by taking into account information about the received block and its LLRs available at the decoder (e.g., channel LLRs, and LLRs stored in HARQ memory) to determine the suitable parity-check matrix H for decoding by decoder 1010 to produce information output 1014.

[0076] FIG. 11 is a diagram illustrating an example of the operation of the system of FIG. 10 according to an embodiment. First transmission 902 and second transmission 904 are received as LLRs, and combined by soft-combining unit 1004. The result is stored in a circular buffer 1118 implemented in HARQ memory 1002. The received data at this point are the permuted bits 914 and 916. Inverse permutation operations are performed at 1102 and 1104 for the systematic bits and the parity-check bits, respectively, to produce the reordered LLR values of codeword composed of systematic bits 1106 and recovered parity-check bits 1108. The determined H matrix is then used to decode the codeword.

[0077] FIG. 12 is a diagram illustrating operation in a layered iterative decoding scheme according to some embodiments. As depicted, a received LDPC codeword includes LLR values for information bits S 1202, parity-check bits P 1204, and punctured parity-check bit positions 1206. The layered decoding ordering may be performed in LDPC decoder 1010 to further improve the performance. The punctured parity-check bit ordering in the list is followed to perform the layered decoding. A row-wise permutation matrix π2 1208 may reorder the check node sequence such that all check nodes connected to the first punctured bit in the list are processed first (e.g., with higher priority), followed by check nodes connected to the second punctured bit, and so on. This ordering can facilitate the recovery of the punctured bits to follow the puncturing order to a certain extent. This operation is advantageous since recovery of punctured bits at the earlier iterations may be achieved with relatively higher confidence. Subsequent punctured parity-check bit recovery is assisted by the recovery of preceding check bits. As a result, faster and more computationally-efficient LDPC decoding convergence may be achieved.

[0078] As an example embodiment, in WiFi-like matrices, the parity-check columns can have a first weight (weight-3) or a second weight (weight-2). The permutation πΐ is used for permuting the parity-check portion such that after permutation, the punctured parity-check bits are placed at the end. The permutation πθ used for permuting the systematic bits can be an identity (i.e., no change). In a related example, for additional diversity, permutation πθ used for permuting the systematic bits may be another permutation.

[0079] As another example, the parity-check columns can have a first weight (weight-3) or a second weight (weight-2) or in general, columns with multiple weights. For instance, the permutation πΐ used for permuting the parity-check portion is such that, after permutation, punctured parity-check bits occur later in the circular buffer relative to non-punctured bits. The permutation πθ used for permuting the systematic bits can be identity. For additional diversity, permutation πθ used for permuting the systematic bits may be another permutation.

[0080] As an illustrative example, with reference to FIG. 4, a puncturing pattern selection and layered decoding process will be described. In this example, 802.11η- style LDPC parity-check matrix H has the coding rate = 5/6, block length n = 648 bits, and subblock size z = 27 bits. The parity-check portion 404 is the last four columns of H, containing 4x27 = 108 single columns and 108 rows.

[0081] To increase the coding rate from 5/6 to 0.9, given n = 648 with the information bits length k = 540, 48 bits need to be punctured. First, a list containing 48 NULL elements is created. Next, it is noted that the first z columns have column weight of 3. If all of 27 corresponding parity-check bits are being punctured, they may be recovered without depending on the rest of the 48-27 = 21 punctured bit locations. Check nodes connected to these 27 punctured bits and without connections to the remaining 21 punctured bits are identifiable. Adding columns 1 to 27 as the puncturing ordering in the list, the list now contains { 1, 2, ... 27, NULL, ... } .

[0082] Since the first 27 bits may be recovered first, the remaining 21 bits being punctured can be selected randomly from among all the other columns since all of them have column weight of two, which is the next- largest weight after removal of columns having a weight of three. Now the list is fully populated, and the selection of the punctured bits is complete with the list comprising { 1, 2, ..., 27, 28, ..., 48 } [0083] Next, the column permutation πΐ is applied, which permutes the punctured bits to the end of parity-check block and moves all non-punctured bits to the beginning of the parity-check block. After permutation, the parity-check bit sequence has index order of {49, ..., 108, 1, ..., 48 }. Parity-check bits 49 to 108 are transmitted with information bits as part of a shortened codeword due to puncturing.

[0084] At the LDPC decoder, using a non - layered decoding algorithm, for example, a standard belief propagation technique may be used to decode LDPC codeword.

[0085] In an embodiment where layered decoding algorithms are used, the order of decoding layer may be determined as follows. In order to recover the punctured bits sequentially in the list, at the LDPC decoder side, after inverting permutation πΐ to recover the original codeword sequence including adding back the punctured bits, in order to decode the first 27 punctured bits, the layered decoding may start with check nodes in either ordering { 82, 83, ...,108, 55, 56, 81, 1, 2, ..., 27, 28, 29, 54} or {55, 56, ..., 81, 82, 83, ...,108, 1, 2, ..., 27, 28, 29, 54}. This layered decoding ordering is fulfilled by permutation π2. One layer may include a single check node, or multiple of check nodes. In the 802.1 In case, due to there not being two or more check nodes within a z x z submatrix connected to the same LDPC coded bit, all check nodes within a submatrix may be updated simultaneously. In this case, one layer includes z check nodes within a submatrix.

[0086] Additional notes and examples:

[0087] Example 1 is apparatus of a communication device configured to encode a message for transmission, the apparatus comprising: memory; and processing circuitry to control the apparatus to: encode a set of information bits to be transmitted according to a parity-check block to produce a first codeword, the first codeword representing a set of parity-check nodes based on the set of information bits and on a set of parity-check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes; select, from among the set of parity-check bits, selected parity-check bits to be deprioritized from the first codeword based on selection criteria that deprioritizes those parity-check bits that are associated with the relatively greater quantity of the parity-check nodes; and produce an output data set for transmission based on the first codeword, wherein the selected parity-check bits are deprioritized. [0088] In Example 2, the subject matter of Example 1 optionally includes wherein the parity-check block is represented in the memory as a parity-check matrix data structure arranged as a set of rows and columns.

[0089] In Example 3, the subject matter of Example 2 optionally includes wherein each column of the parity-check matrix has an effective column weight defined as a number of parity-check nodes to which a corresponding parity-check bit connects that do not contain other as-yet unrecovered deprioritized bits.

[0090] In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein the first codeword is represented in the memory as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritizes those parity-check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity-check bit columns.

[0091] In Example 5, the subject matter of Example 4 optionally includes wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements.

[0092] In Example 6, the subject matter of any one or more of Examples 4-5 optionally include wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

[0093] In Example 7, the subject matter of any one or more of Examples 1-6 optionally include wherein the selected parity-check bits that are deprioritized are omitted from the output data set for transmission.

[0094] In Example 8, the subject matter of any one or more of Examples 1-7 optionally include wherein the selected parity-check bits that are deprioritized are permuted to a least-significant position within the output data set for transmission.

[0095] In Example 9, the subject matter of any one or more of Examples 1-8 optionally include wherein the first codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.

[0096] In Example 10, the subject matter of any one or more of Examples 1-9 optionally include wherein the first codeword includes a first portion containing the information bits, and a second portion containing the parity-check bits, and wherein the processing circuitry is to further control the apparatus to: compute a first permutation of information bits to produce a first permutation result, and compute a second permutation of the set of parity-check bits to obtain a second permutation result; and concatenate the first permutation result with the second permutation result to produce a circular buffer from which the output data set is produced.

[0097] In Example 11, the subject matter of Example 10 optionally includes wherein the second permutation result includes a bit-ordering having a start and an end, wherein the selected parity-check bits that are deprioritized are positioned at the end.

[0098] In Example 12, the subject matter of any one or more of Examples 10-11 optionally include wherein the output data set is produced based on a plurality of read iterations through the circular buffer, wherein different read iterations have different starting points within the circular buffer based on redundancy versions.

[0099] In Example 13, the subject matter of any one or more of Examples 1-12 optionally include wherein the apparatus includes a baseband processor.

[0100] In Example 14, the subject matter of any one or more of Examples 1-13 optionally include wherein the apparatus includes a transceiver circuit coupled to an antenna.

[0101] In Example 15, the subject matter of any one or more of Examples 1-14 optionally include wherein the apparatus includes an e-Node B device.

[0102] In Example 16, the subject matter of any one or more of Examples 1-15 optionally include wherein the apparatus includes a user equipment (UE) device.

[0103] Example 17 is apparatus of a communication device configured to decode an encoded message, the apparatus comprising: memory; and processing circuitry to control the apparatus to: access received messaging that includes a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity-check bits; compute a first reverse-permutation of the first permuted portion, and a second reverse-permutation of the second permuted portion, to produce a codeword containing an unpermuted first portion representing the information bits and an unpermuted second portion representing the parity-check bits; and decode the codeword using a low-density parity-check matrix, the codeword having been previously encoded as a set of parity-check nodes based on the set of information bits and on a set of parity-check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity- check bits associated with a relatively smaller quantity of parity-check nodes, certain parity-check bits having been deprioritized from the codeword based on selection criteria that deprioritized those parity-check bits associated with the relatively greater quantity of the parity-check nodes.

[0104] In Example 18, the subject matter of Example 17 optionally includes wherein the received messaging comprises a set of log- likelihood ratios.

[0105] In Example 19, the subject matter of any one or more of Examples 17-18 optionally include wherein the received messaging includes a first transmission and a second transmission.

[0106] In Example 20, the subject matter of any one or more of Examples 17-19 optionally include wherein the received messaging comprises circular-buffered data.

[0107] In Example 21, the subject matter of any one or more of Examples 17-20 optionally include wherein the codeword is represented in the memory as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritized those parity-check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity- check bit columns.

[0108] In Example 22, the subject matter of Example 21 optionally includes wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements.

[0109] In Example 23, the subject matter of any one or more of Examples 21-22 optionally include wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

[0110] In Example 24, the subject matter of any one or more of Examples 17-23 optionally include wherein the parity-check bits that were deprioritized were omitted from the messaging.

[0111] In Example 25, the subject matter of any one or more of Examples 17-24 optionally include wherein the parity-check bits that were deprioritized were permuted to a least-significant position within the messaging.

[0112] In Example 26, the subject matter of any one or more of Examples 17-25 optionally include wherein the codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.

[0113] In Example 27, the subject matter of any one or more of Examples 17-26 optionally include wherein the apparatus includes a baseband processor. [0114] In Example 28, the subject matter of any one or more of Examples 17-27 optionally include wherein the apparatus includes a transceiver circuit coupled to an antenna.

[0115] In Example 29, the subject matter of any one or more of Examples 17-28 optionally include wherein the apparatus includes an e-Node B device.

[0116] In Example 30, the subject matter of any one or more of Examples 17-29 optionally include wherein the apparatus includes a user equipment (UE) device.

[0117] Example 31 is a computer-readable medium comprising instructions that, when executed on a processing apparatus, cause the apparatus to: encode a set of information bits to be transmitted according to a parity-check block to produce a first codeword, the first codeword representing a set of parity-check nodes based on the set of information bits and on a set of parity-check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes; select parity- check bits to be deprioritized from the first codeword based on selection criteria that deprioritizes those parity-check bits that are associated with the relatively greater quantity of the parity-check nodes; and produce an output data set for transmission based on the first codeword, wherein the selected parity-check bits are deprioritized.

[0118] In Example 32, the subject matter of Example 31 optionally includes wherein the parity-check block is represented as a parity-check matrix data structure arranged as a set of rows and columns.

[0119] In Example 33, the subject matter of Example 32 optionally includes wherein each column of the parity-check matrix has an effective column weight defined as a number of parity-check nodes to which a corresponding parity-check bit connects that do not contain other as-yet unrecovered deprioritized bits.

[0120] In Example 34, the subject matter of any one or more of Examples 31-33 optionally include wherein the first codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritizes those parity-check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity- check bit columns.

[0121] In Example 35, the subject matter of Example 34 optionally includes wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements. [0122] In Example 36, the subject matter of any one or more of Examples 34-35 optionally include wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

[0123] In Example 37, the subject matter of any one or more of Examples 31-36 optionally include wherein the selected parity-check bits that are deprioritized are omitted from the output data set for transmission.

[0124] In Example 38, the subject matter of any one or more of Examples 31-37 optionally include wherein the selected parity-check bits that are deprioritized are permuted to a least-significant position within the output data set for transmission.

[0125] In Example 39, the subject matter of any one or more of Examples 31-38 optionally include wherein the first codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.

[0126] In Example 40, the subject matter of any one or more of Examples 31-39 optionally include wherein the first codeword includes a first portion containing the information bits, and a second portion containing the parity-check bits, and wherein the instructions are to further control the apparatus to: compute a first permutation of information bits to produce a first permutation result, and compute a second permutation of the set of parity-check bits to obtain a second permutation result; and concatenate the first permutation result with the second permutation result to produce a circular buffer from which the output data set is produced.

[0127] In Example 41, the subject matter of Example 40 optionally includes wherein the second permutation result includes a bit-ordering having a start and an end, wherein the selected parity-check bits that are deprioritized are positioned at the end.

[0128] In Example 42, the subject matter of any one or more of Examples 40-41 optionally include wherein the output data set is produced based on a plurality of read iterations through the circular buffer, wherein different read iterations have different starting points within the circular buffer based on redundancy versions.

[0129] Example 43 is a computer-readable medium comprising instructions that, when executed on a processing apparatus, cause the apparatus to: access received messaging that includes a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity-check bits; compute a first reverse-permutation of the first permuted portion, and a second reverse- permutation of the second permuted portion, to produce a codeword containing an unpermuted first portion representing the information bits and an unpermuted second portion representing the parity-check bits; and decode the codeword using a low- density parity-check matrix, the codeword having been previously encoded as a set of parity-check nodes based on the set of information bits and on a set of parity- check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes, certain parity-check bits having been deprioritized from the codeword based on selection criteria that deprioritized those parity-check bits associated with the relatively greater quantity of the parity-check nodes.

[0130] In Example 44, the subject matter of Example 43 optionally includes wherein the received messaging comprises a set of log- likelihood ratios.

[0131] In Example 45, the subject matter of any one or more of Examples 43-44 optionally include wherein the received messaging includes a first transmission and a second transmission.

[0132] In Example 46, the subject matter of any one or more of Examples 43-45 optionally include wherein the received messaging comprises circular-buffered data.

[0133] In Example 47, the subject matter of any one or more of Examples 43-46 optionally include wherein the codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritized those parity-check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity-check bit columns.

[0134] In Example 48, the subject matter of Example 47 optionally includes wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements.

[0135] In Example 49, the subject matter of any one or more of Examples 47-48 optionally include wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

[0136] In Example 50, the subject matter of any one or more of Examples 43-49 optionally include wherein the parity-check bits that were deprioritized were omitted from the messaging. [0137] In Example 51 , the subject matter of any one or more of Examples 43-50 optionally include wherein the parity-check bits that were deprioritized were permuted to a least-significant position within the messaging.

[0138] In Example 52, the subject matter of any one or more of Examples 43-51 optionally include wherein the codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.

[0139] Example 53 is a system for encoding a message for transmission, the system comprising: means for encoding a set of information bits to be transmitted according to a parity-check block to produce a first codeword, the first codeword representing a set of parity-check nodes based on the set of information bits and on a set of parity- check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes; means for selecting parity-check bits to be deprioritized from the first codeword based on selection criteria that deprioritizes those parity-check bits that are associated with the relatively greater quantity of the parity-check nodes; and means for producing an output data set for transmission based on the first codeword, wherein the selected parity-check bits are deprioritized.

[0140] In Example 54, the subject matter of Example 53 optionally includes wherein the parity-check block is represented as a parity-check matrix data structure arranged as a set of rows and columns.

[0141] In Example 55, the subject matter of Example 54 optionally includes wherein each column of the parity-check matrix has an effective column weight defined as a number of parity-check nodes to which a corresponding parity-check bit connects that do not contain other as-yet unrecovered deprioritized bits.

[0142] In Example 56, the subject matter of any one or more of Examples 53-55 optionally include wherein the first codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritizes those parity-check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity- check bit columns.

[0143] In Example 57, the subject matter of Example 56 optionally includes wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements. [0144] In Example 58, the subject matter of any one or more of Examples 56-57 optionally include wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

[0145] In Example 59, the subject matter of any one or more of Examples 53-58 optionally include wherein the selected parity-check bits that are deprioritized are omitted from the output data set for transmission.

[0146] In Example 60, the subject matter of any one or more of Examples 53-59 optionally include wherein the selected parity-check bits that are deprioritized are permuted to a least-significant position within the output data set for transmission.

[0147] In Example 61, the subject matter of any one or more of Examples 53-60 optionally include wherein the first codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.

[0148] In Example 62, the subject matter of any one or more of Examples 53-61 optionally include wherein the first codeword includes a first portion containing the information bits, and a second portion containing the parity-check bits, and wherein the means for encoding include: means for computing a first permutation of information bits to produce a first permutation result, means for computing a second permutation of the set of parity-check bits to obtain a second permutation result; and means for concatenating the first permutation result with the second permutation result to produce a circular buffer from which the output data set is produced.

[0149] In Example 63, the subject matter of Example 62 optionally includes wherein the second permutation result includes a bit-ordering having a start and an end, wherein the selected parity-check bits that are deprioritized are positioned at the end.

[0150] In Example 64, the subject matter of any one or more of Examples 62-63 optionally include wherein the output data set is produced based on a plurality of read iterations through the circular buffer, wherein different read iterations have different starting points within the circular buffer based on redundancy versions.

[0151] In Example 65, the subject matter of any one or more of Examples 53-64 optionally include wherein the system includes a baseband processor.

[0152] In Example 66, the subject matter of any one or more of Examples 53-65 optionally include wherein the system includes a transceiver circuit coupled to an antenna. [0153] In Example 67, the subject matter of any one or more of Examples 53-66 optionally include wherein the system includes an e-Node B device.

[0154] In Example 68, the subject matter of any one or more of Examples 53-67 optionally include wherein the system includes a user equipment (UE) device.

[0155] Example 69 is system of a communication device configured for receiving and decoding an encoded message, the system comprising: means for accessing received messaging that includes a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity-check bits; means for computing a first reverse-permutation of the first permuted portion, and a second reverse-permutation of the second permuted portion, to produce a codeword containing an unpermuted first portion representing the information bits and an unpermuted second portion representing the parity-check bits; and means for decoding the codeword using a low-density parity-check matrix, the codeword having been previously encoded as a set of parity-check nodes based on the set of information bits and on a set of parity-check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes, certain parity-check bits having been deprioritized from the codeword based on selection criteria that deprioritized those parity-check bits associated with the relatively greater quantity of the parity-check nodes.

[0156] In Example 70, the subject matter of Example 69 optionally includes wherein the received messaging comprises a set of log- likelihood ratios.

[0157] In Example 71, the subject matter of any one or more of Examples 69-70 optionally include wherein the received messaging includes a first transmission and a second transmission.

[0158] In Example 72, the subject matter of any one or more of Examples 69-71 optionally include wherein the received messaging comprises circular-buffered data.

[0159] In Example 73, the subject matter of any one or more of Examples 69-72 optionally include wherein the codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritized those parity-check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity-check bit columns. [0160] In Example 74, the subject matter of Example 73 optionally includes wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements.

[0161] In Example 75, the subject matter of any one or more of Examples 73-74 optionally include wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

[0162] In Example 76, the subject matter of any one or more of Examples 69-75 optionally include wherein the parity-check bits that were deprioritized were omitted from the messaging.

[0163] In Example 77, the subject matter of any one or more of Examples 69-76 optionally include wherein the parity-check bits that were deprioritized were permuted to a least-significant position within the messaging.

[0164] In Example 78, the subject matter of any one or more of Examples 69-77 optionally include wherein the codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.

[0165] In Example 79, the subject matter of any one or more of Examples 69-78 optionally include wherein the system includes a baseband processor.

[0166] In Example 80, the subject matter of any one or more of Examples 69-79 optionally include wherein the system includes a transceiver circuit coupled to an antenna.

[0167] In Example 81, the subject matter of any one or more of Examples 69-80 optionally include wherein the system includes an e-Node B device.

[0168] In Example 82, the subject matter of any one or more of Examples 69-81 optionally include wherein the system includes a user equipment (UE) device.

[0169] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments that may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, also contemplated are examples that include the elements shown or described. Moreover, also contemplated are examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0170] Publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) are supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0171] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to suggest a numerical order for their objects.

[0172] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with others. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. However, the claims may not set forth every feature disclosed herein as embodiments may feature a subset of said features. Further, embodiments may include fewer features than those disclosed in a particular example. Thus, the following claims are hereby incorporated into the Detailed Description, with a claim standing on its own as a separate embodiment. The scope of the embodiments disclosed herein is to be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. Apparatus of a communication device configured to encode a message for transmission, the apparatus comprising:

memory; and

processing circuitry to control the apparatus to:

encode a set of information bits to be transmitted according to a parity-check block to produce a first codeword, the first codeword representing a set of parity-check nodes based on the set of information bits and on a set of parity-check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes;

select, from among the set of parity-check bits, selected parity-check bits to be deprioritized from the first codeword based on selection criteria that deprioritizes those parity-check bits that are associated with the relatively greater quantity of the parity-check nodes; and

produce an output data set for transmission based on the first codeword, wherein the selected parity-check bits are deprioritized.

2. The apparatus of claim 1, wherein the parity-check block is represented in the memory as a parity-check matrix data structure arranged as a set of rows and columns.

3. The apparatus of claim 2, wherein each column of the parity-check matrix has an effective column weight defined as a number of parity-check nodes to which a corresponding parity-check bit connects that do not contain other as-yet unrecovered deprioritized bits.

4. Apparatus of a communication device configured to decode an encoded message, the apparatus comprising:

memory; and

processing circuitry to control the apparatus to: access received messaging that includes a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity-check bits;

compute a first reverse-permutation of the first permuted portion, and a second reverse-permutation of the second permuted portion, to produce a codeword containing an unpermuted first portion representing the information bits and an unpermuted second portion representing the parity- check bits; and

decode the codeword using a low-density parity-check matrix, the codeword having been previously encoded as a set of parity-check nodes based on the set of information bits and on a set of parity-check bits including parity-check bits associated with a relatively greater quantity of parity-check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes, certain parity-check bits having been deprioritized from the codeword based on selection criteria that deprioritized those parity-check bits associated with the relatively greater quantity of the parity-check nodes.

5. The apparatus of claim 4, wherein the received messaging comprises a set of log-likelihood ratios.

6. The apparatus of claim 4, wherein the received messaging includes a first transmission and a second transmission.

7. The apparatus of claim 4, wherein the received messaging comprises circular- buffered data.

8. The apparatus according to any one of claims 1 or 4, wherein the codeword is represented in the memory as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritized those parity- check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity-check bit columns.

9. The apparatus of claim 8, wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements.

10. The apparatus of claim 8, wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

11. The apparatus according to any one of claims 1-7, wherein the parity-check bits that are deprioritized are omitted from the messaging.

12. The apparatus according to any one of claims 1-7, wherein the parity-check bits that are deprioritized are permuted to a least-significant position within the messaging.

13. The apparatus according to any one of claims 1-7, wherein the codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.

14. The apparatus according to any one of claims 1-7, wherein the apparatus includes a baseband processor.

15. The apparatus according to any one of claims 1-7, wherein the apparatus includes a transceiver circuit coupled to an antenna.

16. The apparatus according to any one of claims 1-7, wherein the apparatus includes an e-Node B device.

17. The apparatus according to any one of claims 1-7, wherein the apparatus includes a user equipment (UE) device.

18. A computer-readable medium comprising instructions that, when executed on a processing apparatus, cause the apparatus to:

encode a set of information bits to be transmitted according to a parity-check block to produce a first codeword, the first codeword representing a set of parity- check nodes based on the set of information bits and on a set of parity-check bits including parity-check bits associated with a relatively greater quantity of parity- check nodes, and parity-check bits associated with a relatively smaller quantity of parity-check nodes;

select parity-check bits to be deprioritized from the first codeword based on selection criteria that deprioritizes those parity-check bits that are associated with the relatively greater quantity of the parity-check nodes; and

19. The computer-readable medium of claim 18, wherein the parity-check block is represented as a parity-check matrix data structure arranged as a set of rows and columns.

20. The computer-readable medium of claim 19, wherein each column of the parity-check matrix has an effective column weight defined as a number of parity- check nodes to which a corresponding parity-check bit connects that do not contain other as-yet unrecovered deprioritized bits.

21. A computer-readable medium comprising instructions that, when executed on a processing apparatus, cause the apparatus to:

access received messaging that includes a first permuted portion representing a set of information bits and a second permuted portion representing a set of parity- check bits;

compute a first reverse-permutation of the first permuted portion, and a second reverse-permutation of the second permuted portion, to produce a codeword containing an unpermuted first portion representing the information bits and an unpermuted second portion representing the parity-check bits; and

22. The computer-readable medium of claim 21 , wherein the received messaging comprises a set of log- likelihood ratios.

23. The computer-readable medium of claim 21 , wherein the received messaging includes a first transmission and a second transmission.

24. The computer-readable medium of claim 21 , wherein the received messaging comprises circular-buffered data.

25. The computer-readable medium according to any one of claims 18 or 21, wherein the codeword is represented as a matrix data structure arranged as a set of rows and columns of elements, and wherein the selection criteria deprioritized those parity-check bits that belong to parity-check bit columns having a greatest quantity of nonzero elements from among all of the parity-check bit columns.

26. The computer-readable medium of claim 25, wherein the parity-check bit columns having greatest quantity of nonzero elements have at least 3 nonzero elements.

27. The computer-readable medium of claim 25, wherein the parity-check bit columns having greatest quantity of nonzero elements have an odd quantity of nonzero elements.

28. The computer-readable medium according to any one of claims 18-24, wherein the parity-check bits that are deprioritized are omitted from the messaging.

29. The computer-readable medium according to any one of claims 18-24, wherein the parity-check bits that are deprioritized are permuted to a least-significant position within the messaging.

30. The computer-readable medium according to any one of claims 18-24 wherein the codeword contains at least a portion of the set of information bits as a systemic portion concatenated with a parity-check portion of bits.