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WO2017121133A1 - 移位寄存器单元、栅极驱动电路、显示面板及显示装置 - Google Patents

移位寄存器单元、栅极驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2017121133A1
WO2017121133A1 PCT/CN2016/098180 CN2016098180W WO2017121133A1 WO 2017121133 A1 WO2017121133 A1 WO 2017121133A1 CN 2016098180 W CN2016098180 W CN 2016098180W WO 2017121133 A1 WO2017121133 A1 WO 2017121133A1
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WO
WIPO (PCT)
Prior art keywords
node
signal
control
output
switching transistor
Prior art date
Application number
PCT/CN2016/098180
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English (en)
French (fr)
Inventor
马占洁
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/529,532 priority Critical patent/US10019949B2/en
Publication of WO2017121133A1 publication Critical patent/WO2017121133A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a gate driving circuit, a display panel, and a display device.
  • OLED displays are one of the hotspots in the field of flat panel display research. Compared with liquid crystal displays, OLED displays have the advantages of low energy consumption, low production cost, self-illumination, wide viewing angle and fast response. At present, OLED displays in mobile phones, PDAs, digital cameras and other display fields have begun to replace traditional LCD displays. Screen.
  • the organic light emitting display panel requires control of an integrated circuit (IC). For example, the gate driving circuit controls the display panel to implement a progressive scan and a frame-by-frame refresh function, so that image data input to the display panel can be refreshed in real time, thereby Achieve dynamic display.
  • IC integrated circuit
  • the light emitting driving circuit is configured to input a light emitting signal to the display panel, thereby controlling the OLED in each pixel to emit light in the light emitting stage.
  • the gate driving circuit and the light emitting driving circuit are separate circuits respectively designed independently, the gate driving circuit includes a plurality of scanning shift register units, and the light emitting driving circuit includes a plurality of light emitting shift register units.
  • One embodiment of the present invention provides a shift register unit including a first input module, a second input module, a first control module, a second control module, an illumination signal output module, and a scan signal output module.
  • the first control end and the first input end of the first input module are respectively connected to the first clock signal, the second control end and the first output end are respectively connected to the first node, and the second input end is connected to the first signal, and the third The input end is connected to the first reference signal, and the second output end is connected to the second node;
  • the first input module is configured to, under the control of the first clock signal, the first signal and the first reference The signals are respectively output to the first node and the second node, and the first clock signal is output to the second node under the control of the first node.
  • the first control end and the first input end of the second input module are respectively connected to the first clock signal, the second control end and the first output end are respectively connected to the third node, and the second input end is connected to the second signal.
  • the third input is connected to the first reference signal, and the second output is connected to the fourth node;
  • the second input module is configured to output the second signal and the first reference signal to the third node and the fourth node respectively under the control of the first clock signal, in the third
  • the first clock signal is output to the fourth node under the control of the node.
  • the first control end of the first control module is connected to the second node, the second control end is connected to the second clock signal, and the third control end is connected to the first node, the first input end and the second reference
  • the signal is connected, the second input end is connected to the first reference signal, and the output end is connected to the fifth node;
  • the first control module is configured to be under the control of the second node and the second clock signal
  • the first reference signal is output to the fifth node
  • the second reference signal is output to the fifth node under the control of the first node.
  • a first control end of the second control module is connected to the fourth node, a second control end is connected to the first node, a third control end is connected to the fifth node, and the input end and the second reference signal are Connected, the output end is connected to the third node; the second control module is configured to output the second reference signal under the control of the fourth node, the first node, and the fifth node Go to the third node.
  • a first control end of the illuminating signal output module is connected to the first node, a second control end is connected to the fifth node, a first input end is connected to the first reference signal, and a second input end is connected to the first
  • the second reference signal is connected
  • the illuminating signal output module includes an illuminating signal output end, and the illuminating signal output module is configured to, under the control of the first node and the fifth node, the first reference signal or The second reference signal is output to the illuminating signal output terminal.
  • a first control end of the scan signal output module is connected to the third node, a second control end is connected to the fourth node, a first input end is connected to the second reference signal, and a second input end is connected to the second Two scan signals are connected, the scan signal output module includes a scan signal output end; the scan signal output module is configured to, under the control of the third node and the fourth node, the second reference signal or The second clock signal is output to the scan signal output terminal.
  • the illuminating signal output module includes a first output unit and a second output unit.
  • the first output unit has a control end as a second control end of the illumination signal output module, and an input end as a second input end of the illumination signal output module, the first output unit is used in the
  • the second reference signal is output to the illumination signal output terminal under the control of five nodes.
  • the second output unit has a control end as a first control end of the illumination signal output module, and an input end as a first input end of the illumination signal output module, the second output unit is used in the The first reference signal is output to the illumination signal output terminal under the control of a node.
  • the first output unit includes a first switching transistor and a first capacitor, a gate of the first switching transistor is connected to the fifth node, a source is connected to the second reference signal, and a drain Connected to the illuminating signal output end, the first capacitor is connected between the second reference signal and the fifth node.
  • the second output unit includes a second switching transistor and a second capacitor, a gate of the second switching transistor is connected to the first node, and a source is connected to the first reference signal.
  • the drain is connected to the light emitting signal output end, and the second capacitor is connected between the first node and the light emitting signal output end.
  • the scan signal output module includes a third output unit and a fourth output unit.
  • the third output unit has a control end as a second control end of the scan signal output module, and an input end as a first input end of the scan signal output module, the third output unit is used in the
  • the second reference signal is output to the scan signal output terminal under the control of four nodes.
  • the fourth output unit has a control end as a first control end of the scan signal output module, and an input end as a second input end of the scan signal output module, the fourth output unit is used in the The second clock signal is output to the scan signal output terminal under the control of three nodes.
  • the third output unit includes a third switching transistor and a third capacitor, a gate of the third switching transistor is connected to the fourth node, and a source is connected to the second reference signal.
  • the drain is connected to the scan signal output end, and the third capacitor is connected between the fourth node and the second reference signal end.
  • the fourth output unit includes a fourth switching transistor and a fourth capacitor, a gate of the fourth switching transistor is connected to the third node, and a source is connected to the second clock signal. A drain is connected to the scan signal output, and a fourth capacitor is connected between the third node and the scan signal output.
  • the first control module includes a first control unit and a second control unit.
  • the first control unit has a first control end and a second control end as the first control end and the second control end of the first control module, respectively, and an input end as a second input end of the first control module
  • the first control unit is configured to output the first reference signal to the fifth node under the control of the second node and the second clock signal.
  • the second control unit has a control end as a third control end of the first control module and an input end as a first input end of the first control module, and the second control unit is used in the first Outputting the second reference signal to the node under control The fifth node.
  • the first control unit includes a fifth switching transistor, a sixth switching transistor, and a fifth capacitor.
  • a gate of the fifth switching transistor is connected to the second node, a source is connected to the first reference signal, a drain is connected to a source of the sixth switching transistor, and a gate of the sixth switching transistor is The pole is connected to the second clock signal, and the drain is connected to the fifth node.
  • the fifth capacitor is coupled between the second node and the second clock signal.
  • the second control unit includes a seventh switching transistor, a gate of the seventh switching transistor is connected to the first node, a source is connected to the second reference signal, and a drain is The fifth node is connected.
  • the first input module includes a first input unit and a second input unit.
  • the first input unit has a control end as a first control end of the first input module, a first input end as a third input end of the first input module, and a second as the first input module a second input end of the input end, the first input unit is configured to output the first signal and the first reference signal to the first node and the respectively under the control of the first clock signal The second node.
  • the second input unit has a control end as a second control end of the first input module, and an input end as a first input end of the first input module, the second input unit is used in the The first clock signal is output to the second node under the control of a node.
  • the first input unit includes an eighth switching transistor and a ninth switching transistor.
  • the gate of the eighth switching transistor is connected to the first clock signal, the source is connected to the first signal, and the drain is connected to the first node.
  • the gate of the ninth switching transistor is connected to the first clock signal, the source is connected to the first reference signal, and the drain is connected to the second node.
  • the second input unit includes a tenth switching transistor, a gate of the tenth switching transistor is connected to the first node, a source is connected to the first clock signal, and a drain is The second node is connected.
  • the second input module includes a third input unit and a fourth input unit, the third input unit having a control end as a first control end of the second input module, as the second a first input terminal of the third input terminal of the input module, and a second input terminal as a second input terminal of the second input module, the third input unit is configured to be under the control of the first clock signal, The second signal and the first The reference signals are output to the third node and the fourth node, respectively.
  • the fourth input unit has a control end as a second control end of the second input module, and an input end as a first input end of the second input module, the fourth input unit is used in the The first clock signal is output to the fourth node under the control of three nodes.
  • the third input unit includes an eleventh switching transistor and a twelfth switching transistor. a gate of the eleventh switching transistor is connected to the first clock signal, a source is connected to the second signal, a drain is connected to the third node, and a gate of the twelfth switching transistor is The first clock signal is connected, the source is connected to the first reference signal, and the drain is connected to the fourth node.
  • the fourth input unit includes a thirteenth switching transistor, a gate of the thirteenth switching transistor is connected to the third node, a source is connected to the first clock signal, and a drain Connected to the fourth node.
  • the second control module includes a fourteenth switching transistor, a fifteenth switching transistor, and a sixteenth switching transistor, wherein a gate of the fourteenth switching transistor is connected to the fourth node a source connected to the second reference signal, a drain connected to a source of the fifteenth switching transistor and a source of a sixteenth switching transistor, respectively, a gate of the fifteenth switching transistor and the The first node is connected, the drain is connected to the third node, the gate of the sixteenth switching transistor is connected to the fifth node, and the drain is connected to the third node.
  • Another embodiment of the present invention provides a gate drive circuit that can include a plurality of shift register units as described in any of the preceding embodiments including a cascade. Except for the last shift register unit, the illumination signal output terminals of each of the shift register units input the first one for the next-stage shift register unit to the next-stage shift register unit adjacent thereto And a signal, the scan signal output terminal inputs a second signal for the next-stage shift register unit to a next-stage shift register unit adjacent thereto.
  • the first signal and the second signal provided to the first one of the plurality of shift register units of the cascade are respectively a first trigger signal for generating the illumination signal And a second trigger signal for generating the scan signal.
  • Yet another embodiment of the present invention provides a display panel that can include the gate drive circuit of the above-described embodiments of the present invention.
  • Yet another embodiment of the present invention provides a display device that can include a display panel as described in the above embodiments of the present invention.
  • Embodiments of the present invention provide a shift register unit, a gate driving circuit, a display panel, and a display device.
  • the shift register unit includes a first input module, a second input module, a first control module, a second control module, an illumination signal output module, and a scan signal output module.
  • the first input module is configured to output the first signal and the first reference signal end to the first node and the second node respectively under the control of the first clock signal end, and the first clock is controlled under the control of the first node
  • the signal is output to the second node
  • the second input module is configured to output the second signal and the first reference signal to the third node and the fourth node respectively under the control of the first clock signal, and under the control of the third node,
  • the first clock signal is output to the fourth node
  • the first control module is configured to output the first reference signal to the fifth node under the control of the second node and the second clock signal, and the second reference is controlled under the control of the first node
  • the signal is output to the fifth node
  • the second control module is configured to output the second reference signal to the third node under the control of the fourth node, the first node, and the fifth node
  • the illuminating signal output module is used at the first node And outputting, by the fifth node, the first reference signal or the second
  • each module outputs a corresponding signal under the control of the respective control signals, and the output of the scan signal and the illuminating signal can be realized.
  • the illuminating signal output module and the scanning signal output module are combined, and the illuminating signal output module and the scanning signal output module can be synchronously driven, that is, the illuminating shift register unit and the scanning shift register unit can be integrated into one circuit structure. Medium, thereby reducing the number of clock signals required.
  • the shift register unit period normally open shift register unit provided by the embodiment of the invention that is, the illuminating signal is in an active level state for a majority of time in one frame time.
  • the illuminating signal output module can continuously output the first reference signal or the second reference signal, and by controlling the potentials of the third node and the fourth node, the scan signal output module can continuously output the second
  • the reference signal or the second clock signal can realize outputting the illuminating signal having a plurality of pulse widths, that is, integrating the illuminating shift register unit and the scanning shift register unit into one circuit structure, and realizing the illuminating signal Air ratio control.
  • FIG. 1 is a block diagram showing the structure of a shift register unit according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram showing a specific circuit of a shift register unit according to an embodiment of the present invention
  • FIG. 3 is a timing chart of operation of a shift register unit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • the embodiment of the present invention provides a shift register unit, as shown in FIG. 1, which may include: a first input module 01, a second input module 02, a first control module 03, a second control module 04, and an illumination signal output module. 05 and scan signal output module 06.
  • the first control terminal 1a and the first input terminal 1b of the first input module 01 are respectively connected to the first clock signal CLK1, and the second control terminal 1g and the first output terminal 1f are respectively respectively A node P1 is connected, a second input terminal 1c is connected to the first signal STVE, a third input terminal 1d is connected to the first reference signal VGL, and a second output terminal 1e is connected to the second node P2.
  • the first input module 01 is configured to output the first signal STVE and the first reference signal VGL to the first node P1 and the second node P2 under the control of the first clock signal CLK1, respectively, under the control of the first node P1,
  • the first clock signal CLK1 is output to the second node P2.
  • the first control terminal 2a and the first input terminal 2b of the second input module 02 are respectively connected to the first clock signal CLK1, and the second control terminal 2d and the first output terminal 2e are respectively connected to the third node P3, and the second input terminal 2f Connected to the second signal STVG, the third input terminal 2g is connected to the first reference signal VGL, and the second output terminal 2c is connected to the fourth node P4.
  • the second input module 02 is configured to output the second signal STVG and the first reference signal VGL to the third node P3 and the fourth node P4 respectively under the control of the first clock signal CLK1, under the control of the third node P3,
  • the first clock signal CLK1 is output to the fourth node P4.
  • the first control terminal 3f of the first control module 03 is connected to the second node P2, the second control terminal 3c is connected to the second clock signal CLK2, and the third control terminal 3e is connected to the first node P1, the first input terminal 3b and the first The second reference signal VGH is connected, the second input terminal 3a is connected to the first reference signal VGL, and the output terminal 3d is connected to the fifth node P5.
  • the first control module 03 is configured to output the first reference signal VGL to the fifth node P5 under the control of the second node P2 and the second clock signal CLK2, and input the second reference signal VGH under the control of the first node P1. Go out to the fifth node P5.
  • the first control terminal 4b of the second control module 04 is connected to the fourth node P4, the second control terminal 4a is connected to the first node P1, the third control terminal 4c is connected to the fifth node P5, and the input terminal 4f and the second reference signal are connected.
  • VGH is connected, and the output terminal 4e is connected to the third node P3.
  • the second control module 04 is configured to output the second reference signal VGH to the third node P3 under the control of the fourth node P4, the first node P1, and the fifth node P5.
  • the first control terminal 5d of the illuminating signal output module 05 is connected to the first node P1, the second control terminal 5e is connected to the fifth node P5, the first input terminal 5b is connected to the first reference signal VGL, and the second input terminal 5a is connected.
  • the two reference signals VGH are connected, and the output terminal 5c serves as an output of the illumination signal for outputting the illumination signal EM.
  • the illuminating signal output module 05 is configured to output the first reference signal VGL or the second reference signal VGH to the illuminating signal output terminal 5c under the control of the first node P1 and the fifth node P5.
  • the first control terminal 6b of the scan signal output module 06 is connected to the third node P3, the second control terminal 6a is connected to the fourth node P4, the first input terminal 6c is connected to the second reference signal VGH, and the second input terminal 6d and the The two clock signals CLK2 are connected, and the output terminal 6e serves as a scan signal output terminal for outputting the scan signal Gate.
  • the scan signal output module 06 is configured to output the second reference signal VGH or the second clock signal CLK2 to the scan signal output terminal 6e under the control of the third node P3 and the fourth node P4.
  • the illuminating signal output module may include a first output unit 051 and a second output unit 052.
  • the control terminal 5e of the first output unit 051 is connected to the fifth node P5
  • the input terminal 5a is connected to the second reference signal VGH
  • the output terminal 5c is used as the illumination signal output terminal
  • the first output unit 051 is used for the control at the fifth node P5.
  • the second reference signal VGH is output to the light-emitting signal output terminal 5c.
  • the control terminal 5d of the second output unit 052 is connected to the first node P1
  • the input terminal 5b is connected to the first reference signal VGL
  • the output terminal is connected to the illumination signal output terminal 5c
  • the second output unit 052 is used at the first node P1.
  • the first reference signal VGL is output to the light-emitting signal output terminal 5c. Since the illuminating signal output module includes the first output unit and the second output unit, the first reference signal can be continuously output through the second output unit under the control of the first node, and the first output unit is controlled under the control of the fifth node.
  • the second reference signal is output.
  • the first output unit 051 may include a first switching transistor T1 and a first capacitor C1.
  • First switching crystal The first transistor C1 is connected between the second reference signal VGH and the fifth node P5. .
  • the first switching transistor can be turned on under the control of the fifth node, thereby outputting the second reference signal to the illuminating signal output terminal.
  • the second output unit 052 may include a second switching transistor T2 and a second capacitor C2.
  • the second switching transistor T2 has a gate connected to the first node P1, a source connected to the first reference signal VGL, a drain connected to the illuminating signal output terminal 5c, and a second capacitor C2 connected to the first node P1 and the illuminating signal output end. between.
  • the second switching transistor can be turned on under the control of the first node to output the first reference signal to the output of the illuminating signal.
  • the scan signal output module may include a third output unit 061 and a fourth output unit 062.
  • the control terminal 6a of the third output unit 061 is connected to the fourth node P4, the input terminal 6c is connected to the second reference signal VGH, and the output terminal 6e is provided as a scan signal output terminal to provide the scan signal Gate.
  • the third output unit 061 is configured to output the second reference signal VGH to the scan signal output terminal 6e under the control of the fourth node P4.
  • the control terminal 6b of the fourth output unit 062 is connected to the third node P3, the input terminal 6d is connected to the second clock signal CLK2, and the output terminal is connected to the scan signal output terminal 6e.
  • the fourth output unit 062 is configured to output the second clock signal CLK2 to the scan signal output terminal 6e under the control of the third node P3. Since the scan signal output module includes the third output unit and the fourth output unit, the second reference signal can be continuously output through the third output unit under the control of the fourth node, and the fourth output unit is controlled under the control of the third node. The second clock signal is output.
  • the third output unit may include a third switching transistor T3 and a third capacitor C3.
  • the third switching transistor T3 has a gate connected to the fourth node P4, a source connected to the second reference signal VGH, a drain connected to the scan signal output terminal, and a third capacitor C3 connected to the fourth node P4 and the second reference signal VGH. between.
  • the third switching transistor can be turned on under the control of the fourth node to output the second reference signal to the scan signal output terminal.
  • the fourth output unit may include a fourth switching transistor T4 and a fourth capacitor C4.
  • the fourth switching transistor T4 has a gate connected to the third node P3, a source connected to the second clock signal CLK2, a drain connected to the scan signal output terminal, and a fourth capacitor C4 connected to the third node P3 and scanning. Between signal outputs. Therefore, the fourth switching transistor can be turned on under the control of the third node, thereby outputting the second clock signal to the scan signal output terminal.
  • the first control module may include a first control unit 031 and a second control unit 032.
  • the first control terminal 3f of the first control unit 031 is connected to the second node P2
  • the second control terminal 3c is connected to the second clock signal CLK2
  • the input terminal 3a is connected to the first reference signal VGL
  • the output terminal 3d and the fifth node P5 are connected.
  • the first control unit 031 is configured to output the first reference signal VGL to the fifth node P5 under the control of the second node P2 and the second clock signal CLK2.
  • the control terminal 3e of the second control unit 032 is connected to the first node P1, the input terminal 3b is connected to the second reference signal VGH, and the output terminal is connected to the fifth node P5.
  • the second control unit 032 is configured to output the second reference signal VGH to the fifth node P5 under the control of the first node P1. Since the first control module includes the first control unit and the second control unit, the first reference signal may be output to the fifth node by the first control unit under the control of the second node and the second clock signal, at the first The second reference signal is output to the fifth node by the second control unit under the control of the node.
  • the first control unit may include a fifth switching transistor T5, a sixth switching transistor T6, and a fifth capacitor C5.
  • the gate of the fifth switching transistor T5 is connected to the second node P2, the source is connected to the first reference signal VGL, the drain is connected to the source of the sixth switching transistor T6, and the gate of the sixth switching transistor T6 is connected to the second clock.
  • the signal CLK2 is connected, the drain is connected to the fifth node P5, and the fifth capacitor C5 is connected between the second node P2 and the second clock signal CLK2.
  • the fifth switching transistor can be turned on under the control of the second node, thereby outputting the first reference signal to the source of the sixth switching transistor; and the sixth switching transistor can be turned on under the control of the second clock signal, thereby The signal of its source is output to the fifth node.
  • the second control unit may include a seventh switching transistor T7.
  • the gate of the seventh switching transistor T7 is connected to the first node P1, the source is connected to the second reference signal VGH, and the drain is connected to the fifth node P5.
  • the seventh switching transistor can be turned on under the control of the first node, thereby outputting the second reference signal to the fifth node.
  • the first input module may include a first input unit 011 and a second input unit 012.
  • the control terminal 1a of the first input unit 011 is connected to the first clock signal CLK1, and the first input terminal 1d is The first reference signal VGL is connected, the second input terminal 1c is connected to the first signal STVE, the first output terminal 1f is connected to the first node P1, and the second output terminal 1e is connected to the second node P2.
  • the first input unit 011 is configured to output the first signal STVE and the first reference signal VGL to the first node P1 and the second node P2, respectively, under the control of the first clock signal CLK1.
  • the control terminal 1g of the second input unit 012 is connected to the first node P1, the input terminal 1b is connected to the first clock signal CLK1, and the output terminal is connected to the second node P2.
  • the second input unit 012 is configured to output the first clock signal CLK1 to the second node P2 under the control of the first node P1. Since the first input module includes the first input unit and the second input unit, the first signal and the first reference signal may be respectively output to the first node and the first input unit by the first input unit under the control of the first clock signal The two nodes output the first clock signal to the second node through the second input unit under the control of the first node.
  • the first input unit 011 may include an eighth switching transistor T8 and a ninth switching transistor T9.
  • the gate of the eighth switching transistor T8 is connected to the first clock signal CLK1
  • the source is connected to the first signal STVE
  • the drain is connected to the first node P1
  • the gate of the ninth switching transistor T9 is connected to the first clock signal CLK1.
  • the source is connected to the first reference signal VGL
  • the drain is connected to the second node P2.
  • the eighth switching transistor can be turned on under the control of the first clock signal, thereby outputting the first signal to the first node
  • the ninth switching transistor can be turned on under the control of the first clock signal, thereby using the first reference.
  • the signal is output to the second node.
  • the second input unit may include a tenth switching transistor T10.
  • the gate of the tenth switching transistor T10 is connected to the first node P1, the source is connected to the first clock signal CLK1, and the drain is connected to the second node P2.
  • the tenth switching transistor can be turned on under the control of the first node, thereby outputting the first clock signal to the second node.
  • the second input module may include a third input unit 021 and a fourth input unit 022.
  • the control terminal 2a of the third input unit 021 is connected to the first clock signal CLK1
  • the first input terminal 2g is connected to the first reference signal VGL
  • the second input terminal 2f is connected to the second signal STVG
  • the node P3 is connected
  • the second output 2c is connected to the fourth node P4.
  • the third input unit 021 is configured to output the second signal STVG and the first reference signal VGL to the third node P3 and the fourth node P4, respectively, under the control of the first clock signal CLK1.
  • the control terminal 2d of the fourth input unit 022 is connected to the third node P3, and the input terminal 2b is first
  • the clock signal CLK1 is connected, and the output terminal is connected to the fourth node P4.
  • the fourth input unit 022 is configured to output the first clock signal CLK1 to the fourth node P4 under the control of the third node P3. Since the second input module can include the third input unit and the fourth input unit, the second signal and the first reference signal can be respectively output to the third node and the third through the third input unit under the control of the first clock signal.
  • the four nodes output the first clock signal to the fourth node through the fourth input unit under the control of the third node.
  • the third input unit may include an eleventh switching transistor T11 and a twelfth switching transistor T12.
  • the gate of the eleventh switching transistor T11 is connected to the first clock signal CLK1
  • the source is connected to the second signal STVG
  • the drain is connected to the third node P3
  • the gate of the twelfth switching transistor T12 is connected to the first clock signal CLK1.
  • the source is connected to the first reference signal VGL
  • the drain is connected to the fourth node P4.
  • the eleventh switching transistor can be turned on under the control of the first clock signal, and then the second signal is output to the third node; the twelfth switching transistor can be turned on under the control of the first clock signal, and thus The first reference signal is output to the fourth node.
  • the fourth input unit may include a thirteenth switching transistor T13.
  • the gate of the thirteenth switching transistor T13 is connected to the third node P3, the source is connected to the first clock signal CLK1, and the drain is connected to the fourth node P4.
  • the thirteenth switching transistor can be turned on under the control of the third node, thereby outputting the first clock signal to the fourth node.
  • the second control module may include a fourteenth switching transistor T14, a fifteenth switching transistor T15, and a sixteenth switching transistor T16.
  • the gate of the fourteenth switching transistor T14 is connected to the fourth node P4, the source is connected to the second reference signal VGH, and the drain is connected to the source of the fifteenth switching transistor T15 and the source of the sixteenth switching transistor T16, respectively.
  • the fifteenth switching transistor T15 has a gate connected to the first node P1, a drain connected to the third node P3, a sixteenth switching transistor T16 having a gate connected to the fifth node P5, and a drain connected to the third node P3. .
  • the fourteenth switching transistor can be turned on under the control of the fourth node, and then output the second reference signal to the source of the fifteenth switching transistor and the source of the sixteenth switching transistor, respectively;
  • the fifteenth switching transistor It can be turned on under the control of the first node to output the signal of its source to the third node;
  • the sixteenth switching transistor can be turned on under the control of the fifth node, thereby outputting the signal of the source to the first Three nodes.
  • the switching transistor mentioned in the above embodiment of the present invention may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited herein. .
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the sources and drains of these transistors are interchangeable and are not specifically distinguished.
  • a thin film transistor will be described as an example in describing a specific embodiment.
  • the mentioned first reference signal VGL may be a signal having a low voltage level
  • the second reference signal VGH may be a signal having a high voltage level
  • the first signal STVE may be a first trigger signal for generating the illumination signal EM
  • the second signal STVG may be a second trigger signal for generating the scan signal Gate.
  • the working process of the shift register unit provided by the embodiment of the present invention will be described in detail below with reference to the circuit structure and operation timing of the shift register unit provided by the embodiment of the present invention.
  • the operation of the shift register unit provided by the embodiment of the present invention will be described with reference to the timing chart shown in FIG. 3 by taking the shift register unit of the P-type transistor as shown in FIG. 2 as an example.
  • the signal timing chart of the shift register unit includes eight stages from t1 to t8. In the following description, a high level signal is indicated by 1 and a low level signal is indicated by 0.
  • the second reference signal VGH is supplied to the fifth node P5 via the turned-on seventh switching transistor T7, thereby turning off the first switching transistor T1; the turned-on ninth switching transistor T9 and the tenth switching transistor T10 respectively refer to the first reference
  • the fourteenth switching transistor T14 is also in an on state under the control of the fourth node P4, so the second reference signal VGH is supplied to the turned-on fifteenth switching transistor T15 via the turned-on fourteenth switching transistor T14.
  • the third node P3 keeps the third node P3 at a high potential.
  • the first signal STVE, the second signal STVG, and the second clock signal CLK2 are unchanged, and the first clock signal CLK1 is changed from a low level signal to a high level signal, at this time, due to the capacitor C2
  • the potential of the first node P1 can be maintained at a low level, and therefore, the tenth switching transistor T10 can output a high level signal of the first clock signal CLK1 to the second node P2 such that the fifth switching transistor T5 is in an off state.
  • the sixth switching transistor T6 is turned on. Since the potential of the second node P2 is at a high level in the second half of the t1 phase, the fifth switching transistor T5 is in an off state, and therefore, the potential of the second node P2 is maintained in the t2 phase due to the action of the fifth capacitor C5. At a high potential, the signal of the first reference signal terminal VGL is not output to the fifth node P5 through the fifth switching transistor T5 and the sixth switching transistor T6.
  • the first node P1 maintains the low level of the previous stage, the second switching transistor T2 and the seventh transistor T7 are in an on state, the potential of the fifth node P5 is at a high level VGH, and the first switching transistor T1 is still in an off state, thereby The illuminating signal output terminal still outputs the first reference signal VGL.
  • the fourth node P4 remains at the low level of the previous stage, so the third photo transistor T3 is in an on state, and the scan signal output terminal outputs a second reference signal VGH.
  • the scan signal output terminal outputs a high level signal; meanwhile, the turned on thirteenth switching transistor T13 supplies the first clock signal CLK1 to the fourth node P4.
  • the first switching transistor T1 and the second switching transistor T2 are both in an off state, and the output of the illuminating signal maintains the output state of the previous stage, that is, Output a low level signal.
  • the scan signal output terminal outputs a low level signal, and the thirteenth switching transistor T13 is turned on under the control of the third node P3, and outputs the first clock signal CLK1 to the fourth node P. 4.
  • CLK1 1, so that the potential of the fourth node P4 is kept high, and the third switching transistor T3 is turned off.
  • the transistor T15 is turned off;
  • the turned-on ninth switching transistor T9 outputs the first reference signal VGL to the second node P2;
  • the first reference signal VGL is output to the fourth node P4, so that the third switching transistor T3 and the fourteenth switching transistor T14 are turned on, and the turned-on third switching transistor T3 outputs the second reference signal VGH to the scan signal output terminal.
  • the fifth node P5 maintains the low level of the previous stage, so the first switching transistor T1 and the sixteenth switching transistor T16 are turned on, and the turned-on first switching transistor T1 outputs the second reference signal VGH to the output of the illuminating signal.
  • the second reference signal VGH is output to the third node P3 through the turned-on fourteenth switching transistor T14 and the sixteenth switching transistor T16, further maintaining the high potential of the third node P3.
  • the signal VGH is output to the illuminating signal output terminal; at the same time, the fourth node P4 maintains the low level of the previous stage, so the third switching transistor T3 and the fourteenth switching transistor T14 are turned on, and the turned-on third switching transistor T3 will be the second reference.
  • the signal VGH is output to the scan signal output terminal, and the second reference signal VGH is output to the third node P3 through the turned-on fourteenth switching transistor T14 and the sixteenth switching transistor T16, further maintaining the high potential of the third node P3.
  • the turned-on second switching transistor T2 supplies the first reference signal VGL to the illuminating signal output end such that the illuminating signal output terminal outputs a low level signal;
  • the turned-on seventh switching transistor T7 provides the second reference signal VGH to the fifth a node P5, which in turn causes the first switching transistor T1 to be turned off;
  • the turned-on ninth switching transistor T9 and the tenth switching transistor T10 respectively output the first reference signal VGL and the first clock signal CLK1 to the second node P2;
  • the eleventh switching transistor T11 supplies the second signal STVG to the third node P3.
  • the reference signal VGL is supplied to the fourth node P4, and the third switching transistor T3 is turned on, and the turned-on
  • the fourteenth switching transistor T14 is also in an on state under the control of the fourth node P4, and the turned-on fourteenth switching transistor T14 and the turned-on fifteenth switching transistor T15 provide the second reference signal VGH to the first
  • the three nodes P3 keep the third node P3 at a high potential.
  • the first signal STVE, the second signal STVG, and the second clock signal CLK2 are unchanged, and the first clock signal CLK1 is changed from a low level signal to a high level signal.
  • the first clock signal The high level signal of CLK1 is output to the second node P2 via the turned-on tenth switching transistor T10, thereby causing the fifth switching transistor T5 to be in an off state.
  • the process of the t3, t4, t5 phase will be repeated until the first signal STVE changes from the high level signal to the low level signal again. Thereafter, the process of the t7 and t8 phases will be repeated after the completion of the process of the t6 phase.
  • the first signal STVE is always a high level signal
  • the second clock signal CLK2 is in a high state
  • the second signal STVG the first clock signal CLK1 is in a low state, and therefore, is subjected to the first clock signal.
  • the eighth switching transistor T8, the ninth switching transistor T9, the eleventh switching transistor T11 and the twelfth switching transistor T12 controlled by CLK1 are turned on; the turned-on twelfth switching transistor T12 writes the first reference signal VGL to the first The four nodes P4, and then the third switching transistor T3 is turned on, thereby outputting the second reference signal VGH to the scan signal output terminal, and the low level signal of the second signal STVG is output to the third node P3, so that the thirteenth switch The transistor T13 and the fourth switching transistor T4 are in an on state.
  • another embodiment of the present invention provides a gate driving circuit including a plurality of cascaded shift register units provided by any of the above embodiments of the present invention, except for the last shift
  • the illumination signal output terminals of each of the other shift register units input a first signal for the next-stage shift register unit to the next-stage shift register unit adjacent thereto, and the scan signal output terminal The second signal for the next stage shift register unit is input to the next stage shift register unit adjacent thereto.
  • shift register units are a first-stage shift register unit, a second-stage shift register unit, a third-stage shift register unit, and a fourth-stage shift register.
  • the illumination signal EM of the illumination signal output end of the N-1th stage shift register unit is supplied to the Nth stage shift register unit as the first signal for the Nth stage shift register unit, and the scan signal Gate of the scan signal output end is
  • the Nth stage shift register unit is supplied as a second signal for the Nth stage shift register unit.
  • connection positions of the first clock signal CLK1 and the second clock signal CLK2 in the adjacent lower stage are interchanged with the connection positions in the present stage.
  • the first clock signal CLK1 is connected to the control terminal 1a
  • the second clock signal CLK2 is connected to the input terminal 6d
  • the first clock signal CLK1 is connected to the input terminal 6d
  • the second clock signal CLK2 is connected to the control terminal 1a, thereby achieving a top-down shifting effect.
  • a further embodiment of the present invention provides a display panel.
  • the gate driving circuit provided by the above embodiment of the present invention is included. Since the principle of solving the problem of the display panel is similar to that of the gate driving circuit, the implementation of the display panel can be referred to the implementation of the above-mentioned gate driving circuit, and the repeated description is omitted.
  • a further embodiment of the present invention provides a display device including the display panel provided by the above embodiment of the present invention.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Since the principle of solving the problem is similar to that of the display panel, the implementation of the display device can be referred to the implementation of the above display panel, and the repeated description is omitted.
  • Embodiments of the present invention provide a shift register unit, a gate driving circuit, a display panel, and a display device shift register unit.
  • the shift register unit includes a first input module, a second input module, a first control module, a second control module, an illumination signal output module, and a scan signal output module.
  • the first input module is configured to output the first signal and the first reference signal to the first node and the second node respectively under the control of the first clock signal, and output the first clock signal under the control of the first node Going to the second node;
  • the second input module is configured to output the second signal and the first reference signal to the third node and the fourth node respectively under the control of the first clock signal, and under the control of the third node, the first The clock signal is output to the fourth node;
  • the first control module is configured to output the first reference signal to the fifth node under the control of the second node and the second clock signal, and output the second reference signal under the control of the first node Go to the fifth node;
  • the second control module is configured to output the second reference signal to the third node under the control of the fourth node, the first node, and the fifth node;
  • the illuminating signal output module is used in the first node and the first node Under the control of five nodes, the first reference signal or the second reference signal is output to the
  • each module outputs a corresponding signal under the control of the respective control signal terminals, and can realize the output of the scan signal and the illuminating signal; at the same time, the illuminating signal output module and the scan signal output module are combined. Therefore, the illuminating shift register unit and the scan shift register unit can be integrated into one circuit structure, and the number of control clocks is reduced; and the illuminating signal output module and the scan signal output in the shift register unit provided by the embodiment of the invention are provided. Modules can be driven synchronously.
  • the illuminating signal output module can continuously output the signal of the first reference signal end or output the signal of the second reference signal end, and control the The potentials of the three nodes and the fourth node enable the scan signal output module to continuously output the signal of the second reference signal end or output the signal of the second clock signal end, so that the output of the illumination signal having multiple pulse widths, that is, the illumination shift register
  • the shift register unit proposed in the embodiment of the present invention is a period normally open shift register unit, that is, the illuminating signal is in an active level state for a majority of time in one frame time.

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Abstract

一种移位寄存器单元、栅极驱动电路、显示面板及显示装置，该移位寄存器单元将发光信号输出模块（05）和扫描信号输出模块（06）相结合，即，将发光移位寄存器单元和扫描移位寄存器单元整合在一个电路结构中，减少所需的时钟信号的数量。且该移位寄存器单元中的发光信号输出模块（05）和扫描信号输出模块（06）可以被同步驱动。通过控制第一节点（P1）和第五节点（P5）的电位使发光信号输出模块（05）持续输出第一参考信号端的信号（VGL）或输出第二参考信号端的信号（VGH），通过控制第三节点（P3）和第四节点（P4）的电位使扫描信号输出模块（06）持续输出第二参考信号端的信号（VGH）或输出第二时钟信号端的信号（CLK2），这样可实现输出具有多个脉宽的发光信号，即实现了发光信号的占空比控制。

Description

移位寄存器单元、栅极驱动电路、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、栅极驱动电路、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器是当今平板显示器研究领域的热点之一。与液晶显示器相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，目前，在手机、PDA、数码相机等显示领域OLED显示屏已经开始取代传统的LCD显示屏。有机发光显示面板需要集成电路(IC，Integrated Circuit)的控制，例如，栅极驱动电路控制显示面板以实现逐行扫描和逐帧刷新的功能，使得输入到显示面板的图像数据能够实时刷新，从而实现动态显示。发光驱动电路用于向显示面板输入发光信号，从而控制各像素中的OLED在发光阶段发光。通常，栅极驱动电路和发光驱动电路是分别独立设计的单独电路，栅极驱动电路包括多个扫描移位寄存器单元，发光驱动电路包括多个发光移位寄存器单元。
发明内容
本发明的一个实施例提供了一种移位寄存器单元，该移位寄存器单元包括第一输入模块、第二输入模块、第一控制模块、第二控制模块、发光信号输出模块和扫描信号输出模块。第一输入模块的第一控制端和第一输入端分别与第一时钟信号相连，第二控制端和第一输出端分别与第一节点相连，第二输入端与第一信号相连，第三输入端与第一参考信号相连，第二输出端与第二节点相连；所述第一输入模块用于在所述第一时钟信号的控制下，将所述第一信号和所述第一参考信号分别输出到所述第一节点和所述第二节点，在所述第一节点的控制下，将所述第一时钟信号输出到所述第二节点。第二输入模块的第一控制端和第一输入端分别与所述第一时钟信号相连，第二控制端和第一输出端分别与第三节点相连，第二输入端与第二信号相连，第三输入端与所述第一参考信号相连，第二输出端与第四节点相连；所述 第二输入模块用于在所述第一时钟信号的控制下，将所述第二信号和所述第一参考信号分别输出到所述第三节点和所述第四节点，在所述第三节点的控制下，将所述第一时钟信号输出到所述第四节点。所述第一控制模块的第一控制端与所述第二节点相连，第二控制端与第二时钟信号相连，第三控制端与所述第一节点相连，第一输入端与第二参考信号相连，第二输入端与所述第一参考信号相连，输出端与第五节点相连；所述第一控制模块用于在所述第二节点和所述第二时钟信号的控制下将所述第一参考信号输出到所述第五节点，在所述第一节点的控制下将所述第二参考信号输出到所述第五节点。第二控制模块的第一控制端与所述第四节点相连，第二控制端与所述第一节点相连，第三控制端与所述第五节点相连，输入端与所述第二参考信号相连，输出端与所述第三节点相连；所述第二控制模块用于在所述第四节点、所述第一节点和所述第五节点的控制下，将所述第二参考信号输出到所述第三节点。发光信号输出模块的第一控制端与所述第一节点相连，第二控制端与所述第五节点相连，第一输入端与所述第一参考信号相连，第二输入端与所述第二参考信号相连，所述发光信号输出模块包括发光信号输出端；所述发光信号输出模块用于在所述第一节点和所述第五节点的控制下，将所述第一参考信号或所述第二参考信号输出到所述发光信号输出端。扫描信号输出模块的第一控制端与所述第三节点相连，第二控制端与所述第四节点相连，第一输入端与所述第二参考信号相连，第二输入端与所述第二时钟信号相连，所述扫描信号输出模块包括扫描信号输出端；所述扫描信号输出模块用于在所述第三节点和所述第四节点的控制下，将所述第二参考信号或所述第二时钟信号输出到所述扫描信号输出端。
在一个实施例中，发光信号输出模块包括第一输出单元和第二输出单元。所述第一输出单元具有作为所述发光信号输出模块的第二控制端的控制端，和作为所述发光信号输出模块的第二输入端的输入端，所述第一输出单元用于在所述第五节点的控制下，将所述第二参考信号输出到所述发光信号输出端。所述第二输出单元具有作为所述发光信号输出模块的第一控制端的控制端，和作为所述发光信号输出模块的第一输入端的输入端，所述第二输出单元用于在所述第一节点的控制下，将所述第一参考信号输出到所述发光信号输出端。
在一个实施例中，所述第一输出单元包括第一开关晶体管和第一电容，第一开关晶体管的栅极与所述第五节点相连，源极与所述第二参考信号相连，漏极与所述发光信号输出端相连，所述第一电容连接于所述第二参考信号和所述第五节点之间。
在一个实施例中，所述第二输出单元包括第二开关晶体管和第二电容，所述第二开关晶体管的栅极与所述第一节点相连，源极与所述第一参考信号相连，漏极与所述发光信号输出端相连，所述第二电容连接于所述第一节点和所述发光信号输出端之间。
在一个实施例中，所述扫描信号输出模块包括第三输出单元和第四输出单元。所述第三输出单元具有作为所述扫描信号输出模块的第二控制端的控制端，和作为所述扫描信号输出模块的第一输入端的输入端，所述第三输出单元用于在所述第四节点的控制下，将所述第二参考信号输出到所述扫描信号输出端。所述第四输出单元具有作为所述扫描信号输出模块的第一控制端的控制端，和作为所述扫描信号输出模块的第二输入端的输入端，所述第四输出单元用于在所述第三节点的控制下，将所述第二时钟信号输出到所述扫描信号输出端。
在一个实施例中，所述第三输出单元包括第三开关晶体管和第三电容，所述第三开关晶体管的栅极与所述第四节点相连，源极与所述第二参考信号相连，漏极与所述扫描信号输出端相连，所述第三电容连接于所述第四节点和所述第二参考信号端之间。
在一个实施例中，所述第四输出单元包括第四开关晶体管和第四电容，所述第四开关晶体管的栅极与所述第三节点相连，源极与所述第二时钟信号相连，漏极与所述扫描信号输出端相连，所述第四电容连接于所述第三节点和所述扫描信号输出端之间。
在一个实施例中，所述第一控制模块包括第一控制单元和第二控制单元。所述第一控制单元具有分别作为所述第一控制模块的第一控制端和第二控制端的第一控制端和第二控制端，以及作为所述第一控制模块的第二输入端的输入端，所述第一控制单元用于在所述第二节点和所述第二时钟信号的控制下，将所述第一参考信号输出到所述第五节点。所述第二控制单元具有作为所述第一控制模块的第三控制端的控制端和作为所述第一控制模块的第一输入端的输入端，所述第二控制单元用于在所述第一节点的控制下，将所述第二参考信号输出到 所述第五节点。
在一个实施例中，所述第一控制单元包括第五开关晶体管、第六开关晶体管和第五电容。所述第五开关晶体管的栅极与所述第二节点相连，源极与所述第一参考信号相连，漏极与所述第六开关晶体管的源极相连，所述第六开关晶体管的栅极与所述第二时钟信号相连，漏极与所述第五节点相连。所述第五电容连接于所述第二节点和所述第二时钟信号之间。
在一个实施例中，所述第二控制单元包括第七开关晶体管，所述第七开关晶体管的栅极与所述第一节点相连，源极与所述第二参考信号相连，漏极与所述第五节点相连。
在一个实施例中，所述第一输入模块包括第一输入单元和第二输入单元。所述第一输入单元具有作为所述第一输入模块的第一控制端的控制端，作为所述第一输入模块的第三输入端的第一输入端，以及作为所述第一输入模块的第二输入端的第二输入端，所述第一输入单元用于在所述第一时钟信号的控制下，将所述第一信号和所述第一参考信号分别输出到所述第一节点和所述第二节点。所述第二输入单元具有作为所述第一输入模块的第二控制端的控制端，和作为所述第一输入模块的第一输入端的输入端，所述第二输入单元用于在所述第一节点的控制下，将所述第一时钟信号输出到所述第二节点。
在一个实施例中，所述第一输入单元包括第八开关晶体管和第九开关晶体管。所述第八开关晶体管的栅极与所述第一时钟信号相连，源极与所述第一信号相连，漏极与所述第一节点相连。所述第九开关晶体管的栅极与所述第一时钟信号相连，源极与所述第一参考信号相连，漏极与所述第二节点相连。
在一个实施例中，所述第二输入单元包括第十开关晶体管，所述第十开关晶体管的栅极与所述第一节点相连，源极与所述第一时钟信号相连，漏极与所述第二节点相连。
在一个实施例中，所述第二输入模块包括第三输入单元和第四输入单元，所述第三输入单元具有作为所述第二输入模块的第一控制端的控制端，作为所述第二输入模块的第三输入端的第一输入端与，以及作为所述第二输入模块的第二输入端的第二输入端，所述第三输入单元用于在所述第一时钟信号的控制下，将所述第二信号和所述第一 参考信号分别输出到所述第三节点和所述第四节点。所述第四输入单元具有作为所述第二输入模块的第二控制端的控制端，以及作为所述第二输入模块的第一输入端的输入端，所述第四输入单元用于在所述第三节点的控制下，将所述第一时钟信号输出到所述第四节点。
在一个实施例中，所述第三输入单元包括第十一开关晶体管和第十二开关晶体管。所述第十一开关晶体管的栅极与所述第一时钟信号相连，源极与所述第二信号相连，漏极与所述第三节点相连，所述第十二开关晶体管的栅极与所述第一时钟信号相连，源极与所述第一参考信号相连，漏极与所述第四节点相连。
在一个实施例中，所述第四输入单元包括第十三开关晶体管，所述第十三开关晶体管的栅极与所述第三节点相连，源极与所述第一时钟信号相连，漏极与所述第四节点相连。
在一个实施例中，所述第二控制模块包括第十四开关晶体管、第十五开关晶体管和第十六开关晶体管，其中，所述第十四开关晶体管的栅极与所述第四节点相连，源极与所述第二参考信号相连，漏极分别与所述第十五开关晶体管的源极和第十六开关晶体管的源极相连，所述第十五开关晶体管的栅极与所述第一节点相连，漏极与所述第三节点相连，所述第十六开关晶体管的栅极与所述第五节点相连，漏极与所述第三节点相连。
本发明的另一实施例提供了一种栅极驱动电路，其可包括包括级联的多个如前述实施例中的任一实施例所述的移位寄存器单元。除最后一个移位寄存器单元之外，其余每个移位寄存器单元的发光信号输出端均向与其相邻的下一级移位寄存器单元输入用于所述下一级移位寄存器单元的第一信号，扫描信号输出端均向与其相邻的下一级移位寄存器单元输入用于所述下一级移位寄存器单元的第二信号。
在一个实施例中，提供给所述级联的多个移位寄存器单元中的第一个移位寄存器单元的第一信号和第二信号分别是用于产生所述发光信号的第一触发信号和用于产生所述扫描信号的第二触发信号。
本发明的又一实施例提供了一种显示面板，其可包括本发明的上述实施例所述的栅极驱动电路。
本发明的又一实施例提供了一种显示装置，其可包括如本发明的上述实施例所述的显示面板。
本发明实施例提供了一种移位寄存器单元、栅极驱动电路、显示面板及显示装置。该移位寄存器单元包括第一输入模块、第二输入模块、第一控制模块、第二控制模块、发光信号输出模块和扫描信号输出模块。第一输入模块用于在第一时钟信号端控制下，将第一信号和第一参考信号端分别输出到第一节点和所述第二节点，在第一节点的控制下，将第一时钟信号输出到第二节点；第二输入模块用于在第一时钟信号控制下，将第二信号和第一参考信号分别输出到第三节点和第四节点，在第三节点的控制下，将第一时钟信号输出到第四节点；第一控制模块用于在第二节点和第二时钟信号的控制下将第一参考信号输出到第五节点，在第一节点的控制下将第二参考信号输出到第五节点；第二控制模块用于在第四节点、第一节点和第五节点的控制下，将第二参考信号输出到第三节点；发光信号输出模块用于在第一节点和第五节点的控制下，将第一参考信号或第二参考信号输出到发光信号输出端；扫描信号输出模块用于在第三节点和第四节点的控制下，将第二参考信号或第二时钟信号输出到扫描信号输出端。
因此，对于本发明实施例提供的上述移位寄存器单元，各模块在各自的控制信号的控制下输出对应的信号，可以实现扫描信号和发光信号的输出。同时，发光信号输出模块和扫描信号输出模块相结合，并且发光信号输出模块和扫描信号输出模块可以被同步驱动，即，可以实现将发光移位寄存器单元和扫描移位寄存器单元整合在一个电路结构中，从而减少了所需要的时钟信号的数量。而且，本发明实施例提供的移位寄存器单元周期常开型移位寄存器单元，即，在一帧的时间内，发光信号大部分时间处于有效电平状态。通过控制第一节点和第五节点的电位，发光信号输出模块可以持续输出第一参考信号或第二参考信号，通过控制第三节点和第四节点的电位，扫描信号输出模块可以持续输出第二参考信号或第二时钟信号，这样可以实现输出具有多个脉宽的发光信号即，在将发光移位寄存器单元与扫描移位寄存器单元整合到一个电路结构中的同时，实现了发光信号的占空比控制。
附图说明
图1示意性地示出了本发明实施例提供的移位寄存器单元的结构框图；
图2示意性地示出了本发明实施例提供的移位寄存器单元的具体电路；
图3为本发明实施例提供的移位寄存器单元的工作时序图；
图4为本发明实施例提供的栅极驱动电路的结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的移位寄存器单元、栅极驱动电路、显示面板及显示装置的具体实施方式进行详细的说明。
本发明实施例提供了一种移位寄存器单元，如图1所示，可以包括：第一输入模块01、第二输入模块02、第一控制模块03、第二控制模块04、发光信号输出模块05和扫描信号输出模块06。
在图1所示的实施例中，第一输入模块01的第一控制端1a和第一输入端1b分别与第一时钟信号CLK1相连，第二控制端1g和第一输出端1f分别与第一节点P1相连，第二输入端1c与第一信号STVE相连，第三输入端1d与第一参考信号VGL相连，第二输出端1e与第二节点P2相连。第一输入模块01用于在第一时钟信号CLK1控制下，将第一信号STVE和第一参考信号VGL分别输出到第一节点P1和第二节点P2，在第一节点P1的控制下，将第一时钟信号CLK1输出到第二节点P2。
第二输入模块02的第一控制端2a和第一输入端2b分别与第一时钟信号CLK1相连，第二控制端2d和第一输出端2e分别与第三节点P3相连，第二输入端2f与第二信号STVG相连，第三输入端2g与第一参考信号VGL相连，第二输出端2c与第四节点P4相连。第二输入模块02用于在第一时钟信号CLK1控制下，将第二信号STVG和第一参考信号VGL分别输出到第三节点P3和第四节点P4，在第三节点P3的控制下，将第一时钟信号CLK1输出到第四节点P4。
第一控制模块03的第一控制端3f与第二节点P2相连，第二控制端3c与第二时钟信号CLK2相连，第三控制端3e与第一节点P1相连，第一输入端3b与第二参考信号VGH相连，第二输入端3a与第一参考信号VGL相连，输出端3d与第五节点P5相连。第一控制模块03用于在第二节点P2和第二时钟信号CLK2的控制下将第一参考信号VGL输出到第五节点P5，在第一节点P1的控制下将第二参考信号VGH输 出到第五节点P5。
第二控制模块04的第一控制端4b与第四节点P4相连，第二控制端4a与第一节点P1相连，第三控制端4c与第五节点P5相连，输入端4f与第二参考信号VGH相连，输出端4e与第三节点P3相连。第二控制模块04用于在第四节点P4、第一节点P1和第五节点P5的控制下，将第二参考信号VGH输出到第三节点P3。
发光信号输出模块05的第一控制端5d与第一节点P1相连，第二控制端5e与第五节点P5相连，第一输入端5b与第一参考信号VGL相连，第二输入端5a与第二参考信号VGH相连，输出端5c作为发光信号输出端用于输出发光信号EM。发光信号输出模块05用于在第一节点P1和第五节点P5的控制下，将第一参考信号VGL或第二参考信号VGH输出到发光信号输出端5c。
扫描信号输出模块06的第一控制端6b与第三节点P3相连，第二控制端6a与第四节点P4相连，第一输入端6c与第二参考信号VGH相连，第二输入端6d与第二时钟信号CLK2相连，输出端6e作为扫描信号输出端用于输出扫描信号Gate。扫描信号输出模块06用于在第三节点P3和第四节点P4的控制下，将第二参考信号VGH或第二时钟信号CLK2输出到扫描信号输出端6e。
根据本发明的移位寄存器单元的实施例，如图2所示，发光信号输出模块可以包括第一输出单元051和第二输出单元052。第一输出单元051的控制端5e与第五节点P5相连，输入端5a与第二参考信号VGH相连，输出端5c作为发光信号输出端，第一输出单元051用于在第五节点P5的控制下，将第二参考信号VGH输出到发光信号输出端5c。第二输出单元052的控制端5d与第一节点P1相连，输入端5b与第一参考信号VGL相连，输出端与发光信号输出端5c相连，第二输出单元052用于在第一节点P1的控制下，将第一参考信号VGL输出到发光信号输出端5c。由于发光信号输出模块包括第一输出单元和第二输出单元，因此，可以在第一节点的控制下通过第二输出单元持续输出第一参考信号，在第五节点的控制下通过第一输出单元输出第二参考信号。
在本发明实施例提供的移位寄存器单元中，如图2所示，第一输出单元051可以包括第一开关晶体管T1和第一电容C1。第一开关晶 体管T1的栅极与第五节点P5相连，源极与第二参考信号VGH相连，漏极与发光信号输出端相连；第一电容C1连接于第二参考信号VGH和第五节点P5之间。这样，第一开关晶体管可以在第五节点的控制下导通，从而将第二参考信号输出到发光信号输出端。
在本发明实施例提供的移位寄存器单元中，如图2所示，第二输出单元052可以包括第二开关晶体管T2和第二电容C2。第二开关晶体管T2的栅极与第一节点P1相连，源极与第一参考信号VGL相连，漏极与发光信号输出端5c相连，第二电容C2连接于第一节点P1和发光信号输出端之间。这样，第二开关晶体管可以在第一节点的控制下导通，从而将第一参考信号输出到发光信号输出端。
在本发明实施例提供的移位寄存器单元中，如图2所示，扫描信号输出模块可以包括第三输出单元061和第四输出单元062。第三输出单元061的控制端6a与第四节点P4相连，输入端6c与第二参考信号VGH相连，输出端6e作为扫描信号输出端提供扫描信号Gate。第三输出单元061用于在第四节点P4的控制下，将第二参考信号VGH输出到扫描信号输出端6e。第四输出单元062的控制端6b与第三节点P3相连，输入端6d与第二时钟信号CLK2相连，输出端连接至扫描信号输出端6e。第四输出单元062用于在第三节点P3的控制下，将第二时钟信号CLK2输出到扫描信号输出端6e。由于扫描信号输出模块包括第三输出单元和第四输出单元，因此，可以在第四节点的控制下通过第三输出单元持续输出第二参考信号，在第三节点的控制下通过第四输出单元输出第二时钟信号。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第三输出单元可以包括第三开关晶体管T3和第三电容C3。第三开关晶体管T3的栅极与第四节点P4相连，源极与第二参考信号VGH相连，漏极与扫描信号输出端相连，第三电容C3连接于第四节点P4和第二参考信号VGH之间。这样，第三开关晶体管可以在第四节点的控制下导通，从而将第二参考信号输出到扫描信号输出端。
在本发明实施例提供的上述移位寄存器单元中，如2所示，第四输出单元可以包括第四开关晶体管T4和第四电容C4。第四开关晶体管T4的栅极与第三节点P3相连，源极与第二时钟信号CLK2相连，漏极与扫描信号输出端相连，第四电容C4连接于第三节点P3和扫描 信号输出端之间。因此，第四开关晶体管可以在第三节点的控制下导通，从而将第二时钟信号输出到扫描信号输出端。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第一控制模块可以包括第一控制单元031和第二控制单元032。第一控制单元031的第一控制端3f与第二节点P2相连，第二控制端3c与第二时钟信号CLK2相连，输入端3a与第一参考信号VGL相连，输出端3d与第五节点P5相连。第一控制单元031用于在第二节点P2和第二时钟信号CLK2的控制下，将第一参考信号VGL输出到第五节点P5。第二控制单元032的控制端3e与第一节点P1相连，输入端3b与第二参考信号VGH相连，输出端与第五节点P5相连。第二控制单元032用于在第一节点P1的控制下，将第二参考信号VGH输出到第五节点P5。由于第一控制模块包括第一控制单元和第二控制单元，因此，在第二节点和第二时钟信号的控制下可以通过第一控制单元将第一参考信号输出到第五节点，在第一节点的控制下通过第二控制单元将第二参考信号输出到第五节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第一控制单元可以包括第五开关晶体管T5、第六开关晶体管T6和第五电容C5。第五开关晶体管T5的栅极与第二节点P2相连，源极与第一参考信号VGL相连，漏极与第六开关晶体管T6的源极相连；第六开关晶体管T6的栅极与第二时钟信号CLK2相连，漏极与第五节点P5相连；第五电容C5连接于第二节点P2和第二时钟信号CLK2之间。因此，第五开关晶体管可以在第二节点的控制下导通，进而将第一参考信号输出到第六开关晶体管的源极；第六开关晶体管可以在第二时钟信号的控制下导通，进而将其源极的信号输出到第五节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第二控制单元可以包括第七开关晶体管T7。第七开关晶体管T7的栅极与第一节点P1相连，源极与第二参考信号VGH相连，漏极与第五节点P5相连。这样，第七开关晶体管可以在第一节点的控制下导通，进而将第二参考信号输出到第五节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第一输入模块可以包括第一输入单元011和第二输入单元012。第一输入单元011的控制端1a与第一时钟信号CLK1相连，第一输入端1d与 第一参考信号VGL相连，第二输入端1c与第一信号STVE相连，第一输出端1f与第一节点P1相连，第二输出端1e与第二节点P2相连。第一输入单元011用于在第一时钟信号CLK1的控制下，将第一信号STVE和第一参考信号VGL分别输出到第一节点P1和第二节点P2。第二输入单元012的控制端1g与第一节点P1相连，输入端1b与第一时钟信号CLK1相连，输出端与第二节点P2相连。第二输入单元012用于在第一节点P1的控制下，将第一时钟信号CLK1输出到第二节点P2。由于第一输入模块包括第一输入单元和第二输入单元，因此，可以在第一时钟信号的控制下可以通过第一输入单元将第一信号和第一参考信号分别输出到第一节点和第二节点，在第一节点的控制下通过第二输入单元将第一时钟信号输出到第二节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第一输入单元011可以包括第八开关晶体管T8和第九开关晶体管T9。第八开关晶体管T8的栅极与第一时钟信号CLK1相连，源极与第一信号STVE相连，漏极与第一节点P1相连；第九开关晶体管T9的栅极与第一时钟信号CLK1相连，源极与第一参考信号VGL相连，漏极与第二节点P2相连。这样，第八开关晶体管可以在第一时钟信号的控制下导通，进而将第一信号输出到第一节点，第九开关晶体管可以在第一时钟信号的控制下导通，进而将第一参考信号输出到第二节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第二输入单元可以包括第十开关晶体管T10。第十开关晶体管T10的栅极与第一节点P1相连，源极与第一时钟信号CLK1相连，漏极与第二节点P2相连。这样，第十开关晶体管可以在第一节点的控制下导通，进而将第一时钟信号输出到第二节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第二输入模块可以包括第三输入单元021和第四输入单元022。第三输入单元021的控制端2a与第一时钟信号CLK1相连，第一输入端2g与第一参考信号VGL相连，第二输入端2f与第二信号STVG相连，第一输出端2e与第三节点P3相连，第二输出端2c与第四节点P4相连。第三输入单元021用于在第一时钟信号CLK1的控制下，将第二信号STVG和第一参考信号VGL分别输出到第三节点P3和第四节点P4。第四输入单元022的控制端2d与第三节点P3相连，输入端2b与第一 时钟信号CLK1相连，输出端与第四节点P4相连。第四输入单元022用于在第三节点P3的控制下，将第一时钟信号CLK1输出到第四节点P4。由于第二输入模块可以包括第三输入单元和第四输入单元，因此，可以在第一时钟信号的控制下通过第三输入单元将第二信号和第一参考信号分别输出到第三节点和第四节点，在第三节点的控制下通过第四输入单元将第一时钟信号输出到第四节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第三输入单元可以包括第十一开关晶体管T11和第十二开关晶体管T12。第十一开关晶体管T11的栅极与第一时钟信号CLK1相连，源极与第二信号STVG相连，漏极与第三节点P3相连；第十二开关晶体管T12的栅极与第一时钟信号CLK1相连，源极与第一参考信号VGL相连，漏极与第四节点P4相连。这样，第十一开关晶体管可以在第一时钟信号的控制下导通，，进而将第二信号输出到第三节点；第十二开关晶体管可以在第一时钟信号的控制下导通，进而将第一参考信号输出到第四节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第四输入单元可以包括第十三开关晶体管T13。第十三开关晶体管T13的栅极与第三节点P3相连，源极与第一时钟信号CLK1相连，漏极与第四节点P4相连。这样，第十三开关晶体管可以在第三节点的控制下导通，进而将第一时钟信号输出到第四节点。
在本发明实施例提供的上述移位寄存器单元中，如图2所示，第二控制模块可以包括第十四开关晶体管T14、第十五开关晶体管T15和第十六开关晶体管T16。第十四开关晶体管T14的栅极与第四节点P4相连，源极与第二参考信号VGH相连，漏极分别与第十五开关晶体管T15的源极和第十六开关晶体管T16的源极相连；第十五开关晶体管T15的栅极与第一节点P1相连，漏极与第三节点P3相连；第十六开关晶体管T16的栅极与第五节点P5相连，漏极与第三节点P3相连。这样，第十四开关晶体管可以在第四节点的控制下导通，进而将第二参考信号分别输出到第十五开关晶体管的源极和第十六开关晶体管的源极；第十五开关晶体管可以在第一节点的控制下导通，从而将其源极的信号输出到第三节点；第十六开关晶体管可以在第五节点的控制下导通，从而将其源极的信号输出到第三节点。
需要说明的是本发明上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。在本发明的实施例中，这些晶体管的源极和漏极可以互换，不做具体区分。在描述具体实施例时以薄膜晶体管为例进行说明。
此外，对于本发明各实施例提供的移位寄存器单元，所提到的第一参考信号VGL可以是具有低电压水平的信号，第二参考信号VGH可以是具有高电压水平的信号。第一信号STVE可以是用于产生发光信号EM的第一触发信号，第二信号STVG可以是用于产生扫描信号Gate的第二触发信号。
下面结合本发明实施例提供的移位寄存器单元电路结构和工作时序对本发明实施例提供的移位寄存器单元的工作过程进行详细描述。以如图2所示的采用P型晶体管设计的移位寄存器单元为例，结合图3所示时序图，对本发明实施例提供的移位寄存器单元的工作过程予以描述。如图3所示，移位寄存器单元的信号时序图包括t1～t8八个阶段。在下述描述中，以1表示高电平信号，0表示低电平信号。
在t1阶段，STVE＝0，STVG＝1，CLK1＝0，CLK2＝1，VGL＝0，VGH＝1。由于CLK1＝0，因此，第八开关晶体管T8、第九开关晶体管T9、第十一开关晶体管T11和第十二开关晶体管T12导通。相应地，第一信号STVE经由导通的第八开关晶体管T8被输出到第一节点P1，此时由于STVE＝0，因此第二开关晶体管T2、第七开关晶体管T7、第十开关晶体管T10和第十五开关晶体管T15导通。第一参考信号VGL经由导通的第二开关晶体管T2被提供至发光信号输出端，由于VGL＝0，因此使得发光信号输出端输出低电平信号。第二参考信号VGH经由导通的第七开关晶体管T7被提供至第五节点P5，进而使得第一开关晶体管T1截止；导通的第九开关晶体管T9和第十开关晶体管T10分别将第一参考信号VGL和第一时钟信号CLK1输出到第二节点P2；导通的第十一开关晶体管T11将第二信号STVG提供至第三节点P3，由于STVG＝1，进而第四开关晶体管T4在第三节点P3的控制下截止；导通的第十二开关晶体管T12将第一参考信号VGL提供至第四节点P4，进而第三开关晶体管T3在第四节点P4的控制下导通，使得第二参考信号VGH经由导通的第三开关晶体管T3被提供至扫描信号输出 端，由于VGH＝1，因此使得扫描信号输出端输出高电平信号。同时第十四开关晶体管T14在第四节点P4的控制下也处于导通状态，所以第二参考信号VGH经由导通的第十四开关晶体管T14与导通的第十五开关晶体管T15被提供至第三节点P3，使第三节点P3保持高电位。在t1阶段的后半段，第一信号STVE、第二信号STVG和第二时钟信号CLK2不变，第一时钟信号CLK1由低电平信号变为高电平信号，此时，由于电容器C2的存在，第一节点P1的电位可维持低电平，因此，第十开关晶体管T10可将第一时钟信号CLK1的高电平信号输出到第二节点P2，使得第五开关晶体管T5处于截止状态。
在t2阶段，STVE＝0，STVG＝1，CLK1＝1，CLK2＝0，VGL＝0，VGH＝1。由于CLK2＝0，因此，第六开关晶体管T6导通。由于在t1阶段的后半段第二节点P2的电位处于高电平，使得第五开关晶体管T5处于截止状态，因此，在t2阶段第二节点P2的电位由于第五电容C5的作用而保持于高电位，第一参考信号端VGL的信号不会通过第五开关晶体管T5和第六开关晶体管T6而输出到第五节点P5。第一节点P1保持上一阶段的低电位，第二开关晶体管T2和第七晶体管T7处于导通状态，第五节点P5的电位为高电平VGH，第一开关晶体管T1仍处于截止状态，从而发光信号输出端仍输出第一参考信号VGL。同时，第四节点P4保持处于上一阶段的低电位，因此第三开光晶体管T3处于导通状态，扫描信号输出端输出第二参考信号VGH。
在t3阶段，STVE＝1，STVG＝0，CLK1＝0，CLK2＝1，VGL＝0，VGH＝1。由于CLK1＝0，因此，第八开关晶体管T8、第九开关晶体管T9、第十一开关晶体管T11和第十二开关晶体管T12导通。相应地，第一信号STVE经由导通的第八开关晶体管T8被提供至第一节点P1，此时由于STVE＝1，因此第二开关晶体管T2、第七开关晶体管T7、第十开关晶体管T10和第十五开关晶体管T15截止。导通的第九开关晶体管T9将第一参考信号VGL提供至第二节点P2，由于VGL＝0，因此使得第五开关晶体管T5导通，由于此时CLK2＝1，因此第六开关晶体管T6截止。导通的第十一开关晶体管T11将第二信号STVG提供至第三节点P3，由于STVG＝0，进而第四开关晶体管T4和第十三开关晶体管T13在第三节点P3的控制下导通。导通的第四开关晶体管T4将第二时钟信号端CLK2提供至扫描信号输出端，由于此时CLK2＝1，进 而使得扫描信号输出端输出高电平信号；同时，导通的第十三开关晶体管T13将第一时钟信号CLK1提供至第四节点P4，由于此时CLK1＝0，因此第三开关晶体管T3在第四节点P4的控制下导通，进而将第二参考信号VGH提供至扫描信号输出端，由于VGH＝1，因此使得扫描信号输出端输出高电平信号。在此阶段期间，由于第一节点P1和第五节点P5均为高电位，因此第一开关晶体管T1和第二开关晶体管T2均处于截止状态，发光信号输出端保持上一阶段的输出状态，即输出低电平信号。
在t4阶段，STVE＝1，STVG＝1，CLK1＝1，CLK2＝0，VGL＝0，VGH＝1。由于CLK2＝0，因此，第六开关晶体管T6导通，此时，第二节点P2由于第五电容C5的作用保持上一阶段的低电位，因此第五开关晶体管T5处于导通状态，从而第一参考信号端VGL的信号经由导通的第五开关晶体管T5和第六开关晶体管T6输出到第五节点P5，因此第一开关晶体管T1在第五节点P5的控制下导通，进而将第二参考信号VGH输出到发光信号输出端；此时，由于第二时钟信号端CLK2的信号由高电平变为低电平，因此第四开关晶体管T4通过栅源之间的耦合电容(即，第四电容C4)的自举作用，将第三节点P3的电位进一步拉低，因此第四开关晶体管T4在第三节点P3的控制下导通，进而将第二时钟信号CLK2输出到扫描信号输出端，由于此时CLK2＝0，因此扫描信号输出端输出低电平信号，同时第十三开关晶体管T13在第三节点P3的控制下导通，将第一时钟信号CLK1输出到第四节点P4，此时CLK1＝1，因此保持第四节点P4的电位为高电位，使第三开关晶体管T3处于截止状态。
在t5阶段，STVE＝1，STVG＝1，CLK1＝0，CLK2＝1，VGL＝0，VGH＝1。由于CLK1＝0，因此，第八开关晶体管T8、第九开关晶体管T9、第十一开关晶体管T11和第十二开关晶体管T12导通。导通的第八开关晶体管T8将第一信号STVE输出到第一节点P1，此时由于STVE＝1，因此第二开关晶体管T2、第七开关晶体管T7、第十开关晶体管T10和第十五开关晶体管T15截止；导通的第九开关晶体管T9将第一参考信号VGL输出到第二节点P2；导通的第十一开关晶体管T11将第二信号STVG输出到第三节点P3，此时STVG＝1，因此第十三开关晶体管T13和第四开关晶体管T4截止。导通的第十二开关晶体管T12 将第一参考信号VGL输出到第四节点P4，因此第三开关晶体管T3和第十四开关晶体管T14导通，导通的第三开关晶体管T3将第二参考信号VGH输出到扫描信号输出端。同时第五节点P5保持上一阶段的低电位，因此第一开关晶体管T1和第十六开关晶体管T 16导通，导通的第一开关晶体管T1将第二参考信号VGH输出到发光信号输出端，同时第二参考信号VGH通过导通的第十四开关晶体管T14和第十六开关晶体管T16输出到第三节点P3，进一步保持第三节点P3的高电位。
在t6阶段，STVE＝0，STVG＝1，CLK1＝1，CLK2＝0，VGL＝0，VGH＝1。由于CLK2＝0，因此第六开关晶体管T6导通，此时第二节点P2由于第五电容C5的作用保持处于上一阶段的低电位，因此第五开关晶体管T5导通，第一参考信号VGL通过导通的第五开关晶体管T5和第六开关晶体管T6输出到第五节点P5，因此第一开关晶体管T1和第十六开关晶体管T16导通，导通的第一开关晶体管T1将第二参考信号VGH输出到发光信号输出端；同时第四节点P4保持上一阶段的低电位，因此第三开关晶体管T3和第十四开关晶体管T14导通，导通的第三开关晶体管T3将第二参考信号VGH输出到扫描信号输出端，且第二参考信号VGH通过导通的第十四开关晶体管T14和第十六开关晶体管T16输出到第三节点P3，进一步保持第三节点P3的高电位。
在t7阶段，STVE＝0，STVG＝1，CLK1＝0，CLK2＝1，VGL＝0，VGH＝1。由于CLK1＝0，因此第八开关晶体管T8、第九开关晶体管T9、第十一开关晶体管T11和第十二开关晶体管T12导通；导通的第八开关晶体管T8将第一信号STVE输出到第一节点P1，此时由于STVE＝0，因此第二开关晶体管T2、第七开关晶体管T7、第十开关晶体管T10和第十五开关晶体管T15导通。导通的第二开关晶体管T2将第一参考信号VGL提供至发光信号输出端，使得发光信号输出端输出低电平信号；导通的第七开关晶体管T7将第二参考信号VGH提供至第五节点P5，进而使得第一开关晶体管T1截止；导通的第九开关晶体管T9和第十开关晶体管T10分别将第一参考信号VGL和第一时钟信号CLK1输出到第二节点P2；导通的第十一开关晶体管T11将第二信号STVG提供至第三节点P3，由于STVG＝1，进而第四开关晶体管T4在第三节点P3的控制下截止；导通的第十二开关晶体管T12将第一参考信号VGL提供至第四节点P4，进而第三开关晶体管T3导通，而导通的第 三开关晶体管T3将第二参考信号VGH提供至扫描信号输出端，由于VGH＝1，因此使得扫描信号输出端输出高电平信号。同时，第十四开关晶体管T14在第四节点P4的控制下也处于导通状态，导通的第十四开关晶体管T14与导通的第十五开关晶体管T15将第二参考信号VGH提供至第三节点P3，使第三节点P3保持高电位。在t7阶段的后半段，第一信号STVE、第二信号STVG和第二时钟信号CLK2不变，第一时钟信号CLK1由低电平信号变为高电平信号，此时，第一时钟信号CLK1的高电平信号经由导通的第十开关晶体管T10而输出到第二节点P2，从而使得第五开关晶体管T5处于截止状态。
在t8阶段，STVE＝0，STVG＝1，CLK1＝1，CLK2＝0，VGL＝0，VGH＝1。由于CLK2＝0，因此，第六开关晶体管T6导通；由于在t7阶段的后半段，第二节点P2的电位处于高电平，第五开关晶体管T5处于截止状态，因此在t8阶段，第二节点P2的电位由于第五电容C5的作用保持高电位，因此第一参考信号VGL不会通过第五开关晶体管T5和第六开关晶体管T6而输出到第五节点P5，而第一节点P1保持上一阶段的低电位，第二开关晶体管T2和第七晶体管T7处于导通状态，第五节点P5的电位等于高电平VGH，第一开关晶体管T1仍处于截止状态，从而发光信号输出端仍输出第一参考信号VGL；同时，第四节点P4保持上一阶段的低电位，因此第三开光晶体管T3处于导通状态，扫描信号输出端输出第二参考信号VGH。
在之后的阶段中，在第一信号STVE保持低电平时，将不断重复t7和t8的工作状态。当第一信号STVE再次变成高电平信号时，将重复t3，t4，t5阶段的过程，直到第一信号STVE由高电平信号再次变为低电平信号。之后，将在完成t6阶段的过程后重复t7和t8阶段的过程。在t3阶段期间，第一信号STVE一直为高电平信号，第二时钟信号CLK2处于高电平状态，第二信号STVG、第一时钟信号CLK1处于低电平状态，所以，受第一时钟信号CLK1控制的第八开关晶体管T8、第九开关晶体管T9、第十一开关晶体管T11和第十二开关晶体管T12导通；导通的第十二开关晶体管T12将第一参考信号VGL写入到第四节点P4，进而将第三开关晶体管T3导通，从而将第二参考信号VGH输出到扫描信号输出端，同时第二信号STVG的低电平信号输出到第三节点P3，使第十三开关晶体管T13和第四开关晶体管T4处于导通状态， 导通的第四开关晶体管T4将第二时钟信号CLK2提供到扫描信号输出端，由于此时CLK2＝1，进而使得扫描信号输出端输出高电平信号。由于第八开关晶体管T8导通，第一信号STVE被提供到第一节点P1，此时STVE＝1，使得第一节点P1为高电位，因此第二开关晶体管T2截止。且由于第五节点P5保持上一阶段的高电位，因此第一开关晶体管T1处于截止状态，发光信号输出端保持上一阶段的输出状态，即输出低电平信号。紧接着t3阶段的是t4和t5阶段，其间发光信号输出端持续输出第二参考信号VGH的高电平信号。这样，就实现了发光信号输出端输出具有多个脉冲宽度的发光信号，即实现了发光信号的占空比控制。
基于同一发明构思，本发明的另一实施例提供了一种栅极驱动电路，包括级联的多个本发明的上述实施例中任一实施例提供的移位寄存器单元，除最后一个移位寄存器单元之外，其余每个移位寄存器单元的发光信号输出端均向与其相邻的下一级移位寄存器单元输入用于该下一级移位寄存器单元的第一信号，扫描信号输出端均向与其相邻的下一级移位寄存器单元输入用于该下一级移位寄存器单元的第二信号。
为了方便说明，图4中仅示出了八个移位寄存器单元，分别为第1级移位寄存器单元、第2级移位寄存器单元、第3级移位寄存器单元、第4级移位寄存器单元、第N-3级移位寄存器单元、第N-2级移位寄存器单元、第N-1级移位寄存器单元、第N级移位寄存器单元。第N-1级移位寄存器单元的发光信号输出端的发光信号EM被提供给第N级移位寄存器单元作为用于第N级移位寄存器单元的第一信号，扫描信号输出端的扫描信号Gate被提供给第N级移位寄存器单元作为用于第N级移位寄存器单元的第二信号。第一时钟信号CLK1和第二时钟信号CLK2在相邻的下一级中的连接位置和本级中的连接位置互换。例如，对于图2所示的实施例，对于第N级移位寄存器单元，第一时钟信号CLK1连接至控制端1a，第二时钟信号CLK2连接至输入端6d，则对于第N+1级移位寄存器单元而言，第一时钟信号CLK1连接至输入端6d，第二时钟信号CLK2连接至控制端1a，从而实现自上而下的移位效果。
基于同一发明构思，本发明的另外的实施例提供了一种显示面板， 包括本发明上述实施例提供的栅极驱动电路。由于该显示面板解决问题的原理与栅极驱动电路相似，因此该显示面板的实施可以参见上述栅极驱动电路的实施，重复之处不再赘述。
基于同一发明构思，本发明的另外实施例提供了一种显示装置，包括本发明上述实施例提供的显示面板。该显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与显示面板相似，因此该显示装置的实施可以参见上述显示面板的实施，重复之处不再赘述。
本发明实施例提供了一种移位寄存器单元、栅极驱动电路、显示面板及显示装置移位寄存器单元。该移位寄存器单元包括第一输入模块、第二输入模块、第一控制模块、第二控制模块、发光信号输出模块和扫描信号输出模块。第一输入模块用于在第一时钟信号控制下，将第一信号和第一参考信号分别输出到第一节点和所述第二节点，在第一节点的控制下，将第一时钟信号输出到第二节点；第二输入模块用于在第一时钟信号控制下，将第二信号和第一参考信号分别输出到第三节点和第四节点，在第三节点的控制下，将第一时钟信号输出到第四节点；第一控制模块用于在第二节点和第二时钟信号的控制下将第一参考信号输出到第五节点，在第一节点的控制下将第二参考信号输出到第五节点；第二控制模块用于在第四节点、第一节点和第五节点的控制下，将第二参考信号输出到第三节点；发光信号输出模块用于在第一节点和第五节点的控制下，将第一参考信号或第二参考信号输出到发光信号输出端；扫描信号输出模块用于在第三节点和第四节点的控制下，将第二参考信号或第二时钟信号输出到扫描信号输出端。
对于本发明实施例提供的上述移位寄存器单元，各模块在各自的控制信号端的控制下输出对应的信号，可以实现扫描信号和发光信号的输出；同时发光信号输出模块和扫描信号输出模块相结合，从而可以实现将发光移位寄存器单元和扫描移位寄存器单元整合在一个电路结构中，减少控制时钟的数量；且本发明实施例提供的移位寄存器单元中的发光信号输出模块和扫描信号输出模块可以被同步驱动。通过控制第一节点和第五节点的电位，使得发光信号输出模块可以持续输出第一参考信号端的信号或输出第二参考信号端的信号，通过控制第 三节点和第四节点的电位，使得扫描信号输出模块可以持续输出第二参考信号端的信号或输出第二时钟信号端的信号，这样可以实现输出具有多个脉冲宽度的发光信号，即将发光移位寄存器单元与扫描移位寄存器单元整合到一个电路结构中的前提下，实现了发光信号占空比控制。因此，本发明实施例所提出的移位寄存器单元是周期常开型移位寄存器单元，即，在一帧的时间内，发光信号大部分时间处于有效电平状态。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (21)

  1. 一种移位寄存器单元，包括：第一输入模块、第二输入模块、第一控制模块、第二控制模块、发光信号输出模块和扫描信号输出模块，其中，所述第一输入模块的第一控制端和第一输入端分别与第一时钟信号相连，第二控制端和第一输出端分别与第一节点相连，第二输入端与第一信号相连，第三输入端与第一参考信号相连，第二输出端与第二节点相连；所述第一输入模块用于在所述第一时钟信号的控制下，将所述第一信号和所述第一参考信号分别输出到所述第一节点和所述第二节点，在所述第一节点的控制下，将所述第一时钟信号输出到所述第二节点；
    所述第二输入模块的第一控制端和第一输入端分别与所述第一时钟信号相连，第二控制端和第一输出端分别与第三节点相连，第二输入端与第二信号相连，第三输入端与所述第一参考信号相连，第二输出端与第四节点相连；所述第二输入模块用于在所述第一时钟信号的控制下，将所述第二信号和所述第一参考信号分别输出到所述第三节点和所述第四节点，在所述第三节点的控制下，将所述第一时钟信号输出到所述第四节点；
    所述第一控制模块的第一控制端与所述第二节点相连，第二控制端与第二时钟信号相连，第三控制端与所述第一节点相连，第一输入端与第二参考信号相连，第二输入端与所述第一参考信号相连，输出端与第五节点相连；所述第一控制模块用于在所述第二节点和所述第二时钟信号的控制下将所述第一参考信号输出到所述第五节点，在所述第一节点的控制下将所述第二参考信号输出到所述第五节点；
    所述第二控制模块的第一控制端与所述第四节点相连，第二控制端与所述第一节点相连，第三控制端与所述第五节点相连，输入端与所述第二参考信号相连，输出端与所述第三节点相连；所述第二控制模块用于在所述第四节点、所述第一节点和所述第五节点的控制下，将所述第二参考信号输出到所述第三节点；
    所述发光信号输出模块的第一控制端与所述第一节点相连，第二控制端与所述第五节点相连，第一输入端与所述第一参考信号相连，第二输入端与所述第二参考信号相连，所述发光信号输出模块包括发 光信号输出端；所述发光信号输出模块用于在所述第一节点和所述第五节点的控制下，将所述第一参考信号或所述第二参考信号输出到所述发光信号输出端；
    所述扫描信号输出模块的第一控制端与所述第三节点相连，第二控制端与所述第四节点相连，第一输入端与所述第二参考信号相连，第二输入端与所述第二时钟信号相连，所述扫描信号输出模块包括扫描信号输出端；所述扫描信号输出模块用于在所述第三节点和所述第四节点的控制下，将所述第二参考信号或所述第二时钟信号输出到所述扫描信号输出端。
  2. 如权利要求1所述的移位寄存器单元，其中所述发光信号输出模块包括：第一输出单元和第二输出单元；其中，
    所述第一输出单元具有作为所述发光信号输出模块的第二控制端的控制端，和作为所述发光信号输出模块的第二输入端的输入端，所述第一输出单元用于在所述第五节点的控制下，将所述第二参考信号输出到所述发光信号输出端；
    所述第二输出单元具有作为所述发光信号输出模块的第一控制端的控制端，和作为所述发光信号输出模块的第一输入端的输入端，所述第二输出单元用于在所述第一节点的控制下，将所述第一参考信号输出到所述发光信号输出端。
  3. 如权利要求2所述的移位寄存器单元，其中所述第一输出单元包括第一开关晶体管和第一电容，其中所述第一开关晶体管的栅极与所述第五节点相连，源极与所述第二参考信号相连，漏极与所述发光信号输出端相连，所述第一电容连接于所述第二参考信号和所述第五节点之间。
  4. 如权利要求2所述的移位寄存器单元，其中所述第二输出单元包括第二开关晶体管和第二电容，其中所述第二开关晶体管的栅极与所述第一节点相连，源极与所述第一参考信号相连，漏极与所述发光信号输出端相连，所述第二电容连接于所述第一节点和所述发光信号输出端之间。
  5. 如权利要求1所述的移位寄存器单元，其中所述扫描信号输出模块包括第三输出单元和第四输出单元，其中，
    所述第三输出单元具有作为所述扫描信号输出模块的第二控制端的控制端，和作为所述扫描信号输出模块的第一输入端的输入端，所述第三输出单元用于在所述第四节点的控制下，将所述第二参考信号输出到所述扫描信号输出端；
    所述第四输出单元具有作为所述扫描信号输出模块的第一控制端的控制端，和作为所述扫描信号输出模块的第二输入端的输入端，所述第四输出单元用于在所述第三节点的控制下，将所述第二时钟信号输出到所述扫描信号输出端。
  6. 如权利要求5所述的移位寄存器单元，其中所述第三输出单元包括第三开关晶体管和第三电容，其中所述第三开关晶体管的栅极与所述第四节点相连，源极与所述第二参考信号相连，漏极与所述扫描信号输出端相连，所述第三电容连接于所述第四节点和所述第二参考信号端之间。
  7. 如权利要求5所述的移位寄存器单元，其中所述第四输出单元包括第四开关晶体管和第四电容，其中所述第四开关晶体管的栅极与所述第三节点相连，源极与所述第二时钟信号相连，漏极与所述扫描信号输出端相连，所述第四电容连接于所述第三节点和所述扫描信号输出端之间。
  8. 如权利要求1所述的移位寄存器单元，其中所述第一控制模块包括第一控制单元和第二控制单元，其中，
    所述第一控制单元具有分别作为所述第一控制模块的第一控制端和第二控制端的第一控制端和第二控制端，以及作为所述第一控制模块的第二输入端的输入端，所述第一控制单元用于在所述第二节点和所述第二时钟信号的控制下，将所述第一参考信号输出到所述第五节点；
    所述第二控制单元具有作为所述第一控制模块的第三控制端的控制端和作为所述第一控制模块的第一输入端的输入端，所述第二控制单元用于在所述第一节点的控制下，将所述第二参考信号输出到所述第五节点。
  9. 如权利要求8所述的移位寄存器单元，其中所述第一控制单元包括第五开关晶体管、第六开关晶体管和第五电容，其中，
    所述第五开关晶体管的栅极与所述第二节点相连，源极与所述第一参考信号相连，漏极与所述第六开关晶体管的源极相连，
    所述第六开关晶体管的栅极与所述第二时钟信号相连，漏极与所述第五节点相连；
    所述第五电容连接于所述第二节点和所述第二时钟信号之间。
  10. 如权利要求8所述的移位寄存器单元，其中所述第二控制单元包括第七开关晶体管，所述第七开关晶体管的栅极与所述第一节点相连，源极与所述第二参考信号相连，漏极与所述第五节点相连。
  11. 如权利要求1所述的移位寄存器单元，其中所述第一输入模块包括第一输入单元和第二输入单元，其中，
    所述第一输入单元具有作为所述第一输入模块的第一控制端的控制端，作为所述第一输入模块的第三输入端的第一输入端，以及作为所述第一输入模块的第二输入端的第二输入端，所述第一输入单元用于在所述第一时钟信号的控制下，将所述第一信号和所述第一参考信号分别输出到所述第一节点和所述第二节点；
    所述第二输入单元具有作为所述第一输入模块的第二控制端的控制端，和作为所述第一输入模块的第一输入端的输入端，所述第二输入单元用于在所述第一节点的控制下，将所述第一时钟信号输出到所述第二节点。
  12. 如权利要求11所述的移位寄存器单元，其中所述第一输入单元包括第八开关晶体管和第九开关晶体管，其中，
    所述第八开关晶体管的栅极与所述第一时钟信号相连，源极与所述第一信号相连，漏极与所述第一节点相连；
    所述第九开关晶体管的栅极与所述第一时钟信号相连，源极与所述第一参考信号相连，漏极与所述第二节点相连。
  13. 如权利要求11所述的移位寄存器单元，其中所述第二输入单元包括第十开关晶体管，所述第十开关晶体管的栅极与所述第一节点相连，源极与所述第一时钟信号相连，漏极与所述第二节点相连。
  14. 如权利要求1所述的移位寄存器单元，其中所述第二输入模块包括第三输入单元和第四输入单元，其中，
    所述第三输入单元具有作为所述第二输入模块的第一控制端的控制端，作为所述第二输入模块的第三输入端的第一输入端与，以及作 为所述第二输入模块的第二输入端的第二输入端，所述第三输入单元用于在所述第一时钟信号的控制下，将所述第二信号和所述第一参考信号分别输出到所述第三节点和所述第四节点，
    所述第四输入单元具有作为所述第二输入模块的第二控制端的控制端，以及作为所述第二输入模块的第一输入端的输入端，所述第四输入单元用于在所述第三节点的控制下，将所述第一时钟信号输出到所述第四节点。
  15. 如权利要求14所述的移位寄存器单元，其中所述第三输入单元包括第十一开关晶体管和第十二开关晶体管，其中，
    所述第十一开关晶体管的栅极与所述第一时钟信号相连，源极与所述第二信号相连，漏极与所述第三节点相连，
    所述第十二开关晶体管的栅极与所述第一时钟信号相连，源极与所述第一参考信号相连，漏极与所述第四节点相连。
  16. 如权利要求14所述的移位寄存器单元，其中所述第四输入单元包括第十三开关晶体管，所述第十三开关晶体管的栅极与所述第三节点相连，源极与所述第一时钟信号相连，漏极与所述第四节点相连。
  17. 如权利要求1-16任一项所述的移位寄存器单元，其中所述第二控制模块包括第十四开关晶体管、第十五开关晶体管和第十六开关晶体管，其中，所述第十四开关晶体管的栅极与所述第四节点相连，源极与所述第二参考信号相连，漏极分别与所述第十五开关晶体管的源极和第十六开关晶体管的源极相连，所述第十五开关晶体管的栅极与所述第一节点相连，漏极与所述第三节点相连，所述第十六开关晶体管的栅极与所述第五节点相连，漏极与所述第三节点相连。
  18. 一种栅极驱动电路，包括级联的多个如权利要求1-17任一项所述的移位寄存器单元；除最后一个移位寄存器单元之外，其余每个移位寄存器单元的发光信号输出端均向与其相邻的下一级移位寄存器单元输入用于所述下一级移位寄存器单元的第一信号，扫描信号输出端均向与其相邻的下一级移位寄存器单元输入用于所述下一级移位寄存器单元的第二信号。
  19. 如权利要求18所述的栅极驱动电路，其中提供给所述级联的多个移位寄存器单元中的第一个移位寄存器单元的第一信号和第二信 号分别是用于产生所述发光信号的第一触发信号和用于产生所述扫描信号的第二触发信号。
  20. 一种显示面板，包括如权利要求19所述的栅极驱动电路。
  21. 一种显示装置，包括如权利要求20所述的显示面板。
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