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WO2017116832A1 - Appareil à micro-bobine pour compensation inductive dans des boîtiers et des cartes de circuit imprimé pour assemblages à trous d'interconnexion borgnes et enterrés - Google Patents

Appareil à micro-bobine pour compensation inductive dans des boîtiers et des cartes de circuit imprimé pour assemblages à trous d'interconnexion borgnes et enterrés Download PDF

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Publication number
WO2017116832A1
WO2017116832A1 PCT/US2016/067697 US2016067697W WO2017116832A1 WO 2017116832 A1 WO2017116832 A1 WO 2017116832A1 US 2016067697 W US2016067697 W US 2016067697W WO 2017116832 A1 WO2017116832 A1 WO 2017116832A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
micro
bga
pth
coil structure
Prior art date
Application number
PCT/US2016/067697
Other languages
English (en)
Inventor
Richard I. Mellitz
Brandon GORE
Kenneth Young
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN201680070022.2A priority Critical patent/CN108293294A/zh
Priority to DE112016006129.3T priority patent/DE112016006129T5/de
Publication of WO2017116832A1 publication Critical patent/WO2017116832A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • FIG. 1 is a schematic diagram illustrating a conventional packaging scheme for highspeed communication employing a plated through hole (PTH) electrically coupled to a BGA pad and BGA solder ball, which forms a capacitive structure;
  • PTH plated through hole
  • Figure 2a shows a side view of a PCB and package structure illustrating a plated through hole passing through a core layer of the PCB;
  • Figure2b shows a 3D view of a solid model of a pair of PTHs electrically coupled to respective BGA pads via a crankshaft structure
  • Figure 3a shows a 3D view of a solid model of a pair of PTH structures electrically coupled to respective BGA pads via crankshaft structures
  • Figure 3b shows a 3D view of solid model of a pair of PTH structures electrically coupled to respective BGA pads via micro-coil structures
  • Figure 4a shows another 3D view of solid model of a pair of PTH structures electrically coupled to respective BGA pads via micro-coil structures
  • Figure 4b shows a detailed 3D view of a portion of a solid model illustrating a 2-coil micro-coil structure, according to one embodiment
  • Figure 5 shows detailed views of six exemplary micro-coil structure configuration and a graph illustrating effective inductance levels using Ansys HFSS full wave 3D electromagnetic modeling software
  • Figure 6 is a schematic diagram illustrating a COM reference package model specified by the IEEE 802.3bj - 2014 standard
  • Figure 7a is a graph showing the results of differential injection loss test results for a COM reference package model, a COM package terminated with a PTH, crankshaft vias, and a BGA ball, and a COM package terminated with a PTH, micro-coil, and BGA ball;
  • Figure 7b is a graph showing the results of differential reflection loss test results for the COM reference package model, the COM package terminated with a PTH, crankshaft vias, and a BGA ball, and the COM package terminated with a PTH, micro-coil, and BGA ball;
  • Figure 8 is a schematic diagram of a circuit model used for an IEEE 100G BASE KR4
  • Figure 9 is a graph illustrating modeled test results for an ISI COM package with FCI short channel, an ISI plus cross-talk crankshaft terminated package with FCI short channel, and an ISI plus cross-talk micro-coil terminated package with FCI short channel;
  • Figure 10 is a cross-section view of a circuit board assembly including first and second
  • COM packages having first and second semiconductor components coupled to one another along signal paths passing through micro-coil structures formed in a PCB.
  • Embodiments of methods and apparatus for inductive compensation in packages and PCB for assemblies with blind and buried vias are described herein.
  • numerous specific details are set forth to provide a thorough understanding of embodiments of the invention.
  • One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc.
  • well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
  • FIG. 1 shows a package 100 including a PCB board 102.
  • the electrical connection between routing paths (depicted, in part, by electrical traces 105) in the PCB in the package are implemented using solder ball grid array (BGA) connections or the like, as detailed on the right-hand side of Figure 1.
  • BGA solder ball grid array
  • a component such as a semiconductor die or package (not shown), is mounted to the BGA.
  • the plated through holes (PTH) 106 used for the vias in combination with the BGA pads 108 and solder balls 110 form capacitor structures, as illustrated.
  • PTH plated through holes
  • PTH 106 functions as the top plate of the capacitor, with BGA pad 108 and solder ball 110 functioning as the bottom plate.
  • PTH 106 extends through the core layer 200 of PCB 100.
  • the bottom and top package via transition regions is referred to herein as the "crankshaft via area" 202 as shown in the 3D detail view of Figure 2b.
  • bottom crankshaft via area 202 is in the "shadow" of BGA pad 108.
  • crankshaft via area of the prior art is replaced with a micro-coil structure.
  • Figures 3a and 3b respectively shown the prior art structure including crankshaft via area 202 and the new configuration, which has replaced crankshaft via area 202 with a micro-coil structure 300.
  • micro-coil structure 300 Further details of one embodiment of micro-coil structure 300 are shown in Figure 4b.
  • one or more micro-coils 400 are coupled between the base of PTH 106 and BGA pad 108.
  • the inductance of the micro-coil structure is a function of the loop area and trace width, both of which can be controlled during manufacture.
  • the inductance is also proportional to the square of the number of loops. By using a combination of loop area, trace width and number of loops, the amount of inductance can be precisely controlled.
  • Figure 4b illustrates a micro-coil with two windings, which yields above 1 picoHenry (pH) of inductance.
  • PH picoHenry
  • FIG. 5 Additional exemplary configurations of micro-coil structures are shown in Figure 5. As shown, there are three pair-wise sets of configurations that are modeled - 500a and 500b, 502a and 502b, and 504a and 504b. For each pair-wise set, the difference in the models is the arcuate length micro-coil structures 506, 508, and 510. As illustrated, the arcuate length of micro-coil structure 506 is approximately 360 degrees, while the arcuate length of micro-coil structure 508 is approximately 180 degrees and the arcuate length of micro-coil structure 510 is approximately 90 degrees.
  • a graph 512 is shown on the left-hand side of Figure 5 depicting an effective inductance (in nanoHenries (nH) vs. frequency (Hz x 10 10 ) for the different micro-coil structure models, using Ansys HFSS full wave 3D electromagnetic modeling. As shown in graph 512, the models that have a longer coil have greater effective inductance up to approximately 28 GHz. However, at frequencies above 28 GHz, there is quite a variation in effective inductance.
  • IEEE 802.3bj - 2014 limits the reflections with a return loss specification.
  • a channel operating margin (COM) reference package is also specified in IEEE 802.3bj - 2014, along with the procedure to compute COM, which is a signal-to-noise ratio in dB.
  • Figure 6 shows a COM reference package model 600
  • Figures 7a an 7b are graphs illustrating differential insertion loss (IL) and differential reflection loss (RL) for the following three package selections.
  • the s-parameter data for a short backplane channel published in the public area of IEEE802.3bj was cascaded with each of the three following package selections.
  • the package 1 and 2 models have about the same return loss.
  • Package 2 has ⁇ 50fF more capacitance at the BGA than assumed in the COM reference package (180fF).
  • the darkest traces in Figures 7a and 7b represent the micro-coil package and shows a smoother insertion loss and lower retum loss for the 25Gb/s NRZ (non retum to zero) pass band.
  • a COM of greater than 3dB is required to pass the IEEE 802.3bj - 2014 standard.
  • Figures 8 and 9 respectively show a circuit model 800 and a graph 900 depicting test results for an IEEE 100G BASE KR4 COM test.
  • the COM reference package connection, crankshaft via BGA connection, and M-coil BGA connections were added to the IEEE posted channel FCI_CC_Short_Link_Pair_2_to_Pair_10_Through using BGA connections.
  • the channel has two connectors with 5 cm backplane and line card trace routing.
  • the backplane thickness is 6.4mm.
  • the channel operating margin was modeled at a 25GB/s data rate.
  • COM is 2dB for the COM reference package and non-compensated package crankshaft via termination, while COM is 3.6dB for micro-coil package BGA connection.
  • the uncompensated ISI is 16mV better with the micro-coil scheme.
  • FIG. 10 shows one embodiment of a PCB assembly 1000.
  • PCB assembly 1000 includes a PCB 1002 in which various micro-coil structures 400 are formed in the manner described above.
  • a first COM package 1104 including a semiconductor component 1106 coupled to a BGA package 1108 is mounted to PCB 1002 via a plurality of solder balls 1010.
  • a second COM package 1112 including a semiconductor component 1114 coupled to a BGA package 1116 is mounted to PCB 1002 via a plurality of solder balls 1018.
  • the micro-coil structures 400 are coupled to PTHs formed areas 1020 and 1022 in PCB 102.
  • Various interconnect wiring and vias collectively shown by an interconnect layer 1024 for simplicity, couples signals from the PTHs in areas 1020 and 1022.
  • the interconnect wiring and vias may be formed in multiple layers in PCB 1002.
  • Signals generated by semiconductor components 1106 and 1114 are routed through PCB 1002 along routing paths that pass through micro-coil structures 400. As a result, the signals are subject to far less signal degradation due to capacitive coupling between the BGA pads and the bases of the PTHs.
  • PCB printed circuit board
  • a first conductive layer including a ball grid array (BGA) pad
  • a core layer disposed between the second and third conductive layers
  • PTH plated through hole
  • micro-coil structure conductively connecting the base of the PTH and the BGA pad.
  • micro-coil structure includes a first arcuate trace formed in a fourth conductive layer disposed between the first conductive layer and the second conductive layer.
  • micro-coil structure includes a second arcuate trace formed in a fifth conductive layer disposed between the fourth conductive layer and the second conductive layer.
  • micro-coil structure includes a second arcuate trace formed in a fifth conductive layer disposed between the fourth conductive layer and the second conductive layer and a third arcuate trace formed in a sixth layer between the fifth layer and the second conductive layer.
  • micro-coil structure includes at least one trace that follows a radius offset from an axis coincident with a centerline axis of the
  • An apparatus including a circuit board assembly comprising:
  • PCB printed circuit board
  • first conductive layer including a plurality of BGA pads coupled to the ball grid array; second and third conductive layers, wherein the second conductive layer is disposed between the first and third conductive layers;
  • a core layer disposed between the second conductive layer and the third conductive layer
  • PTHs plated through holes
  • a respective micro-coil structure electrically coupled between a respective BGA pad and a respective PTH base in the second conductive layer.
  • At least one micro-coil structure includes a first arcuate trace formed in a fourth conductive layer disposed between the first conductive layer and the second conductive layer.
  • micro-coil structure includes a second arcuate trace formed in a fifth conductive layer disposed between the fourth conductive layer and the first conductive layer.
  • At least one micro-coil structure includes a second arcuate trace formed in a fifth conductive layer disposed between the fourth conductive layer and the first conductive layer and a third arcuate trace formed in a sixth layer between the fifth conductive layer and the first conductive layer.
  • At least one micro-coil structure includes at least one trace that follows a radius offset from an axis coincident with a centerline axis of one of the PTHs, and wherein the centerline axis of the PTH is substantially aligned with a centerline of one of the BGA pads.
  • the integrated circuit is a communications chip having a Physical (PHY) layer interface
  • at least one micro-coil structure is included in a receive or transmit pathway of a high-speed communications channel coupled to the PHY layer interface having a transmission bandwidth of at least 25 Gigabits per second.
  • PCB printed circuit board
  • BGA ball grid array
  • a first conductive layer including a first plurality BGA pads coupled to the first BGA and a second plurality of BGA pads coupled to the second BGA;
  • first and second pluralities of plated through holes each of at least a portion of which having a base formed in the second conductive layer and conductively connecting the base to a trace in the third conductive layer;
  • each of the first plurality of the micro-coil structures is electrically coupled between the base of a respective PTH among the first plurality of PTHs and a respective BGA pad among the first plurality of BGA pads
  • each of the second plurality of the micro-coil structures is electrically coupled between the base of a respective PTH among the second plurality of PTHs and a respective BGA pad among the second plurality of BGA pads
  • the communication chips support an Ethernet communication link having at least one lane with a bandwidth of at least 25 Gigabits per second, and wherein the transmission path for each of the at least one lane passes through a respective micro-coil structure.
  • At least one micro-coil structure includes at least one trace that follows a radius offset from an axis coincident with a centerline axis of the PTH to which the micro-coil structure is coupled, and wherein the centerline axis of the PTH is substantially aligned with a centerline of the BGA pad to which the micro-coil structure is electrically coupled.
  • the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar.
  • an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein.
  • the various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
  • Coupled may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • An embodiment is an implementation or example of the inventions.
  • Reference in the specification to "an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions.
  • the various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
  • An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
  • embodiments of this invention may be used as or to support a software program, software modules, firmware, and/or distributed software executed upon some form of processor, processing core or embedded logic a virtual machine running on a processor or core or otherwise implemented or realized upon or within a computer-readable or machine-readable non-transitory storage medium.
  • a computer-readable or machine-readable non-transitory storage medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g. , a computer).
  • a computer-readable or machine-readable non-transitory storage medium includes any mechanism that provides (i.e. , stores and/or transmits) information in a form accessible by a computer or computing machine (e.g. , computing device, electronic system, etc.), such as recordable/non- recordable media (e.g. , read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).
  • the content may be directly executable ("object” or “executable” form), source code, or difference code (“delta" or "patch” code).
  • a computer-readable or machine-readable non-transitory storage medium may also include a storage or database from which content can be downloaded.
  • the computer- readable or machine-readable non-transitory storage medium may also include a device or product having content stored thereon at a time of sale or delivery.
  • delivering a device with stored content, or offering content for download over a communication medium may be understood as providing an article of manufacture comprising a computer-readable or machine- readable non-transitory storage medium with such content described herein.
  • Various components referred to above as processes, servers, or tools described herein may be a means for performing the functions described.
  • the operations and functions performed by various components described herein may be implemented by software running on a processing element, via embedded hardware or the like, or any combination of hardware and software.
  • Such components may be implemented as software modules, hardware modules, special-purpose hardware (e.g. , application specific hardware, ASICs, DSPs, etc.), embedded controllers, hardwired circuitry, hardware logic, etc.
  • Software content e.g. , data, instructions, configuration information, etc.
  • a list of items joined by the term "at least one of can mean any combination of the listed terms.
  • the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Peptides Or Proteins (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne des procédés et des appareils de compensation inductive dans des boîtiers et des cartes de circuit imprimé (PCB) pour des assemblages à trous d'interconnexion borgnes et enterrés. Les appareils utilisent des structures de micro-bobine qui connectent électriquement des structures de trou métallisé (PTH) à des plages de boîtier matriciel à billes (BGA). Les structures de micro-bobine créent des effets inductifs qui neutralisent des réflexions capacitives provoquées par les structures PTH et les plages BGA, qui forment un condensateur du type à plaques naturelles. En outre, les effets inductifs peuvent être accordés par variation de la quantité d'enroulement de bobine et/ou des dimensions des structures de bobine.
PCT/US2016/067697 2015-12-31 2016-12-20 Appareil à micro-bobine pour compensation inductive dans des boîtiers et des cartes de circuit imprimé pour assemblages à trous d'interconnexion borgnes et enterrés WO2017116832A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201680070022.2A CN108293294A (zh) 2015-12-31 2016-12-20 用于封装和pcb中针对具有盲孔和埋孔的组装件的电感补偿的微线圈装置
DE112016006129.3T DE112016006129T5 (de) 2015-12-31 2016-12-20 Mikrospulenvorrichtung für einen induktiven Ausgleich in Gehäusen und PCB für Anordnungen mit nicht durchgehenden und vergrabenen Durchkontaktierungen

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562274136P 2015-12-31 2015-12-31
US62/274,136 2015-12-31

Publications (1)

Publication Number Publication Date
WO2017116832A1 true WO2017116832A1 (fr) 2017-07-06

Family

ID=59225213

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2016/067697 WO2017116832A1 (fr) 2015-12-31 2016-12-20 Appareil à micro-bobine pour compensation inductive dans des boîtiers et des cartes de circuit imprimé pour assemblages à trous d'interconnexion borgnes et enterrés

Country Status (3)

Country Link
CN (1) CN108293294A (fr)
DE (1) DE112016006129T5 (fr)
WO (1) WO2017116832A1 (fr)

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US5852866A (en) * 1996-04-04 1998-12-29 Robert Bosch Gmbh Process for producing microcoils and microtransformers
US20040257099A1 (en) * 2001-07-20 2004-12-23 Toshio Kazama Conductive coil contact member
JP2011210596A (ja) * 2010-03-30 2011-10-20 Murata Mfg Co Ltd Ｉｃソケット及びその実装構造
KR101096108B1 (ko) * 2009-11-30 2011-12-19 한국생산기술연구원 미세 코일 및 그 제조방법
US20140262498A1 (en) * 2013-03-13 2014-09-18 U.S.A. As Represented By The Administrator Of The National Aeronautics And Space Administration Interconnect Device and Assemblies Made Therewith

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US7474539B2 (en) * 2005-04-11 2009-01-06 Intel Corporation Inductor
EP2012258B2 (fr) * 2006-04-26 2014-10-22 Murata Manufacturing Co. Ltd. Article ayant un module couple de maniere electromagnetique
US7649265B2 (en) * 2006-09-29 2010-01-19 Intel Corporation Micro-via structure design for high performance integrated circuits
US7897880B1 (en) * 2007-12-07 2011-03-01 Force 10 Networks, Inc Inductance-tuned circuit board via crosstalk structures
WO2013024341A1 (fr) * 2011-08-17 2013-02-21 King Abdullah University Of Science And Technology Composants passifs à base de pcl miniaturisés, de haute qualité
CN104321862B (zh) * 2012-07-31 2017-06-27 株式会社村田制作所 层叠基板
US10008316B2 (en) * 2014-03-28 2018-06-26 Qualcomm Incorporated Inductor embedded in a package substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5852866A (en) * 1996-04-04 1998-12-29 Robert Bosch Gmbh Process for producing microcoils and microtransformers
US20040257099A1 (en) * 2001-07-20 2004-12-23 Toshio Kazama Conductive coil contact member
KR101096108B1 (ko) * 2009-11-30 2011-12-19 한국생산기술연구원 미세 코일 및 그 제조방법
JP2011210596A (ja) * 2010-03-30 2011-10-20 Murata Mfg Co Ltd Ｉｃソケット及びその実装構造
US20140262498A1 (en) * 2013-03-13 2014-09-18 U.S.A. As Represented By The Administrator Of The National Aeronautics And Space Administration Interconnect Device and Assemblies Made Therewith

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Publication number Publication date
DE112016006129T5 (de) 2018-10-18
CN108293294A (zh) 2018-07-17

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