[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2017114411A1 - Chip packaging method - Google Patents

Chip packaging method Download PDF

Info

Publication number
WO2017114411A1
WO2017114411A1 PCT/CN2016/112612 CN2016112612W WO2017114411A1 WO 2017114411 A1 WO2017114411 A1 WO 2017114411A1 CN 2016112612 W CN2016112612 W CN 2016112612W WO 2017114411 A1 WO2017114411 A1 WO 2017114411A1
Authority
WO
WIPO (PCT)
Prior art keywords
frame
lead frame
chip
packaging method
chip packaging
Prior art date
Application number
PCT/CN2016/112612
Other languages
French (fr)
Chinese (zh)
Inventor
周敢营
Original Assignee
无锡华润安盛科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润安盛科技有限公司 filed Critical 无锡华润安盛科技有限公司
Publication of WO2017114411A1 publication Critical patent/WO2017114411A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto

Definitions

  • the present invention relates to the field of chip manufacturing, and in particular, to a chip packaging method.
  • lead frames there are two types of lead frames, one is a lead frame formed by an etching process, which may be referred to as an etched lead frame, and the other is a lead frame formed by a stamping process, which may be referred to as a stamped lead frame.
  • the shape of the branch surface of the lead frame formed by the etching process is curved and the side of the end may have sharp edges. As shown in Figure 1, it illustrates the end side of the etched leadframe.
  • the upper surface of the lead frame is designated 110
  • the lower surface is designated 120
  • the end side is designated 130.
  • the end side of Fig. 1 is etched and has a burr, and the end sides are respectively formed with spikes at the interface with the upper surface 110 and the lower surface 120.
  • FIG. 5 illustrates a schematic view of a prior art chip product 520 separated from a leadframe.
  • the frame end portion 512 of the lead frame is connected to the molding body end portion 521 of the molding body, and a layer of metal 514 is electroplated on the surface of the frame end portion 512 of the lead frame.
  • the metal 514 on the frame end 512 is easily brought out to form a wire.
  • the shape of the branch surface of the lead frame formed by the stamping process is a flat surface, and the side surface of the end portion is an R angle without burrs. As shown in Figure 2, it illustrates the end side of the stamped leadframe.
  • the upper surface of the lead frame is labeled 210, the lower surface is labeled 220, and the end side is labeled 230. Since the end side is stamped, there is no burr, and an R angle is formed at the boundary between the end side surface 230 and the lower surface 220. Since the end side of the stamped lead frame is free of burrs, the wire is not formed on the side of the product when the chip product is pulled apart from the stamped lead frame.
  • the corrosion frame is replaced with a stamping frame It can solve the problem of forming wire on the side of the product, but this will bring two other problems: first, it may not meet the customer's requirements; second, the stamping lead frame mold has high mold opening cost, long cycle, and influence Product delivery.
  • an aspect of the present application provides a chip packaging method.
  • the chip packaging method includes: providing a lead frame, the lead frame comprising an island region, a lead terminal, a frame end, and a connecting portion connecting the lead terminal and the island region; and placing the wafer on the island region of the lead frame; Connecting a bonding wire between the pad of the wafer and a corresponding lead terminal by a bonding process; forming a molding body by a molding die to mold the wafer, the bonding wire and a part of the lead frame
  • the molding body includes a plastic body end portion joined to the frame end portion; a metal layer is plated on the lead frame portion exposed outside the plastic sealing body; and the rib portion of the lead frame is cut off to Forming a chip product, wherein the chip product is supported by the frame end; and separating the chip product from the lead frame; wherein the plastic mold is disposed adjacent to the end of the frame An air groove that discharges a portion of the flash from the exhaust groove when plastically sealed by the
  • Figure 1 illustrates the end side of the corrosion lead frame with the hem on the end side
  • Figure 2 illustrates the end side of the stamped lead frame with the end sides without burrs
  • FIG. 3 is a schematic flow chart of a chip packaging method in an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a product obtained after the molding step of the chip packaging method of FIG. 3;
  • Figure 5 is a schematic view of a separation step in the prior art
  • FIG. 6 is a schematic diagram of a separation step of the chip packaging method of FIG. 3.
  • FIG. 6 is a schematic diagram of a separation step of the chip packaging method of FIG. 3.
  • one embodiment or “an embodiment” as used herein refers to a particular feature, structure, or characteristic that can be included in at least one implementation of the invention.
  • FIG. 3 is a schematic flow chart of the chip packaging method 300 in one embodiment of the present application.
  • the chip packaging method 300 can also solve the problem of forming a wire on the side of the chip product while etching the lead frame.
  • the chip packaging method 300 includes the following steps:
  • Step 310 providing a lead frame including an island region, a lead terminal, a frame end, and a rib connecting the lead terminal and the island region.
  • the leadframe is labeled 410.
  • the island regions of leadframe 410 are molded within chip product 420 and are not shown.
  • the ribs of the lead frame 410 are also not shown.
  • the lead terminals of the lead frame 410 are labeled 411, and the frame ends of the lead frame 410 are labeled 412.
  • the lead frame is fabricated by an etching process and may be referred to as an etched lead frame. Due to leads The frame is manufactured by an etching process so that the sides of the frame end 412 may have burrs.
  • step 320 a wafer (not shown) is placed on the island area of the lead frame.
  • Step 330 connecting the bonding wires between the pads of the wafer and the corresponding lead terminals by a bonding process.
  • the bonding process can employ a conventional bonding process in the art, and thus is not specifically described herein.
  • Step 340 a molding step of forming a molding body by molding a mold to mold the wafer, the bonding wire and a part of the lead frame in the molding body, and the molding body includes a molding body end portion 421 joined to the frame end portion 412.
  • FIG. 4 is a schematic diagram of the product structure obtained after the molding step 340 of the chip packaging method 300.
  • a venting groove is provided at a position close to the frame end portion 412 of the molding die, which can be discharged from the vent groove when molded by a plastic sealing die as shown in FIG. 4 and FIG.
  • the flash 413 which covers the partial area of the frame end 412.
  • the depth of the venting groove is from 0.010 mm to 0.030 mm.
  • the depth of the exhaust groove is 0.025 mm.
  • the width of the venting groove is 1/4 to 1/3 of the width of the molding body, for example, the width of the molding body is 4 mm, and the width of the venting groove may be 1 mm.
  • step 350 a layer of metal is plated on the portion of the lead frame exposed outside the plastic package.
  • the area of the frame end 412 with flash is not plated with metal.
  • a region of the frame end 412 adjacent to the chip product 420 is covered with flash, and a region remote from the chip product 420 is formed of a layer of metal by electroplating. In other embodiments, it may also be that the entire surface of the frame end 412 is covered with flash.
  • the metal comprises tin.
  • the rib portion of the lead frame is cut to form a chip product 420, at which time the chip product 420 is supported by the connection of the frame end 412 and the molded body end 421.
  • the chip product 420 is separated from the lead frame 410.
  • the chip product 420 is pulled in the direction of the arrow to separate the chip product 420 from the remainder of the lead frame 410.
  • the lead frame 410 is a corrosion lead frame 410
  • there may be burrs on the side of the frame end portion 412 but since a portion of the frame end portion 412 is covered with the flash 413, Instead of being entirely plated with a metal layer, no wire is formed when the chip product 420 is separated from the lead frame 410.
  • the specific location of the venting groove on the molding die can be set in accordance with the direction in which the chip product 420 is separated from the lead frame 410. Specifically, if the chip product 420 is separated downward from the lead frame 410, the exhaust groove is disposed facing the lower surface of the frame end portion 412 of the lead frame 410.
  • the venting groove may be disposed at a position of the lower cavity of the molding die near the frame end 412. If the chip product 420 is detached upward from the lead frame 410, the vent groove is disposed facing the upper surface of the frame end 412 of the lead frame 410.
  • the solution for solving the wire problem in the present application is easy to operate, low in cost, short in cycle, and has no influence on the chip product itself, and does not involve any change problem of the customer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A chip packaging method comprises: providing a lead frame (410), the lead frame comprising an island area, lead terminals (411), frame end portions (412), and connecting portions; placing a chip on the island area of the lead frame; connecting bonding wires between a bonding pad of the chip and the corresponding lead terminals; forming a plastic encapsulation body using a plastic encapsulation mold for plastic-encapsulating the chip, the bonding wires and part of the lead frame in the plastic encapsulation body, the plastic encapsulation body comprising plastic encapsulation body end portions (421) for engaging with the frame end portions; and separating a chip product (420) from the lead frame. The plastic encapsulation mold is provided with exhaust grooves at positions close to the frame end portions, part of overflow material (413) is discharged from the exhaust grooves when plastic encapsulation is performed using the plastic encapsulation mold, and the part of the overflow material covers part of regions of the frame end portions. In this way, a complete metal layer is not formed on frame end portions during plating, thereby solving the problem in which metal wires are formed on sides of a chip product.

Description

芯片封装方法Chip packaging method
相关申请的交叉引用Cross-reference to related applications
本专利申请要求于2015年12月31日提交的、申请号为201511027882.1、发明名称为“芯片封装方法”的中国专利申请的优先权，该申请的全文以引用的方式并入本文中。The present application claims priority to Chinese Patent Application No. 20151102788, filed Dec.
技术领域Technical field
本发明涉及芯片制造领域，尤其涉及一种芯片封装方法。The present invention relates to the field of chip manufacturing, and in particular, to a chip packaging method.
背景技术Background technique
目前引线框架包括有两种，一种是通过腐蚀工艺形成的引线框架，可以被称为腐蚀引线框架；另一种是通过冲压工艺形成的引线框架，可以被称为冲压引线框架。At present, there are two types of lead frames, one is a lead frame formed by an etching process, which may be referred to as an etched lead frame, and the other is a lead frame formed by a stamping process, which may be referred to as a stamped lead frame.
通过腐蚀工艺形成的引线框架的分行面形状为弧形凹入，端部侧面可能有尖毛边。如图1所示，其示意出了腐蚀引线框架的端部侧面。引线框架的上表面标示为110，下表面标示为120，端部侧面标示为130。图1中端部侧面是腐蚀而成的，其具有毛边，端部侧面在与上表面110和下表面120交界处分别形成有尖刺。The shape of the branch surface of the lead frame formed by the etching process is curved and the side of the end may have sharp edges. As shown in Figure 1, it illustrates the end side of the etched leadframe. The upper surface of the lead frame is designated 110, the lower surface is designated 120, and the end side is designated 130. The end side of Fig. 1 is etched and has a burr, and the end sides are respectively formed with spikes at the interface with the upper surface 110 and the lower surface 120.
在将芯片产品从腐蚀引线框架上拉扯分离时，端部侧面的毛边容易导致腐蚀引线框的端部上层电镀的金属层被带出，而在芯片产品的侧边上形成金属丝，带来引脚短路的风险。图5示意出了现有的芯片产品520从引线框架上分离出来的示意图。引线框架的框架端部512与塑封体的塑封体端部521相连接，在引线框架的框架端部512的表面上电镀形成有一层金属514。在芯片产品520从引线框架上分离出来时，框架端部512上的金属514很容易被带出形成金属丝。When the chip product is pulled apart from the corrosion lead frame, the burrs on the side of the end portion tend to cause the metal layer plated on the upper portion of the end of the corrosion lead frame to be taken out, and a wire is formed on the side of the chip product to bring the lead. The risk of a short circuit. Figure 5 illustrates a schematic view of a prior art chip product 520 separated from a leadframe. The frame end portion 512 of the lead frame is connected to the molding body end portion 521 of the molding body, and a layer of metal 514 is electroplated on the surface of the frame end portion 512 of the lead frame. When the chip product 520 is separated from the lead frame, the metal 514 on the frame end 512 is easily brought out to form a wire.
通过冲压工艺形成的引线框架的分行面形状为平面，端部侧面为R角，无毛边。如图2所示，其示意出了冲压引线框架的端部侧面。引线框架的上表面标示为210，下表面标示为220，端部侧面标示为230。由于端部侧面是冲压而成的，因此无毛边，在端部侧面230与下表面220交界处形成有R角。由于冲压引线框的端部侧面无毛边，因此在将芯片产品从冲压引线框架上拉扯分离时，不会在产品的侧边上形成金属丝。虽然将腐蚀框架更换成冲压框架 可以解决在产品的侧边上形成金属丝的问题，然而这样会带来另外的两个问题：第一、可能无法满足客户要求；第二、冲压引线框架模具开模费用高，周期长，影响产品交期。The shape of the branch surface of the lead frame formed by the stamping process is a flat surface, and the side surface of the end portion is an R angle without burrs. As shown in Figure 2, it illustrates the end side of the stamped leadframe. The upper surface of the lead frame is labeled 210, the lower surface is labeled 220, and the end side is labeled 230. Since the end side is stamped, there is no burr, and an R angle is formed at the boundary between the end side surface 230 and the lower surface 220. Since the end side of the stamped lead frame is free of burrs, the wire is not formed on the side of the product when the chip product is pulled apart from the stamped lead frame. Although the corrosion frame is replaced with a stamping frame It can solve the problem of forming wire on the side of the product, but this will bring two other problems: first, it may not meet the customer's requirements; second, the stamping lead frame mold has high mold opening cost, long cycle, and influence Product delivery.
有必要提出一种新的方案来解决上述至少一个问题。It is necessary to propose a new solution to solve at least one of the above problems.
发明内容Summary of the invention
有鉴于此，本申请的一个方面提供一种芯片封装方法。该芯片封装方法包括：提供引线框架，该引线框架包括岛区、引线端子、框架端部以及连接所述引线端子和岛区的连筋部；将晶片安放于所述引线框架的岛区上；通过键合工艺将键合线连接于所述晶片的焊盘和相应的引线端子之间；通过塑封模具形成塑封体以将所述晶片、所述键合线和部分所述引线框架塑封于所述塑封体内，所述塑封体包括与所述框架端部相接合的塑封体端部；在露于所述塑封体外的引线框架部分上电镀一层金属；切除所述引线框架的连筋部以形成芯片产品，此时所述芯片产品由所述框架端部支撑；和将所述芯片产品从所述引线框架上分离出来；其中，所述塑封模具的靠近所述框架端部的位置设置排气凹槽，在通过所述塑封模具进行塑封时从所述排气凹槽排出部分溢料，这部分溢料覆盖在所述框架端部的部分区域上。In view of this, an aspect of the present application provides a chip packaging method. The chip packaging method includes: providing a lead frame, the lead frame comprising an island region, a lead terminal, a frame end, and a connecting portion connecting the lead terminal and the island region; and placing the wafer on the island region of the lead frame; Connecting a bonding wire between the pad of the wafer and a corresponding lead terminal by a bonding process; forming a molding body by a molding die to mold the wafer, the bonding wire and a part of the lead frame In the plastic package, the molding body includes a plastic body end portion joined to the frame end portion; a metal layer is plated on the lead frame portion exposed outside the plastic sealing body; and the rib portion of the lead frame is cut off to Forming a chip product, wherein the chip product is supported by the frame end; and separating the chip product from the lead frame; wherein the plastic mold is disposed adjacent to the end of the frame An air groove that discharges a portion of the flash from the exhaust groove when plastically sealed by the molding die, the portion of the flash covering a portion of the end of the frame.
附图说明DRAWINGS
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, Those skilled in the art can also obtain other drawings based on these drawings without paying any inventive labor. among them:
图1示意出了腐蚀引线框架的端部侧面，其中端部侧面具有毛边；Figure 1 illustrates the end side of the corrosion lead frame with the hem on the end side;
图2示意出了冲压引线框架的端部侧面，其中端部侧面不具有毛边；Figure 2 illustrates the end side of the stamped lead frame with the end sides without burrs;
图3为本发明中的芯片封装方法在一个实施例中的流程示意图；3 is a schematic flow chart of a chip packaging method in an embodiment of the present invention;
图4为图3中的芯片封装方法的塑封步骤后获得的产品结构示意图；4 is a schematic structural view of a product obtained after the molding step of the chip packaging method of FIG. 3;
图5为现有技术中的分离步骤的示意图；Figure 5 is a schematic view of a separation step in the prior art;
图6为图3中的芯片封装方法的分离步骤的示意图。 FIG. 6 is a schematic diagram of a separation step of the chip packaging method of FIG. 3. FIG.
具体实施方式detailed description
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.
本发明的详细描述主要通过程序、步骤、逻辑块、过程或其他象征性的描述来直接或间接地模拟本发明技术方案的运作。为透彻的理解本发明，在接下来的描述中陈述了很多特定细节。而在没有这些特定细节时，本发明则可能仍可实现。所属领域内的技术人员使用此处的这些描述和陈述向所属领域内的其他技术人员有效的介绍他们的工作本质。换句话说，为避免混淆本发明的目的，由于熟知的方法和程序已经容易理解，因此它们并未被详细描述。The detailed description of the present invention is intended to directly or indirectly exemplify the operation of the embodiments of the present invention, by means of procedures, steps, logic blocks, processes, or other symbolic description. For a thorough understanding of the invention, numerous specific details are set forth in the following description. Without these specific details, the invention may still be achievable. Those skilled in the art will be able to effectively describe the nature of their work to those skilled in the art using these descriptions and statements herein. In other words, to avoid obscuring the object of the present invention, well-known methods and procedures have not been described in detail since they are readily understood.
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。The term "one embodiment" or "an embodiment" as used herein refers to a particular feature, structure, or characteristic that can be included in at least one implementation of the invention. The appearances of the "in one embodiment", "a" or "an"
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It is to be understood that the term "comprises", "comprising" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a It also includes other elements that are not explicitly listed, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.
图3为本申请中的芯片封装方法300在一个实施例中的流程示意图。芯片封装方法300在采用腐蚀引线框的同时还能够解决芯片产品的侧边上形成金属丝的问题。FIG. 3 is a schematic flow chart of the chip packaging method 300 in one embodiment of the present application. The chip packaging method 300 can also solve the problem of forming a wire on the side of the chip product while etching the lead frame.
如图3所示，芯片封装方法300包括如下步骤：As shown in FIG. 3, the chip packaging method 300 includes the following steps:
步骤310，提供引线框架，该引线框架包括岛区、引线端子、框架端部以及连接引线端子和岛区的连筋部。 Step 310, providing a lead frame including an island region, a lead terminal, a frame end, and a rib connecting the lead terminal and the island region.
结合图4所示，引线框架被标记为410。引线框架410的岛区被塑封在芯片产品420内，并未示出。引线框架410的连筋部也未被示出。引线框架410的引线端子被标记为411，引线框架410的框架端部被标记为412。As shown in connection with Figure 4, the leadframe is labeled 410. The island regions of leadframe 410 are molded within chip product 420 and are not shown. The ribs of the lead frame 410 are also not shown. The lead terminals of the lead frame 410 are labeled 411, and the frame ends of the lead frame 410 are labeled 412.
在本申请中，引线框架是由腐蚀工艺制造而成的，可以被称为腐蚀引线框架。由于引线 框架是由腐蚀工艺制造而成的，因此框架端部412的侧面可能会有毛刺。In the present application, the lead frame is fabricated by an etching process and may be referred to as an etched lead frame. Due to leads The frame is manufactured by an etching process so that the sides of the frame end 412 may have burrs.
步骤320，将晶片(未图示)安放于引线框架的岛区上。In step 320, a wafer (not shown) is placed on the island area of the lead frame.
步骤330，通过键合工艺将键合线连接于晶片的焊盘和相应的引线端子之间。键合工艺可以采用所属领域内的常规键合工艺，因此此处并未特别详细说明。 Step 330, connecting the bonding wires between the pads of the wafer and the corresponding lead terminals by a bonding process. The bonding process can employ a conventional bonding process in the art, and thus is not specifically described herein.
步骤340，塑封步骤：通过塑封模具形成塑封体以将晶片、键合线和部分引线框架塑封于塑封体内，塑封体包括与框架端部412相接合的塑封体端部421。 Step 340, a molding step of forming a molding body by molding a mold to mold the wafer, the bonding wire and a part of the lead frame in the molding body, and the molding body includes a molding body end portion 421 joined to the frame end portion 412.
图4为芯片封装方法300的塑封步骤340后获得的产品结构示意图。本申请的优点或特点之一在于：塑封模具的靠近框架端部412的位置设置排气凹槽，可以结合图4和图6所示，在通过塑封模具进行塑封时从排气凹槽排出部分溢料413，这部分溢料413覆盖在框架端部412的部分区域上。FIG. 4 is a schematic diagram of the product structure obtained after the molding step 340 of the chip packaging method 300. One of the advantages or features of the present application is that a venting groove is provided at a position close to the frame end portion 412 of the molding die, which can be discharged from the vent groove when molded by a plastic sealing die as shown in FIG. 4 and FIG. The flash 413, which covers the partial area of the frame end 412.
在一个实施例中，排气凹槽的深度为0.010mm至0.030mm。优选的，排气凹槽的深度为0.025mm。排气凹槽的宽度为塑封体的宽度的1/4至1/3，比如，塑封体的宽度为4mm，排气凹槽的宽度可以为1mm。In one embodiment, the depth of the venting groove is from 0.010 mm to 0.030 mm. Preferably, the depth of the exhaust groove is 0.025 mm. The width of the venting groove is 1/4 to 1/3 of the width of the molding body, for example, the width of the molding body is 4 mm, and the width of the venting groove may be 1 mm.
步骤350，在露于塑封体外的引线框架部分上电镀一层金属。In step 350, a layer of metal is plated on the portion of the lead frame exposed outside the plastic package.
由于框架端部412的部分区域上覆盖有溢料，因此在框架端部412的具有溢料的区域并未被电镀上金属。Since the partial area of the frame end 412 is covered with flash, the area of the frame end 412 with flash is not plated with metal.
结合图4和图6所示，框架端部412的靠近芯片产品420的区域上形成覆盖有溢料，而远离芯片产品420的区域通过电镀形成一层金属。在其他实施例中，也可以是框架端部412的整个表面都覆盖有溢料。4 and 6, a region of the frame end 412 adjacent to the chip product 420 is covered with flash, and a region remote from the chip product 420 is formed of a layer of metal by electroplating. In other embodiments, it may also be that the entire surface of the frame end 412 is covered with flash.
在一个实施例中，金属包括锡。In one embodiment, the metal comprises tin.
步骤360，切除引线框架的连筋部以形成芯片产品420，此时芯片产品420由于框架端部412和塑封体端部421的连接而被支撑。At step 360, the rib portion of the lead frame is cut to form a chip product 420, at which time the chip product 420 is supported by the connection of the frame end 412 and the molded body end 421.
步骤370，将芯片产品420从引线框架410上分离出来。At step 370, the chip product 420 is separated from the lead frame 410.
在一个实施例中，如图6所示，沿箭头方向拉拽芯片产品420以使得芯片产品420与引线框架410的剩余部分分离。In one embodiment, as shown in FIG. 6, the chip product 420 is pulled in the direction of the arrow to separate the chip product 420 from the remainder of the lead frame 410.
而在本申请中，结合图6所示，虽然引线框架410是腐蚀引线框架410，其框架端部412的侧面上可能有毛刺，但是由于框架端部412的部分区域上覆盖有溢料413，而没有被全部电镀上金属层，因此在芯片产品420从引线框架410上分离出来时，并不会形成金属丝。 In the present application, as shown in FIG. 6, although the lead frame 410 is a corrosion lead frame 410, there may be burrs on the side of the frame end portion 412, but since a portion of the frame end portion 412 is covered with the flash 413, Instead of being entirely plated with a metal layer, no wire is formed when the chip product 420 is separated from the lead frame 410.
在一个实施例中，可以根据芯片产品420从引线框架410上分离出来的方向，设置排气凹槽在塑封模具上的具体位置。具体的，如果芯片产品420向下从引线框架410上分离出来，那么排气凹槽被设置的面向引线框架410的框架端部412的下表面。比如，排气凹槽可以设置于塑封模具的下型腔的靠近框架端部412的位置处。如果芯片产品420向上从引线框架410上分离出来，那么排气凹槽被设置的面向引线框架410的框架端部412的上表面。In one embodiment, the specific location of the venting groove on the molding die can be set in accordance with the direction in which the chip product 420 is separated from the lead frame 410. Specifically, if the chip product 420 is separated downward from the lead frame 410, the exhaust groove is disposed facing the lower surface of the frame end portion 412 of the lead frame 410. For example, the venting groove may be disposed at a position of the lower cavity of the molding die near the frame end 412. If the chip product 420 is detached upward from the lead frame 410, the vent groove is disposed facing the upper surface of the frame end 412 of the lead frame 410.
本申请中的解决金属丝问题的方案，易操作、费用低、周期短，且对芯片产品本身无任何影响，而且不涉及客户任何变更问题。The solution for solving the wire problem in the present application is easy to operate, low in cost, short in cycle, and has no influence on the chip product itself, and does not involve any change problem of the customer.
上述说明已经充分揭露了本发明的具体实施方式。需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具体实施方式。 The above description has fully disclosed the specific embodiments of the present invention. It should be noted that any changes to the specific embodiments of the invention will be apparent to those skilled in the art without departing from the scope of the appended claims. Accordingly, the scope of the claims of the invention is not limited to the foregoing specific embodiments.

Claims (9)

  1. 一种芯片封装方法，其特征在于，其包括：A chip packaging method, characterized in that it comprises:
    提供引线框架，该引线框架包括岛区、引线端子、框架端部以及连接所述引线端子和岛区的连筋部；Providing a lead frame including an island region, a lead terminal, a frame end portion, and a rib portion connecting the lead terminal and the island region;
    将晶片安放于所述引线框架的岛区上；Mounting a wafer on an island area of the lead frame;
    通过键合工艺将键合线连接于所述晶片的焊盘和相应的引线端子之间；Connecting a bonding wire between the pad of the wafer and a corresponding lead terminal by a bonding process;
    通过塑封模具形成塑封体以将所述晶片、所述键合线和部分所述引线框架塑封于所述塑封体内，所述塑封体包括与所述框架端部相接合的塑封体端部；Forming a molding body by molding a mold to mold the wafer, the bonding wire and a portion of the lead frame in the molding body, the molding body comprising a molding body end portion engaged with the frame end portion;
    在露于所述塑封体外的引线框架部分上电镀一层金属；Plating a layer of metal on a portion of the lead frame exposed outside the plastic package;
    切除所述引线框架的连筋部以形成芯片产品，此时所述芯片产品由所述框架端部支撑；和Cutting the rib portion of the lead frame to form a chip product, at which time the chip product is supported by the frame end; and
    将所述芯片产品从所述引线框架上分离出来；Separating the chip product from the lead frame;
    其中，所述塑封模具的靠近所述框架端部的位置设置排气凹槽，在通过所述塑封模具进行塑封时从所述排气凹槽排出部分溢料，这部分溢料覆盖在所述框架端部的部分区域上。Wherein the venting groove is disposed at a position of the plastic mold near the end of the frame, and a part of the flash is discharged from the venting groove when the plastic sealing is performed by the plastic sealing mold, and the partial squirt is covered in the On a partial area of the end of the frame.
  2. 根据权利要求1所述的芯片封装方法，其特征在于：所述引线框架是由腐蚀工艺制造而成的。The chip packaging method according to claim 1, wherein the lead frame is fabricated by an etching process.
  3. 根据权利要求1所述的芯片封装方法，其特征在于：所述排气凹槽的深度为0.010mm至0.030mm。The chip packaging method according to claim 1, wherein the exhaust groove has a depth of 0.010 mm to 0.030 mm.
  4. 根据权利要求1所述的芯片封装方法，其特征在于：所述排气凹槽的宽度为所述塑封体的宽度的1/4至1/3。The chip packaging method according to claim 1, wherein the width of the exhaust groove is 1/4 to 1/3 of a width of the molding body.
  5. 根据权利要求1所述的芯片封装方法，其特征在于：所述电镀形成的一层金属包括锡。The chip packaging method according to claim 1, wherein the layer of metal formed by the plating comprises tin.
  6. 根据权利要求1所述的芯片封装方法，其特征在于：根据所述芯片产品从所述引线框架上分离出来的方向，设置所述气凹槽在所述塑封模具上的具体位置。The chip packaging method according to claim 1, wherein a specific position of the gas groove on the plastic mold is set according to a direction in which the chip product is separated from the lead frame.
  7. 根据权利要求1所述的芯片封装方法，其特征在于：所述排气凹槽设置于所述塑封模具的下型腔。The chip packaging method according to claim 1, wherein the exhaust groove is disposed in a lower cavity of the molding die.
  8. 根据权利要求1所述的芯片封装方法，其特征在于：所述框架端部的靠近所述芯片产品的区域上覆盖有溢料。The chip packaging method according to claim 1, wherein the area of the frame end adjacent to the chip product is covered with flash.
  9. 根据权利要求1所述的芯片封装方法，其特征在于：所述框架端部的整个表面覆盖有溢料。 The chip packaging method according to claim 1, wherein the entire surface of the end portion of the frame is covered with flash.
PCT/CN2016/112612 2015-12-31 2016-12-28 Chip packaging method WO2017114411A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201511027882.1 2015-12-31
CN201511027882.1A CN106935518B (en) 2015-12-31 2015-12-31 Chip packaging method

Publications (1)

Publication Number Publication Date
WO2017114411A1 true WO2017114411A1 (en) 2017-07-06

Family

ID=59225643

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/112612 WO2017114411A1 (en) 2015-12-31 2016-12-28 Chip packaging method

Country Status (2)

Country Link
CN (1) CN106935518B (en)
WO (1) WO2017114411A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321129A (en) * 2018-03-30 2018-07-24 深圳赛意法微电子有限公司 The packaging method and its package module of power device, lead frame

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109003957A (en) * 2018-09-18 2018-12-14 江苏捷捷微电子股份有限公司 The preparation method of SOT-89/223-2L lead frame and two leg structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101442035A (en) * 2008-12-14 2009-05-27 天水华天科技股份有限公司 Flat non down-lead encapsulation piece and method for producing the same
CN102403295A (en) * 2010-09-07 2012-04-04 万国半导体股份有限公司 Metal bonded semiconductor package and method thereof
US20150279767A1 (en) * 2012-08-08 2015-10-01 Amkor Technology, Inc. Lead frame package and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101442035A (en) * 2008-12-14 2009-05-27 天水华天科技股份有限公司 Flat non down-lead encapsulation piece and method for producing the same
CN102403295A (en) * 2010-09-07 2012-04-04 万国半导体股份有限公司 Metal bonded semiconductor package and method thereof
US20150279767A1 (en) * 2012-08-08 2015-10-01 Amkor Technology, Inc. Lead frame package and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321129A (en) * 2018-03-30 2018-07-24 深圳赛意法微电子有限公司 The packaging method and its package module of power device, lead frame

Also Published As

Publication number Publication date
CN106935518A (en) 2017-07-07
CN106935518B (en) 2019-04-12

Similar Documents

Publication Publication Date Title
CN102931161B (en) Semiconductor package assembly and a manufacturing method thereof
US8329509B2 (en) Packaging process to create wettable lead flank during board assembly
US11342252B2 (en) Leadframe leads having fully plated end faces
US9184118B2 (en) Micro lead frame structure having reinforcing portions and method
US9337130B2 (en) Leadframe strip and leadframes
JP2010534937A5 (en)
US9136208B2 (en) Semiconductor device and method of manufacturing the same
US9673122B2 (en) Micro lead frame structure having reinforcing portions and method
TWI642160B (en) Lead frame structure for quad flat no-lead package, quad flat no-lead package and method for forming the lead frame structure
US20180122731A1 (en) Plated ditch pre-mold lead frame, semiconductor package, and method of making same
US9620388B2 (en) Integrated circuit package fabrication with die attach paddle having middle channels
WO2017114411A1 (en) Chip packaging method
US10242935B2 (en) Packaged semiconductor device and method for forming
US20140239476A1 (en) Semiconductor device with integral heat sink
JP5264677B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP6338406B2 (en) Manufacturing method of semiconductor device
CN106796931B (en) The manufacturing method of lead frame, semiconductor device
JP4418764B2 (en) Manufacturing method of resin-encapsulated semiconductor package
US20200258822A1 (en) High i/o density flip-chip qfn
TWI689063B (en) Semiconductor device and method of manufacturing the same
JP2014175578A (en) Semiconductor device packaging lead frame
US20240379506A1 (en) Electronic device with improved leadframe trimming process
CN105789068A (en) Preparation method of QFN package device
JP2018056310A (en) Resin encapsulation mold, and method of manufacturing semiconductor device using the same
JP2011228412A (en) Resin seal type semiconductor package and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16881200

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16881200

Country of ref document: EP

Kind code of ref document: A1