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WO2017113438A1 - 栅极驱动电路和使用栅极驱动电路的显示器 - Google Patents

栅极驱动电路和使用栅极驱动电路的显示器 Download PDF

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Publication number
WO2017113438A1
WO2017113438A1 PCT/CN2016/070626 CN2016070626W WO2017113438A1 WO 2017113438 A1 WO2017113438 A1 WO 2017113438A1 CN 2016070626 W CN2016070626 W CN 2016070626W WO 2017113438 A1 WO2017113438 A1 WO 2017113438A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrically connected
transistor
signal
clock signal
gate
Prior art date
Application number
PCT/CN2016/070626
Other languages
English (en)
French (fr)
Inventor
戴荣磊
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US14/907,544 priority Critical patent/US9786242B2/en
Publication of WO2017113438A1 publication Critical patent/WO2017113438A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the invention relates to a display, in particular to a gate driver (Gate driver on Array, GOA) display of the circuit.
  • GOA Gate driver on Array
  • the GOA circuit uses a thin film transistor display Array process to fabricate a gate driver with a thin film transistor (Thin film). Transistor, TFT) on the substrate of the array to implement a progressive scan driving method.
  • the GOA circuit includes a plurality of GOA circuit units, each of which is composed of a plurality of transistors and a plurality of capacitors. Since the GOA circuit directly forms the side of the glass substrate, the smaller the number of transistors and capacitors per GOA circuit unit, the less the glass substrate area occupied by the GOA circuit. In addition, each GOA circuit unit charges and discharges the parasitic capacitance every time the signal is switched. Therefore, a clock signal with a higher frequency has a greater influence on the power consumption of the parasitic capacitance. In particular, the clock signal used for the pull-down module is particularly significant for the power consumption of parasitic capacitance.
  • the technical solution of the present invention provides a gate driving circuit including a plurality of GOA circuit units.
  • a plurality of the GOA circuit units are coupled in series, and each stage of the GOA circuit unit is configured to use a scan signal output by the first two stages of the GOA circuit unit, a scan signal output by the last two stages of the GOA circuit unit, and a first clock signal.
  • a second clock signal, a third clock signal, a fourth clock signal, a first turn-on signal, and a second turn-on signal and output a scan signal at the output end.
  • Each two-stage GOA circuit unit shares a pull-down circuit.
  • the pull-down circuit includes: a first transistor having a gate electrically connected to the first turn-on signal, a drain electrically connected to the first clock signal or the second clock signal; and a second transistor having a gate Electrically connecting the second turn-on signal, the drain thereof is electrically connected to the second clock signal or the first clock signal; and the third transistor has a gate electrically connected to the first transistor and the first The source of the two transistors has a drain electrically connected to the first fixed voltage.
  • Each of the GOA circuit units includes: an input control module electrically coupled to a control node for: according to the first enable signal, the second turn-on signal, a scan signal output by the first two stages of GOA circuit units, and a scan signal outputted by the last two stages of the GOA circuit unit to adjust a voltage of the control node; an output control module electrically connected to the control node for outputting the scan signal according to a voltage applied to the control node; And a pull-down maintaining module electrically connected to the input control module and the output control module for maintaining a low level of the scan signal.
  • the input control module includes: a fourth transistor, a gate electrically connected to the scan signal output by the first two stages of the GOA circuit unit, and a drain electrically connected to the first open signal, The source is electrically connected to the control node; and the fifth transistor has a gate electrically connected to the scan signal output by the second two stages of the GOA circuit unit, and a drain electrically connected to the second open signal, the source thereof The control node is electrically connected.
  • the output control module includes: a sixth transistor having a gate electrically connected to the first fixed voltage, a drain electrically connected to the control node; and a seventh transistor having a gate
  • the source of the sixth transistor is electrically connected, and the drain thereof is electrically connected to the third clock signal or the fourth clock signal, and the source thereof is electrically connected to the output end.
  • the pull-down maintaining module includes: an eighth transistor having a gate electrically connected to a source of the third transistor, a drain electrically connected to the control node, and a source electrically connected a second fixed voltage; a ninth transistor having a gate electrically connected to the control node, a drain electrically connected to a source of the third transistor, a source electrically connected to the second fixed voltage; a transistor having a gate electrically connected to a source of the third transistor, a drain electrically connected to the output terminal, a source electrically connected to the second fixed voltage, and a capacitor connected at both ends thereof The gate of the ninth transistor and the second fixed voltage.
  • the drain of the seventh transistor of one of the GOA circuit units of each two-stage GOA circuit unit is electrically connected to the third clock signal, and the seventh transistor of the other GOA circuit unit The drain is electrically connected to the fourth clock signal.
  • each transistor is an N-type MOS transistor
  • the first fixed voltage is a low level
  • the second fixed voltage is a high level
  • each of the four serially connected GOA circuit units constitutes a GOA circuit unit group
  • the GOA circuit unit group includes a first pull-down circuit and a second pull-down circuit
  • the first pull-down circuit a gate and a drain of a transistor are electrically connected to the first turn-on signal and the first clock signal, respectively, and a gate and a drain of the second transistor of the first pull-down circuit are electrically connected to the first The second turn-on signal and the second clock signal.
  • a gate and a drain of the first transistor of the second pull-down circuit are electrically connected to the first turn-on signal and the second clock signal, respectively, and a gate and a drain of the second transistor of the second pull-down circuit
  • the second turn-on signal and the first clock signal are electrically connected respectively.
  • the timings of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal output pulse do not overlap each other.
  • the technical solution of the present invention further provides a display including a source driver and a gate driving circuit as described above, wherein the gate driving circuit outputs a scan signal such that a plurality of transistors are turned on, and the source driver outputs a corresponding data signal to Several pixel units make it display grayscale.
  • each two-stage GOA circuit unit of the gate driving circuit of the present invention shares a pull-down circuit, which can not only reduce the number of transistors used by the gate driving circuit, but also reduce the first clock signal and the second clock signal. Frequency of. Reducing the frequency of the first clock signal and the second clock signal results in reducing the frequency of charging and discharging the parasitic capacitance, thereby reducing the overall power consumption of the gate driving circuit, and has the beneficial effect of power saving.
  • FIG. 1 is a schematic diagram of a display using a gate drive circuit of the present invention.
  • FIG. 2 is a circuit diagram of a GOA circuit unit in accordance with a preferred embodiment of the present invention.
  • 3 is a timing diagram of input signals and output signals of a GOA circuit unit group.
  • FIG. 1 is a gate driver (Gate driver on) according to the present invention.
  • the display 10 can be a liquid crystal display or an organic light emitting diode display.
  • the display 10 includes a GOA circuit 12, a glass substrate 14, and a source driver (source) Driver) 16 and controller 18.
  • a plurality of pixels arranged in a matrix and a GOA circuit 12 are disposed on the substrate 14, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB).
  • RGB red, green and blue
  • the GOA circuit 12 outputs a scan signal such that the transistors 22 of each row are sequentially turned on, and the source driver 16 outputs corresponding data signals to an entire column of pixel units 20 to charge them to respective required voltages to display different gray scales. .
  • the GOA circuit 12 turns off the scan signal of the row, and then the GOA circuit 12 outputs the scan signal to turn on the transistor 22 of the next row, and then the source driver 16 charges the pixel unit 20 of the next row. Discharge. This is continued until all the pixel units 20 are fully charged, and charging starts from the first line.
  • the GOA circuit 12 is placed on both sides of the glass substrate 14, and the two GOA circuits 12 respectively contain a plurality of GOAs. Circuit units SR(1), SR(3), ...SR(767) and SR(2), SR(4), ...SR(768). Multiple GOA The circuit units SR(1) to SR(768) are one-to-one connected to the plurality of rows of pixel units 20. That is, the two GOA circuits 12 are used to control the pixel units 20 of the singular and even rows, respectively.
  • the clock signals CK1-CK4 generated by the controller 18 and the GOA actuation signals STV1, STV2 are transmitted to the GOA.
  • the GOA circuit units SR(1) to SR(768) When the circuit units SR(1) to SR(768), the GOA circuit units SR(1) to SR(768) generate a scan signal to the pixel unit 20.
  • FIG. 2 is a circuit diagram of a GOA circuit unit SR(n) according to a preferred embodiment of the present invention.
  • every four GOA circuit units SR(2n+1), SR(2n+3), SR(2n+5), and SR(2n+7) constitute one GOA circuit unit group SRG.
  • the GOA circuit unit SR(2n+1) is used for scanning according to the scan signal G(2n-1) output by the first two stages of the GOA circuit unit SR(2n-1) and the output of the last two stages of the GOA circuit unit SR(2n+3).
  • the signal G(2n+3), the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the first turn-on signal U2D, and the second turn-on signal D2U are output and scanned at the output terminal OUT.
  • the adjacent two-stage GOA circuit units SR(2n+1), SR(2n+3) share the first pull-down circuit 100a.
  • the adjacent two-stage GOA circuit units SR(2n+5), SR(2n+7) share the second pull-down circuit 100b.
  • the timings of the output pulses of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 do not overlap each other.
  • the pull-down circuit 100a includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the gate of the first transistor T1 is electrically connected to the first turn-on signal U2D, and the drain thereof is electrically connected to the first clock signal CK1.
  • the gate of the second transistor T2 is electrically connected to the second turn-on signal D2U, and the drain thereof is electrically connected to the second clock signal CK2.
  • the gate of the third transistor T3 is electrically connected to the sources of the first transistor T1 and the second transistor T2, and the drain thereof is electrically connected to the first fixed voltage VGH.
  • the gate of the first transistor T1 of the pull-down circuit 100b is electrically connected to the first turn-on signal U2D, and the drain thereof is electrically connected to the second clock signal CK2.
  • the gate of the second transistor T2 is electrically connected to the second turn-on signal D2U, and the drain thereof is electrically connected to the first clock signal CK1.
  • the gate of the third transistor T3 is electrically connected to the sources of the first transistor T1 and the second transistor T2, and the drain thereof is electrically connected to the first fixed voltage VGH.
  • the GOA circuit unit SR(2n+1) includes an input control module 300, an output control module 400, and a pull-down maintenance module 500.
  • the input control module 300 is electrically connected to the control node Q for using the scan signal G(2n-1) outputted by the first open signal U2D, the second turn-on signal D2U, and the first two stages of the GOA circuit unit SR(2n-1)
  • the scanning signal G(2n+3) outputted by the two-stage GOA circuit unit SR(2n+3) adjusts the voltage of the control node Q.
  • the input control module 300 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is electrically connected to the scan signal G(2n-1) outputted by the first two stages of the GOA circuit unit SR(2n-1), and the drain thereof is electrically connected to the first turn-on signal U2D, and its source is electrically Connect to control node Q.
  • the gate of the fifth transistor T5 is electrically connected to the scan signal G(2n+3) outputted by the two stages of the GOA circuit unit SR(2n+3), and the drain thereof is electrically connected to the second turn-on signal D2U, and its source is electrically connected. Connect to control node Q.
  • the output control module 400 is electrically connected to the control node Q for outputting the scan signal G(2n+1) according to the voltage applied to the control node Q.
  • the output control module 400 includes a sixth transistor T6 and a seventh transistor T7.
  • the gate of the sixth transistor T6 is electrically connected to the first fixed voltage VGH, and the drain thereof is electrically connected to the control node Q.
  • the gate of the seventh transistor T7 is electrically connected to the source of the sixth transistor T6, the drain thereof is electrically connected to the third clock signal CK3, and the source thereof is electrically connected to the output terminal OUT.
  • the gate of the seventh transistor T7 of the GOA circuit unit SR(2n+3) is electrically connected to the source of the sixth transistor T6, and the drain thereof is electrically connected to the fourth clock signal CK4.
  • the pull-down maintaining module 500 is electrically connected to the input control module 300 and the output control module 400 for maintaining the low level of the scan signal G(2n+1).
  • the pull-down maintaining module 500 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a capacitor C.
  • the gate of the eighth transistor T8 is electrically connected to the source of the third transistor T3, and the drain thereof is electrically connected to the control node Q, and the source thereof is electrically connected to the second fixed voltage VHL.
  • the gate of the ninth transistor T9 is electrically connected to the control node Q, and the drain thereof is electrically connected to the source of the third transistor T3, and the source thereof is electrically connected to the second fixed voltage VGL.
  • the gate of the tenth transistor T10 is electrically connected to the source of the third transistor T3, the drain thereof is electrically connected to the output terminal OUT, and the source thereof is electrically connected to the second fixed voltage VGL. Both ends of the capacitor C are connected to the gate of the ninth transistor T9 and the second fixed voltage VGL, respectively.
  • each transistor is an N-type metal oxide transistor (N-type metal oxide transistor).
  • N-type metal oxide transistor Semiconductor, PMOS
  • the first fixed voltage VGH is at a high level
  • the second fixed voltage VGL is at a low level.
  • FIG. 3 is a timing diagram of input signals and output signals of the GOA circuit unit group.
  • the first clock signal CK1 and the first turn-on signal U2D are both at a high level, so that the first transistor T1 is turned on first.
  • the gate of the third transistor T3 is turned on by the high level of the first clock signal CK1 to the high level of the first fixed voltage VGH.
  • the gate of the tenth transistor T10 turns on the low level of the second fixed voltage VGL due to the first fixed voltage VGH of the high level, so that the GOA circuit unit SR(2n+1)
  • the scan signals G(2n+1) and G(2n+3) output by SR(2n+3) are pulled down to a low level.
  • the second clock signal CK2 and the first turn-on signal U2D are both at a high level, so that the first transistor T1 is turned on the second The high level of the clock signal CK2.
  • the gate of the third transistor T3 is turned on by the high level second clock signal CK2 to the high level of the first fixed voltage VGH.
  • the gate of the tenth transistor T10 turns on the low level of the second fixed voltage VGL due to the first fixed voltage VGH of the high level, so that the GOA circuit unit SR(2n+5)
  • the scan signals G(2n+5) and G(2n+7) output by SR(2n+7) are pulled down to a low level.
  • each two-stage GOA circuit unit of the gate driving circuit 12 shares a pull-down circuit.
  • the adjacent two-stage GOA circuit units SR(2n+1), SR(2n+3) share the first pull-down circuit 100a
  • a pull-down module is required.
  • the present invention not only reduces the number of transistors used by the gate driving circuit 12 but also reduces the number of transistors by sharing the structure of the pull-down circuit every two stages of the GOA circuit unit.
  • Reducing the frequencies of the first clock signal CK1 and the second clock signal CK2 results in a reduction in the frequency of charging and discharging the parasitic capacitance, thereby reducing the overall power consumption of the gate driving circuit 12, and has the beneficial effect of power saving.
  • Each of the transistors in this embodiment is exemplified by an NMOS transistor.
  • those skilled in the art can replace all or part of the NMOS transistors with PMOS transistors in accordance with the circuit of the present invention to realize the same function of the GOA circuit unit. No longer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种栅极驱动电路（12），其包含数个GOA电路单元（SR(1)～SR(768)）。每两级GOA电路单元（SR(2n+1)、SR(2n+3)，SR(2n+5)、SR(2n+7)）共享一下拉电路（100a，100b）。下拉电路（100a，100b）包括第一晶体管（T1），其栅极电性连接第一开启信号（U2D），其漏极电性连接第一时钟信号（CK1）或第二时钟信号（CK2）；第二晶体管（T2），其栅极电性连接第二开启信号（D2U），其漏极电性连接第二时钟信号（CK2）或第一时钟信号（CK1）；及第三晶体管（T3），其栅极电性连接第一晶体管（T1）和第二晶体管（T2）的源极，其漏极电性连接第一固定电压（VGH）。栅极驱动电路（12）的每两级GOA电路单元（SR(2n+1)、SR(2n+3)，SR(2n+5)、SR(2n+7)）共享一下拉电路（100a，100b），不仅可以减少栅极驱动电路（12）使用的晶体管数量，也可以减少第一时钟信号（CK1）和第二时钟信号（CK2）的频率。减少第一时钟信号（CK1）和第二时钟信号（CK2）的频率导致减少对寄生电容充放电的频率，进而减低栅极驱动电路（12）的整体功耗。

Description

栅极驱动电路和使用栅极驱动电路的显示器 技术领域
本发明是有关于一种显示器，尤指一种使用栅极驱动(Gate driver on array，GOA)电路的显示器。
 背景技术
GOA电路是利用薄膜晶体管显示器Array制程将栅极驱动器制作在具有薄膜晶体管(Thin film transistor，TFT)阵列的基板上，以实现逐行扫描的驱动方式。
GOA电路包含数个GOA电路单元，每一GOA电路单元由数个晶体管和数个电容构成。由于GOA电路直接形成玻璃基板的侧边上，因此每一GOA电路单元的晶体管和电容的数量越少，GOA电路占用的玻璃基板面积就越少。此外，每一GOA电路单元在每一次信号切换的时候都会对寄生电容的充放电。因此频率较高的时钟信号对寄生电容产生的功耗影响较大。尤其是用于下拉模块的时钟信号对于寄生电容产生的功耗影响尤为明显。
因此如何制造一种可以减少使用晶体管数量和降低功耗的栅极驱动电路是业界努力的目标。
 技术问题
本发明的目的是提供一种栅极驱动电路和使用栅极驱动电路的显示器，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种栅极驱动电路，其包含数个GOA电路单元。数个所述GOA电路单元以串接的方式耦接，每一级GOA电路单元用来依据前两级GOA电路单元输出的扫描信号、后两级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第一开启信号以及第二开启信号，在输出端输出扫描信号。每两级GOA电路单元共享一下拉电路。所述下拉电路包括：第一晶体管，其栅极电性连接所述第一开启信号，其漏极电性连接所述第一时钟信号或所述第二时钟信号；第二晶体管，其栅极电性连接所述第二开启信号，其漏极电性连接所述第二时钟信号或所述第一时钟信号；及第三晶体管，其栅极电性连接所述第一晶体管和所述第二晶体管的源极，其漏极电性连接第一固定电压。每一GOA电路单元包括：输入控制模块，电性连接一控制节点，用来依据所述第一开启信号、所述第二开启信号、所述前两级GOA电路单元输出的扫描信号以及所述后两级GOA电路单元输出的扫描信号，调整所述控制节点的电压；输出控制模块，电性连接所述控制节点，用来依据施加于所述控制节点的电压，输出所述扫描信号；以及下拉维持模块，电性连接所述输入控制模块和所述输出控制模块，用来维持所述扫描信号的低电平。
依据本发明的实施例，所述输入控制模块包括：第四晶体管，其栅极电性连接所述前两级GOA电路单元输出的扫描信号，其漏极电性连接所述第一开启信号，其源极电性连接所述控制节点；及第五晶体管，其栅极电性连接所述后两级GOA电路单元输出的扫描信号，其漏极电性连接所述第二开启信号，其源极电性连接所述控制节点。
依据本发明的实施例，所述输出控制模块包括：第六晶体管，其栅极电性连接所述第一固定电压，其漏极电性连接所述控制节点；及第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第三时钟信号或是所述第四时钟信号，其源极电性连接所述输出端。
依据本发明的实施例，所述下拉维持模块包括：第八晶体管，其栅极电性连接所述第三晶体管的源极，其漏极电性连接所述控制节点，其源极电性连接第二固定电压；第九晶体管，其栅极电性连接所述控制节点，其漏极电性连接所述第三晶体管的源极，其源极电性连接所述第二固定电压；第十晶体管，其栅极电性连接所述第三晶体管的源极，其漏极电性连接所述输出端，其源极电性连接所述第二固定电压；及电容，其两端分别连接所述第九晶体管的栅极和所述第二固定电压。
依据本发明的实施例，每两级GOA电路单元的其中一个GOA电路单元的所述第七晶体管的漏极电性连接所述第三时钟信号，另一个GOA电路单元的所述第七晶体管的漏极电性连接所述第四时钟信号。
依据本发明的实施例，每一晶体管皆为N型金氧半导体晶体管，所述第一固定电压为低电平，所述第二固定电压为高电平。
依据本发明的实施例，每四个串接的GOA电路单元组成一GOA电路单元组，所述GOA电路单元组包含第一下拉电路以及第二下拉电路，所述第一下拉电路的第一晶体管的栅极和漏极分别电性连接所述第一开启信号和所述第一时钟信号，所述第一下拉电路的第二晶体管的栅极和漏极分别电性连接所述第二开启信号和所述第二时钟信号。所述第二下拉电路的第一晶体管的栅极和漏极分别电性连接所述第一开启信号和所述第二时钟信号，所述第二下拉电路的第二晶体管的栅极和漏极分别电性连接所述第二开启信号和所述第一时钟信号。
依据本发明的实施例，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号输出脉冲的时序互不重叠。
本发明的技术方案又提供一种显示器包含源极驱动器以及如上述的栅极驱动电路，所述栅极驱动电路输出扫描信号使得数个晶体管开启，同时所述源极驱动器输出对应的数据信号至数个像素单元使其显示灰阶。
有益效果
相较于现有技术，本发明的栅极驱动电路的每两级GOA电路单元共享一下拉电路，不仅可以减少栅极驱动电路使用的晶体管数量，也可以减少第一时钟信号和第二时钟信号的频率。减少第一时钟信号和第二时钟信号的频率导致减少对寄生电容充放电的频率，进而减低栅极驱动电路的整体功耗，具有省电的有益效果。
附图说明
图1是本发明使用栅极驱动电路的显示器的示意图。
图2是本发明较佳实施例的GOA电路单元的电路图。
图3是GOA电路单元组的输入信号和输出信号的时序图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图1，图1是本发明使用栅极驱动(Gate driver on array，GOA)电路的显示器10的示意图。显示器10可以为液晶显示器或是有机发光二极管显示器。显示器10包含GOA电路12、玻璃基板14、源极驱动器(source driver)16以及控制器18。基板14上设置数个呈矩阵排列的像素(pixel)和GOA电路12，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。以一个1024 × 768分辨率的显示器10来说，共需要1024 × 768 × 3个像素单元20组合而成。GOA电路12输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，GOA电路12便将该行的扫描信号关闭，然后GOA电路12再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到所有像素单元20都充电完成，再从第一行开始充电。
GOA电路12放置在玻璃基板14的两侧， 两个GOA电路12分别包含多个GOA 电路单元SR(1)、SR(3)、…SR(767)以及SR(2)、SR(4)、…SR(768)。多个GOA 电路单元SR(1)~SR(768)是一对一的连接到多行像素单元20。也就是说，两个GOA电路12分别用来控制单数和偶数行的像素单元20。当控制器18产生的时钟信号CK1-CK4以及GOA致动信号STV1、STV2传送至GOA 电路单元SR(1)~SR(768)时，GOA 电路单元SR(1)~SR(768)会产生扫描信号至像素单元20。
请参阅图2，图2是本发明较佳实施例的GOA电路单元SR(n)的电路图。本实施例中每四个GOA电路单元SR(2n+1)、SR(2n+3)、SR(2n+5)、SR(2n+7)构成一个GOA电路单元组SRG。GOA电路单元SR(2n+1)用来依据前两级GOA电路单元SR(2n-1)输出的扫描信号G(2n-1)、后两级GOA电路单元SR(2n+3)输出的扫描信号G(2n+3)、第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4、第一开启信号U2D以及第二开启信号D2U，在输出端OUT输出扫描信号G(2n+1)。相邻两级GOA电路单元SR(2n+1)、SR(2n+3)共享第一下拉电路100a。相邻两级GOA电路单元SR(2n+5)、SR(2n+7)共享第二下拉电路100b。第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4输出脉冲的时序互不重叠。
下拉电路100a包括第一晶体管T1、第二晶体管T2和第三晶体管T3。第一晶体管T1的栅极电性连接第一开启信号U2D，其漏极电性连接第一时钟信号CK1。第二晶体管T2的栅极电性连接第二开启信号D2U，其漏极电性连接第二时钟信号CK2。第三晶体管T3的栅极电性连接第一晶体管T1和第二晶体管T2的源极，其漏极电性连接第一固定电压VGH。下拉电路100b的第一晶体管T1的栅极电性连接第一开启信号U2D，其漏极电性连接第二时钟信号CK2。第二晶体管T2的栅极电性连接第二开启信号D2U，其漏极电性连接第一时钟信号CK1。第三晶体管T3的栅极电性连接第一晶体管T1和第二晶体管T2的源极，其漏极电性连接第一固定电压VGH。
因为每一级GOA电路单元的电路架构相同，因此以下实施例仅以GOA电路单元SR(2n+1)来做说明。GOA电路单元SR(2n+1)包括输入控制模块300、输出控制模块400和下拉维持模块500。输入控制模块300电性连接控制节点Q，用来依据第一开启信号U2D、第二开启信号D2U、前两级GOA电路单元SR(2n-1)输出的扫描信号G(2n-1)以及后两级GOA电路单元SR(2n+3)输出的扫描信号G(2n+3)，调整控制节点Q的电压。输入控制模块300包括第四晶体管T4和第五晶体管T5。第四晶体管T4的栅极电性连接前两级GOA电路单元SR(2n-1)输出的扫描信号G(2n-1)，其漏极电性连接第一开启信号U2D，其源极电性连接控制节点Q。第五晶体管T5的栅极电性连接后两级GOA电路单元SR(2n+3)输出的扫描信号G(2n+3)，其漏极电性连接第二开启信号D2U，其源极电性连接控制节点Q。
输出控制模块400电性连接控制节点Q，用来依据施加于控制节点Q的电压，输出扫描信号G(2n+1)。输出控制模块400包括第六晶体管T6和第七晶体管T7。第六晶体管T6的栅极电性连接第一固定电压VGH，其漏极电性连接控制节点Q。第七晶体管T7的栅极电性连接第六晶体管T6的源极，其漏极电性连接第三时钟信号CK3，其源极电性连接输出端OUT。请注意，GOA电路单元SR(2n+3)的第七晶体管T7的栅极电性连接第六晶体管T6的源极，其漏极电性连接第四时钟信号CK4。
下拉维持模块500电性连接输入控制模块300和输出控制模块400，用来维持扫描信号G(2n+1)的低电平。下拉维持模块500包括第八晶体管T8、第九晶体管T9、第十晶体管T10和电容C。第八晶体管T8的栅极电性连接第三晶体管T3的源极，其漏极电性连接控制节点Q，其源极电性连接第二固定电压VHL。第九晶体管T9的栅极电性连接控制节点Q，其漏极电性连接第三晶体管T3的源极，其源极电性连接第二固定电压VGL。第十晶体管T10的栅极电性连接第三晶体管T3的源极，其漏极电性连接输出端OUT，其源极电性连接第二固定电压VGL。电容C的两端分别连接第九晶体管T9的栅极和第二固定电压VGL。
依据图2所示的实施例，每一晶体管皆为N型金氧半导体晶体管(N-type metal oxide semiconductor，PMOS)，第一固定电压VGH为高电平，第二固定电压VGL为低电平。
请参阅图3，图3是GOA电路单元组的输入信号和输出信号的时序图。对GOA电路单元SR(2n+1)和SR(2n+3)来说，在t1期间，第一时钟信号CK1和第一开启信号U2D皆处于高电平，使得第一晶体管T1导通第一时钟信号CK1的高电平。此时，第三晶体管T3的栅极因为高电平的第一时钟信号CK1而导通第一固定电压VGH的高电平。第十晶体管T10的栅极因为高电平的第一固定电压VGH而导通第二固定电压VGL的低电平，使得GOA电路单元SR(2n+1) 和SR(2n+3)输出的扫描信号G(2n+1)和G(2n+3)皆被下拉为低电平。
对GOA电路单元SR(2n+5)和SR(2n+7)来说，在t2期间，第二时钟信号CK2和第一开启信号U2D皆处于高电平，使得第一晶体管T1导通第二时钟信号CK2的高电平。此时，第三晶体管T3的栅极因为高电平的第二时钟信号CK2而导通第一固定电压VGH的高电平。第十晶体管T10的栅极因为高电平的第一固定电压VGH而导通第二固定电压VGL的低电平，使得GOA电路单元SR(2n+5) 和SR(2n+7)输出的扫描信号G(2n+5)和G(2n+7)皆被下拉为低电平。
由上述实施例可以了解，栅极驱动电路12的每两级GOA电路单元共享一下拉电路。举例来说，相邻两级GOA电路单元SR(2n+1)、SR(2n+3)共享第一下拉电路100a，相邻两级GOA电路单元SR(2n+5)、SR(2n+7)共享第二下拉电路100b。相较于传统每一级GOA电路单元都须要设置下拉模块，本发明通过每两级GOA电路单元共享一下拉电路的架构，不仅可以减少栅极驱动电路12使用的晶体管数量，也可以减少第一时钟信号CK1和第二时钟信号CK2的频率。减少第一时钟信号CK1和第二时钟信号CK2的频率导致减少对寄生电容充放电的频率，进而减低栅极驱动电路12的整体功耗，具有省电的有益效果。
本实施例的每一晶体管是以NMOS晶体管为例做说明，但是本领域技术人员可以根据本发明的电路将其中全部或是部分NMOS晶体管以PMOS晶体管取代，以实现同样功能的GOA电路单元，以下不再赘述。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串接的方式耦接，每一级GOA电路单元用来依据前两级GOA电路单元输出的扫描信号、后两级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第一开启信号以及第二开启信号，在输出端输出扫描信号，其中每两级GOA电路单元共享一下拉电路，且所述下拉电路包括：
    第一晶体管，其栅极电性连接所述第一开启信号，其漏极电性连接所述第一时钟信号或所述第二时钟信号；
    第二晶体管，其栅极电性连接所述第二开启信号，其漏极电性连接所述第二时钟信号或所述第一时钟信号；及
    第三晶体管，其栅极电性连接所述第一晶体管和所述第二晶体管的源极，其漏极电性连接第一固定电压；
    每一GOA电路单元包括：
    输入控制模块，电性连接一控制节点，用来依据所述第一开启信号、所述第二开启信号、所述前两级GOA电路单元输出的扫描信号以及所述后两级GOA电路单元输出的扫描信号，调整所述控制节点的电压；
    输出控制模块，电性连接所述控制节点，用来依据施加于所述控制节点的电压，输出所述扫描信号；以及
    下拉维持模块，电性连接所述输入控制模块和所述输出控制模块，用来维持所述扫描信号的低电平。
  2. 如权利要求1所述的栅极驱动电路，其中所述输入控制模块包括：
    第四晶体管，其栅极电性连接所述前两级GOA电路单元输出的扫描信号，其漏极电性连接所述第一开启信号，其源极电性连接所述控制节点；及
    第五晶体管，其栅极电性连接所述后两级GOA电路单元输出的扫描信号，其漏极电性连接所述第二开启信号，其源极电性连接所述控制节点。
  3. 如权利要求2所述的栅极驱动电路，其中所述输出控制模块包括：
    第六晶体管，其栅极电性连接所述第一固定电压，其漏极电性连接所述控制节点；及
    第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第三时钟信号或是所述第四时钟信号，其源极电性连接所述输出端。
  4. 如权利要求3所述的栅极驱动电路，其中所述下拉维持模块包括：
    第八晶体管，其栅极电性连接所述第三晶体管的源极，其漏极电性连接所述控制节点，其源极电性连接第二固定电压；
    第九晶体管，其栅极电性连接所述控制节点，其漏极电性连接所述第三晶体管的源极，其源极电性连接所述第二固定电压；
    第十晶体管，其栅极电性连接所述第三晶体管的源极，其漏极电性连接所述输出端，其源极电性连接所述第二固定电压；及
    电容，其两端分别连接所述第九晶体管的栅极和所述第二固定电压。
  5. 如权利要求3所述的栅极驱动电路，其中每两级GOA电路单元的其中一个GOA电路单元的所述第七晶体管的漏极电性连接所述第三时钟信号，另一个GOA电路单元的所述第七晶体管的漏极电性连接所述第四时钟信号。
  6. 如权利要求5所述的栅极驱动电路，其中每一晶体管皆为N型金氧半导体晶体管，所述第一固定电压为低电平，所述第二固定电压为高电平。
  7. 如权利要求1所述的栅极驱动电路，其中每四个串接的GOA电路单元组成一GOA电路单元组，所述GOA电路单元组包含第一下拉电路以及第二下拉电路，所述第一下拉电路的第一晶体管的栅极和漏极分别电性连接所述第一开启信号和所述第一时钟信号，所述第一下拉电路的第二晶体管的栅极和漏极分别电性连接所述第二开启信号和所述第二时钟信号；
    所述第二下拉电路的第一晶体管的栅极和漏极分别电性连接所述第一开启信号和所述第二时钟信号，所述第二下拉电路的第二晶体管的栅极和漏极分别电性连接所述第二开启信号和所述第一时钟信号。
  8. 如权利要求1所述的栅极驱动电路，其中所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号输出脉冲的时序互不重叠。
  9. 一种显示器，其包含：
    源极驱动器，输出对应的数据信号至数个像素单元使其显示灰阶；以及
    栅极驱动电路，用來输出扫描信号使得数个晶体管开启，所述栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串接的方式耦接，每一级GOA电路单元用来依据前两级GOA电路单元输出的扫描信号、后两级GOA电路单元输出的扫描信号、第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第一开启信号以及第二开启信号，在输出端输出扫描信号，其中每两级GOA电路单元共享一下拉电路，且所述下拉电路包括：
    第一晶体管，其栅极电性连接所述第一开启信号，其漏极电性连接所述第一时钟信号或所述第二时钟信号；
    第二晶体管，其栅极电性连接所述第二开启信号，其漏极电性连接所述第二时钟信号或所述第一时钟信号；及
    第三晶体管，其栅极电性连接所述第一晶体管和所述第二晶体管的源极，其漏极电性连接第一固定电压；
    每一GOA电路单元包括：
    输入控制模块，电性连接一控制节点，用来依据所述第一开启信号、所述第二开启信号、所述前两级GOA电路单元输出的扫描信号以及所述后两级GOA电路单元输出的扫描信号，调整所述控制节点的电压；
    输出控制模块，电性连接所述控制节点，用来依据施加于所述控制节点的电压，输出所述扫描信号；以及
    下拉维持模块，电性连接所述输入控制模块和所述输出控制模块，用来维持所述扫描信号的低电平。
  10. 如权利要求9所述的显示器，其中所述输入控制模块包括：
    第四晶体管，其栅极电性连接所述前两级GOA电路单元输出的扫描信号，其漏极电性连接所述第一开启信号，其源极电性连接所述控制节点；及
    第五晶体管，其栅极电性连接所述后两级GOA电路单元输出的扫描信号，其漏极电性连接所述第二开启信号，其源极电性连接所述控制节点。
  11. 如权利要求10所述的显示器，其中所述输出控制模块包括：
    第六晶体管，其栅极电性连接所述第一固定电压，其漏极电性连接所述控制节点；及
    第七晶体管，其栅极电性连接所述第六晶体管的源极，其漏极电性连接所述第三时钟信号或是所述第四时钟信号，其源极电性连接所述输出端。
  12. 如权利要求11所述的显示器，其中所述下拉维持模块包括：
    第八晶体管，其栅极电性连接所述第三晶体管的源极，其漏极电性连接所述控制节点，其源极电性连接第二固定电压；
    第九晶体管，其栅极电性连接所述控制节点，其漏极电性连接所述第三晶体管的源极，其源极电性连接所述第二固定电压；
    第十晶体管，其栅极电性连接所述第三晶体管的源极，其漏极电性连接所述输出端，其源极电性连接所述第二固定电压；及
    电容，其两端分别连接所述第九晶体管的栅极和所述第二固定电压。
  13. 如权利要求11所述的显示器，其中每两级GOA电路单元的其中一个GOA电路单元的所述第七晶体管的漏极电性连接所述第三时钟信号，另一个GOA电路单元的所述第七晶体管的漏极电性连接所述第四时钟信号。
  14. 如权利要求13所述的显示器，其中每一晶体管皆为N型金氧半导体晶体管，所述第一固定电压为低电平，所述第二固定电压为高电平。
  15. 如权利要求9所述的显示器，其中每四个串接的GOA电路单元组成一GOA电路单元组，所述GOA电路单元组包含第一下拉电路以及第二下拉电路，所述第一下拉电路的第一晶体管的栅极和漏极分别电性连接所述第一开启信号和所述第一时钟信号，所述第一下拉电路的第二晶体管的栅极和漏极分别电性连接所述第二开启信号和所述第二时钟信号；
    所述第二下拉电路的第一晶体管的栅极和漏极分别电性连接所述第一开启信号和所述第二时钟信号，所述第二下拉电路的第二晶体管的栅极和漏极分别电性连接所述第二开启信号和所述第一时钟信号。
  16. 如权利要求9所述的显示器，其中所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号输出脉冲的时序互不重叠。
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105632441B (zh) * 2016-02-26 2018-03-27 深圳市华星光电技术有限公司 栅极驱动电路
CN105869593B (zh) * 2016-06-01 2018-03-13 深圳市华星光电技术有限公司 一种显示面板及其栅极驱动电路
CN106023933B (zh) * 2016-07-21 2019-02-15 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN106128403B (zh) * 2016-09-05 2018-10-23 京东方科技集团股份有限公司 移位寄存器单元、栅极扫描电路
CN106448607B (zh) * 2016-11-28 2019-01-29 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106548740A (zh) * 2016-12-02 2017-03-29 京东方科技集团股份有限公司 移位寄存电路及其驱动方法、栅极驱动电路及显示装置
CN106652949B (zh) * 2016-12-28 2019-03-26 深圳市华星光电技术有限公司 栅极驱动电路及液晶显示装置
CN106548759B (zh) * 2017-01-14 2018-09-18 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN108346395B (zh) * 2017-01-24 2020-04-21 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN107799083B (zh) * 2017-11-17 2020-02-07 武汉华星光电技术有限公司 一种goa电路
CN107993620B (zh) * 2017-11-17 2020-01-10 武汉华星光电技术有限公司 一种goa电路
CN107731195B (zh) * 2017-11-22 2019-10-11 武汉华星光电技术有限公司 一种nmos型goa电路及显示面板
CN107919101B (zh) * 2018-01-04 2020-06-12 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板及显示装置
CN108806611B (zh) * 2018-06-28 2021-03-19 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
US10769982B2 (en) 2018-08-31 2020-09-08 Apple Inc. Alternate-logic head-to-head gate driver on array
US10891902B2 (en) * 2019-05-06 2021-01-12 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Driving circuit of display device
CN110335572B (zh) * 2019-06-27 2021-10-01 重庆惠科金渝光电科技有限公司 阵列基板行驱动电路单元与其驱动电路及液晶显示面板
CN110517637B (zh) * 2019-08-30 2021-05-25 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示面板
CN110767146A (zh) * 2019-10-25 2020-02-07 福建华佳彩有限公司 多级驱动电路
CN113870755B (zh) * 2020-06-30 2024-01-19 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路、驱动方法及显示装置
CN111696483B (zh) * 2020-07-10 2022-04-08 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN113570996B (zh) 2021-07-30 2022-05-10 惠科股份有限公司 显示面板的驱动电路和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080279327A1 (en) * 2007-05-09 2008-11-13 Chunghwa Picture Tubes, Ltd. Shift register and shift register apparatus thereof
CN103839510A (zh) * 2014-03-26 2014-06-04 华映视讯（吴江）有限公司 栅极驱动电路
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104376826A (zh) * 2014-11-20 2015-02-25 深圳市华星光电技术有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104376825A (zh) * 2014-11-20 2015-02-25 深圳市华星光电技术有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104575436A (zh) * 2015-02-06 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101080352B1 (ko) * 2004-07-26 2011-11-04 삼성전자주식회사 표시 장치
TWI394134B (zh) * 2008-12-12 2013-04-21 Au Optronics Corp 預下拉前級突波之移位暫存器
KR101579082B1 (ko) * 2008-12-23 2015-12-22 삼성디스플레이 주식회사 게이트 구동회로 및 이의 구동 방법
TWI415052B (zh) * 2010-12-29 2013-11-11 Au Optronics Corp 開關裝置與應用該開關裝置之移位暫存器電路
TWI421849B (zh) * 2010-12-30 2014-01-01 Au Optronics Corp 液晶顯示裝置
KR101777135B1 (ko) * 2011-07-12 2017-09-12 엘지디스플레이 주식회사 쉬프트 레지스터
TWI473059B (zh) * 2013-05-28 2015-02-11 Au Optronics Corp 移位暫存器電路
CN104700789B (zh) * 2013-12-09 2017-10-31 北京大学深圳研究生院 移位寄存器、栅极驱动电路单元、栅极驱动电路及显示器
KR102207142B1 (ko) * 2014-01-24 2021-01-25 삼성디스플레이 주식회사 표시 패널에 집적된 게이트 구동부
TWI524325B (zh) * 2014-09-10 2016-03-01 友達光電股份有限公司 移位暫存器
CN104537992B (zh) * 2014-12-30 2017-01-18 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN104766576B (zh) * 2015-04-07 2017-06-27 深圳市华星光电技术有限公司 基于p型薄膜晶体管的goa电路
CN105161060B (zh) * 2015-08-18 2017-12-15 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105096904B (zh) * 2015-09-30 2018-04-10 京东方科技集团股份有限公司 栅极驱动电路、显示装置和驱动方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080279327A1 (en) * 2007-05-09 2008-11-13 Chunghwa Picture Tubes, Ltd. Shift register and shift register apparatus thereof
CN103839510A (zh) * 2014-03-26 2014-06-04 华映视讯（吴江）有限公司 栅极驱动电路
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104376826A (zh) * 2014-11-20 2015-02-25 深圳市华星光电技术有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104376825A (zh) * 2014-11-20 2015-02-25 深圳市华星光电技术有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104575436A (zh) * 2015-02-06 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置

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