[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2017168594A1 - Thin film transistor, display panel, and method for manufacturing thin film transistor - Google Patents

Thin film transistor, display panel, and method for manufacturing thin film transistor Download PDF

Info

Publication number
WO2017168594A1
WO2017168594A1 PCT/JP2016/060253 JP2016060253W WO2017168594A1 WO 2017168594 A1 WO2017168594 A1 WO 2017168594A1 JP 2016060253 W JP2016060253 W JP 2016060253W WO 2017168594 A1 WO2017168594 A1 WO 2017168594A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide semiconductor
film
semiconductor film
electrode film
low
Prior art date
Application number
PCT/JP2016/060253
Other languages
French (fr)
Japanese (ja)
Inventor
悟志 道中
覚 宇津木
伸武 野寺
隆夫 松本
小林 和樹
大亥 桶谷
Original Assignee
堺ディスプレイプロダクト株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 堺ディスプレイプロダクト株式会社 filed Critical 堺ディスプレイプロダクト株式会社
Priority to PCT/JP2016/060253 priority Critical patent/WO2017168594A1/en
Publication of WO2017168594A1 publication Critical patent/WO2017168594A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]

Definitions

  • the present invention relates to a thin film transistor, a display panel including the thin film transistor, and a method for manufacturing the thin film transistor.
  • a TFT (thin film transistor) type liquid crystal display (display panel) has a required gap between a TFT substrate and a color filter substrate having colors of R (red), G (green), and B (blue).
  • the image can be displayed by bonding, injecting liquid crystal between the TFT substrate and the color filter substrate, and controlling the light transmittance of the liquid crystal molecules for each pixel.
  • data lines and scanning lines are arranged in a grid pattern in the vertical and horizontal directions, and pixels in which TFTs are arranged at respective locations where the data lines and the scanning lines intersect are formed.
  • a driving circuit for driving the data lines and the scanning lines is formed around a display area including a plurality of pixels.
  • amorphous silicon (amorphous, a-Si) TFT using a silicon semiconductor low-temperature polysilicon TFT using a semiconductor layer of polysilicon (polycrystalline, p-Si), and the like are being developed.
  • oxide semiconductors have advantages of higher electron mobility than an amorphous silicon TFT and less leakage current than a silicon semiconductor.
  • a TFT using an oxide semiconductor is configured so that the region of the gate electrode film and the region of the source / drain electrode film do not overlap in the thickness direction of the TFT.
  • the self-alignment type self-alignment
  • a region of the oxide semiconductor layer source / drain region that does not overlap with the gate electrode film when irradiated with predetermined light from the back side of the substrate
  • An oxide semiconductor TFT is disclosed in which the resistance is reduced to improve the characteristics (see Patent Document 1).
  • the region that does not overlap the gate electrode film region is a low-resistance oxide semiconductor layer, but the region that overlaps the gate electrode film region is amorphous (non- (Crystalline). Therefore, when backlight light is incident from the back side of the substrate, the backlight light is easily incident on the amorphous oxide semiconductor layer corresponding to the channel region above the gate electrode film. become. For this reason, at the time of light irradiation, for example, there is a problem that characteristic fluctuation such as a relatively large shift of the threshold voltage of the gate voltage occurs and the light stability is lacking.
  • the present invention has been made in view of such circumstances, and an object thereof is to provide a thin film transistor capable of improving light stability, a display panel including the thin film transistor, and a method for manufacturing the thin film transistor.
  • a thin film transistor includes a gate electrode film formed on a surface of the substrate and an amorphous oxide formed on the gate electrode film in the thin film transistor having an oxide semiconductor film on the substrate.
  • the gate electrode film and the amorphous oxide semiconductor film are arranged in a region corresponding to the gate electrode film in a projected state in which the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate.
  • a display panel according to an embodiment of the present invention includes the thin film transistor according to the above-described embodiment.
  • a method for manufacturing a thin film transistor according to an embodiment of the present invention includes a method for manufacturing a thin film transistor having an oxide semiconductor film on a substrate, wherein a gate electrode film is formed on a surface of the substrate, and an amorphous material is formed on the gate electrode film.
  • the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate, and the amorphous oxide semiconductor film is used as the gate electrode film.
  • a first and second low resistance oxide semiconductor films are formed by irradiating an energy beam to a required portion of the amorphous oxide semiconductor film which is formed in a corresponding region, and the first low resistance oxidation semiconductor film is formed.
  • a source electrode film is formed on the physical semiconductor film, and a drain electrode film is formed on the second low-resistance oxide semiconductor film.
  • FIG. 2 is a schematic cross-sectional view of a main part viewed from the line II-II in FIG. It is a manufacturing process figure which shows an example of the manufacturing method of the thin-film transistor of 1st Embodiment. It is a schematic diagram which shows an example of a structure of a partial irradiation type laser. It is a schematic diagram which shows an example of the mode at the time of light irradiation of the thin-film transistor of 1st Embodiment. It is a schematic diagram which shows an example of the characteristic fluctuation
  • FIG. 1 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of the first embodiment, and FIG.
  • a thin film transistor (TFT: Thin Film Transistor, also referred to as a TFT substrate) has a gate electrode film 2 formed on the surface of a glass substrate 1 (also referred to as a substrate).
  • a gate insulating film 3 (for example, a SiO 2 film) is formed so as to cover the surface.
  • the amorphous oxide semiconductor film 4 is an amorphous (amorphous) oxide semiconductor film.
  • the low resistance oxide semiconductor films 5 and 6 are oxide semiconductor films having a lower resistance than the amorphous oxide semiconductor film 4 due to oxygen deficiency caused by energy beam irradiation and increase of free electrons.
  • an oxide semiconductor film including crystals or an oxide semiconductor film having crystallinity may be used.
  • the crystal state may be a state in which the directions of crystal axes are disordered or a state having a certain orientation.
  • the oxide semiconductor film (4, 5, 6) is, for example, an oxide of three elements of indium (In), gallium (Ga), and zinc (Zn), but is not limited to this.
  • an oxide containing at least one element from elements such as gallium, zinc, tin, aluminum, silicon, germanium, titanium, molybdenum, boron, and manganese can also be used.
  • a source electrode film 7 is formed on the first low-resistance oxide semiconductor film 5.
  • a drain electrode film 8 is formed on the second low resistance oxide semiconductor film 6.
  • the first low-resistance oxide semiconductor film 5 and the second low-resistance oxide semiconductor film 6 are also referred to as low-resistance oxide semiconductor films 5 and 6, respectively.
  • an etch stopper film as a protective film is formed after or before the formation of the first low-resistance oxide semiconductor film 5, the second low-resistance oxide semiconductor film 6, and the amorphous oxide semiconductor film 4. May be.
  • a passivation film 9 is formed on the entire TFT substrate so as to cover the source electrode film 7 and the drain electrode film 8, and an organic film 10 is formed on the surface of the passivation film 9 to flatten the surface. .
  • Through holes are formed at required positions of the passivation film 9 and the organic film 10 so that the transparent conductive film (for example, ITO) 11 and the drain electrode film 8 are electrically connected through the through holes.
  • a pixel electrode (not shown) is connected to the transparent conductive film 11.
  • FIG. 1 shows a gate electrode film 2, an amorphous oxide semiconductor film 4, a first low resistance oxide semiconductor film 5, a second low resistance oxide semiconductor film 6, a source electrode film 7 and a drain electrode film 8.
  • the projection state projected on the surface of the substrate 1 is schematically shown.
  • 1 shows a region on the substrate 1 corresponding to the gate electrode film 2, a region on the substrate 1 corresponding to the amorphous oxide semiconductor film 4, and the substrate 1 corresponding to the low-resistance oxide semiconductor films 5 and 6.
  • An upper region, a region on the substrate 1 corresponding to the source electrode film 7 and a region on the substrate 1 corresponding to the drain electrode film 8 are schematically shown.
  • reference numeral 21 denotes a wiring portion to the gate electrode film.
  • region shown in FIG. 1 is shown typically for convenience, and an actual shape may differ.
  • the amorphous oxide semiconductor film 4 is It is arranged in a region corresponding to the gate electrode film 2.
  • the amorphous oxide semiconductor film 4 between the first low-resistance oxide semiconductor film 5 and the second low-resistance oxide semiconductor film 6 is also disposed in a region corresponding to the gate electrode film 2. .
  • FIG. 3 is a manufacturing process diagram showing an example of a manufacturing method of the thin film transistor of the first embodiment.
  • a manufacturing process of the thin film transistor of this embodiment will be described.
  • an aluminum (Al) film is formed on a substrate (glass substrate) 1 using a sputtering method, and the aluminum (Al) film is patterned using a photolithography method and an etching method.
  • a gate electrode film 2 having a width of is formed (S11).
  • the material used for the gate electrode film 2 is not limited to aluminum, and for example, elemental elements such as copper, titanium, tungsten, gold, platinum, molybdenum, or nickel, or alloys thereof may be used.
  • the gate insulating film 3 is formed on the substrate 1 using the plasma CVD method so as to cover the gate electrode film 2 (S12).
  • an oxide semiconductor film is formed on the gate insulating film 3 by using a sputtering method (S13).
  • This oxide semiconductor film is the amorphous oxide semiconductor film 4 and is formed, for example, in an environment below a temperature at which the oxide semiconductor has a low resistance.
  • other film formation methods such as a pulsed laser deposition method, an electron beam deposition method, or a coating deposition method may be used instead of the sputtering method.
  • partial laser annealing is performed by irradiating a required portion of the amorphous oxide semiconductor film 4 with an energy beam such as an excimer laser (S14).
  • an energy beam such as an excimer laser (S14).
  • a required portion for example, a portion indicated by reference numerals 5 and 6 in FIGS. 1 and 2
  • the required portion is a region corresponding to the source region and the drain region in the amorphous oxide semiconductor film 4 formed on the gate insulating film 3.
  • a required pattern is formed on the amorphous oxide semiconductor film 4 and the low-resistance oxide semiconductor films 5 and 6.
  • the required pattern can be appropriately determined according to the arrangement or structure of the source electrode film 7, the drain electrode film 8, and the semiconductor layer.
  • FIG. 4 is a schematic diagram showing an example of the configuration of a partial irradiation type laser.
  • the substrate 1 on which the amorphous oxide semiconductor film 4 is formed is placed on a mounting table (not shown) so as to translate in the direction of the arrow in FIG. 4 at a required speed. It is.
  • a multi-lens array is arranged in which individual lenses are arranged at an appropriate distance along a direction intersecting the moving direction of the substrate 1.
  • the laser beam is partially irradiated to a plurality of required locations separated via different optical paths for each lens. That is, partial laser annealing can be performed.
  • a laser mask (light-shielding member) is disposed between the laser light source and the multi-lens array or between the multi-lens array and the substrate 1.
  • the beam shape of the laser beam can be shaped into, for example, a rectangular shape or a required size by the mask.
  • the first low-resistance oxide semiconductor film 5 and the second low-resistance oxide semiconductor film 6 are amorphous oxides formed on the upper side of the gate electrode film 2. It is formed by irradiating an energy beam (for example, an energy beam of an excimer laser or the like) to a required separated portion of the physical semiconductor film 4.
  • the required portion is a region corresponding to the source region and the drain region in the amorphous oxide semiconductor film 4, and the amorphous oxide semiconductor film 4 is reduced to a low-resistance oxide semiconductor film 5 by irradiation with an energy beam. , 6 can be changed.
  • the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film.
  • the region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance is not lowered and remains amorphous.
  • an energy beam for example, a laser
  • a laser is locally (or partially) applied to a required portion of the amorphous oxide semiconductor film 4 formed on the upper side of the gate electrode film 2.
  • the low-resistance oxide semiconductor films 5 and 6 can be formed so that the amorphous oxide semiconductor film 4 is disposed in a region corresponding to the gate electrode film 2. .
  • the entire surface is irradiated with laser light from the back side of the substrate, so the laser light is irradiated to all locations, such as the gate electrode film, the tapered portion of the gate electrode film, and the opening. It is difficult to obtain uniform crystallinity due to non-uniformity of the intensity distribution of laser light or variations in intensity for each irradiation.
  • the resistance can be reduced by focusing only on a required portion of the amorphous oxide semiconductor film 4 on the upper side of the gate electrode film 2, so that the variation in resistance reduction is small.
  • a display panel with high reliability can be manufactured.
  • FIG. 5 is a schematic view showing an example of the state of the thin film transistor according to the first embodiment during light irradiation.
  • FIG. 5 shows how the light from the backlight is incident from the back side of the substrate 1.
  • the thin film transistor of this embodiment includes the first low-resistance oxide corresponding to the channel region in a projected state in which the gate electrode film 2 and the amorphous oxide semiconductor film 4 are projected onto the surface of the substrate 1.
  • the amorphous oxide semiconductor film 4 between the semiconductor film 5 and the second low resistance oxide semiconductor film 6 is disposed in a region corresponding to the gate electrode film 2.
  • FIG. 6 is a schematic diagram illustrating an example of characteristic variation of the thin film transistor of the first embodiment
  • FIG. 7 is a schematic diagram illustrating an example of characteristic variation of the conventional thin film transistor. 6 and 7, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current.
  • the arrows in the figure indicate the passage of time from the start of applying a positive or negative voltage under a light irradiation environment (also referred to as an optical bias stress state).
  • the initial drain current-gate voltage characteristics of the thin film transistor according to the present embodiment are as shown by the graph indicated by symbol A.
  • symbols B and C indicate the time. It changes as follows. That is, as shown in FIG. 5, light incident on the amorphous oxide semiconductor film 4 corresponding to the channel region can be reduced. Therefore, as shown in FIG. The shift of the threshold voltage of the gate voltage can be reduced, and light stability can be improved.
  • the oxide semiconductor film immediately above the gate electrode film is an amorphous oxide semiconductor film without being reduced in resistance. Therefore, when backlight light is incident from the back side of the substrate, the backlight light is easily incident on the amorphous oxide semiconductor film on the upper side of the gate electrode film.
  • the initial drain current-gate voltage characteristic of the conventional thin film transistor is as shown by a graph indicated by symbol a, and changes with time elapse in an optical bias stress state as indicated by symbols b and c. . That is, in the optical bias stress state, for example, characteristic variation such as a relatively large shift of the threshold voltage of the gate voltage occurs, resulting in lack of light stability. Note that the threshold voltage shift is considered to be caused by oxygen vacancies generated at the channel-gate insulating film interface.
  • FIG. 8 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of the second embodiment.
  • the first low-resistance oxide semiconductor film 51, the amorphous oxide semiconductor film 4 formed on the upper side of the gate electrode film 2, and the source electrode film 7 are projected onto the surface of the substrate 1.
  • the area of the region where the source electrode film 7 and the first low-resistance oxide semiconductor film 51 overlap is the same as that of the source electrode film 7 and the amorphous oxide semiconductor film. 4 is larger than the area of a region where 4 overlaps (region indicated by reference numeral 41 in FIG. 8).
  • the low-resistance oxide semiconductor film 51 immediately below the source electrode film 7 does not form a channel region but has a parasitic resistance. Therefore, by making the area of the low-resistance oxide semiconductor film 51 immediately below the source electrode film 7 larger than the area of the amorphous oxide semiconductor film 41 immediately below the source electrode film 7, in the region directly below the source electrode film 7.
  • the ratio of the region occupied by the low-resistance oxide semiconductor film 51 can be increased, the parasitic resistance can be lowered, and the current driving capability can be increased.
  • the entire region of the amorphous oxide semiconductor film 41 immediately below the source electrode film 7 may be the low resistance oxide semiconductor film 51. In this case, the ratio of the region occupied by the low-resistance oxide semiconductor film 51 in the region immediately below the source electrode film 7 is 100%.
  • the drain electrode overlaps the region where the drain electrode film 8 and the amorphous oxide semiconductor film 4 overlap ( In FIG. 8, the area is larger than the area indicated by reference numeral 42.
  • the low-resistance oxide semiconductor film 61 immediately below the drain electrode film 8 does not form a channel region and has a parasitic resistance. Therefore, by making the area of the low-resistance oxide semiconductor film 61 immediately below the drain electrode film 8 larger than the area of the amorphous oxide semiconductor film 42 immediately below the drain electrode film 8, in the area directly below the drain electrode film 8.
  • the parasitic resistance can be lowered and the current driving capability can be increased.
  • the entire region of the amorphous oxide semiconductor film 42 immediately below the drain electrode film 8 may be the low resistance oxide semiconductor film 61. In this case, the ratio of the region occupied by the low-resistance oxide semiconductor film 61 in the region immediately below the drain electrode film 8 is 100%.
  • FIG. 9 is a schematic diagram showing an example of drain current-gate voltage characteristics of the thin film transistor of the second embodiment.
  • the horizontal axis represents the gate voltage
  • the vertical axis represents the drain current.
  • the resistance can be lowered and the drain current can be reduced. Can be increased.
  • the value of the parasitic resistance can be controlled by controlling the width (for example, area) of the regions of the low-resistance oxide semiconductor films 51 and 61. The description of the same parts as those in the first embodiment is omitted.
  • FIG. 10 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of the third embodiment.
  • the thin film transistor shown in FIG. 10 is used, for example, in a GOA (Gate Driver On Array) circuit section.
  • the gate electrode film 2 having a rectangular shape in plan view is provided on the substrate, and the elongated amorphous oxide semiconductor film 4 and the elongated shape are formed in a region corresponding to the gate electrode film 2.
  • the low resistance oxide semiconductor films 5 and 6 are arranged in order.
  • a source electrode film 7 is formed on the first low resistance oxide semiconductor film 5, and a drain electrode film 8 is formed on the second low resistance oxide semiconductor film 6.
  • the thin film transistor according to the third embodiment is in a projected state in which the gate electrode film 2, the first low-resistance oxide semiconductor film 5, and the second low-resistance oxide semiconductor film 6 are projected onto the surface of the substrate 1.
  • the low resistance oxide semiconductor film 5 and the second low resistance oxide semiconductor film 6 are disposed in a region corresponding to the gate electrode film 2.
  • the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film. Therefore, the region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance cannot be reduced.
  • a local (or a local) (or a local area) is formed on a required portion of the amorphous oxide semiconductor film 4 formed above the gate electrode film 2. Since an energy beam (for example, a laser beam) can be irradiated partially, the low-resistance oxide semiconductor films 5 and 6 can be formed at required positions in the region corresponding to the gate electrode film 2.
  • an energy beam for example, a laser beam
  • FIG. 11 is a schematic diagram showing an example of drain current-gate voltage characteristics of a thin film transistor used in the GOA circuit section.
  • the horizontal axis represents the gate voltage
  • the vertical axis represents the drain current.
  • a graph indicated by a symbol D indicates characteristics when the thin film transistor of the present embodiment is used in the GOA circuit portion
  • a graph indicated by the symbol d indicates characteristics when a self-aligned thin film transistor is used in the GOA circuit portion. Indicates.
  • the resistance of the oxide semiconductor can be reduced in the GOA (Gate Driver On Array) circuit portion in which the oxide semiconductor film is formed inside the gate electrode film.
  • the current driving capability can be increased.
  • the thin film transistor of each of the above embodiments can be used for a display panel. That is, the thin film transistor (TFT substrate) of each embodiment and a color filter substrate having colors of R (red), G (green), and B (blue) are bonded to each other with a necessary gap, and the TFT substrate and the color filter are bonded. By injecting liquid crystal between the substrate and the substrate, a TFT liquid crystal display panel (liquid crystal display) can be manufactured. Thus, a display panel including a thin film transistor that can improve light stability can be realized.
  • the thin film transistor of this embodiment is a thin film transistor having an oxide semiconductor film on a substrate, a gate electrode film formed on the surface of the substrate, and an amorphous oxide formed on the gate electrode film.
  • the gate electrode film and the amorphous oxide semiconductor film are arranged in a region corresponding to the gate electrode film in a projected state in which the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate.
  • the method for manufacturing a thin film transistor of this embodiment is a method for manufacturing a thin film transistor having an oxide semiconductor film on a substrate, in which a gate electrode film is formed on the surface of the substrate, and an amorphous film is formed above the gate electrode film.
  • the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate, and the amorphous oxide semiconductor film is used as the gate electrode film.
  • a first and second low resistance oxide semiconductor films are formed by irradiating an energy beam to a required portion of the amorphous oxide semiconductor film which is formed in a corresponding region, and the first low resistance oxidation semiconductor film is formed.
  • a source electrode film is formed on the physical semiconductor film, and a drain electrode film is formed on the second low-resistance oxide semiconductor film.
  • the amorphous oxide semiconductor film is an amorphous (amorphous) oxide semiconductor film.
  • the low-resistance oxide semiconductor film is an oxide semiconductor film having a lower resistance than an amorphous oxide semiconductor film because oxygen vacancies are generated by energy beam irradiation and free electrons increase.
  • the amorphous oxide semiconductor film (for example, in the channel region) between the first and second low-resistance oxide semiconductor films.
  • the corresponding amorphous oxide semiconductor film is disposed in a region corresponding to the gate electrode film.
  • the first and second low resistance oxide semiconductor films are energized at a required separated position of the amorphous oxide semiconductor film formed on the upper side of the gate electrode film. It is formed by irradiating a beam.
  • the first and second low-resistance oxide semiconductor films are provided with energy beams (in the required positions separated from the amorphous oxide semiconductor film formed above the gate electrode film). For example, it is formed by irradiation with an energy beam such as an excimer laser.
  • the required part is a region corresponding to the source region and the drain region in the amorphous oxide semiconductor film, and the amorphous oxide semiconductor film is changed to a low-resistance oxide semiconductor film by irradiation with an energy beam. Can do.
  • the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film.
  • the region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance is not lowered and remains amorphous.
  • an energy beam for example, laser light
  • the low-resistance oxide semiconductor film can be formed so that the amorphous oxide semiconductor film is disposed in a region corresponding to the gate electrode film.
  • the resistance of the amorphous oxide semiconductor film is reduced by using a laser mask, so that the area of the low resistance oxide semiconductor film can be controlled by the shape of the laser mask.
  • the first low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed on the gate electrode film, and the source electrode film are formed on the surface of the substrate.
  • the area of the region where the source electrode film and the first low-resistance oxide semiconductor film overlap is larger than the area of the region where the source electrode film and the amorphous oxide semiconductor film overlap. It is characterized by that.
  • the first low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed over the gate electrode film, and the source electrode film are projected onto the surface of the substrate.
  • the area of the region where the source electrode film and the first low-resistance oxide semiconductor film overlap is larger than the area of the region where the source electrode film and the amorphous oxide semiconductor film overlap.
  • the low-resistance oxide semiconductor film directly under the source electrode film does not form a channel region and has a parasitic resistance. Therefore, by making the area of the low resistance oxide semiconductor film immediately below the source electrode film larger than the area of the amorphous oxide semiconductor film immediately below the source electrode film, the low resistance oxide semiconductor is formed in the region immediately below the source electrode film. By increasing the ratio of the area occupied by the film, the parasitic resistance can be lowered and the current driving capability can be increased.
  • the second low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed on the upper side of the gate electrode film, and the drain electrode film are formed on the surface of the substrate.
  • the area of the region where the drain electrode film and the second low-resistance oxide semiconductor film overlap is larger than the area of the region where the drain electrode film and the amorphous oxide semiconductor film overlap. It is characterized by that.
  • the second low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed above the gate electrode film, and the drain electrode film are projected onto the surface of the substrate.
  • the area of the region where the drain electrode film and the second low-resistance oxide semiconductor film overlap is larger than the area of the region where the drain electrode film and the amorphous oxide semiconductor film overlap.
  • the low-resistance oxide semiconductor film immediately below the drain electrode film does not form a channel region and has a parasitic resistance. Therefore, by making the area of the low resistance oxide semiconductor film immediately below the drain electrode film larger than the area of the amorphous oxide semiconductor film immediately below the drain electrode film, the low resistance oxide semiconductor is formed in the area immediately below the drain electrode film. By increasing the ratio of the area occupied by the film, the parasitic resistance can be lowered and the current driving capability can be increased.
  • the first and second low-resistance oxide semiconductor films are the gate electrode film and the first and second low-resistance oxide semiconductor films on the surface of the substrate. In the projected state, it is arranged in a region corresponding to the gate electrode film.
  • the first and second low-resistance oxide semiconductor films are in a projected state in which the gate electrode film and the first and second low-resistance oxide semiconductor films are projected onto the surface of the substrate. Are disposed in a region corresponding to the gate electrode film.
  • the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film. Therefore, the region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance cannot be reduced.
  • an energy beam for example, laser light
  • a required portion of the amorphous oxide semiconductor film formed over the gate electrode film Therefore, a low-resistance oxide semiconductor film can be formed at a required position in a region corresponding to the gate electrode film.
  • the GOA Gate Driver On Array
  • the display panel of this embodiment includes the thin film transistor according to the above-described embodiment.
  • the display panel of this embodiment includes a thin film transistor.
  • a display panel including a thin film transistor that can improve light stability can be realized.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

Provided are: a thin film transistor enabling to improve optical stability; a display panel that is provided with the thin film transistor; and a method for manufacturing the thin film transistor. A thin film transistor of the present invention is provided with: a gate electrode film formed on the front surface of a substrate; an amorphous oxide semiconductor film formed on the upper side of the gate electrode film; first and second low-resistance oxide semiconductor films formed by having the amorphous oxide semiconductor film therebetween; a source electrode film formed on the first low-resistance oxide semiconductor film; and a drain electrode film formed on the second low-resistance oxide semiconductor film. The amorphous oxide semiconductor film is disposed in a region corresponding to the gate electrode film in a projection state wherein the gate electrode film and the amorphous oxide semiconductor film are projected on the front surface of the substrate.

Description

薄膜トランジスタ、表示パネル及び薄膜トランジスタの製造方法Thin film transistor, display panel, and method of manufacturing thin film transistor

 本発明は、薄膜トランジスタ、該薄膜トランジスタを備える表示パネル及び前記薄膜トランジスタの製造方法に関する。 The present invention relates to a thin film transistor, a display panel including the thin film transistor, and a method for manufacturing the thin film transistor.

 TFT(Thin Film Transistor:薄膜トランジスタ)方式の液晶ディスプレイ(表示パネル)は、TFT基板とR(赤)、G(緑)、B(青)の色を有するカラーフィルタ基板とを所要の隙間を設けて貼り合わせ、TFT基板とカラーフィルタ基板との間に液晶を注入し、液晶分子による光の透過率を画素毎に制御することにより、映像を表示することができる。 A TFT (thin film transistor) type liquid crystal display (display panel) has a required gap between a TFT substrate and a color filter substrate having colors of R (red), G (green), and B (blue). The image can be displayed by bonding, injecting liquid crystal between the TFT substrate and the color filter substrate, and controlling the light transmittance of the liquid crystal molecules for each pixel.

 TFT基板には、データ線及び走査線が縦横方向に格子状に配線され、データ線と走査線とが交差する箇所それぞれにTFTが配された画素が形成されている。また、複数の画素で構成される表示領域の周囲には、データ線及び走査線を駆動する駆動回路を形成してある。 On the TFT substrate, data lines and scanning lines are arranged in a grid pattern in the vertical and horizontal directions, and pixels in which TFTs are arranged at respective locations where the data lines and the scanning lines intersect are formed. In addition, a driving circuit for driving the data lines and the scanning lines is formed around a display area including a plurality of pixels.

 TFTとしては、シリコン半導体を用いたアモルファスシリコン(非晶質、a-Si)TFT、半導体層をポリシリコン(多結晶、p-Si)とした低温ポリシリコンTFTなどの開発が行われている。一方で、近年では、酸化物半導体を用いたTFTの研究も積極的に行われている。酸化物半導体を用いたTFTでは、アモルファスシリコンTFTよりも電子移動度が高く、またシリコン半導体に比べてリーク電流が少ないという利点を有している。 As the TFT, amorphous silicon (amorphous, a-Si) TFT using a silicon semiconductor, low-temperature polysilicon TFT using a semiconductor layer of polysilicon (polycrystalline, p-Si), and the like are being developed. On the other hand, in recent years, research on TFTs using oxide semiconductors has been actively conducted. A TFT using an oxide semiconductor has advantages of higher electron mobility than an amorphous silicon TFT and less leakage current than a silicon semiconductor.

 従来、酸化物半導体を用いたTFT(酸化物半導体TFTとも称する)では、TFTの膜厚方向にゲート電極膜の領域とソース・ドレイン電極膜の領域とが重ならないように構成し、寄生容量の低減など特性の向上を図った自己整合型(セルフアライメント)のものが注目されている。例えば、ゲート電極膜を最下層に配置したボトムゲート型の酸化物半導体TFTにおいて、基板裏面側から所定の光を照射し、ゲート電極膜と重ならない酸化物半導体層の領域(ソース・ドレイン領域)を低抵抗化して特性を向上させる酸化物半導体TFTが開示されている(特許文献1参照)。 Conventionally, a TFT using an oxide semiconductor (also referred to as an oxide semiconductor TFT) is configured so that the region of the gate electrode film and the region of the source / drain electrode film do not overlap in the thickness direction of the TFT. The self-alignment type (self-alignment) that has improved characteristics such as reduction has been attracting attention. For example, in a bottom gate type oxide semiconductor TFT in which a gate electrode film is disposed in the lowermost layer, a region of the oxide semiconductor layer (source / drain region) that does not overlap with the gate electrode film when irradiated with predetermined light from the back side of the substrate An oxide semiconductor TFT is disclosed in which the resistance is reduced to improve the characteristics (see Patent Document 1).

特開2014-140005号公報JP 2014-140005 A

 しかし、従来の自己整合型の酸化物半導体TFTでは、ゲート電極膜の領域と重ならない領域は、低抵抗の酸化物半導層となるが、ゲート電極膜の領域と重なる領域は、アモルファス(非晶質)のままである。このため、基板裏面側からバックライトの光を入射した場合、バックライトの光は、ゲート電極膜の上側の、チャネル領域に対応する非晶質酸化物半導層にも容易に入射されることになる。このため、光照射時において、例えば、ゲート電圧の閾値電圧が比較的大きくシフトするなどの特性変動を生じ、光安定性に欠けるという問題がある。 However, in the conventional self-aligned oxide semiconductor TFT, the region that does not overlap the gate electrode film region is a low-resistance oxide semiconductor layer, but the region that overlaps the gate electrode film region is amorphous (non- (Crystalline). Therefore, when backlight light is incident from the back side of the substrate, the backlight light is easily incident on the amorphous oxide semiconductor layer corresponding to the channel region above the gate electrode film. become. For this reason, at the time of light irradiation, for example, there is a problem that characteristic fluctuation such as a relatively large shift of the threshold voltage of the gate voltage occurs and the light stability is lacking.

 本発明は斯かる事情に鑑みてなされたものであり、光安定性を向上させることができる薄膜トランジスタ、該薄膜トランジスタを備える表示パネル及び前記薄膜トランジスタの製造方法を提供することを目的とする。 The present invention has been made in view of such circumstances, and an object thereof is to provide a thin film transistor capable of improving light stability, a display panel including the thin film transistor, and a method for manufacturing the thin film transistor.

 本発明の実施の形態に係る薄膜トランジスタは、基板上に酸化物半導体膜を有する薄膜トランジスタにおいて、前記基板の表面に形成されたゲート電極膜と、該ゲート電極膜の上側に形成された非晶質酸化物半導体膜と、該非晶質酸化物半導体膜を間にして形成された第1及び第2の低抵抗酸化物半導体膜と、該第1の低抵抗酸化物半導体膜上に形成されたソース電極膜と、前記第2の低抵抗酸化物半導体膜上に形成されたドレイン電極膜とを備え、前記第1及び第2の低抵抗酸化物半導体膜の間の非晶質酸化物半導体膜は、前記ゲート電極膜及び前記非晶質酸化物半導体膜を前記基板の表面に射影した射影状態で、前記ゲート電極膜に対応する領域内に配置されていることを特徴とする。 A thin film transistor according to an embodiment of the present invention includes a gate electrode film formed on a surface of the substrate and an amorphous oxide formed on the gate electrode film in the thin film transistor having an oxide semiconductor film on the substrate. A material semiconductor film, first and second low-resistance oxide semiconductor films formed with the amorphous oxide semiconductor film in between, and a source electrode formed on the first low-resistance oxide semiconductor film An amorphous oxide semiconductor film between the first and second low resistance oxide semiconductor films, and a drain electrode film formed on the second low resistance oxide semiconductor film. The gate electrode film and the amorphous oxide semiconductor film are arranged in a region corresponding to the gate electrode film in a projected state in which the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate.

 本発明の実施の形態に係る表示パネルは、前述の発明の実施の形態に係る薄膜トランジスタを備えることを特徴とする。 A display panel according to an embodiment of the present invention includes the thin film transistor according to the above-described embodiment.

 本発明の実施の形態に係る薄膜トランジスタの製造方法は、基板上に酸化物半導体膜を有する薄膜トランジスタの製造方法において、前記基板の表面にゲート電極膜を形成し、前記ゲート電極膜の上側に非晶質酸化物半導体膜を形成する場合に、前記ゲート電極膜及び前記非晶質酸化物半導体膜を前記基板の表面に射影した射影状態で、前記非晶質酸化物半導体膜を前記ゲート電極膜に対応する領域内に形成し、該非晶質酸化物半導体膜の離隔した所要箇所にエネルギービームを照射して第1及び第2の低抵抗酸化物半導体膜を形成し、該第1の低抵抗酸化物半導体膜上にソース電極膜を形成し、前記第2の低抵抗酸化物半導体膜上にドレイン電極膜を形成することを特徴とする。 A method for manufacturing a thin film transistor according to an embodiment of the present invention includes a method for manufacturing a thin film transistor having an oxide semiconductor film on a substrate, wherein a gate electrode film is formed on a surface of the substrate, and an amorphous material is formed on the gate electrode film. When forming the oxide semiconductor film, the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate, and the amorphous oxide semiconductor film is used as the gate electrode film. A first and second low resistance oxide semiconductor films are formed by irradiating an energy beam to a required portion of the amorphous oxide semiconductor film which is formed in a corresponding region, and the first low resistance oxidation semiconductor film is formed. A source electrode film is formed on the physical semiconductor film, and a drain electrode film is formed on the second low-resistance oxide semiconductor film.

 本発明によれば、光安定性を向上させることができる。 According to the present invention, light stability can be improved.

第1実施形態の薄膜トランジスタの構造の一例を示す要部平面模式図である。It is a principal part plane schematic diagram which shows an example of the structure of the thin-film transistor of 1st Embodiment. 図1のII-II線から見た要部断面模式図である。FIG. 2 is a schematic cross-sectional view of a main part viewed from the line II-II in FIG. 第1実施形態の薄膜トランジスタの製造方法の一例を示す製造工程図である。It is a manufacturing process figure which shows an example of the manufacturing method of the thin-film transistor of 1st Embodiment. 部分照射型レーザーの構成の一例を示す模式図である。It is a schematic diagram which shows an example of a structure of a partial irradiation type laser. 第1実施形態の薄膜トランジスタの光照射時の様子の一例を示す模式図である。It is a schematic diagram which shows an example of the mode at the time of light irradiation of the thin-film transistor of 1st Embodiment. 第1実施形態の薄膜トランジスタの特性変動の一例を示す模式図である。It is a schematic diagram which shows an example of the characteristic fluctuation | variation of the thin-film transistor of 1st Embodiment. 従来の薄膜トランジスタの特性変動の一例を示す模式図である。It is a schematic diagram which shows an example of the characteristic fluctuation | variation of the conventional thin-film transistor. 第2実施形態の薄膜トランジスタの構造の一例を示す要部平面模式図である。It is a principal part plane schematic diagram which shows an example of the structure of the thin-film transistor of 2nd Embodiment. 第2実施形態の薄膜トランジスタのドレイン電流-ゲート電圧特性の一例を示す模式図である。It is a schematic diagram which shows an example of the drain current-gate voltage characteristic of the thin-film transistor of 2nd Embodiment. 第3実施形態の薄膜トランジスタの構造の一例を示す要部平面模式図である。It is a principal part plane schematic diagram which shows an example of the structure of the thin-film transistor of 3rd Embodiment. GOA回路部に用いられる薄膜トランジスタのドレイン電流-ゲート電圧特性の一例を示す模式図である。It is a schematic diagram showing an example of drain current-gate voltage characteristics of a thin film transistor used in the GOA circuit section.

(第1実施形態)
 以下、本発明をその実施の形態を示す図面に基づいて説明する。図1は第1実施形態の薄膜トランジスタの構造の一例を示す要部平面模式図であり、図2は図1のII-II線から見た要部断面模式図である。図1及び図2に示すように、薄膜トランジスタ(TFT:Thin Film Transistor、TFT基板とも称する)は、ガラス基板1(基板とも称する)の表面にゲート電極膜2を形成してあり、ゲート電極膜2を覆ってゲート絶縁膜3(例えば、SiO2 膜など)を形成してある。
(First embodiment)
Hereinafter, the present invention will be described with reference to the drawings illustrating embodiments thereof. FIG. 1 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of the first embodiment, and FIG. As shown in FIGS. 1 and 2, a thin film transistor (TFT: Thin Film Transistor, also referred to as a TFT substrate) has a gate electrode film 2 formed on the surface of a glass substrate 1 (also referred to as a substrate). A gate insulating film 3 (for example, a SiO 2 film) is formed so as to cover the surface.

 ゲート絶縁膜3の表面であってゲート電極膜2の上側には、非晶質酸化物半導体膜4、及び非晶質酸化物半導体膜4を間にして第1の低抵抗酸化物半導体膜5及び第2の低抵抗酸化物半導体膜6を形成してある。非晶質酸化物半導体膜4は、アモルファス(非晶質)の酸化物半導体膜である。低抵抗酸化物半導体膜5、6は、エネルギービーム照射により酸素欠損が生じ、自由電子が増加することで非晶質酸化物半導体膜4と比較して低い抵抗をもつ酸化物半導体膜であり、例えば、結晶を含む酸化物半導体膜でもよく、あるいは、結晶性を有する酸化物半導体膜であってもよい。結晶状態は、結晶軸の方向が無秩序な状態でも、一定の配向性を有する状態であってもよい。 On the surface of the gate insulating film 3 and above the gate electrode film 2, an amorphous oxide semiconductor film 4 and a first low-resistance oxide semiconductor film 5 with the amorphous oxide semiconductor film 4 interposed therebetween. The second low-resistance oxide semiconductor film 6 is formed. The amorphous oxide semiconductor film 4 is an amorphous (amorphous) oxide semiconductor film. The low resistance oxide semiconductor films 5 and 6 are oxide semiconductor films having a lower resistance than the amorphous oxide semiconductor film 4 due to oxygen deficiency caused by energy beam irradiation and increase of free electrons. For example, an oxide semiconductor film including crystals or an oxide semiconductor film having crystallinity may be used. The crystal state may be a state in which the directions of crystal axes are disordered or a state having a certain orientation.

 酸化物半導体膜(4、5、6)は、例えば、インジウム(In)、ガリウム(Ga)及び亜鉛(Zn)の3つの元素の酸化物であるが、これに限定されるものではなく、インジウム、ガリウム、亜鉛、スズ、アルミニウム、シリコン、ゲルマニウム、チタン、モリブデン、ボロン、マンガン等の元素から少なくとも1つの元素を含む酸化物とすることもできる。 The oxide semiconductor film (4, 5, 6) is, for example, an oxide of three elements of indium (In), gallium (Ga), and zinc (Zn), but is not limited to this. In addition, an oxide containing at least one element from elements such as gallium, zinc, tin, aluminum, silicon, germanium, titanium, molybdenum, boron, and manganese can also be used.

 第1の低抵抗酸化物半導体膜5上にはソース電極膜7を形成してある。また、第2の低抵抗酸化物半導体膜6上にはドレイン電極膜8を形成してある。なお、第1の低抵抗酸化物半導体膜5、第2の低抵抗酸化物半導体膜6は、それぞれ低抵抗酸化物半導体膜5、6とも称する。また、第1の低抵抗酸化物半導体膜5、第2の低抵抗酸化物半導体膜6及び非晶質酸化物半導体膜4の形成後又は形成前に、保護膜としてのエッチストッパー膜を形成してもよい。 A source electrode film 7 is formed on the first low-resistance oxide semiconductor film 5. A drain electrode film 8 is formed on the second low resistance oxide semiconductor film 6. Note that the first low-resistance oxide semiconductor film 5 and the second low-resistance oxide semiconductor film 6 are also referred to as low-resistance oxide semiconductor films 5 and 6, respectively. Further, an etch stopper film as a protective film is formed after or before the formation of the first low-resistance oxide semiconductor film 5, the second low-resistance oxide semiconductor film 6, and the amorphous oxide semiconductor film 4. May be.

 ソース電極膜7及びドレイン電極膜8を覆うようにして、TFT基板全体には、パッシベーション膜9を形成してあり、パッシベーション膜9の表面には有機膜10を形成して表面を平坦化している。パッシベーション膜9及び有機膜10の所要の位置には、スルーホールを形成してあり、当該スルーホールを通して透明導電膜(例えば、ITO)11とドレイン電極膜8とが導通するようにしてある。不図示の画素電極は、透明導電膜11に接続されている。 A passivation film 9 is formed on the entire TFT substrate so as to cover the source electrode film 7 and the drain electrode film 8, and an organic film 10 is formed on the surface of the passivation film 9 to flatten the surface. . Through holes are formed at required positions of the passivation film 9 and the organic film 10 so that the transparent conductive film (for example, ITO) 11 and the drain electrode film 8 are electrically connected through the through holes. A pixel electrode (not shown) is connected to the transparent conductive film 11.

 図1は、ゲート電極膜2、非晶質酸化物半導体膜4、第1の低抵抗酸化物半導体膜5、第2の低抵抗酸化物半導体膜6、ソース電極膜7及びドレイン電極膜8を、基板1の表面に射影した射影状態を模式的に示す。すなわち、図1は、ゲート電極膜2に対応する基板1上の領域、非晶質酸化物半導体膜4に対応する基板1上の領域、低抵抗酸化物半導体膜5、6に対応する基板1上の領域、ソース電極膜7に対応する基板1上の領域及びドレイン電極膜8に対応する基板1上の領域を模式的に示すものである。また、図1において、符号21はゲート電極膜への配線部分を示す。なお、図1に示す各領域の形状は、便宜上模式的に示すものであり、実際の形状は異なる場合もある。 FIG. 1 shows a gate electrode film 2, an amorphous oxide semiconductor film 4, a first low resistance oxide semiconductor film 5, a second low resistance oxide semiconductor film 6, a source electrode film 7 and a drain electrode film 8. The projection state projected on the surface of the substrate 1 is schematically shown. 1 shows a region on the substrate 1 corresponding to the gate electrode film 2, a region on the substrate 1 corresponding to the amorphous oxide semiconductor film 4, and the substrate 1 corresponding to the low-resistance oxide semiconductor films 5 and 6. An upper region, a region on the substrate 1 corresponding to the source electrode film 7 and a region on the substrate 1 corresponding to the drain electrode film 8 are schematically shown. In FIG. 1, reference numeral 21 denotes a wiring portion to the gate electrode film. In addition, the shape of each area | region shown in FIG. 1 is shown typically for convenience, and an actual shape may differ.

 図1に示すように、本実施の形態の薄膜トランジスタは、ゲート電極膜2及び非晶質酸化物半導体膜4を基板1の表面に射影した射影状態において、非晶質酸化物半導体膜4は、ゲート電極膜2に対応する領域内に配置されている。また、第1の低抵抗酸化物半導体膜5と第2の低抵抗酸化物半導体膜6との間の非晶質酸化物半導体膜4もゲート電極膜2に対応する領域内に配置されている。 As shown in FIG. 1, in the thin film transistor of this embodiment, in the projection state in which the gate electrode film 2 and the amorphous oxide semiconductor film 4 are projected onto the surface of the substrate 1, the amorphous oxide semiconductor film 4 is It is arranged in a region corresponding to the gate electrode film 2. The amorphous oxide semiconductor film 4 between the first low-resistance oxide semiconductor film 5 and the second low-resistance oxide semiconductor film 6 is also disposed in a region corresponding to the gate electrode film 2. .

 図3は第1実施形態の薄膜トランジスタの製造方法の一例を示す製造工程図である。以下、本実施の形態の薄膜トランジスタの製造工程について説明する。図3に示すように、スパッタリング法を用いて、基板(ガラス基板)1上にアルミニウム(Al)膜を成膜し、フォトリソグラフィ法及びエッチング法を用いてアルミニウム(Al)膜をパターニングして所要の幅のゲート電極膜2を形成する(S11)。なお、ゲート電極膜2に用いられる材料は、アルミニウムに限定されるものではなく、例えば、銅、チタン、タングステン、金、白金、モリブデン、もしくはニッケル等の元素単体又は合金を用いてよい。 FIG. 3 is a manufacturing process diagram showing an example of a manufacturing method of the thin film transistor of the first embodiment. Hereinafter, a manufacturing process of the thin film transistor of this embodiment will be described. As shown in FIG. 3, an aluminum (Al) film is formed on a substrate (glass substrate) 1 using a sputtering method, and the aluminum (Al) film is patterned using a photolithography method and an etching method. A gate electrode film 2 having a width of is formed (S11). The material used for the gate electrode film 2 is not limited to aluminum, and for example, elemental elements such as copper, titanium, tungsten, gold, platinum, molybdenum, or nickel, or alloys thereof may be used.

 次に、ゲート電極膜2を覆うようにして基板1上に、プラズマCVD法を用いてゲート絶縁膜3を成膜する(S12)。 Next, the gate insulating film 3 is formed on the substrate 1 using the plasma CVD method so as to cover the gate electrode film 2 (S12).

 次に、スパッタリング法を用いて、ゲート絶縁膜3上に酸化物半導体膜を成膜する(S13)。この酸化物半導体膜は、非晶質酸化物半導体膜4であり、例えば、酸化物半導体が低抵抗となる温度以下の環境下で成膜する。なお、前述の酸化物半導体膜等の成膜方法として、スパッタリング法に代えて、パルスレーザー蒸着法、電子ビーム蒸着法、塗布成膜等の他の成膜法を用いてもよい。 Next, an oxide semiconductor film is formed on the gate insulating film 3 by using a sputtering method (S13). This oxide semiconductor film is the amorphous oxide semiconductor film 4 and is formed, for example, in an environment below a temperature at which the oxide semiconductor has a low resistance. Note that as a method for forming the above-described oxide semiconductor film or the like, other film formation methods such as a pulsed laser deposition method, an electron beam deposition method, or a coating deposition method may be used instead of the sputtering method.

 次に、非晶質酸化物半導体膜4の所要箇所に、例えば、エキシマレーザーなどのエネルギービームを照射して部分レーザーアニールを行う(S14)。部分レーザーアニールは、非晶質酸化物半導体膜4の所要箇所(例えば、図1及び図2の符号5、6で示す箇所)を低抵抗酸化物半導体膜5、6に変化させる。所要箇所は、ゲート絶縁膜3上に成膜した非晶質酸化物半導体膜4のうちソース領域及びドレイン領域に相当する領域である。 Next, partial laser annealing is performed by irradiating a required portion of the amorphous oxide semiconductor film 4 with an energy beam such as an excimer laser (S14). In the partial laser annealing, a required portion (for example, a portion indicated by reference numerals 5 and 6 in FIGS. 1 and 2) of the amorphous oxide semiconductor film 4 is changed to the low resistance oxide semiconductor films 5 and 6. The required portion is a region corresponding to the source region and the drain region in the amorphous oxide semiconductor film 4 formed on the gate insulating film 3.

 次に、露光処理、現像処理を行い(S15)、非晶質酸化物半導体膜4及び低抵抗酸化物半導体膜5、6に所要のパターンを形成する。所要のパターンは、ソース電極膜7、ドレイン電極膜8及び半導体層の配置又は構造に応じて適宜定めることができる。 Next, exposure processing and development processing are performed (S15), and a required pattern is formed on the amorphous oxide semiconductor film 4 and the low-resistance oxide semiconductor films 5 and 6. The required pattern can be appropriately determined according to the arrangement or structure of the source electrode film 7, the drain electrode film 8, and the semiconductor layer.

 次に、非晶質酸化物半導体膜4及び低抵抗酸化物半導体膜5、6などの所要の箇所をエッチングし(S16)、エッチング後の低抵抗酸化物半導体膜5、6上にソース電極膜7及びドレイン電極膜8を形成する(S17)。なお、ソース電極膜7及びドレイン電極膜8は、同時に形成されることが多い。 Next, required portions such as the amorphous oxide semiconductor film 4 and the low resistance oxide semiconductor films 5 and 6 are etched (S16), and the source electrode film is formed on the low resistance oxide semiconductor films 5 and 6 after the etching. 7 and the drain electrode film 8 are formed (S17). The source electrode film 7 and the drain electrode film 8 are often formed at the same time.

 図4は部分照射型レーザーの構成の一例を示す模式図である。図4に示すように、非晶質酸化物半導体膜4が表面に形成された基板1は不図示の載置台に載置され、図4中の矢印の方向に所要の速度で平行移動するようにしてある。基板1の上方には、基板1の移動方向と交差する方向に沿って個々のレンズが適長離隔して並んだマルチレンズアレイを配置してある。レーザー光源(不図示)からのレーザー光をマルチレンズアレイへ入射することにより、レーザー光は、レンズ毎に異なる光路を経由して離隔した複数の所要箇所に対して部分照射される。すなわち、部分レーザーアニールを行うことができる。これにより、非晶質酸化物半導体膜4のうち所要の領域だけを選択的に低抵抗酸化物半導体膜5、6に変化させることができる。なお、図4においては、図示していないが、レーザー光源とマルチレンズアレイとの間、あるいは、マルチレンズアレイと基板1との間には、レーザーマスク(遮光部材)を配置してあり、レーザーマスクによりレーザー光のビーム形状を、例えば、矩形状、あるいは所要の大きさに整形することができる。 FIG. 4 is a schematic diagram showing an example of the configuration of a partial irradiation type laser. As shown in FIG. 4, the substrate 1 on which the amorphous oxide semiconductor film 4 is formed is placed on a mounting table (not shown) so as to translate in the direction of the arrow in FIG. 4 at a required speed. It is. Above the substrate 1, a multi-lens array is arranged in which individual lenses are arranged at an appropriate distance along a direction intersecting the moving direction of the substrate 1. By making a laser beam from a laser light source (not shown) enter the multi-lens array, the laser beam is partially irradiated to a plurality of required locations separated via different optical paths for each lens. That is, partial laser annealing can be performed. Thereby, only a required region of the amorphous oxide semiconductor film 4 can be selectively changed to the low resistance oxide semiconductor films 5 and 6. Although not shown in FIG. 4, a laser mask (light-shielding member) is disposed between the laser light source and the multi-lens array or between the multi-lens array and the substrate 1. The beam shape of the laser beam can be shaped into, for example, a rectangular shape or a required size by the mask.

 すなわち、本実施の形態の薄膜トランジスタにあっては、第1の低抵抗酸化物半導体膜5及び第2の低抵抗酸化物半導体膜6は、ゲート電極膜2の上側に形成された非晶質酸化物半導体膜4の離隔した所要箇所にエネルギービーム(例えば、エキシマレーザーなどのエネルギービーム)を照射して形成されている。所要箇所は、非晶質酸化物半導体膜4のうちソース領域及びドレイン領域に相当する領域であり、エネルギービームを照射することにより、非晶質酸化物半導体膜4を低抵抗酸化物半導体膜5、6に変えることができる。 That is, in the thin film transistor of this embodiment, the first low-resistance oxide semiconductor film 5 and the second low-resistance oxide semiconductor film 6 are amorphous oxides formed on the upper side of the gate electrode film 2. It is formed by irradiating an energy beam (for example, an energy beam of an excimer laser or the like) to a required separated portion of the physical semiconductor film 4. The required portion is a region corresponding to the source region and the drain region in the amorphous oxide semiconductor film 4, and the amorphous oxide semiconductor film 4 is reduced to a low-resistance oxide semiconductor film 5 by irradiation with an energy beam. , 6 can be changed.

 従来の自己整合型の薄膜トランジスタの場合、例えば、レーザー光を基板裏面側から全面照射するので、レーザー光はゲート電極膜で遮られる。そして、ゲート電極膜の上側であってゲート電極膜の領域に対応する非晶質酸化物半導体膜の領域は、レーザー光が照射されないので、低抵抗化されず非晶質のままである。 In the case of a conventional self-aligned thin film transistor, for example, the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film. The region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance is not lowered and remains amorphous.

 これに対して、本実施の形態の薄膜トランジスタの場合、ゲート電極膜2の上側に形成された非晶質酸化物半導体膜4の所要箇所に局所的(又は部分的)にエネルギービーム(例えば、レーザー光)を照射することができるので、非晶質酸化物半導体膜4がゲート電極膜2に対応する領域内に配置されるように、低抵抗酸化物半導体膜5、6を形成することができる。 In contrast, in the case of the thin film transistor of the present embodiment, an energy beam (for example, a laser) is locally (or partially) applied to a required portion of the amorphous oxide semiconductor film 4 formed on the upper side of the gate electrode film 2. The low-resistance oxide semiconductor films 5 and 6 can be formed so that the amorphous oxide semiconductor film 4 is disposed in a region corresponding to the gate electrode film 2. .

 また、従来の自己整合型の薄膜トランジスタの場合、レーザー光を基板裏面側から全面照射するので、ゲート電極膜、ゲート電極膜のテーパ部、開口部など、レーザー光をすべての箇所に照射するので、レーザー光の強度分布の不均一性、あるいは、照射ごとの強度のばらつきにより、均一な結晶性を得ることが困難である。 In the case of a conventional self-aligned thin film transistor, the entire surface is irradiated with laser light from the back side of the substrate, so the laser light is irradiated to all locations, such as the gate electrode film, the tapered portion of the gate electrode film, and the opening. It is difficult to obtain uniform crystallinity due to non-uniformity of the intensity distribution of laser light or variations in intensity for each irradiation.

 これに対して、本実施の形態の薄膜トランジスタの場合、ゲート電極膜2の上側の非晶質酸化物半導体膜4の所要箇所だけに絞って低抵抗化できるので、低抵抗化のばらつきが小さく、信頼性の高い表示パネルを製造することができる。 On the other hand, in the case of the thin film transistor of this embodiment, the resistance can be reduced by focusing only on a required portion of the amorphous oxide semiconductor film 4 on the upper side of the gate electrode film 2, so that the variation in resistance reduction is small. A display panel with high reliability can be manufactured.

 図5は第1実施形態の薄膜トランジスタの光照射時の様子の一例を示す模式図である。図5は、バックライトの光が、基板1の裏面側から入射する様子を示す。なお、簡便のため、図2で示した構成の一部を省略している。前述のとおり、本実施の形態の薄膜トランジスタは、ゲート電極膜2及び非晶質酸化物半導体膜4を基板1の表面に射影した射影状態において、チャネル領域に対応する、第1の低抵抗酸化物半導体膜5及び第2の低抵抗酸化物半導体膜6の間の非晶質酸化物半導体膜4は、ゲート電極膜2に対応する領域内に配置されている。 FIG. 5 is a schematic view showing an example of the state of the thin film transistor according to the first embodiment during light irradiation. FIG. 5 shows how the light from the backlight is incident from the back side of the substrate 1. For convenience, a part of the configuration shown in FIG. 2 is omitted. As described above, the thin film transistor of this embodiment includes the first low-resistance oxide corresponding to the channel region in a projected state in which the gate electrode film 2 and the amorphous oxide semiconductor film 4 are projected onto the surface of the substrate 1. The amorphous oxide semiconductor film 4 between the semiconductor film 5 and the second low resistance oxide semiconductor film 6 is disposed in a region corresponding to the gate electrode film 2.

 図5に示すように、基板1の裏面側からバックライトの光(図5中矢印で示す)を入射した場合に、バックライトの光が、基板1の面に対して斜め方向、かつゲート電極膜2の上側に向かって入射しても、チャネル領域に対応する非晶質酸化物半導体膜4は、ゲート電極膜2に対応する領域内に配置されているので、非晶質酸化物半導体膜4に入射する光を軽減することができる。 As shown in FIG. 5, when backlight light (indicated by an arrow in FIG. 5) is incident from the back side of the substrate 1, the backlight light is oblique with respect to the surface of the substrate 1 and the gate electrode Even if it is incident on the upper side of the film 2, the amorphous oxide semiconductor film 4 corresponding to the channel region is disposed in the region corresponding to the gate electrode film 2, so that the amorphous oxide semiconductor film The light incident on 4 can be reduced.

 図6は第1実施形態の薄膜トランジスタの特性変動の一例を示す模式図であり、図7は従来の薄膜トランジスタの特性変動の一例を示す模式図である。図6及び図7において、横軸はゲート電圧を示し、縦軸はドレイン電流を示す。また、図中の矢印は、光の照射環境下で正又は負の電圧を印加し始めた状態(光バイアスストレス状態とも称する)を開始してからの時間経過を示す。 FIG. 6 is a schematic diagram illustrating an example of characteristic variation of the thin film transistor of the first embodiment, and FIG. 7 is a schematic diagram illustrating an example of characteristic variation of the conventional thin film transistor. 6 and 7, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. In addition, the arrows in the figure indicate the passage of time from the start of applying a positive or negative voltage under a light irradiation environment (also referred to as an optical bias stress state).

 図6に示すように、本実施の形態の薄膜トランジスタの初期のドレイン電流-ゲート電圧特性は、符号Aで示すグラフのようになり、光バイアスストレス状態での時間経過とともに、符号B、符号Cの如く変化する。すなわち、図5で示したように、チャネル領域に対応する非晶質酸化物半導体膜4に入射する光を軽減することができるので、図6に示すように、光バイアスストレス状態において、例えば、ゲート電圧の閾値電圧のシフトを低減することができ、光安定性を向上させることができる。 As shown in FIG. 6, the initial drain current-gate voltage characteristics of the thin film transistor according to the present embodiment are as shown by the graph indicated by symbol A. As time elapses in the optical bias stress state, symbols B and C indicate the time. It changes as follows. That is, as shown in FIG. 5, light incident on the amorphous oxide semiconductor film 4 corresponding to the channel region can be reduced. Therefore, as shown in FIG. The shift of the threshold voltage of the gate voltage can be reduced, and light stability can be improved.

 一方、従来の自己整合型の薄膜トランジスタの場合、ゲート電極膜の直上の酸化物半導体膜は、低抵抗化されず非晶質酸化物半導膜である。このため、基板裏面側からバックライトの光を入射した場合、バックライトの光は、ゲート電極膜の上側の非晶質酸化物半導膜にも容易に入射されることになる。図7に示すように、従来の薄膜トランジスタの初期のドレイン電流-ゲート電圧特性は、符号aで示すグラフのようになり、光バイアスストレス状態での時間経過とともに、符号b、符号cの如く変化する。すなわち、光バイアスストレス状態において、例えば、ゲート電圧の閾値電圧が比較的大きくシフトするなどの特性変動を生じ、光安定性に欠ける。なお、閾値電圧のシフトは、チャネル-ゲート絶縁膜界面に発生する酸素欠損が起因していると考えられる。 On the other hand, in the case of a conventional self-aligned thin film transistor, the oxide semiconductor film immediately above the gate electrode film is an amorphous oxide semiconductor film without being reduced in resistance. Therefore, when backlight light is incident from the back side of the substrate, the backlight light is easily incident on the amorphous oxide semiconductor film on the upper side of the gate electrode film. As shown in FIG. 7, the initial drain current-gate voltage characteristic of the conventional thin film transistor is as shown by a graph indicated by symbol a, and changes with time elapse in an optical bias stress state as indicated by symbols b and c. . That is, in the optical bias stress state, for example, characteristic variation such as a relatively large shift of the threshold voltage of the gate voltage occurs, resulting in lack of light stability. Note that the threshold voltage shift is considered to be caused by oxygen vacancies generated at the channel-gate insulating film interface.

(第2実施形態)
 図8は第2実施形態の薄膜トランジスタの構造の一例を示す要部平面模式図である。第2実施形態の薄膜トランジスタは、第1の低抵抗酸化物半導体膜51、ゲート電極膜2の上側に形成された非晶質酸化物半導体膜4及びソース電極膜7を基板1の表面に射影した射影状態において、ソース電極膜7と第1の低抵抗酸化物半導体膜51とが重なる領域(図8中、模様を付した領域)の面積は、ソース電極膜7と非晶質酸化物半導体膜4とが重なる領域(図8中、符号41で示す領域)の面積より大きい。
(Second Embodiment)
FIG. 8 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of the second embodiment. In the thin film transistor of the second embodiment, the first low-resistance oxide semiconductor film 51, the amorphous oxide semiconductor film 4 formed on the upper side of the gate electrode film 2, and the source electrode film 7 are projected onto the surface of the substrate 1. In the projected state, the area of the region where the source electrode film 7 and the first low-resistance oxide semiconductor film 51 overlap (the region marked with a pattern in FIG. 8) is the same as that of the source electrode film 7 and the amorphous oxide semiconductor film. 4 is larger than the area of a region where 4 overlaps (region indicated by reference numeral 41 in FIG. 8).

 ソース電極膜7直下(ソース電極膜7と重なる領域)の低抵抗酸化物半導体膜51の大部分は、チャネル領域を形成せず、寄生抵抗となる。そこで、ソース電極膜7直下の低抵抗酸化物半導体膜51の面積を、ソース電極膜7直下の非晶質酸化物半導体膜41の面積よりも大きくすることにより、ソース電極膜7直下の領域において低抵抗酸化物半導体膜51が占める領域の割合を大きくして、寄生抵抗を下げて、電流駆動能力を増加させることができる。なお、図8において、ソース電極膜7直下の非晶質酸化物半導体膜41の領域を、すべて低抵抗酸化物半導体膜51にしてもよい。この場合、ソース電極膜7直下の領域において低抵抗酸化物半導体膜51が占める領域の割合は100%となる。 Most of the low-resistance oxide semiconductor film 51 immediately below the source electrode film 7 (a region overlapping with the source electrode film 7) does not form a channel region but has a parasitic resistance. Therefore, by making the area of the low-resistance oxide semiconductor film 51 immediately below the source electrode film 7 larger than the area of the amorphous oxide semiconductor film 41 immediately below the source electrode film 7, in the region directly below the source electrode film 7. The ratio of the region occupied by the low-resistance oxide semiconductor film 51 can be increased, the parasitic resistance can be lowered, and the current driving capability can be increased. In FIG. 8, the entire region of the amorphous oxide semiconductor film 41 immediately below the source electrode film 7 may be the low resistance oxide semiconductor film 51. In this case, the ratio of the region occupied by the low-resistance oxide semiconductor film 51 in the region immediately below the source electrode film 7 is 100%.

 また、第2の低抵抗酸化物半導体膜61、ゲート電極膜2の上側に形成された非晶質酸化物半導体膜4及びドレイン電極膜8を基板1の表面に射影した射影状態において、ドレイン電極膜8と第2の低抵抗酸化物半導体膜61とが重なる領域(図8中、模様を付した領域)の面積は、ドレイン電極膜8と非晶質酸化物半導体膜4とが重なる領域(図8中、符号42で示す領域)の面積より大きい。 Further, in the projection state in which the second low-resistance oxide semiconductor film 61, the amorphous oxide semiconductor film 4 formed on the gate electrode film 2 and the drain electrode film 8 are projected onto the surface of the substrate 1, the drain electrode The area of the region where the film 8 and the second low-resistance oxide semiconductor film 61 overlap (the region with a pattern in FIG. 8) overlaps the region where the drain electrode film 8 and the amorphous oxide semiconductor film 4 overlap ( In FIG. 8, the area is larger than the area indicated by reference numeral 42.

 ドレイン電極膜8直下(ドレイン電極膜8と重なる領域)の低抵抗酸化物半導体膜61の大部分は、チャネル領域を形成せず、寄生抵抗となる。そこで、ドレイン電極膜8直下の低抵抗酸化物半導体膜61の面積を、ドレイン電極膜8直下の非晶質酸化物半導体膜42の面積よりも大きくすることにより、ドレイン電極膜8直下の領域において低抵抗酸化物半導体膜61が占める領域の割合を大きくして、寄生抵抗を下げて、電流駆動能力を増加させることができる。なお、図8において、ドレイン電極膜8直下の非晶質酸化物半導体膜42の領域を、すべて低抵抗酸化物半導体膜61にしてもよい。この場合、ドレイン電極膜8直下の領域において低抵抗酸化物半導体膜61が占める領域の割合は100%となる。 Most of the low-resistance oxide semiconductor film 61 immediately below the drain electrode film 8 (region overlapping with the drain electrode film 8) does not form a channel region and has a parasitic resistance. Therefore, by making the area of the low-resistance oxide semiconductor film 61 immediately below the drain electrode film 8 larger than the area of the amorphous oxide semiconductor film 42 immediately below the drain electrode film 8, in the area directly below the drain electrode film 8. By increasing the ratio of the region occupied by the low-resistance oxide semiconductor film 61, the parasitic resistance can be lowered and the current driving capability can be increased. In FIG. 8, the entire region of the amorphous oxide semiconductor film 42 immediately below the drain electrode film 8 may be the low resistance oxide semiconductor film 61. In this case, the ratio of the region occupied by the low-resistance oxide semiconductor film 61 in the region immediately below the drain electrode film 8 is 100%.

 図9は第2実施形態の薄膜トランジスタのドレイン電流-ゲート電圧特性の一例を示す模式図である。図9において、横軸はゲート電圧を示し、縦軸はドレイン電流を示す。図9に示すように、ソース電極膜7側又はドレイン電極膜8側の少なくとも一方側の低抵抗酸化物半導体膜51、61の領域を広くすることにより、抵抗を下げることができ、ドレイン電流を増加させることができる。また、低抵抗酸化物半導体膜51、61の領域の広さ(例えば、面積)を制御することにより寄生抵抗の値を制御することも可能となる。なお、第1実施形態と同様の箇所は説明を省略する。 FIG. 9 is a schematic diagram showing an example of drain current-gate voltage characteristics of the thin film transistor of the second embodiment. In FIG. 9, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. As shown in FIG. 9, by increasing the region of the low-resistance oxide semiconductor films 51 and 61 on at least one side of the source electrode film 7 side or the drain electrode film 8 side, the resistance can be lowered and the drain current can be reduced. Can be increased. In addition, the value of the parasitic resistance can be controlled by controlling the width (for example, area) of the regions of the low-resistance oxide semiconductor films 51 and 61. The description of the same parts as those in the first embodiment is omitted.

(第3実施形態)
 図10は第3実施形態の薄膜トランジスタの構造の一例を示す要部平面模式図である。図10に示す薄膜トランジスタは、例えば、GOA(Gate Driver On Array)回路部に用いられる。図10に示すように、平面視が矩形状のゲート電極膜2が基板上に設けられ、ゲート電極膜2に対応する領域内に長尺状の非晶質酸化物半導体膜4及び長尺状の低抵抗酸化物半導体膜5、6が順番に配置してある。また、第1の低抵抗酸化物半導体膜5上にはソース電極膜7を形成し、第2の低抵抗酸化物半導体膜6上にはドレイン電極膜8を形成してある。
(Third embodiment)
FIG. 10 is a schematic plan view of an essential part showing an example of the structure of the thin film transistor of the third embodiment. The thin film transistor shown in FIG. 10 is used, for example, in a GOA (Gate Driver On Array) circuit section. As shown in FIG. 10, the gate electrode film 2 having a rectangular shape in plan view is provided on the substrate, and the elongated amorphous oxide semiconductor film 4 and the elongated shape are formed in a region corresponding to the gate electrode film 2. The low resistance oxide semiconductor films 5 and 6 are arranged in order. A source electrode film 7 is formed on the first low resistance oxide semiconductor film 5, and a drain electrode film 8 is formed on the second low resistance oxide semiconductor film 6.

 すなわち、第3実施形態の薄膜トランジスタは、ゲート電極膜2、第1の低抵抗酸化物半導体膜5及び第2の低抵抗酸化物半導体膜6を基板1の表面に射影した射影状態で、第1の低抵抗酸化物半導体膜5及び第2の低抵抗酸化物半導体膜6は、ゲート電極膜2に対応する領域内に配置されている。 That is, the thin film transistor according to the third embodiment is in a projected state in which the gate electrode film 2, the first low-resistance oxide semiconductor film 5, and the second low-resistance oxide semiconductor film 6 are projected onto the surface of the substrate 1. The low resistance oxide semiconductor film 5 and the second low resistance oxide semiconductor film 6 are disposed in a region corresponding to the gate electrode film 2.

 従来の自己整合型の薄膜トランジスタの場合、例えば、レーザー光を基板裏面側から全面照射するので、レーザー光はゲート電極膜で遮られる。このため、ゲート電極膜の上側であってゲート電極膜の領域に対応する非晶質酸化物半導体膜の領域は、レーザー光が照射されないので、低抵抗化することができない。 In the case of a conventional self-aligned thin film transistor, for example, the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film. Therefore, the region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance cannot be reduced.

 一方、第3実施形態の薄膜トランジスタの場合、第1実施形態及び第2実施形態と同様に、ゲート電極膜2の上側に形成された非晶質酸化物半導体膜4の所要箇所に局所的(又は部分的)にエネルギービーム(例えば、レーザー光)を照射することができるので、ゲート電極膜2に対応する領域内の所要の箇所に低抵抗酸化物半導体膜5、6を形成することができる。 On the other hand, in the case of the thin film transistor of the third embodiment, as in the first embodiment and the second embodiment, a local (or a local) (or a local area) is formed on a required portion of the amorphous oxide semiconductor film 4 formed above the gate electrode film 2. Since an energy beam (for example, a laser beam) can be irradiated partially, the low-resistance oxide semiconductor films 5 and 6 can be formed at required positions in the region corresponding to the gate electrode film 2.

 図11はGOA回路部に用いられる薄膜トランジスタのドレイン電流-ゲート電圧特性の一例を示す模式図である。図11において、横軸はゲート電圧を示し、縦軸はドレイン電流を示す。また、符号Dで示すグラフは、GOA回路部に本実施の形態の薄膜トランジスタを用いた場合の特性を示し、符号dで示すグラフは、GOA回路部に自己整合型の薄膜トランジスタを用いた場合の特性を示す。図11に示すように、本実施の形態では、ゲート電極膜の内側に酸化物半導体膜を形成するGOA(Gate Driver On Array)回路部において、酸化物半導体を低抵抗化することができるので、非晶質の酸化物半導体膜を用いた従来の自己整合型の薄膜トランジスタを用いたGOA回路部に比べて、電流駆動能力を増加させることができる。 FIG. 11 is a schematic diagram showing an example of drain current-gate voltage characteristics of a thin film transistor used in the GOA circuit section. In FIG. 11, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. A graph indicated by a symbol D indicates characteristics when the thin film transistor of the present embodiment is used in the GOA circuit portion, and a graph indicated by the symbol d indicates characteristics when a self-aligned thin film transistor is used in the GOA circuit portion. Indicates. As shown in FIG. 11, in this embodiment, the resistance of the oxide semiconductor can be reduced in the GOA (Gate Driver On Array) circuit portion in which the oxide semiconductor film is formed inside the gate electrode film. Compared with a GOA circuit portion using a conventional self-aligned thin film transistor using an amorphous oxide semiconductor film, the current driving capability can be increased.

 上述の各実施形態の薄膜トランジスタは、表示パネルに用いることができる。すなわち、各実施形態の薄膜トランジスタ(TFT基板)と、R(赤)、G(緑)、B(青)の色を有するカラーフィルタ基板とを所要の隙間を設けて貼り合わせ、TFT基板とカラーフィルタ基板との間に液晶を注入することにより、TFT方式の液晶表示パネル(液晶ディスプレイ)を製造することができる。これにより、光安定性を向上させることができる薄膜トランジスタを備えた表示パネルを実現することができる。 The thin film transistor of each of the above embodiments can be used for a display panel. That is, the thin film transistor (TFT substrate) of each embodiment and a color filter substrate having colors of R (red), G (green), and B (blue) are bonded to each other with a necessary gap, and the TFT substrate and the color filter are bonded. By injecting liquid crystal between the substrate and the substrate, a TFT liquid crystal display panel (liquid crystal display) can be manufactured. Thus, a display panel including a thin film transistor that can improve light stability can be realized.

 (1)本実施の形態の薄膜トランジスタは、基板上に酸化物半導体膜を有する薄膜トランジスタにおいて、前記基板の表面に形成されたゲート電極膜と、該ゲート電極膜の上側に形成された非晶質酸化物半導体膜と、該非晶質酸化物半導体膜を間にして形成された第1及び第2の低抵抗酸化物半導体膜と、該第1の低抵抗酸化物半導体膜上に形成されたソース電極膜と、前記第2の低抵抗酸化物半導体膜上に形成されたドレイン電極膜とを備え、前記第1及び第2の低抵抗酸化物半導体膜の間の非晶質酸化物半導体膜は、前記ゲート電極膜及び前記非晶質酸化物半導体膜を前記基板の表面に射影した射影状態で、前記ゲート電極膜に対応する領域内に配置されていることを特徴とする。 (1) The thin film transistor of this embodiment is a thin film transistor having an oxide semiconductor film on a substrate, a gate electrode film formed on the surface of the substrate, and an amorphous oxide formed on the gate electrode film. A material semiconductor film, first and second low-resistance oxide semiconductor films formed with the amorphous oxide semiconductor film in between, and a source electrode formed on the first low-resistance oxide semiconductor film An amorphous oxide semiconductor film between the first and second low resistance oxide semiconductor films, and a drain electrode film formed on the second low resistance oxide semiconductor film. The gate electrode film and the amorphous oxide semiconductor film are arranged in a region corresponding to the gate electrode film in a projected state in which the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate.

 (7)本実施の形態の薄膜トランジスタの製造方法は、基板上に酸化物半導体膜を有する薄膜トランジスタの製造方法において、前記基板の表面にゲート電極膜を形成し、前記ゲート電極膜の上側に非晶質酸化物半導体膜を形成する場合に、前記ゲート電極膜及び前記非晶質酸化物半導体膜を前記基板の表面に射影した射影状態で、前記非晶質酸化物半導体膜を前記ゲート電極膜に対応する領域内に形成し、該非晶質酸化物半導体膜の離隔した所要箇所にエネルギービームを照射して第1及び第2の低抵抗酸化物半導体膜を形成し、該第1の低抵抗酸化物半導体膜上にソース電極膜を形成し、前記第2の低抵抗酸化物半導体膜上にドレイン電極膜を形成することを特徴とする。 (7) The method for manufacturing a thin film transistor of this embodiment is a method for manufacturing a thin film transistor having an oxide semiconductor film on a substrate, in which a gate electrode film is formed on the surface of the substrate, and an amorphous film is formed above the gate electrode film. When forming the oxide semiconductor film, the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate, and the amorphous oxide semiconductor film is used as the gate electrode film. A first and second low resistance oxide semiconductor films are formed by irradiating an energy beam to a required portion of the amorphous oxide semiconductor film which is formed in a corresponding region, and the first low resistance oxidation semiconductor film is formed. A source electrode film is formed on the physical semiconductor film, and a drain electrode film is formed on the second low-resistance oxide semiconductor film.

 本実施の形態の薄膜トランジスタ及び薄膜トランジスタの製造方法にあっては、基板の表面に形成されたゲート電極膜と、ゲート電極膜の上側に形成された非晶質酸化物半導体膜と、非晶質酸化物半導体膜を間にして形成された第1及び第2の低抵抗酸化物半導体膜と、第1の低抵抗酸化物半導体膜上に形成されたソース電極膜及び第2の低抵抗酸化物半導体膜上に形成されたドレイン電極膜とを備える。非晶質酸化物半導体膜は、アモルファス(非晶質)の酸化物半導体膜である。低抵抗酸化物半導体膜は、エネルギービーム照射により酸素欠損が生じ、自由電子が増加することで非晶質酸化物半導体膜と比較して低い抵抗をもつ酸化物半導体膜である。 In the thin film transistor and the thin film transistor manufacturing method of the present embodiment, the gate electrode film formed on the surface of the substrate, the amorphous oxide semiconductor film formed on the gate electrode film, the amorphous oxide First and second low-resistance oxide semiconductor films formed with a physical semiconductor film interposed therebetween, and a source electrode film and a second low-resistance oxide semiconductor formed on the first low-resistance oxide semiconductor film A drain electrode film formed on the film. The amorphous oxide semiconductor film is an amorphous (amorphous) oxide semiconductor film. The low-resistance oxide semiconductor film is an oxide semiconductor film having a lower resistance than an amorphous oxide semiconductor film because oxygen vacancies are generated by energy beam irradiation and free electrons increase.

 ゲート電極膜及び非晶質酸化物半導体膜を基板の表面に射影した射影状態において、第1及び第2の低抵抗酸化物半導体膜の間の非晶質酸化物半導体膜(例えば、チャネル領域に対応する非晶質酸化物半導体膜)は、ゲート電極膜に対応する領域内に配置されている。基板裏面側からバックライトの光を入射した場合に、バックライトの光が、基板の面に対して斜め方向、かつゲート電極膜の上側に向かって入射しても、非晶質酸化物半導体膜は、ゲート電極膜に対応する領域内に配置されているので、非晶質酸化物半導体膜に入射する光を軽減することができる。これにより、光照射時において、例えば、ゲート電圧の閾値電圧のシフトを低減することができ、光安定性を向上させることができる。 In the projected state in which the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate, the amorphous oxide semiconductor film (for example, in the channel region) between the first and second low-resistance oxide semiconductor films. The corresponding amorphous oxide semiconductor film) is disposed in a region corresponding to the gate electrode film. When backlight light is incident from the back side of the substrate, even if the backlight light is incident obliquely with respect to the surface of the substrate and toward the upper side of the gate electrode film, the amorphous oxide semiconductor film Is disposed in a region corresponding to the gate electrode film, so that light incident on the amorphous oxide semiconductor film can be reduced. Thereby, at the time of light irradiation, for example, the shift of the threshold voltage of the gate voltage can be reduced, and the light stability can be improved.

 (2)本実施の形態の薄膜トランジスタは、前記第1及び第2の低抵抗酸化物半導体膜は、前記ゲート電極膜の上側に形成された非晶質酸化物半導体膜の離隔した所要箇所にエネルギービームを照射して形成されていることを特徴とする。 (2) In the thin film transistor of this embodiment, the first and second low resistance oxide semiconductor films are energized at a required separated position of the amorphous oxide semiconductor film formed on the upper side of the gate electrode film. It is formed by irradiating a beam.

 本実施の形態の薄膜トランジスタにあっては、第1及び第2の低抵抗酸化物半導体膜は、ゲート電極膜の上側に形成された非晶質酸化物半導体膜の離隔した所要箇所にエネルギービーム(例えば、エキシマレーザーなどのエネルギービーム)を照射して形成されている。所要箇所は、非晶質酸化物半導体膜のうちソース領域及びドレイン領域に相当する領域であり、エネルギービームを照射することにより、非晶質酸化物半導体膜を低抵抗酸化物半導体膜に変えることができる。 In the thin film transistor of this embodiment, the first and second low-resistance oxide semiconductor films are provided with energy beams (in the required positions separated from the amorphous oxide semiconductor film formed above the gate electrode film). For example, it is formed by irradiation with an energy beam such as an excimer laser. The required part is a region corresponding to the source region and the drain region in the amorphous oxide semiconductor film, and the amorphous oxide semiconductor film is changed to a low-resistance oxide semiconductor film by irradiation with an energy beam. Can do.

 従来の自己整合型の薄膜トランジスタの場合、例えば、レーザー光を基板裏面側から全面照射するので、レーザー光はゲート電極膜で遮られる。そして、ゲート電極膜の上側であってゲート電極膜の領域に対応する非晶質酸化物半導体膜の領域は、レーザー光が照射されないので、低抵抗化されず非晶質のままである。 In the case of a conventional self-aligned thin film transistor, for example, the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film. The region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance is not lowered and remains amorphous.

 一方、本実施の形態の薄膜トランジスタの場合、ゲート電極膜の上側に形成された非晶質酸化物半導体膜の所要箇所に局所的(又は部分的)にエネルギービーム(例えば、レーザー光)を照射することができるので、非晶質酸化物半導体膜がゲート電極膜に対応する領域内に配置されるように、低抵抗酸化物半導体膜を形成することができる。また、部分照射型レーザーを用いる場合、レーザーマスクを用いて非晶質酸化物半導体膜を低抵抗化させるため、レーザーマスクの形状によって、低抵抗酸化物半導体膜の面積を制御することができる。 On the other hand, in the case of the thin film transistor of this embodiment, an energy beam (for example, laser light) is irradiated locally (or partially) to a required portion of the amorphous oxide semiconductor film formed over the gate electrode film. Therefore, the low-resistance oxide semiconductor film can be formed so that the amorphous oxide semiconductor film is disposed in a region corresponding to the gate electrode film. In the case of using a partial irradiation laser, the resistance of the amorphous oxide semiconductor film is reduced by using a laser mask, so that the area of the low resistance oxide semiconductor film can be controlled by the shape of the laser mask.

 (3)本実施の形態の薄膜トランジスタは、前記第1の低抵抗酸化物半導体膜、前記ゲート電極膜の上側に形成された非晶質酸化物半導体膜及び前記ソース電極膜を前記基板の表面に射影した射影状態で、前記ソース電極膜と前記第1の低抵抗酸化物半導体膜とが重なる領域の面積は、前記ソース電極膜と前記非晶質酸化物半導体膜とが重なる領域の面積より大きいことを特徴とする。 (3) In the thin film transistor of this embodiment, the first low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed on the gate electrode film, and the source electrode film are formed on the surface of the substrate. In the projected state, the area of the region where the source electrode film and the first low-resistance oxide semiconductor film overlap is larger than the area of the region where the source electrode film and the amorphous oxide semiconductor film overlap. It is characterized by that.

 本実施の形態の薄膜トランジスタにあっては、第1の低抵抗酸化物半導体膜、ゲート電極膜の上側に形成された非晶質酸化物半導体膜及びソース電極膜を基板の表面に射影した射影状態において、ソース電極膜と第1の低抵抗酸化物半導体膜とが重なる領域の面積は、ソース電極膜と非晶質酸化物半導体膜とが重なる領域の面積より大きい。 In the thin film transistor of this embodiment, the first low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed over the gate electrode film, and the source electrode film are projected onto the surface of the substrate. The area of the region where the source electrode film and the first low-resistance oxide semiconductor film overlap is larger than the area of the region where the source electrode film and the amorphous oxide semiconductor film overlap.

 ソース電極膜直下(ソース電極膜と重なる領域)の低抵抗酸化物半導体膜の大部分は、チャネル領域を形成せず、寄生抵抗となる。そこで、ソース電極膜直下の低抵抗酸化物半導体膜の面積を、ソース電極膜直下の非晶質酸化物半導体膜の面積よりも大きくすることにより、ソース電極膜直下の領域において低抵抗酸化物半導体膜が占める領域の割合を大きくして、寄生抵抗を下げて、電流駆動能力を増加させることができる。 Most of the low-resistance oxide semiconductor film directly under the source electrode film (a region overlapping with the source electrode film) does not form a channel region and has a parasitic resistance. Therefore, by making the area of the low resistance oxide semiconductor film immediately below the source electrode film larger than the area of the amorphous oxide semiconductor film immediately below the source electrode film, the low resistance oxide semiconductor is formed in the region immediately below the source electrode film. By increasing the ratio of the area occupied by the film, the parasitic resistance can be lowered and the current driving capability can be increased.

 (4)本実施の形態の薄膜トランジスタは、前記第2の低抵抗酸化物半導体膜、前記ゲート電極膜の上側に形成された非晶質酸化物半導体膜及び前記ドレイン電極膜を前記基板の表面に射影した射影状態で、前記ドレイン電極膜と前記第2の低抵抗酸化物半導体膜とが重なる領域の面積は、前記ドレイン電極膜と前記非晶質酸化物半導体膜とが重なる領域の面積より大きいことを特徴とする。 (4) In the thin film transistor of this embodiment, the second low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed on the upper side of the gate electrode film, and the drain electrode film are formed on the surface of the substrate. In the projected state, the area of the region where the drain electrode film and the second low-resistance oxide semiconductor film overlap is larger than the area of the region where the drain electrode film and the amorphous oxide semiconductor film overlap. It is characterized by that.

 本実施の形態の薄膜トランジスタにあっては、第2の低抵抗酸化物半導体膜、ゲート電極膜の上側に形成された非晶質酸化物半導体膜及びドレイン電極膜を基板の表面に射影した射影状態において、ドレイン電極膜と第2の低抵抗酸化物半導体膜とが重なる領域の面積は、ドレイン電極膜と非晶質酸化物半導体膜とが重なる領域の面積より大きい。 In the thin film transistor of this embodiment, the second low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed above the gate electrode film, and the drain electrode film are projected onto the surface of the substrate. The area of the region where the drain electrode film and the second low-resistance oxide semiconductor film overlap is larger than the area of the region where the drain electrode film and the amorphous oxide semiconductor film overlap.

 ドレイン電極膜直下(ドレイン電極膜と重なる領域)の低抵抗酸化物半導体膜の大部分は、チャネル領域を形成せず、寄生抵抗となる。そこで、ドレイン電極膜直下の低抵抗酸化物半導体膜の面積を、ドレイン電極膜直下の非晶質酸化物半導体膜の面積よりも大きくすることにより、ドレイン電極膜直下の領域において低抵抗酸化物半導体膜が占める領域の割合を大きくして、寄生抵抗を下げて、電流駆動能力を増加させることができる。 Most of the low-resistance oxide semiconductor film immediately below the drain electrode film (a region overlapping with the drain electrode film) does not form a channel region and has a parasitic resistance. Therefore, by making the area of the low resistance oxide semiconductor film immediately below the drain electrode film larger than the area of the amorphous oxide semiconductor film immediately below the drain electrode film, the low resistance oxide semiconductor is formed in the area immediately below the drain electrode film. By increasing the ratio of the area occupied by the film, the parasitic resistance can be lowered and the current driving capability can be increased.

 (5)本実施の形態の薄膜トランジスタは、前記第1及び第2の低抵抗酸化物半導体膜は、前記ゲート電極膜及び前記第1及び第2の低抵抗酸化物半導体膜を前記基板の表面に射影した射影状態で、前記ゲート電極膜に対応する領域内に配置されていることを特徴とする。 (5) In the thin film transistor of this embodiment, the first and second low-resistance oxide semiconductor films are the gate electrode film and the first and second low-resistance oxide semiconductor films on the surface of the substrate. In the projected state, it is arranged in a region corresponding to the gate electrode film.

 本実施の形態の薄膜トランジスタにあっては、ゲート電極膜、第1及び第2の低抵抗酸化物半導体膜を基板の表面に射影した射影状態で、第1及び第2の低抵抗酸化物半導体膜は、ゲート電極膜に対応する領域内に配置されている。 In the thin film transistor of this embodiment, the first and second low-resistance oxide semiconductor films are in a projected state in which the gate electrode film and the first and second low-resistance oxide semiconductor films are projected onto the surface of the substrate. Are disposed in a region corresponding to the gate electrode film.

 従来の自己整合型の薄膜トランジスタの場合、例えば、レーザー光を基板裏面側から全面照射するので、レーザー光はゲート電極膜で遮られる。このため、ゲート電極膜の上側であってゲート電極膜の領域に対応する非晶質酸化物半導体膜の領域は、レーザー光が照射されないので、低抵抗化することができない。 In the case of a conventional self-aligned thin film transistor, for example, the entire surface of the substrate is irradiated with laser light, so that the laser light is blocked by the gate electrode film. Therefore, the region of the amorphous oxide semiconductor film above the gate electrode film and corresponding to the region of the gate electrode film is not irradiated with laser light, so that the resistance cannot be reduced.

 一方、本実施の形態の薄膜トランジスタの場合、ゲート電極膜の上側に形成された非晶質酸化物半導体膜の所要箇所に局所的(又は部分的)にエネルギービーム(例えば、レーザー光)を照射することができるので、ゲート電極膜に対応する領域内の所要の箇所に低抵抗酸化物半導体膜を形成することができる。これにより、例えば、ゲート電極の内側に酸化物半導体膜を形成するGOA(Gate Driver On Array)回路部において、酸化物半導体を低抵抗化することができるので、非晶質の酸化物半導体膜を用いたGOA回路部に比べて、電流駆動能力を増加させることができる。 On the other hand, in the case of the thin film transistor of this embodiment, an energy beam (for example, laser light) is irradiated locally (or partially) to a required portion of the amorphous oxide semiconductor film formed over the gate electrode film. Therefore, a low-resistance oxide semiconductor film can be formed at a required position in a region corresponding to the gate electrode film. Thereby, for example, in the GOA (Gate Driver On Array) circuit portion in which the oxide semiconductor film is formed inside the gate electrode, the resistance of the oxide semiconductor can be reduced. Compared with the used GOA circuit unit, the current drive capability can be increased.

 本実施の形態の表示パネルは、前述の実施の形態に係る薄膜トランジスタを備えることを特徴とする。 The display panel of this embodiment includes the thin film transistor according to the above-described embodiment.

 本実施の形態の表示パネルにあっては、薄膜トランジスタを備える。これにより、光安定性を向上させることができる薄膜トランジスタを備えた表示パネルを実現することができる。 The display panel of this embodiment includes a thin film transistor. Thus, a display panel including a thin film transistor that can improve light stability can be realized.

 1 ガラス基板(基板)
 2 ゲート電極膜
 3 ゲート絶縁膜
 4 非晶質酸化物半導体膜
 5、51 低抵抗酸化物半導体膜(第1の低抵抗酸化物半導体膜)
 6、61 低抵抗酸化物半導体膜(第2の低抵抗酸化物半導体膜)
 7 ソース電極膜
 8 ドレイン電極膜
1 Glass substrate (substrate)
2 Gate electrode film 3 Gate insulating film 4 Amorphous oxide semiconductor film 5, 51 Low resistance oxide semiconductor film (first low resistance oxide semiconductor film)
6, 61 Low resistance oxide semiconductor film (second low resistance oxide semiconductor film)
7 Source electrode film 8 Drain electrode film

Claims (7)

 基板上に酸化物半導体膜を有する薄膜トランジスタにおいて、
 前記基板の表面に形成されたゲート電極膜と、
 該ゲート電極膜の上側に形成された非晶質酸化物半導体膜と、
 該非晶質酸化物半導体膜を間にして形成された第1及び第2の低抵抗酸化物半導体膜と、
 該第1の低抵抗酸化物半導体膜上に形成されたソース電極膜と、
 前記第2の低抵抗酸化物半導体膜上に形成されたドレイン電極膜と
 を備え、
 前記第1及び第2の低抵抗酸化物半導体膜の間の非晶質酸化物半導体膜は、
 前記ゲート電極膜及び前記非晶質酸化物半導体膜を前記基板の表面に射影した射影状態で、前記ゲート電極膜に対応する領域内に配置されていることを特徴とする薄膜トランジスタ。
In a thin film transistor having an oxide semiconductor film over a substrate,
A gate electrode film formed on the surface of the substrate;
An amorphous oxide semiconductor film formed above the gate electrode film;
First and second low-resistance oxide semiconductor films formed with the amorphous oxide semiconductor film interposed therebetween;
A source electrode film formed on the first low-resistance oxide semiconductor film;
A drain electrode film formed on the second low-resistance oxide semiconductor film,
The amorphous oxide semiconductor film between the first and second low-resistance oxide semiconductor films is
A thin film transistor, wherein the gate electrode film and the amorphous oxide semiconductor film are disposed in a region corresponding to the gate electrode film in a projected state in which the surface of the substrate is projected.
 前記第1及び第2の低抵抗酸化物半導体膜は、
 前記ゲート電極膜の上側に形成された非晶質酸化物半導体膜の離隔した所要箇所にエネルギービームを照射して形成されていることを特徴とする請求項1に記載の薄膜トランジスタ。
The first and second low-resistance oxide semiconductor films are
2. The thin film transistor according to claim 1, wherein the thin film transistor is formed by irradiating an energy beam to a required separated portion of an amorphous oxide semiconductor film formed on the gate electrode film.
 前記第1の低抵抗酸化物半導体膜、前記ゲート電極膜の上側に形成された非晶質酸化物半導体膜及び前記ソース電極膜を前記基板の表面に射影した射影状態で、前記ソース電極膜と前記第1の低抵抗酸化物半導体膜とが重なる領域の面積は、前記ソース電極膜と前記非晶質酸化物半導体膜とが重なる領域の面積より大きいことを特徴とする請求項1又は請求項2に記載の薄膜トランジスタ。 The first low resistance oxide semiconductor film, the amorphous oxide semiconductor film formed above the gate electrode film, and the source electrode film are projected onto the surface of the substrate, and the source electrode film and The area of the region where the first low-resistance oxide semiconductor film overlaps is larger than the area of the region where the source electrode film and the amorphous oxide semiconductor film overlap. 2. The thin film transistor according to 2.  前記第2の低抵抗酸化物半導体膜、前記ゲート電極膜の上側に形成された非晶質酸化物半導体膜及び前記ドレイン電極膜を前記基板の表面に射影した射影状態で、前記ドレイン電極膜と前記第2の低抵抗酸化物半導体膜とが重なる領域の面積は、前記ドレイン電極膜と前記非晶質酸化物半導体膜とが重なる領域の面積より大きいことを特徴とする請求項1から請求項3までのいずれか1項に記載の薄膜トランジスタ。 In the projected state in which the second low-resistance oxide semiconductor film, the amorphous oxide semiconductor film formed on the gate electrode film and the drain electrode film are projected onto the surface of the substrate, the drain electrode film and The area of the region where the second low-resistance oxide semiconductor film overlaps is larger than the area of the region where the drain electrode film and the amorphous oxide semiconductor film overlap. 4. The thin film transistor according to any one of up to 3.  前記第1及び第2の低抵抗酸化物半導体膜は、
 前記ゲート電極膜及び前記第1及び第2の低抵抗酸化物半導体膜を前記基板の表面に射影した射影状態で、前記ゲート電極膜に対応する領域内に配置されていることを特徴とする請求項1から請求項4までのいずれか1項に記載の薄膜トランジスタ。
The first and second low-resistance oxide semiconductor films are
The gate electrode film and the first and second low-resistance oxide semiconductor films are arranged in a region corresponding to the gate electrode film in a projected state projected onto the surface of the substrate. The thin film transistor according to any one of claims 1 to 4.
 請求項1から請求項5までのいずれか1項に記載の薄膜トランジスタを備えることを特徴とする表示パネル。 A display panel comprising the thin film transistor according to any one of claims 1 to 5.  基板上に酸化物半導体膜を有する薄膜トランジスタの製造方法において、
 前記基板の表面にゲート電極膜を形成し、
 前記ゲート電極膜の上側に非晶質酸化物半導体膜を形成する場合に、前記ゲート電極膜及び前記非晶質酸化物半導体膜を前記基板の表面に射影した射影状態で、前記非晶質酸化物半導体膜を前記ゲート電極膜に対応する領域内に形成し、
 該非晶質酸化物半導体膜の離隔した所要箇所にエネルギービームを照射して第1及び第2の低抵抗酸化物半導体膜を形成し、
 該第1の低抵抗酸化物半導体膜上にソース電極膜を形成し、
 前記第2の低抵抗酸化物半導体膜上にドレイン電極膜を形成することを特徴とする薄膜トランジスタの製造方法。
In a method for manufacturing a thin film transistor having an oxide semiconductor film over a substrate,
Forming a gate electrode film on the surface of the substrate;
When an amorphous oxide semiconductor film is formed on the gate electrode film, the amorphous oxide semiconductor film is projected in a state in which the gate electrode film and the amorphous oxide semiconductor film are projected onto the surface of the substrate. Forming a physical semiconductor film in a region corresponding to the gate electrode film;
Irradiating an energy beam to a required separated portion of the amorphous oxide semiconductor film to form first and second low resistance oxide semiconductor films;
Forming a source electrode film on the first low-resistance oxide semiconductor film;
A method of manufacturing a thin film transistor, comprising forming a drain electrode film on the second low-resistance oxide semiconductor film.
PCT/JP2016/060253 2016-03-29 2016-03-29 Thin film transistor, display panel, and method for manufacturing thin film transistor WO2017168594A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/060253 WO2017168594A1 (en) 2016-03-29 2016-03-29 Thin film transistor, display panel, and method for manufacturing thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/060253 WO2017168594A1 (en) 2016-03-29 2016-03-29 Thin film transistor, display panel, and method for manufacturing thin film transistor

Publications (1)

Publication Number Publication Date
WO2017168594A1 true WO2017168594A1 (en) 2017-10-05

Family

ID=59963664

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/060253 WO2017168594A1 (en) 2016-03-29 2016-03-29 Thin film transistor, display panel, and method for manufacturing thin film transistor

Country Status (1)

Country Link
WO (1) WO2017168594A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111125A (en) * 2007-10-30 2009-05-21 Fujifilm Corp Oxide semiconductor element and manufacturing method thereof, thin film sensor, and electro-optical device
JP2012178439A (en) * 2011-02-25 2012-09-13 Nippon Hoso Kyokai <Nhk> Semiconductor device and manufacturing method thereof
JP2012182388A (en) * 2011-03-02 2012-09-20 Toshiba Corp Thin-film transistor, method of manufacturing the same, and display device
JP2013165257A (en) * 2012-02-13 2013-08-22 Samsung Electronics Co Ltd Thin film transistor, and display panel adopting the same
JP2014086705A (en) * 2012-10-26 2014-05-12 Nippon Hoso Kyokai <Nhk> Thin film transistor manufacturing method and thin film device
JP2014157893A (en) * 2013-02-15 2014-08-28 Mitsubishi Electric Corp Thin-film transistor and method of manufacturing the same
JP2015015459A (en) * 2013-06-05 2015-01-22 株式会社半導体エネルギー研究所 Display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111125A (en) * 2007-10-30 2009-05-21 Fujifilm Corp Oxide semiconductor element and manufacturing method thereof, thin film sensor, and electro-optical device
JP2012178439A (en) * 2011-02-25 2012-09-13 Nippon Hoso Kyokai <Nhk> Semiconductor device and manufacturing method thereof
JP2012182388A (en) * 2011-03-02 2012-09-20 Toshiba Corp Thin-film transistor, method of manufacturing the same, and display device
JP2013165257A (en) * 2012-02-13 2013-08-22 Samsung Electronics Co Ltd Thin film transistor, and display panel adopting the same
JP2014086705A (en) * 2012-10-26 2014-05-12 Nippon Hoso Kyokai <Nhk> Thin film transistor manufacturing method and thin film device
JP2014157893A (en) * 2013-02-15 2014-08-28 Mitsubishi Electric Corp Thin-film transistor and method of manufacturing the same
JP2015015459A (en) * 2013-06-05 2015-01-22 株式会社半導体エネルギー研究所 Display device

Similar Documents

Publication Publication Date Title
US10453876B2 (en) Method for manufacturing thin film transistor and display panel
US10008606B2 (en) Thin film transistor and display panel
JP6334057B2 (en) Thin film transistor and display panel
JP5600255B2 (en) Display device, switching circuit, and field effect transistor
US10038098B2 (en) Method for manufacturing thin film transistor, thin film transistor and display panel
US10361229B2 (en) Display device
JP5615605B2 (en) FFS mode liquid crystal device
US20060141685A1 (en) Liquid crystal display device and fabrication method thereof
WO2016098651A1 (en) Semiconductor device and method for manufacturing same, and display device provided with semiconductor device
KR101250790B1 (en) Method of fabricating liquid crystal display device
JP6471237B2 (en) Display device and manufacturing method of display device
JP5363009B2 (en) Display device and manufacturing method thereof
US20110157113A1 (en) Display panel and display device using the same
WO2017007004A1 (en) Active matrix substrate, display device and method for manufacturing display device
JP2008165028A (en) Liquid crystal display
KR20120007764A (en) Array substrate including thin film transistor using micro polysilicon and manufacturing method thereof
WO2017158843A1 (en) Display panel and method for manufacturing display panel
WO2017168594A1 (en) Thin film transistor, display panel, and method for manufacturing thin film transistor
KR20100130523A (en) Array substrate including thin film transistor using polysilicon and manufacturing method thereof
JP2002050762A (en) Display element, its manufacturing method, and display unit
KR102092544B1 (en) Array substrate for liquid crystal display device and method of fabricating the same
KR20070072208A (en) Liquid Crystal Display Using Polysilicon Thin Film Transistor and Manufacturing Method Thereof
KR20030082139A (en) TFT for LCD having an offset structure and the fabrication method thereof
KR20060019130A (en) LCD and its manufacturing method
JP2006317638A (en) Method for manufacturing liquid crystal display apparatus

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16896814

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16896814

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP