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WO2017163498A1 - Solar cell and method for manufacturing solar cell - Google Patents

Solar cell and method for manufacturing solar cell Download PDF

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Publication number
WO2017163498A1
WO2017163498A1 PCT/JP2016/086614 JP2016086614W WO2017163498A1 WO 2017163498 A1 WO2017163498 A1 WO 2017163498A1 JP 2016086614 W JP2016086614 W JP 2016086614W WO 2017163498 A1 WO2017163498 A1 WO 2017163498A1
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WIPO (PCT)
Prior art keywords
layer
solar cell
type
film
protective film
Prior art date
Application number
PCT/JP2016/086614
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French (fr)
Japanese (ja)
Inventor
裕美子 小林
達郎 綿引
孝之 森岡
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2017519697A priority Critical patent/JP6257847B1/en
Priority to CN201680082746.9A priority patent/CN109075216A/en
Priority to TW106104443A priority patent/TWI626756B/en
Publication of WO2017163498A1 publication Critical patent/WO2017163498A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the technology disclosed in this specification relates to a solar cell and a method for manufacturing the solar cell.
  • a very thin oxide layer that is, a tunnel oxide layer is formed on the top surface of a semiconductor substrate, and a silicon doped layer is formed on the top surface of the tunnel oxide layer. There is a way to do it.
  • the fill factor is a value obtained by dividing the output (maximum output) at the optimum operating point by the product of the open circuit voltage and the short circuit current.
  • Non-Patent Document 1 a tunnel oxide layer is formed on the back surface of an n-type silicon substrate, and a phosphorus-doped silicon layer is further formed on the back surface of the tunnel oxide layer. And after a phosphorus dope silicon layer is formed, heat processing is performed at 600 degreeC or more and less than 1000 degreeC. Thereafter, a back electrode is formed entirely on the lower surface of the phosphorus-doped silicon layer.
  • an electrode forming method a method of performing Ag plating after thermally depositing a seed layer made of Ti, Pd, and Ag is used.
  • a semiconductor layer is formed on the upper surface of a silicon oxide layer that is a tunnel oxide layer, and a transparent conductive film is further formed on the upper surface of the semiconductor layer. Then, a comb-shaped electrode is formed on the upper surface of the transparent conductive film.
  • the transparent conductive film is a film that protects the semiconductor layer, which is a silicon-doped layer, from electrode formation damage.
  • the transparent conductive film has conductivity, the electrode can be contacted without requiring an opening treatment unlike the insulating layer.
  • Non-Patent Document 1 or Patent Document 1 described above in order to collect photocurrent caused by photoelectrons, an electrode is formed by vapor deposition or plating on a silicon doped layer in a tunnel junction layer, or silicon The doped layer is brought into contact with the electrode with a transparent conductive film interposed therebetween.
  • the method of forming electrode contacts by printing baked silver using a high temperature baking process is simple and highly productive. Furthermore, if a high-temperature firing process is used, the firing silver paste can reduce the resistance of the electrode, has good contact properties, and has high reliability.
  • characteristics of the tunnel junction layer may deteriorate due to physical damage due to printing of the fired silver, thermal damage due to the firing process, or erosion of the fired silver. There is.
  • the characteristics of the tunnel junction layer may deteriorate.
  • the deterioration of the characteristics of the tunnel junction layer due to firing is caused by the fire-through electrode breaking through the silicon doped layer having a thickness of 100 nm or less, for example. This is caused by erosion of the semiconductor substrate.
  • Patent Document 1 if the transparent conductive film is sandwiched between the silicon doped layer and the electrode, the substrate erosion of the electrode as described above and physical damage during printing are suppressed. I think it can be done.
  • the transparent conductive film has a high carrier concentration and high light absorption. As a result, current loss may increase. In addition, the transparent conductive film has poor resistance to high-temperature processing such as baking. Therefore, electrical characteristics or structural deterioration due to firing occurs.
  • the technology disclosed in the specification of the present application has been made in order to solve the problems described above, and relates to a technology capable of suppressing damage caused by firing while being provided with a fired electrode. is there.
  • One aspect of the technology disclosed in this specification is a tunnel oxide layer formed on a semiconductor substrate, a semiconductor layer of a first conductivity type formed on the tunnel oxide layer, and the semiconductor layer A protective film formed on the protective film; and an electrode formed through the protective film and in contact with the semiconductor layer.
  • the electrode is a fired electrode including glass particles. .
  • a tunnel oxide layer is formed on a semiconductor substrate, a semiconductor layer of a first conductivity type is formed on the tunnel oxide layer, and A heat treatment is performed on the semiconductor layer at a temperature of 400 ° C. or more, a protective film is formed on the heat-treated semiconductor layer, an electrode is printed on the protective film, and the electrode and the semiconductor layer are baked. Are electrically connected to each other.
  • One aspect of the technology disclosed in this specification is a tunnel oxide layer formed on a semiconductor substrate, a semiconductor layer of a first conductivity type formed on the tunnel oxide layer, and the semiconductor layer A protective film formed on the protective film; and an electrode formed through the protective film and in contact with the semiconductor layer.
  • the electrode is a fired electrode including glass particles.
  • the protective film suppresses a large amount of hydrogen from being desorbed from the semiconductor layer by heat treatment or baking, thereby suppressing a decrease in the passivation effect of the semiconductor layer.
  • a tunnel oxide layer is formed on a semiconductor substrate, a semiconductor layer of a first conductivity type is formed on the tunnel oxide layer, and A heat treatment is performed on the semiconductor layer at a temperature of 400 ° C. or more, a protective film is formed on the heat-treated semiconductor layer, an electrode is printed on the protective film, and the electrode and the semiconductor layer are baked.
  • the protective film formed on the semiconductor layer is pierced by the electrode to be baked, and further, the electrode that has broken through the semiconductor layer Can be prevented from reaching the semiconductor substrate.
  • the protective film can withstand high temperature processing, the manufacturing process is not limited.
  • FIG. 2 is a cross-sectional view taken along line A-A ′ in FIG. 1.
  • It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment.
  • It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment.
  • It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment.
  • It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment.
  • FIG. 12 is a B-B ′ sectional view in FIG. 11. It is a flowchart which illustrates the manufacturing method of the solar cell regarding embodiment. It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment.
  • FIG. 1 is a plan view schematically illustrating the structure of a solar cell formed by the method for manufacturing a solar cell according to the present embodiment.
  • FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG.
  • an n-type single crystal silicon substrate 100 having a light receiving surface 100A and a back surface 100B as a crystalline semiconductor substrate is used. Use.
  • a tunnel oxide layer 104 is formed on the back surface 100B of the n-type single crystal silicon substrate 100.
  • an n-type amorphous silicon layer 105 containing an n-type dopant is formed on the lower surface of the tunnel oxide layer 104.
  • n-type dopant contained in the n-type amorphous silicon layer 105 is activated. Is crystallized to form an n-type crystalline thin film silicon layer 106.
  • a silicon nitride layer as a protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106.
  • the back electrode 111 is printed from the lower surface of the protective film 107, and further, the back electrode 111 is fired through the protective film 107 by firing, whereby the contact of the back electrode 111 with the n-type crystalline thin film silicon layer 106 is made.
  • a light receiving surface electrode 110 including a grid electrode 110G and a bus electrode 110B is formed on the light receiving surface 100A side of the n-type single crystal silicon substrate 100.
  • a back electrode 111 including a grid electrode 110G and a bus electrode 110B is formed on the back surface 100B side of the n-type single crystal silicon substrate 100.
  • the protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106. Then, the back electrode 111 is printed from the lower surface of the protective film 107, and the back electrode 111 is baked.
  • the electrode when an electrode is directly printed on an n-type crystalline thin film silicon layer and the electrode is fired, the electrode is formed by a fire-through tunnel oxide layer and an n-type crystalline thin film silicon. Break through the layers. Therefore, the electrode comes into contact with the tunnel oxide layer and further the silicon substrate, and the open circuit voltage is lowered due to the increase of recombination.
  • the n-type crystalline thin film silicon layer may be damaged by contact with the printing plate or friction, and the passivation effect may be reduced. There is.
  • FIG. 3 is a flowchart illustrating a method for manufacturing a solar cell according to this embodiment.
  • 4 to 9 are cross-sectional views of the solar cell illustrating the solar cell manufacturing method according to this embodiment.
  • an n-type single crystal silicon substrate 100 is prepared.
  • the n-type single crystal silicon substrate 100 is manufactured by cutting and slicing a silicon ingot using a mechanical cutting method such as a wire saw. Therefore, contamination or damage may remain on the surface.
  • a fine concavo-convex structure called a texture structure is formed on the surface of the n-type single crystal silicon substrate 100 by performing a wet etching process using an alkali solution such as a sodium hydroxide solution.
  • An alkaline solution and an additive are used for forming the texture structure.
  • the light incident on the n-type single crystal silicon substrate 100 undergoes multiple reflections on the substrate surface due to the minute uneven structure on the surface of the n-type single crystal silicon substrate 100. Therefore, the reflection loss of light can be reduced. In addition, light absorption increases with an increase in optical path length. As a result, an improvement in short circuit current can be expected. For simplicity, the texture structure is not shown in the drawing.
  • RCA cleaning SPM (Surfuric Acid Hydroxide Mixture) cleaning
  • HPM Hydrogen Peroxide Mixture
  • RCA cleaning SPM (Surfuric Acid Hydroxide Mixture) cleaning
  • HPM Hydrogen Peroxide Mixture cleaning method using a concentrated chemical solution containing hydrogen peroxide as a base and an alkali or acid added at a high temperature.
  • Acid Hydrogen Peroxide Mixture is performed to remove organic substances adhering to the surface of the n-type single crystal silicon substrate 100 or adhering substances due to metal contamination.
  • a p-type impurity diffusion layer 103 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100 (see step ST100 in FIG. 3).
  • n-type single crystal silicon substrate 100 for example, a gas phase reaction using BBr 3 or an atmospheric pressure chemical vapor deposition (ie, APCVD) method using B 2 H 6 is used.
  • a boron-doped silicon glass (BSG) film as the p-type impurity diffusion source 101 is formed by the vapor phase method.
  • the p-type impurity diffusion layer 103 is formed by thermally diffusing boron in a diffusion furnace.
  • the p-type impurity diffusion layer 103 may be formed by implanting boron into the surface of the n-type single crystal silicon substrate 100 by ion implantation and then thermally diffusing boron in a diffusion furnace.
  • the sheet resistance of the formed p-type impurity diffusion layer 103 can be, for example, 50 ⁇ / ⁇ or more and less than 150 ⁇ / ⁇ .
  • the sheet resistance is determined in consideration of recombination of minority carriers in the diffusion layer, light absorption, contact resistance with the electrode, and the like.
  • the BSG film can be formed only on the light-receiving surface 100A of the n-type single crystal silicon substrate 100.
  • the BSG film slightly wraps around the end surface of the n-type single crystal silicon substrate 100 and the back surface of the n-type single crystal silicon substrate 100, for example, 0.5% or more after forming the BSG film.
  • the BSG film that wraps around the end surface of the n-type single crystal silicon substrate 100 and the back surface of the n-type single crystal silicon substrate 100 can be removed with 1.0% or less hydrofluoric acid.
  • NSG non-doped silicon glass
  • the NSG film 102 functions as a cap layer to prevent boron in the p-type impurity diffusion source 101 made of the BSG film from desorbing into the gas phase. Therefore, boron can be diffused efficiently.
  • the NSG film 102 also functions as a diffusion barrier layer during heat treatment for dopant activation of the n-type amorphous silicon layer 105 to be formed later on the back surface of the n-type single crystal silicon substrate 100.
  • the thickness of the BSG film which is the p-type impurity diffusion source 101 is, for example, 30 nm or more and less than 150 nm. If the thickness of the BSG film which is the p-type impurity diffusion source 101 is too thin, it cannot function as a diffusion source. On the other hand, if the thickness of the BSG film that is the p-type impurity diffusion source 101 is too thick, it becomes difficult to form the BSG film and remove the BSG film.
  • the film thickness of the NSG film 102 is, for example, 100 nm or more and less than 500 nm. If the NSG film 102 is too thin, it cannot function as a cap layer or a diffusion barrier layer. On the other hand, if the film thickness of the NSG film 102 is too thick, it becomes difficult to form the NSG film 102 and remove the NSG film 102.
  • the BSG film is not only applied to the light receiving surface 100A but also to the back surface 100B of the n-type single crystal silicon substrate 100. It is formed.
  • a barrier layer made of a thermal oxide film or a nitride film is formed on the upper surface of the BSG film formed on the light receiving surface 100A of the n-type single crystal silicon substrate 100, and then formed on the back surface 100B of the n-type single crystal silicon substrate 100.
  • the formed BSG film is removed with hydrofluoric acid.
  • the p-type impurity diffusion layer 103 is removed on one side with a treatment agent such as hydrofluoric acid or sodium hydroxide.
  • the nitride film can be formed using, for example, a plasma CVD method using silane gas, nitrogen gas, ammonia gas, or the like.
  • said barrier layer functions as a barrier layer also at the time of the heat processing for dopant activation later, it is preferable to form with a thickness of 50 nm or more, for example.
  • a tunnel oxide layer 104 is formed on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST101 in FIG. 3).
  • a dielectric material such as a silicon oxide film or an aluminum oxide film can be used.
  • the silicon oxide film can be formed by, for example, immersion in ozone water. In this case, the ozone concentration and the immersion time are controlled so that an oxide film having a desired thickness is obtained.
  • the silicon oxide film can be formed by thermal oxidation, nitric acid oxidation, plasma enhanced chemical vapor deposition (PECVD) method, atomic layer deposition (ALD) method, UV irradiation, or ozone.
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • UV irradiation or ozone.
  • a method such as irradiation can also be used.
  • the film thickness of the tunnel oxide layer 104 is, for example, 0.5 nm or more and less than 5 nm.
  • the film thickness of the tunnel oxide layer 104 is, for example, 0.5 nm or more and less than 5 nm.
  • an n-type amorphous silicon layer 105 is formed on the lower surface of the tunnel oxide layer 104 (see step ST102 in FIG. 3).
  • An n-type amorphous silicon layer 105 is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 or PH 3 .
  • the film thickness of the n-type amorphous silicon layer 105 is, for example, 5 nm or more and less than 100 nm.
  • the thickness of the n-type amorphous silicon layer 105 is too thin, the field effect is weakened.
  • the electrical resistance in the tunnel junction layer increases, and the minority carrier repulsion effect decreases. Therefore, the characteristics of the n-type amorphous silicon layer 105 deteriorate.
  • the thermal strain increases. For this reason, it is known that the passivation effect of the silicon layer is reduced as compared with the case where the film thickness of the n-type amorphous silicon layer 105 is in an appropriate range.
  • the structure illustrated in FIG. 6 is introduced into the diffusion furnace, and the temperature is raised while flowing nitrogen gas. Then, heat treatment is performed by holding at a constant temperature for a certain time (see step ST103 in FIG. 3).
  • the n-type amorphous silicon layer 105 is crystallized to be changed into the n-type crystalline thin film silicon layer 106.
  • the film thickness of the n-type crystalline thin film silicon layer 106 is, for example, 5 nm or more and less than 100 nm.
  • the n-type dopant in the n-type amorphous silicon layer 105 is activated by the heat treatment. By doing so, the sheet resistance decreases.
  • the optimum annealing temperature varies depending on the phosphorus concentration contained in the silicon doped layer or the thickness of the silicon doped layer.
  • the peak temperature which is the highest temperature during the heat treatment of the n-type amorphous silicon layer 105, is 400 ° C. or higher and lower than 900 ° C.
  • the heat treatment temperature is low, the crystallization of the n-type amorphous silicon layer 105 is not sufficiently promoted. Therefore, the electric field effect on the back surface 100B is reduced, and a high passivation effect cannot be obtained. In addition, since the n-type amorphous silicon layer 105 has a high resistance, transport of majority carriers may be hindered. Note that when the heat treatment temperature exceeds 400 ° C., hydrogen begins to be desorbed from the n-type amorphous silicon layer 105, so that crystallization is promoted.
  • the n-type dopant in the n-type amorphous silicon layer 105 penetrates the tunnel oxide layer 104 and diffuses to the n-type single crystal silicon substrate 100 in a large amount by high-temperature heat treatment. Even if the n-type crystalline thin film silicon layer 106 is formed due to the structural breakdown of the oxide layer 104 or the diffusion of the dopant from the n-type amorphous silicon layer 105, the field effect is reduced. This is because it happens.
  • the n-type crystalline thin film silicon layer 106 may be formed by diffusing an n-type dopant after forming a non-doped (intrinsic) amorphous silicon layer.
  • a non-doped amorphous silicon layer is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 .
  • an n-type dopant is diffused into the non-doped amorphous silicon layer by gas phase reaction and thermal diffusion using POCl 3 or phosphorus ion implantation and thermal diffusion.
  • the n-type crystalline thin film silicon layer 106 is formed by chemical vapor deposition such as low pressure chemical vapor deposition (ie, LPCVD) using SiH 4 and PH 3. You may form in a process. In that case, for example, the n-type crystalline thin film silicon layer 106 may be formed at a temperature of 500 ° C. or higher, and heat treatment after the film formation may be performed as necessary.
  • chemical vapor deposition such as low pressure chemical vapor deposition (ie, LPCVD) using SiH 4 and PH 3. You may form in a process. In that case, for example, the n-type crystalline thin film silicon layer 106 may be formed at a temperature of 500 ° C. or higher, and heat treatment after the film formation may be performed as necessary.
  • the BSG film which is the p-type impurity diffusion source 101 formed on the light receiving surface 100 ⁇ / b> A of the n-type single crystal silicon substrate 100 and the NSG film 102 are mixed with hydrofluoric acid. Use to remove completely.
  • This step can be performed before the heat treatment step of step ST103.
  • boron diffuses into the atmosphere from the BSG film as the p-type impurity diffusion source 101 during the heat treatment, so that the boron adheres to the n-type amorphous silicon layer 105 and further diffuses. Can be prevented.
  • the n-type dopant may diffuse from the n-type amorphous silicon layer 105 into the atmosphere and diffuse into the p-type impurity diffusion layer 103.
  • the NSG film 102 which is a cap layer is formed on the upper surface of the BSG film which is the p-type impurity diffusion source 101, and there is a possibility that boron may diffuse into the n-type amorphous silicon layer 105. Therefore, it is preferable to remove the BSG film and the NSG film 102 after the heat treatment in step ST103.
  • a protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 on the back surface 100B of the n-type single crystal silicon substrate 100 (step ST104 in FIG. 3 is performed). reference).
  • the material of the protective film 107 is, for example, silicon nitride, silicon oxide, silicon nitride oxide, amorphous silicon, microcrystalline silicon, or silicide. Further, the protective film 107 may have a stacked structure of a plurality of films.
  • the protective film 107 preferably has a higher hardness than the n-type crystalline thin film silicon layer 106 which is a silicon doped layer. This is to protect the n-type crystalline thin film silicon layer 106 from physical damage due to contact with the plate or friction when electrodes are screen-printed on the protective film 107.
  • the hydrogen concentration in the protective film 107 is preferably higher than the hydrogen concentration in the n-type crystalline thin silicon layer 106. If the protective film 107 contains sufficient hydrogen, the hydrogen is desorbed during heat treatment and electrode firing. Then, dangling bonds in the formed n-type crystalline thin film silicon layer 106 and the interface between the tunnel oxide layer 104 and the single crystal silicon substrate 100 are terminated by hydrogen desorbed from the protective film 107. The This improves the passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104.
  • the film thickness of the protective film 107 is preferably, for example, 5 nm or more and less than 200 nm. If the film thickness of the protective film 107 is too thin, it cannot be prevented that the electrode penetrates the n-type crystalline thin film silicon layer 106 and erodes the n-type single crystal silicon substrate 100 during firing. If the thickness of the protective film 107 is too thin, sufficient hydrogen cannot be supplied from the protective film 107, so that the passivation effect of the n-type crystalline thin film silicon layer 106 is reduced.
  • the electrode is less likely to contact the n-type crystalline thin film silicon layer 106, and the contact resistance increases.
  • a dielectric layer 108 on the light receiving surface 100 ⁇ / b> A side is formed on the upper surface of the p-type impurity diffusion layer 103 in the light receiving surface 100 ⁇ / b> A of the n-type single crystal silicon substrate 100.
  • an antireflection film 109 is formed on the upper surface of the dielectric layer 108 (see step ST105 in FIG. 3).
  • the dielectric layer 108 for example, an oxide film can be used.
  • a dielectric layer such as an atomic layer deposition (ALD) or an aluminum oxide film formed by a CVD method can be used.
  • ALD atomic layer deposition
  • the aluminum oxide film has a negative fixed charge, it is known to exhibit an excellent passivation effect for the p-type impurity diffusion layer 103.
  • the film thickness of the dielectric layer 108 is, for example, 2 nm or more and less than 50 nm.
  • An antireflection film 109 is formed on the upper surface of the dielectric layer 108.
  • the antireflection film 109 for example, a silicon nitride film formed by a plasma CVD method is used.
  • the film thickness of the antireflection film 109 is designed to be an optimal film thickness for the solar spectrum, for example, about 30 nm or more and less than 80 nm according to the thickness of the dielectric layer 108.
  • the light-receiving surface electrode 110 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100. Further, the back electrode 111 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 (see step ST106 in FIG. 3). Thereby, the solar cell illustrated in FIGS. 1 and 2 is formed.
  • a paste containing metal particles and glass particles is first applied in a comb pattern on the antireflection film 109 and the protective film 107 by a coating method such as a screen printing method. Further, they are formed by drying them.
  • the content of the glass particles is 0.5 wt% or more and 10.0 wt% or less, preferably 1.0 wt% or more and 3.0 wt% based on the weight of the metal particles. % Or less.
  • the above paste is dried in a drying oven at 200 ° C. for about 10 minutes, for example. After drying, the light-receiving surface electrode 110 and the back surface electrode 111 are simultaneously heat-treated at a high temperature of about 800 ° C. and fired.
  • the glass particles etch the dielectric layer 108 on the light receiving surface 100A side and the antireflection film 109 by firing. Then, the p-type impurity diffusion layer 103 is exposed, and the light-receiving surface electrode 110 is electrically connected to the p-type impurity diffusion layer 103.
  • the glass particles etch the protective film 107 also on the back surface 100B side. Then, the n-type crystalline thin film silicon layer 106 is exposed, and the back electrode 111 is electrically connected to the n-type crystalline thin film silicon layer 106.
  • the back electrode penetrates the n-type crystalline thin film silicon layer and erodes the n-type single crystal silicon substrate during firing.
  • the structure including the tunnel oxide layer and the n-type crystalline thin film silicon layer deteriorates due to heat during firing.
  • the n-type crystalline thin film silicon layer may be damaged during printing, resulting in deterioration of characteristics.
  • the electrode when the electrode is baked through the transparent conductive film, the light absorption of the transparent conductive film is large, which may cause a current drop. Moreover, when baking an electrode through a transparent conductive film, since the transparent conductive film has poor resistance to high-temperature treatment such as baking, there is a possibility that a decrease in electrical characteristics, for example, a voltage drop may occur.
  • a protective film 107 is formed on the n-type crystalline thin film silicon layer 106, and electrodes are printed and baked through the protective film 107. Therefore, at the time of firing, the electrode does not penetrate into the n-type single crystal silicon substrate 100, and can only be eroded into the n-type crystalline thin film silicon layer 106.
  • the protective film 107 passivates the lower surface of the n-type crystalline thin film silicon layer 106. Furthermore, hydrogen in the protective film 107 is supplied to the n-type crystalline thin film silicon layer 106 during firing, and in the n-type crystalline thin film silicon layer 106 and between the tunnel oxide layer 104 and the single crystal silicon substrate 100. Terminates dangling bonds at the interface. As a result, recombination of minority carriers is suppressed, and an improvement in solar cell characteristics can be expected.
  • the peak temperature during the heat treatment of the n-type amorphous silicon layer 105 and the peak temperature during the electrode firing are preferably higher than the formation temperature of the protective film 107. If the peak temperature during the heat treatment and the peak temperature during the electrode firing are higher than the formation temperature of the protective film 107, the hydrogen contained in the protective film 107 is n-type crystalline thin film silicon during the heat treatment and during the electrode firing. It diffuses in the layer 106 and at the interface between the tunnel oxide layer 104 and the single crystal silicon substrate 100. Therefore, the passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104 are improved.
  • FIG. 10 shows the estimation of the open-circuit voltage obtained from the heat treatment temperature [° C.] of the n-type amorphous silicon layer and the minority carrier lifetime for each of the case where the protective film is not formed and the case where the protective film is formed. It is a figure which illustrates the relationship with value [mV].
  • a tunnel oxide layer and an n-type amorphous silicon layer were respectively formed on the upper and lower surfaces of the n-type single crystal silicon substrate, and then heat treatment and baking were performed.
  • the heat treatment temperature was, for example, 725 ° C. or higher and 825 ° C. or lower, and firing was performed at 800 ° C.
  • the evaluation was performed by measuring the estimated open circuit voltage after heat treatment and after firing.
  • the estimated value of the open circuit voltage after heat treatment improved with increasing heat treatment temperature up to a specific temperature. Then, it was found that the estimated value of the open circuit voltage after the heat treatment reached a peak when the heat treatment temperature was 775 ° C. and decreased at a heat treatment temperature higher than that.
  • the protective film when the protective film is not formed, it is necessary to set the heat treatment temperature higher than the temperature at which the passivation effect reaches a peak in consideration that the passivation effect is reduced by firing. As a result, the optimum annealing temperature may not be set. In that case, the reduction in conversion efficiency cannot be avoided.
  • the heat treatment temperature is set to, for example, 725 ° C. or more and 800 ° C. or less.
  • the estimated value of the open circuit voltage was measured about each after heat processing of 800 degreeC, formation of a protective film, and baking processing of 800 degreeC.
  • the estimated value of the open-circuit voltage after the heat treatment improved as the heat treatment temperature increased up to a specific temperature. Then, it was found that the estimated value of the open circuit voltage after the heat treatment reached a peak at a certain temperature and decreased at a heat treatment temperature higher than that.
  • the surface of the n-type crystalline thin film silicon layer is passivated.
  • the dopant is not sufficiently activated, and there are few recombination sites in the n-type crystalline thin film silicon layer.
  • the field effect of the n-type crystalline thin film silicon layer is weak, it is easy to obtain a passivation effect of the protective film.
  • the n-type crystalline thin film silicon layer has a strong electric field effect, and is not easily affected by the passivation effect of the protective film.
  • the estimated open circuit voltage slightly increased. This is because the protective film prevents a large amount of hydrogen desorption from the n-type crystalline thin film silicon layer, and at the interface between the n-type crystalline thin film silicon layer and the tunnel oxide layer and the single crystal silicon substrate. This is because hydrogen is supplied.
  • the heat treatment temperature of the n-type crystalline thin film silicon layer is set higher than the temperature at which the passivation effect peaks. There is no need to set it high.
  • the protective film when a protective film is formed in contact with the n-type crystalline thin film silicon layer, the protective film functions as a cap layer, so that hydrogen desorption from the n-type crystalline thin film silicon layer during firing is performed. Separation can be prevented. Therefore, the passivation effect of the n-type crystalline thin film silicon layer can be maximized. Thereby, a high open circuit voltage can be realized.
  • the protective film is formed not only when the protective film is not formed but also when the open circuit voltage is reduced due to electrode erosion. Can be suppressed. Specifically, as a result of producing a cell using the fired electrode, when the protective film was formed, an improvement of 30 mV or more and 50 mV or less of the estimated open circuit voltage was observed. However, the thickness of a protective film and the thickness of a silicon dope layer shall be produced in each design range.
  • FIG. 11 is a plan view schematically illustrating the structure of the solar cell formed by the solar cell manufacturing method according to the present embodiment.
  • FIG. 12 is a cross-sectional view taken along the line BB ′ in FIG.
  • FIG. 13 is a flowchart illustrating a method for manufacturing a solar cell according to this embodiment.
  • 14 to 19 are cross-sectional views of the solar cell illustrating the method for manufacturing the solar cell according to this embodiment.
  • a p-type single crystal silicon substrate 200 is used instead of the n-type single crystal silicon substrate 100 in FIG. Therefore, the conductivity type is the reverse of the configuration in FIG.
  • the n-type impurity diffusion layer 203 is formed on the light-receiving surface 200A of the p-type single crystal silicon substrate 200.
  • a tunnel oxide layer 204 is formed on the back surface 200B of the p-type single crystal silicon substrate 200, and the p-type is formed on the lower surface of the tunnel oxide layer 204.
  • An amorphous silicon layer 205 is formed.
  • a protective film 207 is formed on the lower surface of the p-type crystalline thin film silicon layer 206.
  • the back electrode 211 is printed from the lower surface of the protective film 207, and the back electrode 211 is fired through the p-type crystalline thin film silicon layer 206 by baking to form a contact.
  • an n-type impurity diffusion layer 203 is formed on the light-receiving surface 200A of the p-type single crystal silicon substrate 200 (see step ST200 in FIG. 13).
  • the PSG film as the n-type impurity diffusion source 201 and the NSG film 202 are formed by a vapor phase reaction using POCl 3 or a vapor phase method such as an APCVD method using PH 3
  • phosphorus is thermally diffused in a diffusion furnace.
  • phosphorus may be implanted by ion implantation and thermally diffused.
  • a tunnel oxide layer 204 is formed on the back surface 200B of the p-type single crystal silicon substrate 200 (see step ST201 in FIG. 13).
  • a p-type amorphous silicon layer 205 is formed on the lower surface of the tunnel oxide layer 204 (see step ST202 in FIG. 13).
  • the p-type amorphous silicon layer 205 is formed by a chemical vapor deposition method such as PECVD using SiH 4 or B 2 H 6 .
  • heat treatment is performed to form a p-type crystalline thin film silicon layer 206 (see step ST203 in FIG. 13).
  • the p-type crystalline thin film silicon layer 206 may be formed by forming a non-doped amorphous silicon layer and then doping a p-type dopant.
  • the p-type crystalline thin film silicon layer 206 may be formed in one step by a chemical vapor deposition method such as LPCVD.
  • a dielectric layer 208 is formed on the upper surface of the n-type impurity diffusion layer 203. Then, an antireflection film 209 is formed on the upper surface of the dielectric layer 208 (see step ST205 in FIG. 13).
  • dielectric layer 208 for example, a silicon oxide film can be used.
  • antireflection film 209 for example, a silicon nitride film can be used.
  • the light receiving surface electrode 210 is formed on the light receiving surface 200A of the p-type single crystal silicon substrate 200. Further, a back electrode 211 is formed on the lower surface of the p-type crystalline thin film silicon layer 206 (see step ST206 in FIG. 13). Thereby, the solar cell illustrated in FIGS. 11 and 12 is formed.
  • Each electrode is formed by applying a paste containing metal particles and glass particles in a comb pattern by a coating method such as a screen printing method, and drying them.
  • the above paste is dried in a drying oven at 200 ° C. for about 10 minutes, for example. After drying, the light-receiving surface electrode 210 and the back surface electrode 211 are simultaneously heat-treated at a high temperature of about 800 ° C. and fired.
  • the glass particles etch the dielectric layer 208 and the antireflection film 209 on the light receiving surface 200A side by firing. Then, the n-type impurity diffusion layer 203 is exposed, and the light-receiving surface electrode 210 is electrically connected to the n-type impurity diffusion layer 203.
  • the glass particles etch the protective film 207 on the back surface 200B side as well. Then, the p-type crystalline thin film silicon layer 206 is exposed, and the back electrode 211 is electrically connected to the p-type crystalline thin film silicon layer 206.
  • the same effects as in the first embodiment can be obtained.
  • the p-type cell uses the p-type single crystal silicon substrate 200, the substrate is less expensive than the n-type cell. Therefore, manufacturing cost can be reduced.
  • FIG. 20 is a cross-sectional view schematically illustrating the structure of the solar cell formed by the solar cell manufacturing method according to the present embodiment.
  • FIG. 21 is a flowchart illustrating a method for manufacturing a solar cell according to this embodiment.
  • 22 to 27 are cross-sectional views of the solar cell illustrating the method for manufacturing the solar cell according to this embodiment.
  • the back emitter structure solar cell in which the emitter layer is provided on the back surface 100B of the n-type single crystal silicon substrate 100 and the back surface electric field layer is provided on the light receiving surface 100A of the n-type single crystal silicon substrate 100. Is produced.
  • a BSG film is formed as a p-type impurity diffusion source 101 on the back surface 100B of the n-type single crystal silicon substrate 100, as illustrated in FIG.
  • an NSG film 102 is formed as a cap layer on the lower surface of the BSG film as the p-type impurity diffusion source 101.
  • a p-type impurity diffusion layer 103 is formed on the back surface 100B of the n-type single crystal silicon substrate 100 by thermal diffusion (see step ST300 in FIG. 21).
  • a tunnel oxide layer 104 is formed on the light receiving surface 100A of the n-type single crystal silicon substrate 100 (see step ST301 in FIG. 21). Then, as illustrated in FIG. 24, an n-type amorphous silicon layer 105 is formed on the upper surface of the tunnel oxide layer 104 (see step ST302 in FIG. 21).
  • heat treatment is performed to form an n-type crystalline thin film silicon layer 106 from the n-type amorphous silicon layer 105 as illustrated in FIG. 25 (see step ST303 in FIG. 21).
  • a protective film 107 is formed (see step ST304 in FIG. 21).
  • the protective film 107 is provided on the light receiving surface 100A, it is desirable that the protective film 107 be a low light absorption material.
  • the protective film 107 a material that is a single layer structure or a laminated structure and has an optimum reflectance with respect to the sunlight spectrum is selected.
  • the thickness of the protective film 107 is selected so as to obtain an optimum reflectance with respect to the sunlight spectrum.
  • the thickness is designed to be 60 nm or more and less than 100 nm.
  • a dielectric layer 108 is formed on the lower surface of the p-type impurity diffusion layer 103 on the back surface 100B. Further, an antireflection film 109 is formed on the lower surface of the dielectric layer 108 (see step ST305 in FIG. 21).
  • the light-receiving surface electrode 110 is printed from the upper surface of the protective film 107, and the light-receiving surface electrode 110 is fired through the n-type crystalline thin film silicon layer 106 by baking to form a contact.
  • the back electrode 111 is also printed on the back surface 100B, and the back electrode 111 is electrically connected to the p-type impurity diffusion layer 103 by firing (see step ST306 in FIG. 21).
  • the same effects as in the first embodiment can be obtained.
  • the emitter layer is formed on the back surface 100B, it is not necessary to consider the light shielding loss of the grid electrode formed on the bottom surface of the emitter layer. Therefore, the pitch of the grid electrodes can be reduced, and the resistance of the emitter layer can be increased, so that the passivation effect can be improved.
  • FIG. 28 is a cross-sectional view schematically illustrating the structure of a solar cell formed by the solar cell manufacturing method according to the present embodiment.
  • FIG. 29 is a flowchart illustrating the method for manufacturing the solar cell according to this embodiment.
  • the solar cell according to the present embodiment has a structure in which impurities are selectively diffused in the n-type single crystal silicon substrate 100 immediately below the back surface electrode 111 in the first embodiment.
  • FIG. 29 is a flowchart illustrating the method for manufacturing the solar cell according to this embodiment.
  • an n-type single crystal silicon substrate 100 is prepared.
  • the n-type single crystal silicon substrate 100 is manufactured by cutting and slicing a silicon ingot using a mechanical cutting method such as a wire saw. Therefore, contamination or damage may remain on the surface.
  • a fine concavo-convex structure called a texture structure is formed on the surface of the n-type single crystal silicon substrate 100 by performing a wet etching process using an alkali solution such as a sodium hydroxide solution.
  • An alkaline solution and an additive are used for forming the texture structure.
  • the light incident on the n-type single crystal silicon substrate 100 undergoes multiple reflections on the substrate surface due to the minute uneven structure on the surface of the n-type single crystal silicon substrate 100. Therefore, the reflection loss of light can be reduced. In addition, light absorption increases with an increase in optical path length. As a result, an improvement in short circuit current can be expected. For simplicity, the texture structure is not shown in the drawing.
  • RCA cleaning, SPM cleaning, or HPM cleaning which is a cleaning method using a concentrated chemical solution containing hydrogen peroxide as a base and an alkali or acid added at a high temperature, is performed.
  • Organic substances adhering to the surface of the crystalline silicon substrate 100 or adhering substances due to metal contamination are removed.
  • a p-type impurity diffusion layer 103 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100 (see step ST400 in FIG. 29).
  • a BSG as a p-type impurity diffusion source 101 is formed on an n-type single crystal silicon substrate 100 by, for example, a vapor phase reaction using BBr 3 or an APCVD method using B 2 H 6. A film is formed. Thereafter, the p-type impurity diffusion layer 103 is formed by thermally diffusing boron in a diffusion furnace.
  • the n-type impurity diffusion region 112 is selectively formed on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST407 in FIG. 29). .
  • the n-type impurity diffusion region 112 is formed at a position corresponding to a region where a back electrode 111 described later is formed, for example, a region at least partially overlapping with a region where the back electrode 111 is formed in plan view.
  • An example of a method for forming the n-type impurity diffusion region 112 is a method using a dopant paste containing phosphorus atoms in the paste.
  • a dopant paste is screen-printed on the back surface 100B of the n-type single crystal silicon substrate 100 opposite to the surface on which the p-type impurity diffusion layer 103 is formed.
  • the region where the dopant paste is printed is a region where the back electrode 111 is printed later.
  • the width of the region where the dopant paste is printed is designed wider than the formation width of the back electrode 111 in consideration of misalignment of the back electrode 111 when the back electrode 111 is printed.
  • phosphorus atoms are diffused from the printed dopant paste into the n-type single crystal silicon substrate 100 by annealing at a temperature of 700 ° C. or higher, for example, in a diffusion furnace.
  • the n-type single crystal silicon substrate 100 is immersed in a hydrofluoric acid solution.
  • the BSG film generated when the p-type impurity diffusion layer 103 is formed can be removed at this time.
  • the n-type impurity diffusion region 112 can be selectively formed.
  • a tunnel oxide layer 104 is formed on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST401 in FIG. 29).
  • a dielectric material such as a silicon oxide film or an aluminum oxide film can be used.
  • the silicon oxide film can be formed by, for example, immersion in ozone water. In this case, the ozone concentration and the immersion time are controlled so that an oxide film having a desired thickness is obtained.
  • a method such as thermal oxidation, nitric acid oxidation, PECVD method, ALD method, UV irradiation, or ozone irradiation can be used for forming the silicon oxide film.
  • the film thickness of the tunnel oxide layer 104 is, for example, 0.5 nm or more and less than 5 nm.
  • the film thickness of the tunnel oxide layer 104 is, for example, 0.5 nm or more and less than 5 nm.
  • an n-type amorphous silicon layer 105 is formed on the lower surface of the tunnel oxide layer 104 (see step ST402 in FIG. 29).
  • An n-type amorphous silicon layer 105 is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 or PH 3 .
  • the film thickness of the n-type amorphous silicon layer 105 is, for example, 5 nm or more and less than 100 nm.
  • the thickness of the n-type amorphous silicon layer 105 is too thin, the field effect is weakened.
  • the electrical resistance in the tunnel junction layer increases, and the minority carrier repulsion effect decreases. Therefore, the characteristics of the n-type amorphous silicon layer 105 deteriorate.
  • the thermal strain increases. For this reason, it is known that the passivation effect of the silicon layer is reduced as compared with the case where the film thickness of the n-type amorphous silicon layer 105 is in an appropriate range.
  • the formed structure is introduced into a diffusion furnace, and the temperature is raised while flowing nitrogen gas. Then, heat treatment is performed by holding at a constant temperature for a certain time (see step ST403 in FIG. 29).
  • the n-type amorphous silicon layer 105 is crystallized to be changed into the n-type crystalline thin film silicon layer 106.
  • the film thickness of the n-type crystalline thin film silicon layer 106 is, for example, 5 nm or more and less than 100 nm.
  • the n-type dopant in the n-type amorphous silicon layer 105 is activated by the heat treatment. By doing so, the sheet resistance decreases.
  • the optimum annealing temperature varies depending on the phosphorus concentration contained in the silicon doped layer or the thickness of the silicon doped layer.
  • the peak temperature which is the highest temperature during the heat treatment of the n-type amorphous silicon layer 105, is 400 ° C. or higher and lower than 900 ° C.
  • the heat treatment temperature is low, the crystallization of the n-type amorphous silicon layer 105 is not sufficiently promoted. Therefore, the electric field effect on the back surface 100B is reduced, and a high passivation effect cannot be obtained. In addition, since the n-type amorphous silicon layer 105 has a high resistance, transport of majority carriers may be hindered. Note that when the heat treatment temperature exceeds 400 ° C., hydrogen begins to be desorbed from the n-type amorphous silicon layer 105, so that crystallization is promoted.
  • the n-type dopant in the n-type amorphous silicon layer 105 penetrates the tunnel oxide layer 104 and diffuses to the n-type single crystal silicon substrate 100 in a large amount by high-temperature heat treatment. Even if the n-type crystalline thin film silicon layer 106 is formed due to the structural breakdown of the oxide layer 104 or the diffusion of the dopant from the n-type amorphous silicon layer 105, the field effect is reduced. This is because it happens.
  • the n-type crystalline thin film silicon layer 106 may be formed by diffusing an n-type dopant after forming a non-doped (intrinsic) amorphous silicon layer.
  • a non-doped amorphous silicon layer is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 .
  • an n-type dopant is diffused into the non-doped amorphous silicon layer by gas phase reaction and thermal diffusion using POCl 3 or phosphorus ion implantation and thermal diffusion.
  • the n-type crystalline thin film silicon layer 106 may be formed in one step by a chemical vapor deposition method such as an LPCVD method using SiH 4 and PH 3 .
  • the n-type crystalline thin film silicon layer 106 may be formed at a temperature of 500 ° C. or higher, and heat treatment after the film formation may be performed as necessary.
  • the BSG film as the p-type impurity diffusion source 101 and the NSG film 102 formed on the light receiving surface 100A of the n-type single crystal silicon substrate 100 are completely removed using hydrofluoric acid.
  • This step can be performed before the heat treatment step of step ST403.
  • boron diffuses into the atmosphere from the BSG film as the p-type impurity diffusion source 101 during the heat treatment, so that the boron adheres to the n-type amorphous silicon layer 105 and further diffuses. Can be prevented.
  • the n-type dopant may diffuse from the n-type amorphous silicon layer 105 into the atmosphere and diffuse into the p-type impurity diffusion layer 103.
  • the NSG film 102 which is a cap layer is formed on the upper surface of the BSG film which is the p-type impurity diffusion source 101, and there is a possibility that boron may diffuse into the n-type amorphous silicon layer 105. Therefore, it is preferable to remove the BSG film and the NSG film 102 after the heat treatment in step ST403.
  • a protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST404 in FIG. 29).
  • the material of the protective film 107 is, for example, silicon nitride, silicon oxide, silicon nitride oxide, amorphous silicon, or microcrystalline silicon. Further, the protective film 107 may have a stacked structure of a plurality of films.
  • the protective film 107 preferably has a higher hardness than the n-type crystalline thin film silicon layer 106 which is a silicon doped layer. This is to protect the n-type crystalline thin film silicon layer 106 from physical damage due to contact with the plate or friction when electrodes are screen-printed on the protective film 107.
  • the hydrogen concentration in the protective film 107 is preferably higher than the hydrogen concentration in the n-type crystalline thin silicon layer 106. If the protective film 107 contains sufficient hydrogen, the hydrogen is desorbed during heat treatment and electrode firing. Then, dangling bonds in the formed n-type crystalline thin film silicon layer 106 and the interface between the tunnel oxide layer 104 and the single crystal silicon substrate 100 are terminated by hydrogen desorbed from the protective film 107. The This improves the passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104.
  • the film thickness of the protective film 107 is preferably, for example, 5 nm or more and less than 200 nm. If the film thickness of the protective film 107 is too thin, it cannot be prevented that the electrode penetrates the n-type crystalline thin film silicon layer 106 and erodes the n-type single crystal silicon substrate 100 during firing. If the thickness of the protective film 107 is too thin, sufficient hydrogen cannot be supplied from the protective film 107, so that the passivation effect of the n-type crystalline thin film silicon layer 106 is reduced.
  • the electrode is less likely to contact the n-type crystalline thin film silicon layer 106, and the contact resistance increases.
  • a dielectric layer 108 on the light receiving surface 100A side is formed on the upper surface of the p-type impurity diffusion layer 103 in the light receiving surface 100A of the n-type single crystal silicon substrate 100. Then, an antireflection film 109 is formed on the upper surface of the dielectric layer 108 (see step ST405 in FIG. 29).
  • the dielectric layer 108 for example, an oxide film can be used. Further, as the dielectric layer 108, for example, a dielectric layer such as an ALD or an aluminum oxide film formed by a CVD method can be used. In particular, since the aluminum oxide film has a negative fixed charge, it is known to exhibit an excellent passivation effect for the p-type impurity diffusion layer 103.
  • the film thickness of the dielectric layer 108 is, for example, 2 nm or more and less than 50 nm.
  • An antireflection film 109 is formed on the upper surface of the dielectric layer 108.
  • the antireflection film 109 for example, a silicon nitride film formed by a plasma CVD method is used.
  • the film thickness of the antireflection film 109 is designed to be an optimal film thickness for the solar spectrum, for example, about 30 nm or more and less than 80 nm according to the thickness of the dielectric layer 108.
  • the light-receiving surface electrode 110 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100. Further, the back electrode 111 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 (see step ST406 in FIG. 29). Thereby, the solar cell illustrated in FIGS. 1 and 2 is formed.
  • a paste containing metal particles and glass particles is first applied in a comb pattern on the antireflection film 109 and the protective film 107 by a coating method such as a screen printing method. Further, they are formed by drying them.
  • the content of the glass particles is 0.5 wt% or more and 10.0 wt% or less, preferably 1.0 wt% or more and 3.0 wt% based on the weight of the metal particles. % Or less.
  • the above paste is dried in a drying oven at 200 ° C. for about 10 minutes, for example. After drying, the light-receiving surface electrode 110 and the back surface electrode 111 are simultaneously heat-treated at a high temperature of about 800 ° C. and fired.
  • the glass particles etch the dielectric layer 108 on the light receiving surface 100A side and the antireflection film 109 by firing. Then, the p-type impurity diffusion layer 103 is exposed, and the light-receiving surface electrode 110 is electrically connected to the p-type impurity diffusion layer 103.
  • the glass particles etch the protective film 107 also on the back surface 100B side. Then, the n-type crystalline thin film silicon layer 106 is exposed, and the back electrode 111 is electrically connected to the n-type crystalline thin film silicon layer 106.
  • the impurity diffusion region 112 can be formed by using the ion implantation method, so that steps such as thermal diffusion or cleaning at the time of formation with the above-described dopant paste can be omitted.
  • a PSG film is formed on the back surface 100B of the n-type single crystal silicon substrate 100 by, for example, POCl3 or APCVD, and the impurity diffusion region 112 is formed thereon.
  • This method is a laser doping method in which impurities are diffused by locally heating the n-type single crystal silicon substrate 100.
  • FIG. 30 is a diagram illustrating the open-circuit voltage characteristics of the solar cell manufactured by the method as described above.
  • FIG. 30 as a comparative example of the solar cell C relating to the present embodiment, the solar cell A when the impurity diffusion region 112 which is the same as the configuration of the first embodiment is not formed, and the impurity diffusion region is n A solar cell B in the case where it is uniformly formed on the back surface 100B of the single crystal silicon substrate 100 of the type is simultaneously produced and evaluated.
  • Solar cell C related to the present embodiment had an open circuit voltage value of 726 mV.
  • the said value was the highest value in the solar cell A, the solar cell B, and the solar cell C.
  • the impurity diffusion region 112 similar to the configuration of the first embodiment is provided. A higher open-circuit voltage value was obtained as compared with the solar cell A when it was not formed.
  • the impurity diffusion region is formed uniformly on the back surface 100B of the n-type single crystal silicon substrate 100, Auger recombination increases in the impurity diffusion region. Therefore, it is preferable that the impurity diffusion region is selectively formed only directly below the back electrode 111. For these reasons, the highest open-circuit voltage value is obtained in the solar cell B including the impurity diffusion region 112.
  • the replacement may be made across a plurality of embodiments.
  • the configurations exemplified in different embodiments may be combined to produce the same effect.
  • the solar cell includes the tunnel oxide layer 104, the first conductive type semiconductor layer, the protective film 107, and the electrode.
  • the n-type crystalline thin film silicon layer 106 corresponds to the first conductive type semiconductor layer.
  • the back electrode 111 corresponds to an electrode.
  • the tunnel oxide layer 104 is formed on the semiconductor substrate, for example, on the back surface of the semiconductor substrate.
  • the n-type single crystal silicon substrate 100 corresponds to a semiconductor substrate.
  • the n-type crystalline thin film silicon layer 106 is formed on the tunnel oxide layer 104, for example, on the lower surface of the tunnel oxide layer 104.
  • the protective film 107 is formed on the n-type crystalline thin film silicon layer 106, for example, on the lower surface of the n-type crystalline thin film silicon layer 106.
  • the back electrode 111 is formed through the protective film 107 from above the protective film 107 and in contact with the n-type crystalline thin film silicon layer 106.
  • the back electrode 111 is a fired electrode containing glass particles.
  • the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100. Therefore, deterioration of characteristics such as erosion damage, printing damage, or current loss of the tunnel junction layer including the tunnel oxide layer 104 and the n-type crystalline thin film silicon layer 106 can be suppressed.
  • the protective film 107 suppresses the release of a large amount of hydrogen from the n-type crystalline thin film silicon layer 106, the tunnel oxide layer 104, and the single crystal silicon substrate 100 by heat treatment or baking. , The passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104 are suppressed from decreasing. By these, a solar cell with high productivity and high reliability can be manufactured.
  • the protective film 107 can withstand high temperature treatment, the manufacturing process is not limited.
  • the silver electrode having high reliability and low resistance can be formed by firing, the conversion efficiency of the solar cell can be improved.
  • the film thickness of the n-type crystalline thin film silicon layer 106 is 5 nm or more and less than 100 nm. According to such a configuration, since the n-type crystalline thin film silicon layer 106 has an appropriate film thickness, erosion of the electrode to the n-type single crystal silicon substrate 100 can be prevented. Further, the n-type crystalline thin film silicon layer 106 can obtain a high passivation effect.
  • the thickness of the protective film 107 is 5 nm or more and less than 200 nm. According to such a configuration, when the thickness of the protective film 107 is 5 nm or more, the electrode penetrates the n-type crystalline thin film silicon layer 106 and erodes into the n-type single crystal silicon substrate 100 during firing. This can be suppressed. Moreover, when the film thickness of the protective film 107 is less than 200 nm, an increase in series resistance can be suppressed without impairing the fire-through property.
  • the hardness of the protective film 107 is higher than the hardness of the n-type crystalline thin film silicon layer 106. According to such a configuration, when the electrode is screen-printed on the protective film 107, the n-type crystalline thin film silicon layer 106 can be protected from physical damage due to contact with the plate or friction. Therefore, characteristic deterioration of the n-type crystalline thin film silicon layer 106 can be suppressed.
  • the conductivity type of the n-type single crystal silicon substrate 100 is the first conductivity type.
  • the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100.
  • the tunnel oxide layer is formed on the n-type single crystal silicon substrate 100, for example, on the back surface 100B of the n-type single crystal silicon substrate 100.
  • 104 is formed.
  • a semiconductor layer of the first conductivity type is formed on the tunnel oxide layer 104, for example, on the lower surface of the tunnel oxide layer 104.
  • the n-type amorphous silicon layer 105 corresponds to the first conductivity type semiconductor layer at this stage, that is, before the heat treatment.
  • heat treatment is performed on the n-type amorphous silicon layer 105 at a temperature of 400 ° C. or higher.
  • the n-type crystalline thin film silicon layer 106 corresponds to the heat-treated first conductive type semiconductor layer. Then, a protective film 107 is formed on the heat-treated n-type crystalline thin film silicon layer 106, for example, on the lower surface of the n-type crystalline thin film silicon layer 106. Then, the back electrode 111 is printed on the protective film 107, for example, on the lower surface of the protective film 107. Then, the back electrode 111 and the n-type crystalline thin film silicon layer 106 are electrically connected by baking.
  • the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100. Therefore, deterioration of characteristics such as erosion damage, printing damage, or current loss of the tunnel junction layer including the tunnel oxide layer 104 and the n-type crystalline thin film silicon layer 106 can be suppressed.
  • the protective film 107 can withstand high temperature treatment, the manufacturing process is not limited.
  • the silver electrode having high reliability and low resistance can be formed by firing, the conversion efficiency of the solar cell can be improved.
  • the formation of the n-type amorphous silicon layer 105 on the tunnel oxide layer 104 is performed on the tunnel oxide layer 104.
  • an intrinsic semiconductor layer that is, a non-doped semiconductor layer is formed, and a heat treatment is performed on the non-doped semiconductor layer at a temperature of 400 ° C. or more to diffuse the first conductivity type dopant in the non-doped semiconductor layer.
  • the n-type amorphous silicon layer 105 is formed.
  • the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100.
  • the n-type amorphous silicon layer 105 is formed on the tunnel oxide layer 104, and at the same time, the n-type amorphous silicon is formed.
  • a heat treatment is performed on the silicon layer 105 at a temperature of 400 ° C. or higher. According to such a configuration, since the n-type crystalline thin film silicon layer 106 is formed in one step, the process becomes simple.
  • the back surface electrode 111 and the n-type amorphous silicon layer 105 are subjected to the peak temperature when the n-type amorphous silicon layer 105 is heat-treated and the firing.
  • the peak temperature when electrically connecting the n-type crystalline thin film silicon layer 106 is higher than the temperature when forming the protective film 107.
  • hydrogen contained in the protective film 107 diffuses into the n-type crystalline thin film silicon layer 106 during the heat treatment and the electrode firing. The passivation effect is improved.
  • the hydrogen concentration in the protective film 107 is higher than the hydrogen concentration in the heat-treated n-type crystalline thin film silicon layer 106.
  • the protective film 107 contains sufficient hydrogen, the hydrogen desorbed from the protective film 107 is formed into an n-type crystalline thin film silicon layer 106 formed by heat treatment or the like. Terminate the dangling bond inside. Therefore, the passivation effect of the n-type crystalline thin film silicon layer 106 is improved. Further, it is possible to suppress a large amount of hydrogen from being released from the n-type crystalline thin film silicon layer 106 in the baking step.
  • each component in the embodiment described above is a conceptual unit, and one component is composed of a plurality of structures within the scope of the technique disclosed in this specification.
  • one component corresponds to a part of a structure and a case where a plurality of components are provided in one structure are included.
  • each component in the embodiment described above includes a structure having another structure or shape as long as the same function is exhibited.
  • the material when a material name or the like is described without being particularly specified, the material contains other additives, for example, an alloy or the like unless a contradiction arises. Shall be included.

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Abstract

The art disclosed in the present description relates to the art capable of suppressing damages due to firing, while being provided with a fired electrode. A solar cell relating to the present art is provided with: a tunnel oxide layer (104) formed on a semiconductor substrate (100); a first conductivity-type semiconductor layer (106) formed on the tunnel oxide layer (104); a protection film (107) formed on the semiconductor layer (106); and an electrode (111), which penetrates the protection film (107) from above the protection film (107), and which is formed in contact with the semiconductor layer (106). The electrode (111) is a fired electrode containing glass particles.

Description

太陽電池、および、太陽電池の製造方法Solar cell and method for manufacturing solar cell
　本願明細書に開示される技術は、太陽電池、および、太陽電池の製造方法に関するものである。 The technology disclosed in this specification relates to a solar cell and a method for manufacturing the solar cell.
　結晶シリコンが用いられた太陽電池のパッシベーション技術として、半導体基板の上面に非常に薄い酸化物の層、すなわち、トンネル酸化物層を形成し、さらに、トンネル酸化物層の上面にシリコンドープ層を形成する方法がある。 As a passivation technology for solar cells using crystalline silicon, a very thin oxide layer, that is, a tunnel oxide layer is formed on the top surface of a semiconductor substrate, and a silicon doped layer is formed on the top surface of the tunnel oxide layer. There is a way to do it.
　上記のように、トンネル酸化物層とシリコンドープ層とから形成されたトンネル接合層を用いる方法では、トンネル酸化物層が形成するバンド障壁、および、シリコンドープ層に起因する電界効果によって少数キャリアを追い返し、再結合を抑制する。これによって、たとえば、７００ｍＶを超える高い開放電圧を得ることができる。 As described above, in the method using the tunnel junction layer formed of the tunnel oxide layer and the silicon doped layer, minority carriers are generated by the band barrier formed by the tunnel oxide layer and the electric field effect caused by the silicon doped layer. Turn back and suppress recombination. Thereby, for example, a high open circuit voltage exceeding 700 mV can be obtained.
　一方で、トンネル効果によって多数キャリアの輸送はスムーズに行われる。そのため、直列抵抗を増大させずに、高い開放電圧と大きい曲線因子とを両立させることができる。ここで、曲線因子とは、最適動作点での出力（最大出力）を、開放電圧と短絡電流との積で割った値である。 On the other hand, the majority carrier is transported smoothly by the tunnel effect. Therefore, it is possible to achieve both a high open-circuit voltage and a large fill factor without increasing the series resistance. Here, the fill factor is a value obtained by dividing the output (maximum output) at the optimum operating point by the product of the open circuit voltage and the short circuit current.
　たとえば、非特許文献１に開示された方法では、ｎ型のシリコン基板の裏面にトンネル酸化物層が形成され、さらに、トンネル酸化物層の裏面にリンドープシリコン層が形成される。そして、リンドープシリコン層が形成された後、６００℃以上、かつ、１０００℃未満で熱処理が行われる。その後、リンドープシリコン層の下面に直接、裏面電極が全面形成される。電極形成方法としては、Ｔｉ、Ｐｄ、および、Ａｇからなるシード層を熱蒸着した後、Ａｇめっきを行う方法が用いられる。 For example, in the method disclosed in Non-Patent Document 1, a tunnel oxide layer is formed on the back surface of an n-type silicon substrate, and a phosphorus-doped silicon layer is further formed on the back surface of the tunnel oxide layer. And after a phosphorus dope silicon layer is formed, heat processing is performed at 600 degreeC or more and less than 1000 degreeC. Thereafter, a back electrode is formed entirely on the lower surface of the phosphorus-doped silicon layer. As an electrode forming method, a method of performing Ag plating after thermally depositing a seed layer made of Ti, Pd, and Ag is used.
　また、たとえば、特許文献１に開示された方法では、トンネル酸化物層である酸化シリコン層の上面に半導体層が形成され、さらに、半導体層の上面に透明導電膜が形成される。そして、透明導電膜の上面にくし型の電極が形成される。 For example, in the method disclosed in Patent Document 1, a semiconductor layer is formed on the upper surface of a silicon oxide layer that is a tunnel oxide layer, and a transparent conductive film is further formed on the upper surface of the semiconductor layer. Then, a comb-shaped electrode is formed on the upper surface of the transparent conductive film.
　透明導電膜は、シリコンドープ層である半導体層を電極形成ダメージから守る膜である。また、透明導電膜は、導電性を有するため、絶縁層のように開口処理を必要とせずに、電極をコンタクトさせることができる。 The transparent conductive film is a film that protects the semiconductor layer, which is a silicon-doped layer, from electrode formation damage. In addition, since the transparent conductive film has conductivity, the electrode can be contacted without requiring an opening treatment unlike the insulating layer.
特開２０１２－６００８０号公報JP 2012-60080 A
　上記の非特許文献１、または、上記の特許文献１では、光電子に起因して生じる光電流を収集するため、トンネル接合層におけるシリコンドープ層に対して蒸着またはめっきによって電極を形成したり、シリコンドープ層に対して透明導電膜を挟んで電極とコンタクトさせたりする。 In Non-Patent Document 1 or Patent Document 1 described above, in order to collect photocurrent caused by photoelectrons, an electrode is formed by vapor deposition or plating on a silicon doped layer in a tunnel junction layer, or silicon The doped layer is brought into contact with the electrode with a transparent conductive film interposed therebetween.
　しかしながら、装置の量産性を考慮すると、高温焼成プロセスを用いる焼成銀を印刷して電極コンタクトを形成する手法が、簡便で、かつ、生産性が高い。さらに、高温焼成プロセスを用いれば、焼成用銀ペーストは電極を低抵抗化ができ、コンタクト性もよく、さらに、信頼性も高い。 However, in consideration of the mass productivity of the apparatus, the method of forming electrode contacts by printing baked silver using a high temperature baking process is simple and highly productive. Furthermore, if a high-temperature firing process is used, the firing silver paste can reduce the resistance of the electrode, has good contact properties, and has high reliability.
　一方で、焼成によって電極を形成する場合には、焼成銀の印刷に起因する物理的ダメージ、焼成プロセスに起因する熱ダメージ、または、焼成銀の浸食などによって、トンネル接合層の特性劣化が生じる場合がある。 On the other hand, when the electrodes are formed by firing, characteristics of the tunnel junction layer may deteriorate due to physical damage due to printing of the fired silver, thermal damage due to the firing process, or erosion of the fired silver. There is.
　焼成に起因するトンネル接合層の特性劣化については、トンネル接合層に接触する電極を形成する場合であっても、トンネル接合層に接触しない電極を形成する場合であっても、焼成時の高温過程によってトンネル接合層の特性劣化が生じ得る。 Regarding the deterioration of characteristics of the tunnel junction layer due to firing, whether the electrode that contacts the tunnel junction layer is formed or the electrode that does not contact the tunnel junction layer is formed, the high temperature process during firing As a result, the characteristics of the tunnel junction layer may deteriorate.
　また、焼成に起因するトンネル接合層の特性劣化は、シリコンドープ層の上面に直接電極を形成する場合には、ファイアースルーによって電極が、たとえば、厚さが１００ｎｍ以下であるシリコンドープ層を突き破って半導体基板を浸食することによって生じる。 In addition, when the electrode is formed directly on the upper surface of the silicon doped layer, the deterioration of the characteristics of the tunnel junction layer due to firing is caused by the fire-through electrode breaking through the silicon doped layer having a thickness of 100 nm or less, for example. This is caused by erosion of the semiconductor substrate.
　これを防ぐために、たとえば、焼成温度の低温化、または、低温焼結銀を用いるなどの手法が考えられるが、これらの場合には、銀電極の高抵抗化、または、電気的コンタクト性の悪化などを招く場合がある。 In order to prevent this, for example, methods such as lowering the firing temperature or using low-temperature sintered silver are conceivable. In these cases, however, the resistance of the silver electrode is increased or the electrical contact property is deteriorated. May be invited.
　また、電極印刷時の摩擦などの物理ダメージが、シリコンドープ層を傷つけることも問題である。 Also, physical damage such as friction during electrode printing damages the silicon dope layer.
　また、特許文献１に開示されるように、シリコンドープ層と電極との間に透明導電膜が挟まれる構造であれば、上記のような電極の基板浸食、および、印刷時の物理ダメージは抑制することができると考えられる。 In addition, as disclosed in Patent Document 1, if the transparent conductive film is sandwiched between the silicon doped layer and the electrode, the substrate erosion of the electrode as described above and physical damage during printing are suppressed. I think it can be done.
　しかしながら、透明導電膜は、キャリア濃度が高く、かつ、光吸収が大きい。そのため、電流ロスが増加する場合がある。また、透明導電膜は、焼成などの高温処理に対する耐性に乏しい。そのため、焼成による電気特性、または、構造の劣化が生じる。 However, the transparent conductive film has a high carrier concentration and high light absorption. As a result, current loss may increase. In addition, the transparent conductive film has poor resistance to high-temperature processing such as baking. Therefore, electrical characteristics or structural deterioration due to firing occurs.
　このため、透明導電膜を作製するプロセスは限定されてしまい、簡易で、量産性および信頼性の高いプロセスを選択することができないという問題がある。 For this reason, the process for producing the transparent conductive film is limited, and there is a problem that it is not possible to select a simple, mass-productive and highly reliable process.
　本願明細書に開示される技術は、以上に記載されたような問題を解決するためになされたものであり、焼成電極を備えつつ、焼成に起因するダメージを抑制することができる技術に関するものである。 The technology disclosed in the specification of the present application has been made in order to solve the problems described above, and relates to a technology capable of suppressing damage caused by firing while being provided with a fired electrode. is there.
　本願明細書に開示される技術の一の態様は、半導体基板上に形成されるトンネル酸化物層と、前記トンネル酸化物層上に形成される第１の導電型の半導体層と、前記半導体層上に形成される保護膜と、前記保護膜上から前記保護膜を貫通し、かつ、前記半導体層に接触して形成される電極とを備え、前記電極は、ガラス粒子を含む焼成電極である。 One aspect of the technology disclosed in this specification is a tunnel oxide layer formed on a semiconductor substrate, a semiconductor layer of a first conductivity type formed on the tunnel oxide layer, and the semiconductor layer A protective film formed on the protective film; and an electrode formed through the protective film and in contact with the semiconductor layer. The electrode is a fired electrode including glass particles. .
　また、本願明細書に開示される技術の別の態様は、半導体基板上に、トンネル酸化物層を形成し、前記トンネル酸化物層上に、第１の導電型の半導体層を形成し、前記半導体層に対し、４００℃以上の温度で熱処理を行い、熱処理された前記半導体層上に、保護膜を形成し、前記保護膜上に、電極を印刷し、焼成によって、前記電極と前記半導体層とを電気的に接続させる。 According to another aspect of the technology disclosed in this specification, a tunnel oxide layer is formed on a semiconductor substrate, a semiconductor layer of a first conductivity type is formed on the tunnel oxide layer, and A heat treatment is performed on the semiconductor layer at a temperature of 400 ° C. or more, a protective film is formed on the heat-treated semiconductor layer, an electrode is printed on the protective film, and the electrode and the semiconductor layer are baked. Are electrically connected to each other.
　本願明細書に開示される技術の一の態様は、半導体基板上に形成されるトンネル酸化物層と、前記トンネル酸化物層上に形成される第１の導電型の半導体層と、前記半導体層上に形成される保護膜と、前記保護膜上から前記保護膜を貫通し、かつ、前記半導体層に接触して形成される電極とを備え、前記電極は、ガラス粒子を含む焼成電極である。このような構成によれば、焼成によって電極を形成する場合において、半導体層上に形成された保護膜が、焼成される電極によって半導体層が突き破られること、さらには、半導体層を突き破った電極が半導体基板にまで到達することを防ぐことができる。したがって、トンネル酸化物層、および、半導体層を含むトンネル接合層の浸食ダメージ、印刷ダメージ、または、電流ロスなどの特性低下を抑制することができる。また、保護膜が、熱処理、または、焼成によって半導体層から多量の水素が脱離することを抑制することによって、半導体層のパッシベーション効果が低下することを抑制する。これらによって、量産性、および、信頼性の高い太陽電池を製造することができる。 One aspect of the technology disclosed in this specification is a tunnel oxide layer formed on a semiconductor substrate, a semiconductor layer of a first conductivity type formed on the tunnel oxide layer, and the semiconductor layer A protective film formed on the protective film; and an electrode formed through the protective film and in contact with the semiconductor layer. The electrode is a fired electrode including glass particles. . According to such a configuration, when the electrode is formed by baking, the protective film formed on the semiconductor layer is pierced by the electrode to be baked, and further, the electrode that has broken through the semiconductor layer Can be prevented from reaching the semiconductor substrate. Therefore, characteristic degradation such as erosion damage, printing damage, or current loss of the tunnel oxide layer and the tunnel junction layer including the semiconductor layer can be suppressed. In addition, the protective film suppresses a large amount of hydrogen from being desorbed from the semiconductor layer by heat treatment or baking, thereby suppressing a decrease in the passivation effect of the semiconductor layer. By these, a solar cell with high productivity and high reliability can be manufactured.
　また、本願明細書に開示される技術の別の態様は、半導体基板上に、トンネル酸化物層を形成し、前記トンネル酸化物層上に、第１の導電型の半導体層を形成し、前記半導体層に対し、４００℃以上の温度で熱処理を行い、熱処理された前記半導体層上に、保護膜を形成し、前記保護膜上に、電極を印刷し、焼成によって、前記電極と前記半導体層とを電気的に接続させる。このような構成によれば、焼成によって電極を形成する場合において、半導体層上に形成された保護膜が、焼成される電極によって半導体層が突き破られること、さらには、半導体層を突き破った電極が半導体基板にまで到達することを防ぐことができる。また、保護膜が高温処理にも耐えうるため、製造プロセスが限定されない。 According to another aspect of the technology disclosed in this specification, a tunnel oxide layer is formed on a semiconductor substrate, a semiconductor layer of a first conductivity type is formed on the tunnel oxide layer, and A heat treatment is performed on the semiconductor layer at a temperature of 400 ° C. or more, a protective film is formed on the heat-treated semiconductor layer, an electrode is printed on the protective film, and the electrode and the semiconductor layer are baked. Are electrically connected to each other. According to such a configuration, when the electrode is formed by baking, the protective film formed on the semiconductor layer is pierced by the electrode to be baked, and further, the electrode that has broken through the semiconductor layer Can be prevented from reaching the semiconductor substrate. Further, since the protective film can withstand high temperature processing, the manufacturing process is not limited.
　本願明細書に開示される技術に関する目的と、特徴と、局面と、利点とは、以下に示される詳細な説明と添付図面とによって、さらに明白となる。 The objectives, features, aspects, and advantages of the technology disclosed in the present specification will become more apparent from the detailed description and the accompanying drawings shown below.
実施の形態に関する太陽電池の製造方法で形成された、太陽電池の構造を概略的に例示する平面図である。It is a top view which illustrates schematically the structure of the solar cell formed with the manufacturing method of the solar cell regarding embodiment. 図１におけるＡ－Ａ’断面図である。FIG. 2 is a cross-sectional view taken along line A-A ′ in FIG. 1. 実施の形態に関する、太陽電池の製造方法を例示するフローチャートである。It is a flowchart which illustrates the manufacturing method of the solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 保護膜を形成しない場合、および、保護膜を形成する場合それぞれについての、ｎ型の非晶質シリコン層の熱処理温度と、開放電圧の推定値［ｍＶ］との関係を例示する図である。It is a figure which illustrates the relationship between the heat processing temperature of an n-type amorphous silicon layer, and the estimated value [mV] of an open circuit voltage about the case where a protective film is not formed and the case where a protective film is formed, respectively. 実施の形態に関する太陽電池の製造方法で形成された、太陽電池の構造を概略的に例示する平面図である。It is a top view which illustrates schematically the structure of the solar cell formed with the manufacturing method of the solar cell regarding embodiment. 図１１におけるＢ－Ｂ’断面図である。FIG. 12 is a B-B ′ sectional view in FIG. 11. 実施の形態に関する、太陽電池の製造方法を例示するフローチャートである。It is a flowchart which illustrates the manufacturing method of the solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する太陽電池の製造方法で形成された、太陽電池の構造を概略的に例示する断面図である。It is sectional drawing which illustrates schematically the structure of the solar cell formed with the manufacturing method of the solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示するフローチャートである。It is a flowchart which illustrates the manufacturing method of the solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示する太陽電池の断面図である。It is sectional drawing of the solar cell which illustrates the manufacturing method of a solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法で形成された、太陽電池の構造を概略的を例示する断面図である。It is sectional drawing which illustrates schematically the structure of the solar cell formed with the manufacturing method of the solar cell regarding embodiment. 実施の形態に関する、太陽電池の製造方法を例示するフローチャートである。It is a flowchart which illustrates the manufacturing method of the solar cell regarding embodiment. 製造された太陽電池の開放電圧特性を例示する図である。It is a figure which illustrates the open circuit voltage characteristic of the manufactured solar cell.
　以下、添付される図面を参照しながら実施の形態について説明する。 Hereinafter, embodiments will be described with reference to the accompanying drawings.
　なお、図面は概略的に示されるものであり、異なる図面にそれぞれ示される画像の大きさと位置との相互関係は、必ずしも正確に記載されるものではなく、適宜変更され得るものである。 Note that the drawings are schematically shown, and the mutual relationship between the size and the position of images shown in different drawings is not necessarily described accurately, and can be changed as appropriate.
　また、以下に示される説明では、同様の構成要素には同じ符号を付して図示し、それらの名称と機能とについても同様のものとする。したがって、それらについての詳細な説明を省略する場合がある。 In the following description, the same components are denoted by the same reference numerals, and the names and functions thereof are also the same. Therefore, detailed description thereof may be omitted.
　また、以下に記載される説明において、「上」、「下」、「側」、「底」、「表」または「裏」などの特定の位置と方向とを意味する用語が用いられる場合があっても、これらの用語は、実施の形態の内容を理解することを容易にするために便宜上用いられるものであり、実際に実施される際の方向とは関係しないものである。 In the description described below, terms that mean a specific position and direction such as “top”, “bottom”, “side”, “bottom”, “front” or “back” may be used. Even if it exists, these terms are used for convenience in order to make it easy to understand the contents of the embodiment, and are not related to the direction in actual implementation.
　＜第１の実施の形態＞
　以下、本実施の形態に関する太陽電池、および、太陽電池の製造方法について説明する。 <First Embodiment>
Hereinafter, the solar cell regarding this Embodiment and the manufacturing method of a solar cell are demonstrated.
　＜太陽電池の構成について＞
　図１は、本実施の形態に関する太陽電池の製造方法で形成された、太陽電池の構造を概略的に例示する平面図である。また、図２は、図１におけるＡ－Ａ’断面図である。 <About solar cell configuration>
FIG. 1 is a plan view schematically illustrating the structure of a solar cell formed by the method for manufacturing a solar cell according to the present embodiment. FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG.
　全体の説明に先立ち、まず、本実施の形態に関する太陽電池の製造方法の要旨を説明する。本実施の形態に関する太陽電池の製造方法では、図１、および、図２に例示されるように、結晶系の半導体基板として受光面１００Ａと裏面１００Ｂとを有するｎ型の単結晶シリコン基板１００を用いる。 Prior to the overall description, first, the gist of the solar cell manufacturing method according to the present embodiment will be described. In the solar cell manufacturing method according to the present embodiment, as illustrated in FIG. 1 and FIG. 2, an n-type single crystal silicon substrate 100 having a light receiving surface 100A and a back surface 100B as a crystalline semiconductor substrate is used. Use.
　そして、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに、トンネル酸化物層１０４を形成する。次に、トンネル酸化物層１０４の下面に、ｎ型のドーパントを含むｎ型の非晶質シリコン層１０５を形成する。 Then, a tunnel oxide layer 104 is formed on the back surface 100B of the n-type single crystal silicon substrate 100. Next, an n-type amorphous silicon layer 105 containing an n-type dopant is formed on the lower surface of the tunnel oxide layer 104.
　その後、熱処理を行うことによって、シリコンドープ層としてのｎ型の非晶質シリコン層１０５中に含まれるｎ型のドーパントを活性化するとともに、ｎ型の非晶質シリコン層１０５の一部または全体を結晶化させることによって、ｎ型の結晶系薄膜シリコン層１０６を形成する。トンネル酸化物層１０４とｎ型の結晶系薄膜シリコン層１０６との積層構造を備えることによって、少数キャリアの再結合を抑制し、かつ、多数キャリアの収集効率を高めることができる。 Thereafter, heat treatment is performed to activate the n-type dopant contained in the n-type amorphous silicon layer 105 as the silicon doped layer, and a part or the whole of the n-type amorphous silicon layer 105 is activated. Is crystallized to form an n-type crystalline thin film silicon layer 106. By providing a stacked structure of the tunnel oxide layer 104 and the n-type crystalline thin film silicon layer 106, recombination of minority carriers can be suppressed and the collection efficiency of majority carriers can be increased.
　この後、ｎ型の結晶系薄膜シリコン層１０６の下面に、保護膜１０７としての窒化シリコン層を形成する。そして、保護膜１０７の下面から裏面電極１１１を印刷し、さらに、焼成によって裏面電極１１１を保護膜１０７にファイアースルーさせることによって、裏面電極１１１の、ｎ型の結晶系薄膜シリコン層１０６に対するコンタクトを形成する。 Thereafter, a silicon nitride layer as a protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106. Then, the back electrode 111 is printed from the lower surface of the protective film 107, and further, the back electrode 111 is fired through the protective film 107 by firing, whereby the contact of the back electrode 111 with the n-type crystalline thin film silicon layer 106 is made. Form.
　ｎ型の単結晶シリコン基板１００の受光面１００Ａ側には、グリッド電極１１０Ｇとバス電極１１０Ｂとを備える受光面電極１１０が形成される。一方、ｎ型の単結晶シリコン基板１００の裏面１００Ｂ側には、グリッド電極１１０Ｇとバス電極１１０Ｂとを備える裏面電極１１１が形成される。 On the light receiving surface 100A side of the n-type single crystal silicon substrate 100, a light receiving surface electrode 110 including a grid electrode 110G and a bus electrode 110B is formed. On the other hand, on the back surface 100B side of the n-type single crystal silicon substrate 100, a back electrode 111 including a grid electrode 110G and a bus electrode 110B is formed.
　本実施の形態に関する太陽電池の製造方法では、ｎ型の結晶系薄膜シリコン層１０６の下面に保護膜１０７を形成する。そして、保護膜１０７の下面から裏面電極１１１を印刷し、さらに、裏面電極１１１を焼成する。 In the solar cell manufacturing method according to this embodiment, the protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106. Then, the back electrode 111 is printed from the lower surface of the protective film 107, and the back electrode 111 is baked.
　このように形成することによって、電極の印刷、および、電極の焼成に起因して、トンネル酸化物層１０４の劣化、および、ｎ型の結晶系薄膜シリコン層１０６の劣化を防ぐことができる。そのため、高い開放電圧を維持することができ、太陽電池の特性を維持することができる。 By forming in this way, it is possible to prevent deterioration of the tunnel oxide layer 104 and deterioration of the n-type crystalline thin film silicon layer 106 due to electrode printing and electrode firing. Therefore, a high open circuit voltage can be maintained and the characteristics of the solar cell can be maintained.
　これに対し、ｎ型の結晶系薄膜シリコン層に直接電極を印刷し、さらに、当該電極を焼成する場合には、電極が、ファイアースルーによってトンネル酸化物層、および、ｎ型の結晶系薄膜シリコン層を突き破ってしまう。そのため、電極が、トンネル酸化物層、さらには、シリコン基板に接触してしまい、再結合の増加によって開放電圧が低下する。 On the other hand, when an electrode is directly printed on an n-type crystalline thin film silicon layer and the electrode is fired, the electrode is formed by a fire-through tunnel oxide layer and an n-type crystalline thin film silicon. Break through the layers. Therefore, the electrode comes into contact with the tunnel oxide layer and further the silicon substrate, and the open circuit voltage is lowered due to the increase of recombination.
　また、ｎ型の結晶系薄膜シリコン層に直接電極を印刷した場合には、印刷版との接触、または、摩擦などによってｎ型の結晶系薄膜シリコン層が傷ついてしまい、パッシベーション効果が低下するおそれがある。 In addition, when an electrode is printed directly on an n-type crystalline thin film silicon layer, the n-type crystalline thin film silicon layer may be damaged by contact with the printing plate or friction, and the passivation effect may be reduced. There is.
　＜太陽電池の製造方法について＞
　以下、図３から図９を参照しつつ、本実施の形態に関する太陽電池の製造方法を詳細に説明する。ここで、図３は、本実施の形態に関する太陽電池の製造方法を例示するフローチャートである。また、図４から図９は、本実施の形態に関する太陽電池の製造方法を例示する太陽電池の断面図である。 <About solar cell manufacturing method>
Hereinafter, the solar cell manufacturing method according to the present embodiment will be described in detail with reference to FIGS. 3 to 9. Here, FIG. 3 is a flowchart illustrating a method for manufacturing a solar cell according to this embodiment. 4 to 9 are cross-sectional views of the solar cell illustrating the solar cell manufacturing method according to this embodiment.
　まず、図４に例示されるように、ｎ型の単結晶シリコン基板１００を用意する。ｎ型の単結晶シリコン基板１００は、シリコンインゴットをワイヤーソーなどによる機械的切断法を用いてカット、および、スライスすることによって製造される。そのため、表面には汚染、または、ダメージが残存する場合がある。 First, as illustrated in FIG. 4, an n-type single crystal silicon substrate 100 is prepared. The n-type single crystal silicon substrate 100 is manufactured by cutting and slicing a silicon ingot using a mechanical cutting method such as a wire saw. Therefore, contamination or damage may remain on the surface.
　そこで、水酸化ナトリウム溶液などのアルカリ溶液を用いたウェットエッチングプロセスを実施することによって、ｎ型の単結晶シリコン基板１００の表面に、テクスチャ構造と呼ばれる微小な凹凸構造を形成する。テクスチャ構造の形成には、アルカリ溶液、および、添加剤を用いる。 Therefore, a fine concavo-convex structure called a texture structure is formed on the surface of the n-type single crystal silicon substrate 100 by performing a wet etching process using an alkali solution such as a sodium hydroxide solution. An alkaline solution and an additive are used for forming the texture structure.
　ｎ型の単結晶シリコン基板１００の表面における微小な凹凸構造によって、ｎ型の単結晶シリコン基板１００に入射する光が、基板表面で多重反射する。したがって、光の反射損失を低減することができる。加えて、光路長の増加によって光吸収が増大する。その結果、短絡電流の向上が見込める。なお、簡単のため、図面にはテクスチャ構造は示されない。 The light incident on the n-type single crystal silicon substrate 100 undergoes multiple reflections on the substrate surface due to the minute uneven structure on the surface of the n-type single crystal silicon substrate 100. Therefore, the reflection loss of light can be reduced. In addition, light absorption increases with an increase in optical path length. As a result, an improvement in short circuit current can be expected. For simplicity, the texture structure is not shown in the drawing.
　テクスチャ構造を形成した後に、たとえば、過酸化水素をベースに、アルカリまたは酸を加えた濃厚薬液を高温で用いる洗浄方法であるＲＣＡ洗浄、ＳＰＭ（Ｓｕｌｆｕｒｉｃ　Ａｃｉｄ　Ｈｙｄｒｏｇｅｎ　Ｐｅｒｏｘｉｄｅ　Ｍｉｘｔｕｒｅ）洗浄、または、ＨＰＭ（Ｈｙｄｒｏｃｈｌｏｒｉｃ　Ａｃｉｄ　Ｈｙｄｒｏｇｅｎ　Ｐｅｒｏｘｉｄｅ　Ｍｉｘｔｕｒｅ）洗浄などを行い、ｎ型の単結晶シリコン基板１００の表面に付着している有機物、または、金属汚染などによる付着物を取り除く。 After the texture structure is formed, for example, RCA cleaning, SPM (Surfuric Acid Hydroxide Mixture) cleaning, or HPM (Hydrochloric) cleaning method using a concentrated chemical solution containing hydrogen peroxide as a base and an alkali or acid added at a high temperature. (Acid Hydrogen Peroxide Mixture) cleaning is performed to remove organic substances adhering to the surface of the n-type single crystal silicon substrate 100 or adhering substances due to metal contamination.
　次に、図４に例示されるように、ｎ型の単結晶シリコン基板１００の受光面１００Ａに、ｐ型の不純物拡散層１０３を形成する（図３におけるステップＳＴ１００を参照）。 Next, as illustrated in FIG. 4, a p-type impurity diffusion layer 103 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100 (see step ST100 in FIG. 3).
　ｎ型の単結晶シリコン基板１００上に、たとえば、ＢＢｒ３を用いた気相反応、または、Ｂ２Ｈ６を用いた大気圧化学気相堆積（ａｔｍｏｓｐｈｅｒｉｃ　ｐｒｅｓｓｕｒｅ　ｃｈｅｍｉｃａｌ　ｖａｐｏｒ　ｄｅｐｏｓｉｔｉｏｎ、すなわち、ＡＰＣＶＤ）法などの気相法によって、ｐ型の不純物拡散源１０１としてのボロンドープシリコンガラス（Ｂｏｒｏｎ　Ｓｉｌｉｃａｔｅ　Ｇｌａｓｓ：ＢＳＧ）膜を形成する。その後、拡散炉中でボロンを熱拡散することによって、ｐ型の不純物拡散層１０３を形成する。 On the n-type single crystal silicon substrate 100, for example, a gas phase reaction using BBr 3 or an atmospheric pressure chemical vapor deposition (ie, APCVD) method using B 2 H 6 is used. A boron-doped silicon glass (BSG) film as the p-type impurity diffusion source 101 is formed by the vapor phase method. Thereafter, the p-type impurity diffusion layer 103 is formed by thermally diffusing boron in a diffusion furnace.
　なお、イオン注入によってｎ型の単結晶シリコン基板１００の表面にボロンを打ち込み、その後、拡散炉中でボロンを熱拡散することによって、ｐ型の不純物拡散層１０３を形成してもよい。 Note that the p-type impurity diffusion layer 103 may be formed by implanting boron into the surface of the n-type single crystal silicon substrate 100 by ion implantation and then thermally diffusing boron in a diffusion furnace.
　この場合、形成されるｐ型の不純物拡散層１０３のシート抵抗は、たとえば、５０Ω／□以上、かつ、１５０Ω／□未満とすることができる。シート抵抗は、拡散層内での少数キャリアの再結合、光吸収、および、電極とのコンタクト抵抗などを考慮して決定する。 In this case, the sheet resistance of the formed p-type impurity diffusion layer 103 can be, for example, 50Ω / □ or more and less than 150Ω / □. The sheet resistance is determined in consideration of recombination of minority carriers in the diffusion layer, light absorption, contact resistance with the electrode, and the like.
　ＢＳＧ膜からなるｐ型の不純物拡散源１０１を形成する際にＡＰＣＶＤを用いる場合には、ＢＳＧ膜をｎ型の単結晶シリコン基板１００の受光面１００Ａのみに形成することができる。 When APCVD is used to form the p-type impurity diffusion source 101 made of a BSG film, the BSG film can be formed only on the light-receiving surface 100A of the n-type single crystal silicon substrate 100.
　ただし、ｎ型の単結晶シリコン基板１００の端面、および、ｎ型の単結晶シリコン基板１００の裏面にもＢＳＧ膜が僅かに回り込むため、ＢＳＧ膜を形成した後に、たとえば、０．５％以上、かつ、１．０％以下のフッ酸で、ｎ型の単結晶シリコン基板１００の端面、および、ｎ型の単結晶シリコン基板１００の裏面に回り込んだ分のＢＳＧ膜を除去することができる。 However, since the BSG film slightly wraps around the end surface of the n-type single crystal silicon substrate 100 and the back surface of the n-type single crystal silicon substrate 100, for example, 0.5% or more after forming the BSG film, In addition, the BSG film that wraps around the end surface of the n-type single crystal silicon substrate 100 and the back surface of the n-type single crystal silicon substrate 100 can be removed with 1.0% or less hydrofluoric acid.
　ここで、図４に例示されるように、ｐ型の不純物拡散源１０１を形成した後には、誘電体膜としてノンドープシリコンガラス（Ｎｏｎ　ｄｏｐｅｄ　Ｓｉｌｉｃａｔｅ　Ｇｌａｓｓ：ＮＳＧ）膜１０２を形成することが好ましい。 Here, as illustrated in FIG. 4, after forming the p-type impurity diffusion source 101, it is preferable to form a non-doped silicon glass (NSG) film 102 as a dielectric film.
　ＮＳＧ膜１０２がキャップ層の働きをして、ＢＳＧ膜からなるｐ型の不純物拡散源１０１中のボロンが気相中に脱離することを防ぐ。そのため、ボロンを効率的に拡散することができる。 The NSG film 102 functions as a cap layer to prevent boron in the p-type impurity diffusion source 101 made of the BSG film from desorbing into the gas phase. Therefore, boron can be diffused efficiently.
　また、ＮＳＧ膜１０２は、後でｎ型の単結晶シリコン基板１００の裏面に形成するｎ型の非晶質シリコン層１０５のドーパント活性化のための熱処理時に、拡散バリア層としても働く。 The NSG film 102 also functions as a diffusion barrier layer during heat treatment for dopant activation of the n-type amorphous silicon layer 105 to be formed later on the back surface of the n-type single crystal silicon substrate 100.
　ここで、ｐ型の不純物拡散源１０１であるＢＳＧ膜の膜厚は、たとえば、３０ｎｍ以上、かつ、１５０ｎｍ未満である。ｐ型の不純物拡散源１０１であるＢＳＧ膜の膜厚が薄すぎると、拡散源としての役割を果たすことができなくなる。一方で、ｐ型の不純物拡散源１０１であるＢＳＧ膜の膜厚が厚すぎると、ＢＳＧ膜の形成、および、ＢＳＧ膜の除去が困難となる。 Here, the thickness of the BSG film which is the p-type impurity diffusion source 101 is, for example, 30 nm or more and less than 150 nm. If the thickness of the BSG film which is the p-type impurity diffusion source 101 is too thin, it cannot function as a diffusion source. On the other hand, if the thickness of the BSG film that is the p-type impurity diffusion source 101 is too thick, it becomes difficult to form the BSG film and remove the BSG film.
　また、ＮＳＧ膜１０２の膜厚は、たとえば、１００ｎｍ以上、かつ、５００ｎｍ未満である。ＮＳＧ膜１０２の膜厚が薄すぎると、キャップ層としての役割、または、拡散バリア層としての役割を果たすことができなくなる。一方で、ＮＳＧ膜１０２の膜厚が厚すぎると、ＮＳＧ膜１０２の形成、および、ＮＳＧ膜１０２の除去が困難となる。 The film thickness of the NSG film 102 is, for example, 100 nm or more and less than 500 nm. If the NSG film 102 is too thin, it cannot function as a cap layer or a diffusion barrier layer. On the other hand, if the film thickness of the NSG film 102 is too thick, it becomes difficult to form the NSG film 102 and remove the NSG film 102.
　また、ｐ型の不純物拡散源１０１としてのＢＳＧ膜の形成にＢＢｒ３気相反応を用いる場合には、ＢＳＧ膜が受光面１００Ａだけではなく、ｎ型の単結晶シリコン基板１００の裏面１００Ｂにも形成される。 When the BBr 3 gas phase reaction is used for forming the BSG film as the p-type impurity diffusion source 101, the BSG film is not only applied to the light receiving surface 100A but also to the back surface 100B of the n-type single crystal silicon substrate 100. It is formed.
　そこで、ｎ型の単結晶シリコン基板１００の受光面１００Ａに形成されたＢＳＧ膜の上面に熱酸化膜または窒化膜によるバリア層を形成した後、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに形成されたＢＳＧ膜をフッ酸で除去する。その後、ｐ型の不純物拡散層１０３をフッ硝酸、または、水酸化ナトリウムなどの処理剤で片面除去する。 Therefore, a barrier layer made of a thermal oxide film or a nitride film is formed on the upper surface of the BSG film formed on the light receiving surface 100A of the n-type single crystal silicon substrate 100, and then formed on the back surface 100B of the n-type single crystal silicon substrate 100. The formed BSG film is removed with hydrofluoric acid. Thereafter, the p-type impurity diffusion layer 103 is removed on one side with a treatment agent such as hydrofluoric acid or sodium hydroxide.
　ここで、窒化膜は、たとえば、シランガス、窒素ガス、または、アンモニアガスなどを用いたプラズマＣＶＤ法を用いて形成することができる。なお、上記のバリア層は、後でドーパント活性化のための熱処理時にもバリア層として働くため、たとえば、５０ｎｍ以上の厚さで形成しておくことが好ましい。 Here, the nitride film can be formed using, for example, a plasma CVD method using silane gas, nitrogen gas, ammonia gas, or the like. In addition, since said barrier layer functions as a barrier layer also at the time of the heat processing for dopant activation later, it is preferable to form with a thickness of 50 nm or more, for example.
　次に、図５に例示されるように、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに、トンネル酸化物層１０４を形成する（図３におけるステップＳＴ１０１を参照）。 Next, as illustrated in FIG. 5, a tunnel oxide layer 104 is formed on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST101 in FIG. 3).
　トンネル酸化物層１０４の材料には、シリコン酸化膜、または、酸化アルミニウム膜などの誘電体材料を用いることができる。シリコン酸化膜の形成は、たとえば、オゾン水への浸漬によって行うことができる。この場合、所望の厚さの酸化膜が得られるように、オゾン濃度、および、浸漬時間を制御する。 As the material of the tunnel oxide layer 104, a dielectric material such as a silicon oxide film or an aluminum oxide film can be used. The silicon oxide film can be formed by, for example, immersion in ozone water. In this case, the ozone concentration and the immersion time are controlled so that an oxide film having a desired thickness is obtained.
　また、シリコン酸化膜の形成には、熱酸化、硝酸酸化、プラズマ化学気相堆積（Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ：ＰＥＣＶＤ）法、原子層堆積（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ：ＡＬＤ）法、ＵＶ照射、または、オゾン照射などの方法も用いることができる。 In addition, the silicon oxide film can be formed by thermal oxidation, nitric acid oxidation, plasma enhanced chemical vapor deposition (PECVD) method, atomic layer deposition (ALD) method, UV irradiation, or ozone. A method such as irradiation can also be used.
　トンネル酸化物層１０４の膜厚は、たとえば、０．５ｎｍ以上、かつ、５ｎｍ未満である。トンネル酸化物層１０４の膜厚が薄すぎると、多数キャリアのみならず少数キャリアもトンネル酸化物層１０４を通過してしまう。そのため、再結合の増加によって開放電圧が低下する。また、トンネル酸化物層１０４の膜厚が厚すぎる場合であっても、多数キャリアのトンネル輸送が妨げられる。そのため、直列抵抗が増加することによって、電気的特性が劣化する。 The film thickness of the tunnel oxide layer 104 is, for example, 0.5 nm or more and less than 5 nm. When the tunnel oxide layer 104 is too thin, not only majority carriers but also minority carriers pass through the tunnel oxide layer 104. Therefore, the open circuit voltage decreases due to the increase in recombination. Even when the tunnel oxide layer 104 is too thick, tunneling of majority carriers is hindered. Therefore, the electrical characteristics are deteriorated by increasing the series resistance.
　次に、図６に例示されるように、トンネル酸化物層１０４の下面にｎ型の非晶質シリコン層１０５を形成する（図３におけるステップＳＴ１０２を参照）。ＳｉＨ４、または、ＰＨ３を用いたＰＥＣＶＤ法などの化学気相堆積法によって、ｎ型の非晶質シリコン層１０５を形成する。 Next, as illustrated in FIG. 6, an n-type amorphous silicon layer 105 is formed on the lower surface of the tunnel oxide layer 104 (see step ST102 in FIG. 3). An n-type amorphous silicon layer 105 is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 or PH 3 .
　ｎ型の非晶質シリコン層１０５の膜厚は、たとえば、５ｎｍ以上、かつ、１００ｎｍ未満である。ｎ型の非晶質シリコン層１０５の膜厚が薄すぎると、電界効果が弱くなる。そして、トンネル接合層における電気的抵抗が増大し、かつ、少数キャリアの追い返し効果も小さくなる。そのため、ｎ型の非晶質シリコン層１０５の特性が劣化する。 The film thickness of the n-type amorphous silicon layer 105 is, for example, 5 nm or more and less than 100 nm. When the thickness of the n-type amorphous silicon layer 105 is too thin, the field effect is weakened. In addition, the electrical resistance in the tunnel junction layer increases, and the minority carrier repulsion effect decreases. Therefore, the characteristics of the n-type amorphous silicon layer 105 deteriorate.
　一方、ｎ型の非晶質シリコン層１０５の膜厚が厚いと、熱歪みが大きくなる。そのため、ｎ型の非晶質シリコン層１０５の膜厚が適正な範囲である場合に比べて、シリコン層のパッシベーション効果が低下することが分かっている。 On the other hand, when the thickness of the n-type amorphous silicon layer 105 is large, the thermal strain increases. For this reason, it is known that the passivation effect of the silicon layer is reduced as compared with the case where the film thickness of the n-type amorphous silicon layer 105 is in an appropriate range.
　その後、図７に例示されるように、図６に例示された構造を拡散炉に導入し、窒素ガスを流しながら昇温する。そして、一定温度で一定時間保持して、熱処理を行う（図３におけるステップＳＴ１０３を参照）。 Then, as illustrated in FIG. 7, the structure illustrated in FIG. 6 is introduced into the diffusion furnace, and the temperature is raised while flowing nitrogen gas. Then, heat treatment is performed by holding at a constant temperature for a certain time (see step ST103 in FIG. 3).
　これによって、ｎ型の非晶質シリコン層１０５の一部、または、全体が結晶化し、ｎ型の結晶系薄膜シリコン層１０６に変化する。ｎ型の結晶系薄膜シリコン層１０６の膜厚は、たとえば、５ｎｍ以上、かつ、１００ｎｍ未満である。また、上記の熱処理によって、ｎ型の非晶質シリコン層１０５中のｎ型のドーパントが活性化する。そうすることによって、シート抵抗が低下する。 Thereby, a part or the whole of the n-type amorphous silicon layer 105 is crystallized to be changed into the n-type crystalline thin film silicon layer 106. The film thickness of the n-type crystalline thin film silicon layer 106 is, for example, 5 nm or more and less than 100 nm. In addition, the n-type dopant in the n-type amorphous silicon layer 105 is activated by the heat treatment. By doing so, the sheet resistance decreases.
　最適なアニール温度は、シリコンドープ層に含まれるリン濃度、または、シリコンドープ層の厚さによって異なる。ここで、ｎ型の非晶質シリコン層１０５の熱処理時における最も高い温度であるピーク温度は、４００℃以上、かつ、９００℃未満である。 The optimum annealing temperature varies depending on the phosphorus concentration contained in the silicon doped layer or the thickness of the silicon doped layer. Here, the peak temperature, which is the highest temperature during the heat treatment of the n-type amorphous silicon layer 105, is 400 ° C. or higher and lower than 900 ° C.
　熱処理温度が低いと、ｎ型の非晶質シリコン層１０５の結晶化が十分に促進されない。そのため、裏面１００Ｂにおける電界効果が低下し、高いパッシベーション効果を得られない。また、ｎ型の非晶質シリコン層１０５が高抵抗となるため、多数キャリアの輸送が妨げられる恐れがある。なお、熱処理温度が４００℃を超える場合には、ｎ型の非晶質シリコン層１０５中から水素が脱離し始めるため、結晶化が促進される。 If the heat treatment temperature is low, the crystallization of the n-type amorphous silicon layer 105 is not sufficiently promoted. Therefore, the electric field effect on the back surface 100B is reduced, and a high passivation effect cannot be obtained. In addition, since the n-type amorphous silicon layer 105 has a high resistance, transport of majority carriers may be hindered. Note that when the heat treatment temperature exceeds 400 ° C., hydrogen begins to be desorbed from the n-type amorphous silicon layer 105, so that crystallization is promoted.
　一方、熱処理温度が９００℃を超えると、リン濃度に関係なくパッシベーション効果が著しく低下し始める。したがって、開放電圧の低下につながる。 On the other hand, when the heat treatment temperature exceeds 900 ° C., the passivation effect starts to decrease remarkably regardless of the phosphorus concentration. Therefore, the open circuit voltage is reduced.
　これは、高温の熱処理によってｎ型の非晶質シリコン層１０５中のｎ型のドーパントがトンネル酸化物層１０４を貫通してｎ型の単結晶シリコン基板１００にまで多量に拡散することによって、トンネル酸化物層１０４の構造破壊、または、ｎ型の非晶質シリコン層１０５からドーパントが拡散してしまうことによって、ｎ型の結晶系薄膜シリコン層１０６となった場合であっても電界効果の低下が起きるためである。 This is because the n-type dopant in the n-type amorphous silicon layer 105 penetrates the tunnel oxide layer 104 and diffuses to the n-type single crystal silicon substrate 100 in a large amount by high-temperature heat treatment. Even if the n-type crystalline thin film silicon layer 106 is formed due to the structural breakdown of the oxide layer 104 or the diffusion of the dopant from the n-type amorphous silicon layer 105, the field effect is reduced. This is because it happens.
　なお、ｎ型の結晶系薄膜シリコン層１０６は、ノンドープ（真性）非晶質シリコン層を形成した後に、ｎ型のドーパントを拡散させて形成してもよい。その場合、ステップＳＴ１０２において、ＳｉＨ４を用いたＰＥＣＶＤ法などの化学気相堆積法によって、ノンドープ非晶質シリコン層を形成する。その後、ステップＳＴ１０３において、ＰＯＣｌ３を用いた気相反応および熱拡散、または、リンのイオン注入および熱拡散によって、ｎ型のドーパントをノンドープ非晶質シリコン層中に拡散させる。 The n-type crystalline thin film silicon layer 106 may be formed by diffusing an n-type dopant after forming a non-doped (intrinsic) amorphous silicon layer. In that case, in step ST102, a non-doped amorphous silicon layer is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 . Thereafter, in step ST103, an n-type dopant is diffused into the non-doped amorphous silicon layer by gas phase reaction and thermal diffusion using POCl 3 or phosphorus ion implantation and thermal diffusion.
　また、ｎ型の結晶系薄膜シリコン層１０６は、ＳｉＨ４、および、ＰＨ３を用いた減圧化学気相堆積（ｌｏｗ　ｐｒｅｓｓｕｒｅ　ｃｈｅｍｉｃａｌ　ｖａｐｏｒ　ｄｅｐｏｓｉｔｉｏｎ、すなわち、ＬＰＣＶＤ）法などの化学気相堆積法によって、一工程で形成してもよい。その場合、たとえば、５００℃以上の温度でｎ型の結晶系薄膜シリコン層１０６の成膜を行い、成膜後の熱処理は必要に応じて行えばよい。 The n-type crystalline thin film silicon layer 106 is formed by chemical vapor deposition such as low pressure chemical vapor deposition (ie, LPCVD) using SiH 4 and PH 3. You may form in a process. In that case, for example, the n-type crystalline thin film silicon layer 106 may be formed at a temperature of 500 ° C. or higher, and heat treatment after the film formation may be performed as necessary.
　次に、図８に例示されるように、ｎ型の単結晶シリコン基板１００の受光面１００Ａに形成されたｐ型の不純物拡散源１０１であるＢＳＧ膜、および、ＮＳＧ膜１０２を、フッ酸を用いて完全に除去する。 Next, as illustrated in FIG. 8, the BSG film which is the p-type impurity diffusion source 101 formed on the light receiving surface 100 </ b> A of the n-type single crystal silicon substrate 100 and the NSG film 102 are mixed with hydrofluoric acid. Use to remove completely.
　本工程は、ステップＳＴ１０３の熱処理工程前に行うことも可能である。その場合、熱処理中にｐ型の不純物拡散源１０１であるＢＳＧ膜からボロンが雰囲気中に拡散することによって、当該ボロンがｎ型の非晶質シリコン層１０５に付着し、さらに、拡散することを防ぐことができる。 This step can be performed before the heat treatment step of step ST103. In that case, boron diffuses into the atmosphere from the BSG film as the p-type impurity diffusion source 101 during the heat treatment, so that the boron adheres to the n-type amorphous silicon layer 105 and further diffuses. Can be prevented.
　一方で、ｎ型の非晶質シリコン層１０５からｎ型のドーパントが雰囲気中に拡散し、ｐ型の不純物拡散層１０３中に拡散してしまう可能性がある。ただし、ｐ型の不純物拡散源１０１であるＢＳＧ膜の上面にはキャップ層であるＮＳＧ膜１０２が形成されており、ボロンがｎ型の非晶質シリコン層１０５中に拡散する可能性の方が低いため、ステップＳＴ１０３の熱処理後にＢＳＧ膜、および、ＮＳＧ膜１０２を除去することが好ましい。 On the other hand, the n-type dopant may diffuse from the n-type amorphous silicon layer 105 into the atmosphere and diffuse into the p-type impurity diffusion layer 103. However, the NSG film 102 which is a cap layer is formed on the upper surface of the BSG film which is the p-type impurity diffusion source 101, and there is a possibility that boron may diffuse into the n-type amorphous silicon layer 105. Therefore, it is preferable to remove the BSG film and the NSG film 102 after the heat treatment in step ST103.
　次に、図８に例示されるように、ｎ型の単結晶シリコン基板１００の裏面１００Ｂにおけるｎ型の結晶系薄膜シリコン層１０６の下面に、保護膜１０７を形成する（図３におけるステップＳＴ１０４を参照）。 Next, as illustrated in FIG. 8, a protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 on the back surface 100B of the n-type single crystal silicon substrate 100 (step ST104 in FIG. 3 is performed). reference).
　保護膜１０７の材料は、たとえば、窒化シリコン、酸化シリコン、窒酸化シリコン、非晶質シリコン、微結晶シリコン、または、ケイ化物などである。また、保護膜１０７は、複数の膜の積層構造であってもよい。 The material of the protective film 107 is, for example, silicon nitride, silicon oxide, silicon nitride oxide, amorphous silicon, microcrystalline silicon, or silicide. Further, the protective film 107 may have a stacked structure of a plurality of films.
　ここで、保護膜１０７は、シリコンドープ層であるｎ型の結晶系薄膜シリコン層１０６よりも高い硬度を有することが好ましい。これは、保護膜１０７上に電極をスクリーン印刷する際、版との接触または摩擦などによる物理ダメージからｎ型の結晶系薄膜シリコン層１０６を保護するためである。 Here, the protective film 107 preferably has a higher hardness than the n-type crystalline thin film silicon layer 106 which is a silicon doped layer. This is to protect the n-type crystalline thin film silicon layer 106 from physical damage due to contact with the plate or friction when electrodes are screen-printed on the protective film 107.
　また、保護膜１０７の膜中水素濃度は、ｎ型の結晶系薄膜シリコン層１０６中の水素濃度よりも高いことが好ましい。保護膜１０７中に十分な水素が含まれていると、熱処理時、および、電極焼成時に当該水素が脱離する。そして、形成されたｎ型の結晶系薄膜シリコン層１０６中、および、トンネル酸化物層１０４と単結晶シリコン基板１００との界面のダングリングボンドが、保護膜１０７中から脱離した水素によって終端される。これによって、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果、および、トンネル酸化物層１０４のパッシベーション効果が向上する。 The hydrogen concentration in the protective film 107 is preferably higher than the hydrogen concentration in the n-type crystalline thin silicon layer 106. If the protective film 107 contains sufficient hydrogen, the hydrogen is desorbed during heat treatment and electrode firing. Then, dangling bonds in the formed n-type crystalline thin film silicon layer 106 and the interface between the tunnel oxide layer 104 and the single crystal silicon substrate 100 are terminated by hydrogen desorbed from the protective film 107. The This improves the passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104.
　また、保護膜１０７の膜厚は、たとえば、５ｎｍ以上、かつ、２００ｎｍ未満であることが好ましい。保護膜１０７の膜厚が薄すぎると、電極が焼成時にｎ型の結晶系薄膜シリコン層１０６を突き抜けてｎ型の単結晶シリコン基板１００を浸食することを防げない。また、保護膜１０７の膜厚が薄すぎると、保護膜１０７から十分な水素を供給することができないため、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果が低下してしまう。 The film thickness of the protective film 107 is preferably, for example, 5 nm or more and less than 200 nm. If the film thickness of the protective film 107 is too thin, it cannot be prevented that the electrode penetrates the n-type crystalline thin film silicon layer 106 and erodes the n-type single crystal silicon substrate 100 during firing. If the thickness of the protective film 107 is too thin, sufficient hydrogen cannot be supplied from the protective film 107, so that the passivation effect of the n-type crystalline thin film silicon layer 106 is reduced.
　一方で、保護膜１０７の膜厚が厚すぎる場合であっても、電極がｎ型の結晶系薄膜シリコン層１０６に接触しにくくなるため、コンタクト抵抗が増大してしまう。 On the other hand, even if the protective film 107 is too thick, the electrode is less likely to contact the n-type crystalline thin film silicon layer 106, and the contact resistance increases.
　次に、図９に例示されるように、ｎ型の単結晶シリコン基板１００の受光面１００Ａにおけるｐ型の不純物拡散層１０３の上面に、受光面１００Ａ側の誘電体層１０８を形成する。そして、誘電体層１０８の上面に、反射防止膜１０９を形成する（図３におけるステップＳＴ１０５を参照）。 Next, as illustrated in FIG. 9, a dielectric layer 108 on the light receiving surface 100 </ b> A side is formed on the upper surface of the p-type impurity diffusion layer 103 in the light receiving surface 100 </ b> A of the n-type single crystal silicon substrate 100. Then, an antireflection film 109 is formed on the upper surface of the dielectric layer 108 (see step ST105 in FIG. 3).
　誘電体層１０８として、たとえば、酸化膜を用いることができる。また、誘電体層１０８として、たとえば、原子層堆積法（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ：ＡＬＤ）、または、ＣＶＤ法によって形成される酸化アルミニウム膜などの誘電体層を用いることができる。特に、酸化アルミニウム膜は負の固定電荷を有しているため、ｐ型の不純物拡散層１０３に対して優れたパッシベーション効果を発揮することが知られている。誘電体層１０８の膜厚は、たとえば、２ｎｍ以上、かつ、５０ｎｍ未満である。 As the dielectric layer 108, for example, an oxide film can be used. As the dielectric layer 108, for example, a dielectric layer such as an atomic layer deposition (ALD) or an aluminum oxide film formed by a CVD method can be used. In particular, since the aluminum oxide film has a negative fixed charge, it is known to exhibit an excellent passivation effect for the p-type impurity diffusion layer 103. The film thickness of the dielectric layer 108 is, for example, 2 nm or more and less than 50 nm.
　誘電体層１０８の上面には、反射防止膜１０９を形成する。反射防止膜１０９として、たとえば、プラズマＣＶＤ法によって形成される窒化シリコン膜を用いる。反射防止膜１０９の膜厚は、誘電体層１０８の厚さに応じて、太陽光スペクトルに対して最適な膜厚、たとえば、３０ｎｍ以上、かつ、８０ｎｍ未満程度の膜厚に設計する。 An antireflection film 109 is formed on the upper surface of the dielectric layer 108. As the antireflection film 109, for example, a silicon nitride film formed by a plasma CVD method is used. The film thickness of the antireflection film 109 is designed to be an optimal film thickness for the solar spectrum, for example, about 30 nm or more and less than 80 nm according to the thickness of the dielectric layer 108.
　最後に、ｎ型の単結晶シリコン基板１００の受光面１００Ａに、受光面電極１１０を形成する。また、ｎ型の結晶系薄膜シリコン層１０６の下面に、裏面電極１１１を形成する（図３におけるステップＳＴ１０６を参照）。これによって、図１および図２に例示された太陽電池が形成される。 Finally, the light-receiving surface electrode 110 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100. Further, the back electrode 111 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 (see step ST106 in FIG. 3). Thereby, the solar cell illustrated in FIGS. 1 and 2 is formed.
　それぞれの電極は、金属粒子およびガラス粒子を含むペーストをスクリーン印刷法などの塗布法によって、まず、それぞれ反射防止膜１０９上および保護膜１０７上に櫛形パターン状に塗布する。そして、さらに、それらを乾燥させることによって形成される。 For each electrode, a paste containing metal particles and glass particles is first applied in a comb pattern on the antireflection film 109 and the protective film 107 by a coating method such as a screen printing method. Further, they are formed by drying them.
　ここで、ガラス粒子の含有量は、金属粒子の重量に基づいて、０．５重量％以上、かつ、１０．０重量％以下、好ましくは、１．０重量％以上、かつ、３．０重量％以下である。 Here, the content of the glass particles is 0.5 wt% or more and 10.0 wt% or less, preferably 1.0 wt% or more and 3.0 wt% based on the weight of the metal particles. % Or less.
　上記のペーストの乾燥は、たとえば、２００℃の乾燥オーブン中で１０分程度で行う。乾燥後、受光面電極１１０、および、裏面電極１１１を８００℃程度の高温で同時に熱処理し、焼成する。 The above paste is dried in a drying oven at 200 ° C. for about 10 minutes, for example. After drying, the light-receiving surface electrode 110 and the back surface electrode 111 are simultaneously heat-treated at a high temperature of about 800 ° C. and fired.
　この際、受光面１００Ａ側では、焼成によって、ガラス粒子が受光面１００Ａ側の誘電体層１０８、および、反射防止膜１０９をエッチングする。そして、ｐ型の不純物拡散層１０３が露出し、さらに、受光面電極１１０がｐ型の不純物拡散層１０３に電気的に接続する。 At this time, on the light receiving surface 100A side, the glass particles etch the dielectric layer 108 on the light receiving surface 100A side and the antireflection film 109 by firing. Then, the p-type impurity diffusion layer 103 is exposed, and the light-receiving surface electrode 110 is electrically connected to the p-type impurity diffusion layer 103.
　また、裏面１００Ｂ側においても同様に、ガラス粒子が保護膜１０７をエッチングする。そして、ｎ型の結晶系薄膜シリコン層１０６が露出し、さらに、裏面電極１１１がｎ型の結晶系薄膜シリコン層１０６に電気的に接続する。 Similarly, the glass particles etch the protective film 107 also on the back surface 100B side. Then, the n-type crystalline thin film silicon layer 106 is exposed, and the back electrode 111 is electrically connected to the n-type crystalline thin film silicon layer 106.
　従来の裏面電極形成においては、ｎ型の結晶系薄膜シリコン層の下面に直接、蒸着電極、または、めっき電極などを形成する方法、または、ｎ型の結晶系薄膜シリコン層の下面に透明導電膜を成膜し、さらに、透明導電膜の下面に電極を形成する方法が用いられていた。 In conventional backside electrode formation, a method of forming a vapor deposition electrode or a plating electrode directly on the lower surface of the n-type crystalline thin film silicon layer, or a transparent conductive film on the lower surface of the n-type crystalline thin film silicon layer And forming an electrode on the lower surface of the transparent conductive film.
　これらの方法を本実施の形態に関する電極形成に適用しようとすると、焼成時に裏面電極がｎ型の結晶系薄膜シリコン層を貫通してｎ型の単結晶シリコン基板を浸食する。また、焼成時の熱によってトンネル酸化物層、および、ｎ型の結晶系薄膜シリコン層を備える構造が劣化する。 When these methods are applied to the electrode formation according to the present embodiment, the back electrode penetrates the n-type crystalline thin film silicon layer and erodes the n-type single crystal silicon substrate during firing. In addition, the structure including the tunnel oxide layer and the n-type crystalline thin film silicon layer deteriorates due to heat during firing.
　また、ｎ型の結晶系薄膜シリコン層の下面に直接電極を印刷すると、印刷時にｎ型の結晶系薄膜シリコン層が傷つき、特性低下が生じる恐れがあった。 In addition, when an electrode is printed directly on the lower surface of the n-type crystalline thin film silicon layer, the n-type crystalline thin film silicon layer may be damaged during printing, resulting in deterioration of characteristics.
　また、透明導電膜越しに電極を焼成する場合には、透明導電膜の光吸収が大きいため、電流低下が生じる可能性があった。また、透明導電膜越しに電極を焼成する場合、透明導電膜が焼成などの高温処理に対する耐性に乏しいため、電気的特性の低下、たとえば、電圧低下が生じる可能性があった。 Also, when the electrode is baked through the transparent conductive film, the light absorption of the transparent conductive film is large, which may cause a current drop. Moreover, when baking an electrode through a transparent conductive film, since the transparent conductive film has poor resistance to high-temperature treatment such as baking, there is a possibility that a decrease in electrical characteristics, for example, a voltage drop may occur.
　一方、本実施の形態では、ｎ型の結晶系薄膜シリコン層１０６上に保護膜１０７を形成し、保護膜１０７越しに電極の印刷、および、焼成を行う。そのため、焼成時に電極はｎ型の単結晶シリコン基板１００内まで貫通せず、ｎ型の結晶系薄膜シリコン層１０６内への浸食にとどめることができる。 On the other hand, in the present embodiment, a protective film 107 is formed on the n-type crystalline thin film silicon layer 106, and electrodes are printed and baked through the protective film 107. Therefore, at the time of firing, the electrode does not penetrate into the n-type single crystal silicon substrate 100, and can only be eroded into the n-type crystalline thin film silicon layer 106.
　また、保護膜１０７は、ｎ型の結晶系薄膜シリコン層１０６の下面をパッシベーションする。さらに、焼成時に保護膜１０７中の水素がｎ型の結晶系薄膜シリコン層１０６に供給され、ｎ型の結晶系薄膜シリコン層１０６中、および、トンネル酸化物層１０４と単結晶シリコン基板１００との界面のダングリングボンドを終端する。その結果、少数キャリアの再結合が抑制され、太陽電池特性の向上を見込むことができる。 The protective film 107 passivates the lower surface of the n-type crystalline thin film silicon layer 106. Furthermore, hydrogen in the protective film 107 is supplied to the n-type crystalline thin film silicon layer 106 during firing, and in the n-type crystalline thin film silicon layer 106 and between the tunnel oxide layer 104 and the single crystal silicon substrate 100. Terminates dangling bonds at the interface. As a result, recombination of minority carriers is suppressed, and an improvement in solar cell characteristics can be expected.
　また、ｎ型の非晶質シリコン層１０５の熱処理時のピーク温度、および、電極焼成時のピーク温度は、保護膜１０７の形成温度よりも高いことが好ましい。熱処理時のピーク温度、および、電極焼成時のピーク温度が保護膜１０７の形成温度よりも高ければ、熱処理時および電極焼成時に、保護膜１０７に含まれている水素がｎ型の結晶系薄膜シリコン層１０６中、および、トンネル酸化物層１０４と単結晶シリコン基板１００との界面に拡散する。そのため、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果、および、トンネル酸化物層１０４のパッシベーション効果が向上する。 Further, the peak temperature during the heat treatment of the n-type amorphous silicon layer 105 and the peak temperature during the electrode firing are preferably higher than the formation temperature of the protective film 107. If the peak temperature during the heat treatment and the peak temperature during the electrode firing are higher than the formation temperature of the protective film 107, the hydrogen contained in the protective film 107 is n-type crystalline thin film silicon during the heat treatment and during the electrode firing. It diffuses in the layer 106 and at the interface between the tunnel oxide layer 104 and the single crystal silicon substrate 100. Therefore, the passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104 are improved.
　図１０は、保護膜を形成しない場合、および、保護膜を形成する場合それぞれについての、ｎ型の非晶質シリコン層の熱処理温度［℃］と、少数キャリアライフタイムから求められる開放電圧の推定値［ｍＶ］との関係を例示する図である。 FIG. 10 shows the estimation of the open-circuit voltage obtained from the heat treatment temperature [° C.] of the n-type amorphous silicon layer and the minority carrier lifetime for each of the case where the protective film is not formed and the case where the protective film is formed. It is a figure which illustrates the relationship with value [mV].
　まず、保護膜を形成しない場合は、ｎ型の単結晶シリコン基板の上下面にトンネル酸化物層、および、ｎ型の非晶質シリコン層をそれぞれ形成した後、熱処理および焼成を行った。熱処理温度は、たとえば、７２５℃以上、かつ、８２５℃以下とし、焼成は８００℃で行った。評価は、熱処理後および焼成後について、開放電圧の推定値の測定を行った。 First, when the protective film was not formed, a tunnel oxide layer and an n-type amorphous silicon layer were respectively formed on the upper and lower surfaces of the n-type single crystal silicon substrate, and then heat treatment and baking were performed. The heat treatment temperature was, for example, 725 ° C. or higher and 825 ° C. or lower, and firing was performed at 800 ° C. The evaluation was performed by measuring the estimated open circuit voltage after heat treatment and after firing.
　図１０に例示されるように、熱処理後の開放電圧の推定値は、特定の温度までは、熱処理温度の増加に伴い向上した。そして、熱処理後の開放電圧の推定値は、熱処理温度が７７５℃の場合でピークとなり、それ以上の熱処理温度では減少していくことが分かった。 As illustrated in FIG. 10, the estimated value of the open circuit voltage after heat treatment improved with increasing heat treatment temperature up to a specific temperature. Then, it was found that the estimated value of the open circuit voltage after the heat treatment reached a peak when the heat treatment temperature was 775 ° C. and decreased at a heat treatment temperature higher than that.
　その後、保護膜を形成せずに焼成を行うと、開放電圧の推定値は低下した。ただし、熱処理温度が低いほど、開放電圧の推定値の低下幅が大きかった。 Thereafter, when firing was carried out without forming a protective film, the estimated value of the open circuit voltage decreased. However, the lower the heat treatment temperature, the greater the reduction in the estimated open circuit voltage.
　これは、熱処理温度が低い場合、熱処理温度と焼成温度である８００℃との差が大きくなるため、焼成によってｎ型の結晶系薄膜シリコン層中の水素が多く脱離し、パッシベーション効果が大きく低下するためであると考えられる。 This is because when the heat treatment temperature is low, the difference between the heat treatment temperature and the firing temperature of 800 ° C. becomes large, so that a large amount of hydrogen in the n-type crystalline thin film silicon layer is desorbed by firing, and the passivation effect is greatly reduced. This is probably because of this.
　そのため、保護膜が形成されない場合には、焼成によってパッシベーション効果が低下することを考慮し、熱処理温度を、パッシベーション効果がピークとなる温度よりも高く設定する必要がある。そうすると、最適なアニール温度に設定することができない場合が生じる。その場合、変換効率の低下を免れることができない。 Therefore, when the protective film is not formed, it is necessary to set the heat treatment temperature higher than the temperature at which the passivation effect reaches a peak in consideration that the passivation effect is reduced by firing. As a result, the optimum annealing temperature may not be set. In that case, the reduction in conversion efficiency cannot be avoided.
　次に、保護膜を形成する場合は、熱処理温度は、たとえば、７２５℃以上、かつ、８００℃以下とした。そして、８００℃の熱処理後、保護膜の形成後、および、８００℃の焼成処理後のそれぞれについて、開放電圧の推定値を測定した。 Next, when the protective film is formed, the heat treatment temperature is set to, for example, 725 ° C. or more and 800 ° C. or less. And the estimated value of the open circuit voltage was measured about each after heat processing of 800 degreeC, formation of a protective film, and baking processing of 800 degreeC.
　まず、８００℃の熱処理後については、保護膜を形成しない場合と同様に、熱処理後の開放電圧の推定値は、特定の温度までは、熱処理温度の増加に伴い向上した。そして、熱処理後の開放電圧の推定値は、ある温度でピークとなり、それ以上の熱処理温度では減少していくことが分かった。 First, after the heat treatment at 800 ° C., as in the case where the protective film was not formed, the estimated value of the open-circuit voltage after the heat treatment improved as the heat treatment temperature increased up to a specific temperature. Then, it was found that the estimated value of the open circuit voltage after the heat treatment reached a peak at a certain temperature and decreased at a heat treatment temperature higher than that.
　次に、保護膜の形成後では、熱処理温度が低い場合には、開放電圧の推定値が大きく向上した。一方で、熱処理温度が高い場合には、開放電圧の推定値はほとんど変化しなかった。 Next, after the formation of the protective film, when the heat treatment temperature was low, the estimated value of the open circuit voltage was greatly improved. On the other hand, when the heat treatment temperature was high, the estimated value of the open-circuit voltage hardly changed.
　この現象については、次のように考えることができる。 This phenomenon can be considered as follows.
　保護膜の形成によって、ｎ型の結晶系薄膜シリコン層の表面がパッシベーションされる。この状態で低温での熱処理を行った場合には、ドーパントの活性化が不十分となり、ｎ型の結晶系薄膜シリコン層内の再結合サイトが少ない。それとともに、ｎ型の結晶系薄膜シリコン層の電界効果が弱いため、保護膜のパッシベーション効果を得やすい。 By forming the protective film, the surface of the n-type crystalline thin film silicon layer is passivated. When heat treatment is performed at a low temperature in this state, the dopant is not sufficiently activated, and there are few recombination sites in the n-type crystalline thin film silicon layer. At the same time, since the field effect of the n-type crystalline thin film silicon layer is weak, it is easy to obtain a passivation effect of the protective film.
　一方で、高温での熱処理を行った場合には、多くのドーパントが活性化するため、ｎ型の結晶系薄膜シリコン層内の再結合サイトが多い。それとともに、ｎ型の結晶系薄膜シリコン層の電界効果が強いため、保護膜のパッシベーション効果の影響を受けにくい。 On the other hand, when heat treatment is performed at a high temperature, many dopants are activated, so that there are many recombination sites in the n-type crystalline thin film silicon layer. At the same time, the n-type crystalline thin film silicon layer has a strong electric field effect, and is not easily affected by the passivation effect of the protective film.
　次に、８００℃の焼成処理後では、開放電圧の推定値はわずかに上昇した。これは、保護膜がｎ型の結晶系薄膜シリコン層からの多量の水素脱離を防ぐとともに、ｎ型の結晶系薄膜シリコン層内、および、トンネル酸化物層と単結晶シリコン基板との界面に水素を供給しているためである。 Next, after the baking process at 800 ° C., the estimated open circuit voltage slightly increased. This is because the protective film prevents a large amount of hydrogen desorption from the n-type crystalline thin film silicon layer, and at the interface between the n-type crystalline thin film silicon layer and the tunnel oxide layer and the single crystal silicon substrate. This is because hydrogen is supplied.
　以上のことから、ｎ型の結晶系薄膜シリコン層に接触して保護膜が形成されている場合には、ｎ型の結晶系薄膜シリコン層の熱処理温度を、パッシベーション効果がピークとなる温度よりも高く設定する必要がない。 From the above, when the protective film is formed in contact with the n-type crystalline thin film silicon layer, the heat treatment temperature of the n-type crystalline thin film silicon layer is set higher than the temperature at which the passivation effect peaks. There is no need to set it high.
　また、ｎ型の結晶系薄膜シリコン層に接触して保護膜が形成されている場合には、保護膜がキャップ層として機能するため、焼成時のｎ型の結晶系薄膜シリコン層からの水素脱離を防ぐことができる。そのため、ｎ型の結晶系薄膜シリコン層のパッシベーション効果を最大限に発揮することができる。これによって、高い開放電圧を実現することができる。 In addition, when a protective film is formed in contact with the n-type crystalline thin film silicon layer, the protective film functions as a cap layer, so that hydrogen desorption from the n-type crystalline thin film silicon layer during firing is performed. Separation can be prevented. Therefore, the passivation effect of the n-type crystalline thin film silicon layer can be maximized. Thereby, a high open circuit voltage can be realized.
　以上のように、焼成された電極を用いてセルを作製する場合、保護膜を形成しない場合よりも保護膜を形成する場合の方が、焼成ダメージだけでなく、電極浸食による開放電圧の低下も抑制することができる。具体的には、焼成された電極を用いてセルを作製した結果、保護膜を形成する場合、開放電圧の推定値の３０ｍＶ以上、かつ、５０ｍＶ以下の向上が見られた。ただし、保護膜の厚さ、および、シリコンドープ層の厚さがそれぞれの設計範囲において作製されているものとする。 As described above, when a cell is manufactured using a baked electrode, the protective film is formed not only when the protective film is not formed but also when the open circuit voltage is reduced due to electrode erosion. Can be suppressed. Specifically, as a result of producing a cell using the fired electrode, when the protective film was formed, an improvement of 30 mV or more and 50 mV or less of the estimated open circuit voltage was observed. However, the thickness of a protective film and the thickness of a silicon dope layer shall be produced in each design range.
　＜第２の実施の形態＞
　本実施の形態に関する太陽電池、および、太陽電池の製造方法について説明する。以下では、以上に記載された実施の形態で説明された構成と同様の構成については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。 <Second Embodiment>
A solar cell and a method for manufacturing the solar cell according to the present embodiment will be described. In the following, the same components as those described in the embodiment described above are denoted by the same reference numerals and detailed description thereof will be appropriately omitted.
　＜太陽電池の構成について＞
　図１１は、本実施の形態に関する太陽電池の製造方法で形成された、太陽電池の構造を概略的を例示する平面図である。また、図１２は、図１１におけるＢ－Ｂ’断面図である。 <About solar cell configuration>
FIG. 11 is a plan view schematically illustrating the structure of the solar cell formed by the solar cell manufacturing method according to the present embodiment. FIG. 12 is a cross-sectional view taken along the line BB ′ in FIG.
　また、図１３は、本実施の形態に関する太陽電池の製造方法を例示するフローチャートである。また、図１４から図１９は、本実施の形態に関する太陽電池の製造方法を例示する太陽電池の断面図である。 FIG. 13 is a flowchart illustrating a method for manufacturing a solar cell according to this embodiment. 14 to 19 are cross-sectional views of the solar cell illustrating the method for manufacturing the solar cell according to this embodiment.
　本実施の形態では、図２におけるｎ型の単結晶シリコン基板１００に代えて、ｐ型の単結晶シリコン基板２００を用いる。そのため、導電型が図２における構成と逆となる。 In this embodiment, a p-type single crystal silicon substrate 200 is used instead of the n-type single crystal silicon substrate 100 in FIG. Therefore, the conductivity type is the reverse of the configuration in FIG.
　本実施の形態の太陽電池の製造方法では、図１４に例示されるように、ｐ型の単結晶シリコン基板２００の受光面２００Ａに、ｎ型の不純物拡散層２０３を形成する。 In the solar cell manufacturing method of the present embodiment, as illustrated in FIG. 14, the n-type impurity diffusion layer 203 is formed on the light-receiving surface 200A of the p-type single crystal silicon substrate 200.
　そして、図１５、および、図１６に例示されるように、ｐ型の単結晶シリコン基板２００の裏面２００Ｂに、トンネル酸化物層２０４を形成し、さらに、トンネル酸化物層２０４の下面にｐ型の非晶質シリコン層２０５を形成する。 15 and FIG. 16, a tunnel oxide layer 204 is formed on the back surface 200B of the p-type single crystal silicon substrate 200, and the p-type is formed on the lower surface of the tunnel oxide layer 204. An amorphous silicon layer 205 is formed.
　その後、熱処理を行い、ｐ型の非晶質シリコン層２０５中に含まれるｐ型のドーパントを活性化するとともに、ｐ型の非晶質シリコン層２０５の一部、または、全体を結晶化させ、ｐ型の結晶系薄膜シリコン層２０６を形成する（図１７を参照）。 Thereafter, heat treatment is performed to activate the p-type dopant contained in the p-type amorphous silicon layer 205, and a part or the whole of the p-type amorphous silicon layer 205 is crystallized, A p-type crystalline thin film silicon layer 206 is formed (see FIG. 17).
　この後、図１８に例示されるように、ｐ型の結晶系薄膜シリコン層２０６の下面に保護膜２０７を形成する。最後に、保護膜２０７の下面から裏面電極２１１を印刷し、焼成によって裏面電極２１１をｐ型の結晶系薄膜シリコン層２０６にファイアースルーさせてコンタクトを形成する。 Thereafter, as illustrated in FIG. 18, a protective film 207 is formed on the lower surface of the p-type crystalline thin film silicon layer 206. Finally, the back electrode 211 is printed from the lower surface of the protective film 207, and the back electrode 211 is fired through the p-type crystalline thin film silicon layer 206 by baking to form a contact.
　＜太陽電池の製造方法について＞
　以下、図１３から図１９を参照しつつ、特に、第１の実施の形態と異なる点について、本実施の形態に関する太陽電池の製造方法を詳細に説明する。 <About solar cell manufacturing method>
Hereinafter, with reference to FIG. 13 to FIG. 19, the method for manufacturing the solar cell according to the present embodiment will be described in detail with respect to differences from the first embodiment.
　図１４に例示されるように、ｐ型の単結晶シリコン基板２００の受光面２００Ａに、ｎ型の不純物拡散層２０３を形成する（図１３におけるステップＳＴ２００を参照）。 As illustrated in FIG. 14, an n-type impurity diffusion layer 203 is formed on the light-receiving surface 200A of the p-type single crystal silicon substrate 200 (see step ST200 in FIG. 13).
　この工程では、ＰＯＣｌ３を用いた気相反応、または、ＰＨ３を用いたＡＰＣＶＤ法などの気相法によって、ｎ型の不純物拡散源２０１としてのＰＳＧ膜、および、ＮＳＧ膜２０２を形成した後、拡散炉中でリンを熱拡散させる。また、イオン注入によってリンを打ち込み、熱拡散させてもよい。 In this step, after the PSG film as the n-type impurity diffusion source 201 and the NSG film 202 are formed by a vapor phase reaction using POCl 3 or a vapor phase method such as an APCVD method using PH 3 Then, phosphorus is thermally diffused in a diffusion furnace. Alternatively, phosphorus may be implanted by ion implantation and thermally diffused.
　ｐ型の単結晶シリコン基板２００の裏面２００Ｂには、図１５に例示されるように、トンネル酸化物層２０４を形成する（図１３におけるステップＳＴ２０１を参照）。 As shown in FIG. 15, a tunnel oxide layer 204 is formed on the back surface 200B of the p-type single crystal silicon substrate 200 (see step ST201 in FIG. 13).
　その後、図１６に例示されるように、トンネル酸化物層２０４の下面にｐ型の非晶質シリコン層２０５を形成する（図１３におけるステップＳＴ２０２を参照）。この工程では、ＳｉＨ４、または、Ｂ２Ｈ６を用いたＰＥＣＶＤなどの化学気相堆積法によって、ｐ型の非晶質シリコン層２０５を形成する。 Thereafter, as illustrated in FIG. 16, a p-type amorphous silicon layer 205 is formed on the lower surface of the tunnel oxide layer 204 (see step ST202 in FIG. 13). In this step, the p-type amorphous silicon layer 205 is formed by a chemical vapor deposition method such as PECVD using SiH 4 or B 2 H 6 .
　この後、図１７に例示されるように、熱処理を行い、ｐ型の結晶系薄膜シリコン層２０６を形成する（図１３におけるステップＳＴ２０３を参照）。 Thereafter, as illustrated in FIG. 17, heat treatment is performed to form a p-type crystalline thin film silicon layer 206 (see step ST203 in FIG. 13).
　また、第１の実施の形態と同様に、ｐ型の結晶系薄膜シリコン層２０６は、ノンドープ非晶質シリコン層を形成した後に、ｐ型のドーパントをドーピングして形成してもよい。また、ＬＰＣＶＤなどの化学気相堆積法によって、ｐ型の結晶系薄膜シリコン層２０６を一工程で形成してもよい。 Similarly to the first embodiment, the p-type crystalline thin film silicon layer 206 may be formed by forming a non-doped amorphous silicon layer and then doping a p-type dopant. Alternatively, the p-type crystalline thin film silicon layer 206 may be formed in one step by a chemical vapor deposition method such as LPCVD.
　次に、図１８に例示されるように、ｎ型の不純物拡散源２０１としてのＰＳＧ膜、および、ＮＳＧ膜２０２をフッ酸で除去した後、ｐ型の結晶系薄膜シリコン層２０６の下面に保護膜２０７を形成する（図１３におけるステップＳＴ２０４を参照）。 Next, as illustrated in FIG. 18, after removing the PSG film as the n-type impurity diffusion source 201 and the NSG film 202 with hydrofluoric acid, the lower surface of the p-type crystalline thin film silicon layer 206 is protected. A film 207 is formed (see step ST204 in FIG. 13).
　その後、図１９に例示されるように、ｎ型の不純物拡散層２０３の上面に誘電体層２０８を形成する。そして、誘電体層２０８の上面に、反射防止膜２０９を形成する（図１３におけるステップＳＴ２０５を参照）。 Thereafter, as illustrated in FIG. 19, a dielectric layer 208 is formed on the upper surface of the n-type impurity diffusion layer 203. Then, an antireflection film 209 is formed on the upper surface of the dielectric layer 208 (see step ST205 in FIG. 13).
　誘電体層２０８として、たとえば、酸化シリコン膜を用いることができる。また、反射防止膜２０９として、たとえば、窒化シリコン膜を用いることができる。 As the dielectric layer 208, for example, a silicon oxide film can be used. As the antireflection film 209, for example, a silicon nitride film can be used.
　最後に、ｐ型の単結晶シリコン基板２００の受光面２００Ａに、受光面電極２１０を形成する。また、ｐ型の結晶系薄膜シリコン層２０６の下面に、裏面電極２１１を形成する（図１３におけるステップＳＴ２０６を参照）。これによって、図１１および図１２に例示された太陽電池が形成される。 Finally, the light receiving surface electrode 210 is formed on the light receiving surface 200A of the p-type single crystal silicon substrate 200. Further, a back electrode 211 is formed on the lower surface of the p-type crystalline thin film silicon layer 206 (see step ST206 in FIG. 13). Thereby, the solar cell illustrated in FIGS. 11 and 12 is formed.
　それぞれの電極は、金属粒子およびガラス粒子を含むペーストをスクリーン印刷法などの塗布法によって櫛形パターン状に塗布し、さらに、それらを乾燥させることによって形成される。 Each electrode is formed by applying a paste containing metal particles and glass particles in a comb pattern by a coating method such as a screen printing method, and drying them.
　上記のペーストの乾燥は、たとえば、２００℃の乾燥オーブン中で１０分程度で行う。乾燥後、受光面電極２１０、および、裏面電極２１１を８００℃程度の高温で同時に熱処理し、焼成する。 The above paste is dried in a drying oven at 200 ° C. for about 10 minutes, for example. After drying, the light-receiving surface electrode 210 and the back surface electrode 211 are simultaneously heat-treated at a high temperature of about 800 ° C. and fired.
　この際、受光面２００Ａ側では、焼成によって、ガラス粒子が受光面２００Ａ側の誘電体層２０８、および、反射防止膜２０９をエッチングする。そして、ｎ型の不純物拡散層２０３が露出し、さらに、受光面電極２１０がｎ型の不純物拡散層２０３に電気的に接続する。 At this time, on the light receiving surface 200A side, the glass particles etch the dielectric layer 208 and the antireflection film 209 on the light receiving surface 200A side by firing. Then, the n-type impurity diffusion layer 203 is exposed, and the light-receiving surface electrode 210 is electrically connected to the n-type impurity diffusion layer 203.
　また、裏面２００Ｂ側においても同様に、ガラス粒子が保護膜２０７をエッチングする。そして、ｐ型の結晶系薄膜シリコン層２０６が露出し、さらに、裏面電極２１１がｐ型の結晶系薄膜シリコン層２０６に電気的に接続する。 Similarly, the glass particles etch the protective film 207 on the back surface 200B side as well. Then, the p-type crystalline thin film silicon layer 206 is exposed, and the back electrode 211 is electrically connected to the p-type crystalline thin film silicon layer 206.
　本実施の形態においても、第１の実施の形態と同様の効果を奏する。それに加えて、本実施の形態においては、ｐ型の単結晶シリコン基板２００を用いたｐ型のセルであるため、ｎ型のセルである場合に比べ、基板が安価である。そのため、製造コストを低減することができる。 Also in this embodiment, the same effects as in the first embodiment can be obtained. In addition, in this embodiment, since the p-type cell uses the p-type single crystal silicon substrate 200, the substrate is less expensive than the n-type cell. Therefore, manufacturing cost can be reduced.
　＜第３の実施の形態＞
　本実施の形態に関する太陽電池、および、太陽電池の製造方法について説明する。以下では、以上に記載された実施の形態で説明された構成と同様の構成については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。 <Third Embodiment>
A solar cell and a method for manufacturing the solar cell according to the present embodiment will be described. In the following, the same components as those described in the embodiment described above are denoted by the same reference numerals and detailed description thereof will be appropriately omitted.
　＜太陽電池の製造方法について＞
　図２０は、本実施の形態に関する太陽電池の製造方法で形成された、太陽電池の構造を概略的に例示する断面図である。また、図２１は、本実施の形態に関する太陽電池の製造方法を例示するフローチャートである。 <About solar cell manufacturing method>
FIG. 20 is a cross-sectional view schematically illustrating the structure of the solar cell formed by the solar cell manufacturing method according to the present embodiment. FIG. 21 is a flowchart illustrating a method for manufacturing a solar cell according to this embodiment.
　また、図２２から図２７は、本実施の形態に関する太陽電池の製造方法を例示する太陽電池の断面図である。 22 to 27 are cross-sectional views of the solar cell illustrating the method for manufacturing the solar cell according to this embodiment.
　本実施の形態では、エミッタ層がｎ型の単結晶シリコン基板１００の裏面１００Ｂに設けられ、裏面電界層がｎ型の単結晶シリコン基板１００の受光面１００Ａに設けられる、バックエミッタ構造の太陽電池が作製される。 In the present embodiment, the back emitter structure solar cell in which the emitter layer is provided on the back surface 100B of the n-type single crystal silicon substrate 100 and the back surface electric field layer is provided on the light receiving surface 100A of the n-type single crystal silicon substrate 100. Is produced.
　本実施の形態の太陽電池の製造方法では、図２２に例示されるように、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに、ｐ型の不純物拡散源１０１としてＢＳＧ膜を形成する。そして、ｐ型の不純物拡散源１０１としてＢＳＧ膜の下面に、キャップ層としてＮＳＧ膜１０２を形成する。 In the method for manufacturing a solar cell according to the present embodiment, a BSG film is formed as a p-type impurity diffusion source 101 on the back surface 100B of the n-type single crystal silicon substrate 100, as illustrated in FIG. Then, an NSG film 102 is formed as a cap layer on the lower surface of the BSG film as the p-type impurity diffusion source 101.
　そして、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに、熱拡散によってｐ型の不純物拡散層１０３を形成する（図２１におけるステップＳＴ３００を参照）。 Then, a p-type impurity diffusion layer 103 is formed on the back surface 100B of the n-type single crystal silicon substrate 100 by thermal diffusion (see step ST300 in FIG. 21).
　次に、図２３に例示されるように、ｎ型の単結晶シリコン基板１００の受光面１００Ａに、トンネル酸化物層１０４を形成する（図２１におけるステップＳＴ３０１を参照）。そして、図２４に例示されるように、トンネル酸化物層１０４の上面に、ｎ型の非晶質シリコン層１０５を形成する（図２１におけるステップＳＴ３０２を参照）。 Next, as illustrated in FIG. 23, a tunnel oxide layer 104 is formed on the light receiving surface 100A of the n-type single crystal silicon substrate 100 (see step ST301 in FIG. 21). Then, as illustrated in FIG. 24, an n-type amorphous silicon layer 105 is formed on the upper surface of the tunnel oxide layer 104 (see step ST302 in FIG. 21).
　その後、熱処理を行い、図２５に例示されるように、ｎ型の非晶質シリコン層１０５からｎ型の結晶系薄膜シリコン層１０６を形成する（図２１におけるステップＳＴ３０３を参照）。 Then, heat treatment is performed to form an n-type crystalline thin film silicon layer 106 from the n-type amorphous silicon layer 105 as illustrated in FIG. 25 (see step ST303 in FIG. 21).
　そして、裏面１００Ｂのｐ型の不純物拡散源１０１であるＢＳＧ膜、および、ＮＳＧ膜１０２をフッ酸で除去した後、図２６に例示されるように、ｎ型の結晶系薄膜シリコン層１０６の上面に保護膜１０７を形成する（図２１におけるステップＳＴ３０４を参照）。 Then, after removing the BSG film as the p-type impurity diffusion source 101 on the back surface 100B and the NSG film 102 with hydrofluoric acid, the upper surface of the n-type crystalline thin film silicon layer 106 is exemplified as shown in FIG. Then, a protective film 107 is formed (see step ST304 in FIG. 21).
　保護膜１０７は、受光面１００Ａに設けられるため、低光吸収材料であることが望ましい。保護膜１０７としては、単層構造体、または、積層構造体であり、太陽光スペクトルに対して最適な反射率となるような材料を選択する。 Since the protective film 107 is provided on the light receiving surface 100A, it is desirable that the protective film 107 be a low light absorption material. As the protective film 107, a material that is a single layer structure or a laminated structure and has an optimum reflectance with respect to the sunlight spectrum is selected.
　また、保護膜１０７の厚さは、太陽光スペクトルに対して最適な反射率となるような厚さを選択する。たとえば、窒化シリコン膜の単層構造体であれば、６０ｎｍ以上、かつ、１００ｎｍ未満の厚さに設計する。 Further, the thickness of the protective film 107 is selected so as to obtain an optimum reflectance with respect to the sunlight spectrum. For example, in the case of a single layer structure of a silicon nitride film, the thickness is designed to be 60 nm or more and less than 100 nm.
　そして、図２７に例示されるように、裏面１００Ｂのｐ型の不純物拡散層１０３の下面に、誘電体層１０８を形成する。また、誘電体層１０８の下面に、反射防止膜１０９を形成する（図２１におけるステップＳＴ３０５を参照）。 Then, as illustrated in FIG. 27, a dielectric layer 108 is formed on the lower surface of the p-type impurity diffusion layer 103 on the back surface 100B. Further, an antireflection film 109 is formed on the lower surface of the dielectric layer 108 (see step ST305 in FIG. 21).
　最後に、保護膜１０７の上面から受光面電極１１０を印刷し、焼成によって受光面電極１１０をｎ型の結晶系薄膜シリコン層１０６にファイアースルーさせてコンタクトを形成する。一方、裏面１００Ｂにも裏面電極１１１を印刷し、焼成によって裏面電極１１１をｐ型の不純物拡散層１０３に電気的に接続させる（図２１におけるステップＳＴ３０６を参照）。 Finally, the light-receiving surface electrode 110 is printed from the upper surface of the protective film 107, and the light-receiving surface electrode 110 is fired through the n-type crystalline thin film silicon layer 106 by baking to form a contact. On the other hand, the back electrode 111 is also printed on the back surface 100B, and the back electrode 111 is electrically connected to the p-type impurity diffusion layer 103 by firing (see step ST306 in FIG. 21).
　本実施の形態においても、第１の実施の形態と同様の効果を奏する。それに加えて、エミッタ層を裏面１００Ｂに形成する構造であるため、エミッタ層の下面に形成されるグリッド電極の遮光ロスを考慮する必要がない。したがって、グリッド電極を狭ピッチ化することができ、エミッタ層の高抵抗化が実現することができるため、パッシベーション効果を向上させることができる。 Also in this embodiment, the same effects as in the first embodiment can be obtained. In addition, since the emitter layer is formed on the back surface 100B, it is not necessary to consider the light shielding loss of the grid electrode formed on the bottom surface of the emitter layer. Therefore, the pitch of the grid electrodes can be reduced, and the resistance of the emitter layer can be increased, so that the passivation effect can be improved.
　＜第４の実施の形態＞
　本実施の形態に関する太陽電池、および、太陽電池の製造方法について説明する。以下では、以上に記載された実施の形態で説明された構成と同様の構成については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。 <Fourth embodiment>
A solar cell and a method for manufacturing the solar cell according to the present embodiment will be described. In the following, the same components as those described in the embodiment described above are denoted by the same reference numerals and detailed description thereof will be appropriately omitted.
　＜太陽電池の構成について＞
　図２８は、本実施の形態に関する太陽電池の製造方法で形成された、太陽電池の構造を概略的を例示する断面図である。また、図２９は、本実施の形態に関する太陽電池の製造方法を例示するフローチャートである。 <About solar cell configuration>
FIG. 28 is a cross-sectional view schematically illustrating the structure of a solar cell formed by the solar cell manufacturing method according to the present embodiment. FIG. 29 is a flowchart illustrating the method for manufacturing the solar cell according to this embodiment.
　本実施の形態に関する太陽電池は、第１の実施の形態における裏面電極１１１の直下のｎ型の単結晶シリコン基板１００に、選択的に不純物が拡散された構造である。 The solar cell according to the present embodiment has a structure in which impurities are selectively diffused in the n-type single crystal silicon substrate 100 immediately below the back surface electrode 111 in the first embodiment.
　＜太陽電池の製造方法について＞
　以下、図２９を参照しつつ、本実施の形態に関する太陽電池の製造方法を詳細に説明する。ここで、図２９は、本実施の形態に関する太陽電池の製造方法を例示するフローチャートである。 <About solar cell manufacturing method>
Hereinafter, the solar cell manufacturing method according to the present embodiment will be described in detail with reference to FIG. Here, FIG. 29 is a flowchart illustrating the method for manufacturing the solar cell according to this embodiment.
　まず、ｎ型の単結晶シリコン基板１００を用意する。ｎ型の単結晶シリコン基板１００は、シリコンインゴットをワイヤーソーなどによる機械的切断法を用いてカット、および、スライスすることによって製造される。そのため、表面には汚染、または、ダメージが残存する場合がある。 First, an n-type single crystal silicon substrate 100 is prepared. The n-type single crystal silicon substrate 100 is manufactured by cutting and slicing a silicon ingot using a mechanical cutting method such as a wire saw. Therefore, contamination or damage may remain on the surface.
　そこで、水酸化ナトリウム溶液などのアルカリ溶液を用いたウェットエッチングプロセスを実施することによって、ｎ型の単結晶シリコン基板１００の表面に、テクスチャ構造と呼ばれる微小な凹凸構造を形成する。テクスチャ構造の形成には、アルカリ溶液、および、添加剤を用いる。 Therefore, a fine concavo-convex structure called a texture structure is formed on the surface of the n-type single crystal silicon substrate 100 by performing a wet etching process using an alkali solution such as a sodium hydroxide solution. An alkaline solution and an additive are used for forming the texture structure.
　ｎ型の単結晶シリコン基板１００の表面における微小な凹凸構造によって、ｎ型の単結晶シリコン基板１００に入射する光が、基板表面で多重反射する。したがって、光の反射損失を低減することができる。加えて、光路長の増加によって光吸収が増大する。その結果、短絡電流の向上が見込める。なお、簡単のため、図面にはテクスチャ構造は示されない。 The light incident on the n-type single crystal silicon substrate 100 undergoes multiple reflections on the substrate surface due to the minute uneven structure on the surface of the n-type single crystal silicon substrate 100. Therefore, the reflection loss of light can be reduced. In addition, light absorption increases with an increase in optical path length. As a result, an improvement in short circuit current can be expected. For simplicity, the texture structure is not shown in the drawing.
　テクスチャ構造を形成した後に、たとえば、過酸化水素をベースに、アルカリまたは酸を加えた濃厚薬液を高温で用いる洗浄方法であるＲＣＡ洗浄、ＳＰＭ洗浄、または、ＨＰＭ洗浄などを行い、ｎ型の単結晶シリコン基板１００の表面に付着している有機物、または、金属汚染などによる付着物を取り除く。 After forming the texture structure, for example, RCA cleaning, SPM cleaning, or HPM cleaning, which is a cleaning method using a concentrated chemical solution containing hydrogen peroxide as a base and an alkali or acid added at a high temperature, is performed. Organic substances adhering to the surface of the crystalline silicon substrate 100 or adhering substances due to metal contamination are removed.
　次に、ｎ型の単結晶シリコン基板１００の受光面１００Ａに、ｐ型の不純物拡散層１０３を形成する（図２９におけるステップＳＴ４００を参照）。 Next, a p-type impurity diffusion layer 103 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100 (see step ST400 in FIG. 29).
　ｎ型の単結晶シリコン基板１００上に、たとえば、ＢＢｒ３を用いた気相反応、または、Ｂ２Ｈ６を用いたＡＰＣＶＤ法などの気相法によって、ｐ型の不純物拡散源１０１としてのＢＳＧ膜を形成する。その後、拡散炉中でボロンを熱拡散することによって、ｐ型の不純物拡散層１０３を形成する。 A BSG as a p-type impurity diffusion source 101 is formed on an n-type single crystal silicon substrate 100 by, for example, a vapor phase reaction using BBr 3 or an APCVD method using B 2 H 6. A film is formed. Thereafter, the p-type impurity diffusion layer 103 is formed by thermally diffusing boron in a diffusion furnace.
　次に、ｐ型の不純物拡散層１０３を形成した後に、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに、ｎ型の不純物拡散領域１１２を選択的に形成する（図２９におけるステップＳＴ４０７を参照）。ｎ型の不純物拡散領域１１２は、後述する裏面電極１１１が形成される領域に対応する位置、たとえば、平面視において裏面電極１１１が形成される領域と少なくとも一部が重なる領域に形成される。 Next, after forming the p-type impurity diffusion layer 103, the n-type impurity diffusion region 112 is selectively formed on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST407 in FIG. 29). . The n-type impurity diffusion region 112 is formed at a position corresponding to a region where a back electrode 111 described later is formed, for example, a region at least partially overlapping with a region where the back electrode 111 is formed in plan view.
　ｎ型の不純物拡散領域１１２の形成方法の一例としては、ペースト中にリン原子を含むドーパントペーストを用いる方法がある。 An example of a method for forming the n-type impurity diffusion region 112 is a method using a dopant paste containing phosphorus atoms in the paste.
　まず、ｎ型の単結晶シリコン基板１００の、ｐ型の不純物拡散層１０３が形成された面とは反対側の裏面１００Ｂに、ドーパントペーストをスクリーン印刷する。 First, a dopant paste is screen-printed on the back surface 100B of the n-type single crystal silicon substrate 100 opposite to the surface on which the p-type impurity diffusion layer 103 is formed.
　ドーパントペーストを印刷する領域は、後に裏面電極１１１を印刷する領域とする。ドーパントペーストを印刷する領域の幅は、裏面電極１１１を印刷した際の裏面電極１１１のアライメントのずれを考慮して、裏面電極１１１の形成幅よりも広く設計する。 The region where the dopant paste is printed is a region where the back electrode 111 is printed later. The width of the region where the dopant paste is printed is designed wider than the formation width of the back electrode 111 in consideration of misalignment of the back electrode 111 when the back electrode 111 is printed.
　ドーパントペーストを印刷した後は、ドーパントペースト中の有機溶媒を取り除くために熱乾燥を行う。その後、拡散炉において、たとえば、７００℃以上の温度でアニールすることによって、印刷されたドーパントペーストからｎ型の単結晶シリコン基板１００へリン原子を拡散させる。 After printing the dopant paste, heat drying is performed to remove the organic solvent in the dopant paste. Then, phosphorus atoms are diffused from the printed dopant paste into the n-type single crystal silicon substrate 100 by annealing at a temperature of 700 ° C. or higher, for example, in a diffusion furnace.
　その後、ドーパントペーストを除去するために、ｎ型の単結晶シリコン基板１００をフッ酸溶液に浸漬する。ｐ型の不純物拡散層１０３の形成する際に生じるＢＳＧ膜は、この時に同時に除去することができる。 Thereafter, in order to remove the dopant paste, the n-type single crystal silicon substrate 100 is immersed in a hydrofluoric acid solution. The BSG film generated when the p-type impurity diffusion layer 103 is formed can be removed at this time.
　以上の工程によって、ｎ型の不純物拡散領域１１２を選択的に形成することができる。 Through the above steps, the n-type impurity diffusion region 112 can be selectively formed.
　次に、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに、トンネル酸化物層１０４を形成する（図２９におけるステップＳＴ４０１を参照）。 Next, a tunnel oxide layer 104 is formed on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST401 in FIG. 29).
　トンネル酸化物層１０４の材料には、シリコン酸化膜、または、酸化アルミニウム膜などの誘電体材料を用いることができる。シリコン酸化膜の形成は、たとえば、オゾン水への浸漬によって行うことができる。この場合、所望の厚さの酸化膜が得られるように、オゾン濃度、および、浸漬時間を制御する。 As the material of the tunnel oxide layer 104, a dielectric material such as a silicon oxide film or an aluminum oxide film can be used. The silicon oxide film can be formed by, for example, immersion in ozone water. In this case, the ozone concentration and the immersion time are controlled so that an oxide film having a desired thickness is obtained.
　また、シリコン酸化膜の形成には、熱酸化、硝酸酸化、ＰＥＣＶＤ法、ＡＬＤ法、ＵＶ照射、または、オゾン照射などの方法も用いることができる。 Also, a method such as thermal oxidation, nitric acid oxidation, PECVD method, ALD method, UV irradiation, or ozone irradiation can be used for forming the silicon oxide film.
　トンネル酸化物層１０４の膜厚は、たとえば、０．５ｎｍ以上、かつ、５ｎｍ未満である。トンネル酸化物層１０４の膜厚が薄すぎると、多数キャリアのみならず少数キャリアもトンネル酸化物層１０４を通過してしまう。そのため、再結合の増加によって開放電圧が低下する。また、トンネル酸化物層１０４の膜厚が厚すぎる場合であっても、多数キャリアのトンネル輸送が妨げられる。そのため、直列抵抗が増加することによって、電気的特性が劣化する。 The film thickness of the tunnel oxide layer 104 is, for example, 0.5 nm or more and less than 5 nm. When the tunnel oxide layer 104 is too thin, not only majority carriers but also minority carriers pass through the tunnel oxide layer 104. Therefore, the open circuit voltage decreases due to the increase in recombination. Even when the tunnel oxide layer 104 is too thick, tunneling of majority carriers is hindered. Therefore, the electrical characteristics are deteriorated by increasing the series resistance.
　次に、トンネル酸化物層１０４の下面にｎ型の非晶質シリコン層１０５を形成する（図２９におけるステップＳＴ４０２を参照）。ＳｉＨ４、または、ＰＨ３を用いたＰＥＣＶＤ法などの化学気相堆積法によって、ｎ型の非晶質シリコン層１０５を形成する。 Next, an n-type amorphous silicon layer 105 is formed on the lower surface of the tunnel oxide layer 104 (see step ST402 in FIG. 29). An n-type amorphous silicon layer 105 is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 or PH 3 .
　ｎ型の非晶質シリコン層１０５の膜厚は、たとえば、５ｎｍ以上、かつ、１００ｎｍ未満である。ｎ型の非晶質シリコン層１０５の膜厚が薄すぎると、電界効果が弱くなる。そして、トンネル接合層における電気的抵抗が増大し、かつ、少数キャリアの追い返し効果も小さくなる。そのため、ｎ型の非晶質シリコン層１０５の特性が劣化する。 The film thickness of the n-type amorphous silicon layer 105 is, for example, 5 nm or more and less than 100 nm. When the thickness of the n-type amorphous silicon layer 105 is too thin, the field effect is weakened. In addition, the electrical resistance in the tunnel junction layer increases, and the minority carrier repulsion effect decreases. Therefore, the characteristics of the n-type amorphous silicon layer 105 deteriorate.
　一方、ｎ型の非晶質シリコン層１０５の膜厚が厚いと、熱歪みが大きくなる。そのため、ｎ型の非晶質シリコン層１０５の膜厚が適正な範囲である場合に比べて、シリコン層のパッシベーション効果が低下することが分かっている。 On the other hand, when the thickness of the n-type amorphous silicon layer 105 is large, the thermal strain increases. For this reason, it is known that the passivation effect of the silicon layer is reduced as compared with the case where the film thickness of the n-type amorphous silicon layer 105 is in an appropriate range.
　その後、形成された構造を拡散炉に導入し、窒素ガスを流しながら昇温する。そして、一定温度で一定時間保持して、熱処理を行う（図２９におけるステップＳＴ４０３を参照）。 Then, the formed structure is introduced into a diffusion furnace, and the temperature is raised while flowing nitrogen gas. Then, heat treatment is performed by holding at a constant temperature for a certain time (see step ST403 in FIG. 29).
　これによって、ｎ型の非晶質シリコン層１０５の一部、または、全体が結晶化し、ｎ型の結晶系薄膜シリコン層１０６に変化する。ｎ型の結晶系薄膜シリコン層１０６の膜厚は、たとえば、５ｎｍ以上、かつ、１００ｎｍ未満である。また、上記の熱処理によって、ｎ型の非晶質シリコン層１０５中のｎ型のドーパントが活性化する。そうすることによって、シート抵抗が低下する。 Thereby, a part or the whole of the n-type amorphous silicon layer 105 is crystallized to be changed into the n-type crystalline thin film silicon layer 106. The film thickness of the n-type crystalline thin film silicon layer 106 is, for example, 5 nm or more and less than 100 nm. In addition, the n-type dopant in the n-type amorphous silicon layer 105 is activated by the heat treatment. By doing so, the sheet resistance decreases.
　最適なアニール温度は、シリコンドープ層に含まれるリン濃度、または、シリコンドープ層の厚さによって異なる。ここで、ｎ型の非晶質シリコン層１０５の熱処理時における最も高い温度であるピーク温度は、４００℃以上、かつ、９００℃未満である。 The optimum annealing temperature varies depending on the phosphorus concentration contained in the silicon doped layer or the thickness of the silicon doped layer. Here, the peak temperature, which is the highest temperature during the heat treatment of the n-type amorphous silicon layer 105, is 400 ° C. or higher and lower than 900 ° C.
　熱処理温度が低いと、ｎ型の非晶質シリコン層１０５の結晶化が十分に促進されない。そのため、裏面１００Ｂにおける電界効果が低下し、高いパッシベーション効果を得られない。また、ｎ型の非晶質シリコン層１０５が高抵抗となるため、多数キャリアの輸送が妨げられる恐れがある。なお、熱処理温度が４００℃を超える場合には、ｎ型の非晶質シリコン層１０５中から水素が脱離し始めるため、結晶化が促進される。 If the heat treatment temperature is low, the crystallization of the n-type amorphous silicon layer 105 is not sufficiently promoted. Therefore, the electric field effect on the back surface 100B is reduced, and a high passivation effect cannot be obtained. In addition, since the n-type amorphous silicon layer 105 has a high resistance, transport of majority carriers may be hindered. Note that when the heat treatment temperature exceeds 400 ° C., hydrogen begins to be desorbed from the n-type amorphous silicon layer 105, so that crystallization is promoted.
　一方、熱処理温度が９００℃を超えると、リン濃度に関係なくパッシベーション効果が著しく低下し始める。したがって、開放電圧の低下につながる。 On the other hand, when the heat treatment temperature exceeds 900 ° C., the passivation effect starts to decrease remarkably regardless of the phosphorus concentration. Therefore, the open circuit voltage is reduced.
　これは、高温の熱処理によってｎ型の非晶質シリコン層１０５中のｎ型のドーパントがトンネル酸化物層１０４を貫通してｎ型の単結晶シリコン基板１００にまで多量に拡散することによって、トンネル酸化物層１０４の構造破壊、または、ｎ型の非晶質シリコン層１０５からドーパントが拡散してしまうことによって、ｎ型の結晶系薄膜シリコン層１０６となった場合であっても電界効果の低下が起きるためである。 This is because the n-type dopant in the n-type amorphous silicon layer 105 penetrates the tunnel oxide layer 104 and diffuses to the n-type single crystal silicon substrate 100 in a large amount by high-temperature heat treatment. Even if the n-type crystalline thin film silicon layer 106 is formed due to the structural breakdown of the oxide layer 104 or the diffusion of the dopant from the n-type amorphous silicon layer 105, the field effect is reduced. This is because it happens.
　なお、ｎ型の結晶系薄膜シリコン層１０６は、ノンドープ（真性）非晶質シリコン層を形成した後に、ｎ型のドーパントを拡散させて形成してもよい。その場合、ステップＳＴ４０２において、ＳｉＨ４を用いたＰＥＣＶＤ法などの化学気相堆積法によって、ノンドープ非晶質シリコン層を形成する。その後、ステップＳＴ４０３において、ＰＯＣｌ３を用いた気相反応および熱拡散、または、リンのイオン注入および熱拡散によって、ｎ型のドーパントをノンドープ非晶質シリコン層中に拡散させる。 The n-type crystalline thin film silicon layer 106 may be formed by diffusing an n-type dopant after forming a non-doped (intrinsic) amorphous silicon layer. In that case, in step ST402, a non-doped amorphous silicon layer is formed by a chemical vapor deposition method such as a PECVD method using SiH 4 . Thereafter, in step ST403, an n-type dopant is diffused into the non-doped amorphous silicon layer by gas phase reaction and thermal diffusion using POCl 3 or phosphorus ion implantation and thermal diffusion.
　また、ｎ型の結晶系薄膜シリコン層１０６は、ＳｉＨ４、および、ＰＨ３を用いたＬＰＣＶＤ法などの化学気相堆積法によって、一工程で形成してもよい。その場合、たとえば、５００℃以上の温度でｎ型の結晶系薄膜シリコン層１０６の成膜を行い、成膜後の熱処理は必要に応じて行えばよい。 Further, the n-type crystalline thin film silicon layer 106 may be formed in one step by a chemical vapor deposition method such as an LPCVD method using SiH 4 and PH 3 . In that case, for example, the n-type crystalline thin film silicon layer 106 may be formed at a temperature of 500 ° C. or higher, and heat treatment after the film formation may be performed as necessary.
　次に、ｎ型の単結晶シリコン基板１００の受光面１００Ａに形成されたｐ型の不純物拡散源１０１であるＢＳＧ膜、および、ＮＳＧ膜１０２を、フッ酸を用いて完全に除去する。 Next, the BSG film as the p-type impurity diffusion source 101 and the NSG film 102 formed on the light receiving surface 100A of the n-type single crystal silicon substrate 100 are completely removed using hydrofluoric acid.
　本工程は、ステップＳＴ４０３の熱処理工程前に行うことも可能である。その場合、熱処理中にｐ型の不純物拡散源１０１であるＢＳＧ膜からボロンが雰囲気中に拡散することによって、当該ボロンがｎ型の非晶質シリコン層１０５に付着し、さらに、拡散することを防ぐことができる。 This step can be performed before the heat treatment step of step ST403. In that case, boron diffuses into the atmosphere from the BSG film as the p-type impurity diffusion source 101 during the heat treatment, so that the boron adheres to the n-type amorphous silicon layer 105 and further diffuses. Can be prevented.
　一方で、ｎ型の非晶質シリコン層１０５からｎ型のドーパントが雰囲気中に拡散し、ｐ型の不純物拡散層１０３中に拡散してしまう可能性がある。ただし、ｐ型の不純物拡散源１０１であるＢＳＧ膜の上面にはキャップ層であるＮＳＧ膜１０２が形成されており、ボロンがｎ型の非晶質シリコン層１０５中に拡散する可能性の方が低いため、ステップＳＴ４０３の熱処理後にＢＳＧ膜、および、ＮＳＧ膜１０２を除去することが好ましい。 On the other hand, the n-type dopant may diffuse from the n-type amorphous silicon layer 105 into the atmosphere and diffuse into the p-type impurity diffusion layer 103. However, the NSG film 102 which is a cap layer is formed on the upper surface of the BSG film which is the p-type impurity diffusion source 101, and there is a possibility that boron may diffuse into the n-type amorphous silicon layer 105. Therefore, it is preferable to remove the BSG film and the NSG film 102 after the heat treatment in step ST403.
　次に、ｎ型の単結晶シリコン基板１００の裏面１００Ｂにおけるｎ型の結晶系薄膜シリコン層１０６の下面に、保護膜１０７を形成する（図２９におけるステップＳＴ４０４を参照）。 Next, a protective film 107 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 on the back surface 100B of the n-type single crystal silicon substrate 100 (see step ST404 in FIG. 29).
　保護膜１０７の材料は、たとえば、窒化シリコン、酸化シリコン、窒酸化シリコン、非晶質シリコン、または、微結晶シリコンなどである。また、保護膜１０７は、複数の膜の積層構造であってもよい。 The material of the protective film 107 is, for example, silicon nitride, silicon oxide, silicon nitride oxide, amorphous silicon, or microcrystalline silicon. Further, the protective film 107 may have a stacked structure of a plurality of films.
　ここで、保護膜１０７は、シリコンドープ層であるｎ型の結晶系薄膜シリコン層１０６よりも高い硬度を有することが好ましい。これは、保護膜１０７上に電極をスクリーン印刷する際、版との接触または摩擦などによる物理ダメージからｎ型の結晶系薄膜シリコン層１０６を保護するためである。 Here, the protective film 107 preferably has a higher hardness than the n-type crystalline thin film silicon layer 106 which is a silicon doped layer. This is to protect the n-type crystalline thin film silicon layer 106 from physical damage due to contact with the plate or friction when electrodes are screen-printed on the protective film 107.
　また、保護膜１０７の膜中水素濃度は、ｎ型の結晶系薄膜シリコン層１０６中の水素濃度よりも高いことが好ましい。保護膜１０７中に十分な水素が含まれていると、熱処理時、および、電極焼成時に当該水素が脱離する。そして、形成されたｎ型の結晶系薄膜シリコン層１０６中、および、トンネル酸化物層１０４と単結晶シリコン基板１００との界面のダングリングボンドが、保護膜１０７中から脱離した水素によって終端される。これによって、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果、および、トンネル酸化物層１０４のパッシベーション効果が向上する。 The hydrogen concentration in the protective film 107 is preferably higher than the hydrogen concentration in the n-type crystalline thin silicon layer 106. If the protective film 107 contains sufficient hydrogen, the hydrogen is desorbed during heat treatment and electrode firing. Then, dangling bonds in the formed n-type crystalline thin film silicon layer 106 and the interface between the tunnel oxide layer 104 and the single crystal silicon substrate 100 are terminated by hydrogen desorbed from the protective film 107. The This improves the passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104.
　また、保護膜１０７の膜厚は、たとえば、５ｎｍ以上、かつ、２００ｎｍ未満であることが好ましい。保護膜１０７の膜厚が薄すぎると、電極が焼成時にｎ型の結晶系薄膜シリコン層１０６を突き抜けてｎ型の単結晶シリコン基板１００を浸食することを防げない。また、保護膜１０７の膜厚が薄すぎると、保護膜１０７から十分な水素を供給することができないため、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果が低下してしまう。 The film thickness of the protective film 107 is preferably, for example, 5 nm or more and less than 200 nm. If the film thickness of the protective film 107 is too thin, it cannot be prevented that the electrode penetrates the n-type crystalline thin film silicon layer 106 and erodes the n-type single crystal silicon substrate 100 during firing. If the thickness of the protective film 107 is too thin, sufficient hydrogen cannot be supplied from the protective film 107, so that the passivation effect of the n-type crystalline thin film silicon layer 106 is reduced.
　一方で、保護膜１０７の膜厚が厚すぎる場合であっても、電極がｎ型の結晶系薄膜シリコン層１０６に接触しにくくなるため、コンタクト抵抗が増大してしまう。 On the other hand, even if the protective film 107 is too thick, the electrode is less likely to contact the n-type crystalline thin film silicon layer 106, and the contact resistance increases.
　次に、ｎ型の単結晶シリコン基板１００の受光面１００Ａにおけるｐ型の不純物拡散層１０３の上面に、受光面１００Ａ側の誘電体層１０８を形成する。そして、誘電体層１０８の上面に、反射防止膜１０９を形成する（図２９におけるステップＳＴ４０５を参照）。 Next, a dielectric layer 108 on the light receiving surface 100A side is formed on the upper surface of the p-type impurity diffusion layer 103 in the light receiving surface 100A of the n-type single crystal silicon substrate 100. Then, an antireflection film 109 is formed on the upper surface of the dielectric layer 108 (see step ST405 in FIG. 29).
　誘電体層１０８として、たとえば、酸化膜を用いることができる。また、誘電体層１０８として、たとえば、ＡＬＤ、または、ＣＶＤ法によって形成される酸化アルミニウム膜などの誘電体層を用いることができる。特に、酸化アルミニウム膜は負の固定電荷を有しているため、ｐ型の不純物拡散層１０３に対して優れたパッシベーション効果を発揮することが知られている。誘電体層１０８の膜厚は、たとえば、２ｎｍ以上、かつ、５０ｎｍ未満である。 As the dielectric layer 108, for example, an oxide film can be used. Further, as the dielectric layer 108, for example, a dielectric layer such as an ALD or an aluminum oxide film formed by a CVD method can be used. In particular, since the aluminum oxide film has a negative fixed charge, it is known to exhibit an excellent passivation effect for the p-type impurity diffusion layer 103. The film thickness of the dielectric layer 108 is, for example, 2 nm or more and less than 50 nm.
　誘電体層１０８の上面には、反射防止膜１０９を形成する。反射防止膜１０９として、たとえば、プラズマＣＶＤ法によって形成される窒化シリコン膜を用いる。反射防止膜１０９の膜厚は、誘電体層１０８の厚さに応じて、太陽光スペクトルに対して最適な膜厚、たとえば、３０ｎｍ以上、かつ、８０ｎｍ未満程度の膜厚に設計する。 An antireflection film 109 is formed on the upper surface of the dielectric layer 108. As the antireflection film 109, for example, a silicon nitride film formed by a plasma CVD method is used. The film thickness of the antireflection film 109 is designed to be an optimal film thickness for the solar spectrum, for example, about 30 nm or more and less than 80 nm according to the thickness of the dielectric layer 108.
　最後に、ｎ型の単結晶シリコン基板１００の受光面１００Ａに、受光面電極１１０を形成する。また、ｎ型の結晶系薄膜シリコン層１０６の下面に、裏面電極１１１を形成する（図２９におけるステップＳＴ４０６を参照）。これによって、図１および図２に例示された太陽電池が形成される。 Finally, the light-receiving surface electrode 110 is formed on the light-receiving surface 100A of the n-type single crystal silicon substrate 100. Further, the back electrode 111 is formed on the lower surface of the n-type crystalline thin film silicon layer 106 (see step ST406 in FIG. 29). Thereby, the solar cell illustrated in FIGS. 1 and 2 is formed.
　それぞれの電極は、金属粒子およびガラス粒子を含むペーストをスクリーン印刷法などの塗布法によって、まず、それぞれ反射防止膜１０９上および保護膜１０７上に櫛形パターン状に塗布する。そして、さらに、それらを乾燥させることによって形成される。 For each electrode, a paste containing metal particles and glass particles is first applied in a comb pattern on the antireflection film 109 and the protective film 107 by a coating method such as a screen printing method. Further, they are formed by drying them.
　ここで、ガラス粒子の含有量は、金属粒子の重量に基づいて、０．５重量％以上、かつ、１０．０重量％以下、好ましくは、１．０重量％以上、かつ、３．０重量％以下である。 Here, the content of the glass particles is 0.5 wt% or more and 10.0 wt% or less, preferably 1.0 wt% or more and 3.0 wt% based on the weight of the metal particles. % Or less.
　上記のペーストの乾燥は、たとえば、２００℃の乾燥オーブン中で１０分程度で行う。乾燥後、受光面電極１１０、および、裏面電極１１１を８００℃程度の高温で同時に熱処理し、焼成する。 The above paste is dried in a drying oven at 200 ° C. for about 10 minutes, for example. After drying, the light-receiving surface electrode 110 and the back surface electrode 111 are simultaneously heat-treated at a high temperature of about 800 ° C. and fired.
　この際、受光面１００Ａ側では、焼成によって、ガラス粒子が受光面１００Ａ側の誘電体層１０８、および、反射防止膜１０９をエッチングする。そして、ｐ型の不純物拡散層１０３が露出し、さらに、受光面電極１１０がｐ型の不純物拡散層１０３に電気的に接続する。 At this time, on the light receiving surface 100A side, the glass particles etch the dielectric layer 108 on the light receiving surface 100A side and the antireflection film 109 by firing. Then, the p-type impurity diffusion layer 103 is exposed, and the light-receiving surface electrode 110 is electrically connected to the p-type impurity diffusion layer 103.
　また、裏面１００Ｂ側においても同様に、ガラス粒子が保護膜１０７をエッチングする。そして、ｎ型の結晶系薄膜シリコン層１０６が露出し、さらに、裏面電極１１１がｎ型の結晶系薄膜シリコン層１０６に電気的に接続する。 Similarly, the glass particles etch the protective film 107 also on the back surface 100B side. Then, the n-type crystalline thin film silicon layer 106 is exposed, and the back electrode 111 is electrically connected to the n-type crystalline thin film silicon layer 106.
　また、不純物拡散領域１１２は、イオンインプランテーション法を用いて形成することによって、上記のドーパントペーストによる形成時の熱拡散または洗浄などの工程を省略することができる。 Further, the impurity diffusion region 112 can be formed by using the ion implantation method, so that steps such as thermal diffusion or cleaning at the time of formation with the above-described dopant paste can be omitted.
　また、不純物拡散領域１１２の他の形成方法としては、たとえば、ＰＯＣｌ３、または、ＡＰＣＶＤによってＰＳＧ膜をｎ型の単結晶シリコン基板１００の裏面１００Ｂに形成し、その上から、不純物拡散領域１１２を形成したい領域にレーザーをスキャンする方法がある。当該方法は、局所的にｎ型の単結晶シリコン基板１００を加熱することによって、不純物を拡散させるレーザードーピング法である。 As another method for forming the impurity diffusion region 112, a PSG film is formed on the back surface 100B of the n-type single crystal silicon substrate 100 by, for example, POCl3 or APCVD, and the impurity diffusion region 112 is formed thereon. There is a way to scan the laser in the area you want. This method is a laser doping method in which impurities are diffused by locally heating the n-type single crystal silicon substrate 100.
　図３０は、以上のような方法で製造された太陽電池の開放電圧特性を例示する図である。 FIG. 30 is a diagram illustrating the open-circuit voltage characteristics of the solar cell manufactured by the method as described above.
　図３０では、本実施の形態に関する太陽電池Ｃの比較例として、第１の実施の形態の構成と同様である不純物拡散領域１１２が形成されていない場合の太陽電池Ａと、不純物拡散領域がｎ型の単結晶シリコン基板１００の裏面１００Ｂに均等に形成されている場合の太陽電池Ｂとを、同時に作製し評価する。 In FIG. 30, as a comparative example of the solar cell C relating to the present embodiment, the solar cell A when the impurity diffusion region 112 which is the same as the configuration of the first embodiment is not formed, and the impurity diffusion region is n A solar cell B in the case where it is uniformly formed on the back surface 100B of the single crystal silicon substrate 100 of the type is simultaneously produced and evaluated.
　本実施の形態に関する太陽電池Ｃは、開放電圧値が７２６ｍＶであった。当該値は、太陽電池Ａ、太陽電池Ｂ、および、太陽電池Ｃの中で最も高い値であった。一方で、不純物拡散領域がｎ型の単結晶シリコン基板１００の裏面１００Ｂに均等に形成されている場合の太陽電池Ｂにおいても、第１の実施の形態の構成と同様である不純物拡散領域１１２が形成されていない場合の太陽電池Ａと比較して、高い開放電圧値が得られた。 Solar cell C related to the present embodiment had an open circuit voltage value of 726 mV. The said value was the highest value in the solar cell A, the solar cell B, and the solar cell C. On the other hand, also in the solar cell B when the impurity diffusion regions are uniformly formed on the back surface 100B of the n-type single crystal silicon substrate 100, the impurity diffusion region 112 similar to the configuration of the first embodiment is provided. A higher open-circuit voltage value was obtained as compared with the solar cell A when it was not formed.
　これらの結果は、保護膜１０７によって完全に緩和することのできなかったｎ型の単結晶シリコン基板１００へのダメージも、不純物拡散領域１１２によって緩和できていることを示している。 These results indicate that the damage to the n-type single crystal silicon substrate 100 that could not be completely mitigated by the protective film 107 can also be mitigated by the impurity diffusion region 112.
　不純物拡散領域１１２を設けることによって、少数キャリアがｎ型の単結晶シリコン基板１００側へ追い返される。したがって、焼成する際に、一部でｎ型の単結晶シリコン基板１００に侵食していた電極の、近傍におけるキャリア再結合は減少する。 By providing the impurity diffusion region 112, minority carriers are driven back to the n-type single crystal silicon substrate 100 side. Therefore, carrier recombination in the vicinity of the electrode partially eroded by the n-type single crystal silicon substrate 100 during firing is reduced.
　また、不純物拡散領域がｎ型の単結晶シリコン基板１００の裏面１００Ｂに均等に形成されている場合では、不純物の拡散領域においてはオージェ再結合が増加する。そのため、不純物の拡散領域は、裏面電極１１１の直下のみに選択的に形成されていることが好ましい。これらのことから、不純物拡散領域１１２を備える太陽電池Ｂにおいて、最も高い開放電圧値が得られる。 Further, when the impurity diffusion region is formed uniformly on the back surface 100B of the n-type single crystal silicon substrate 100, Auger recombination increases in the impurity diffusion region. Therefore, it is preferable that the impurity diffusion region is selectively formed only directly below the back electrode 111. For these reasons, the highest open-circuit voltage value is obtained in the solar cell B including the impurity diffusion region 112.
　＜以上に記載された実施の形態によって生じる効果について＞
　以下に、以上に記載された実施の形態によって生じる効果を例示する。なお、以下では、以上に記載された実施の形態に例示された具体的な構成に基づいて当該効果が記載されるが、同様の効果が生じる範囲で、本願明細書に例示される他の具体的な構成と置き換えられてもよい。 <About the effects produced by the embodiment described above>
Below, the effect produced by embodiment described above is illustrated. In the following, the effect will be described based on the specific configuration exemplified in the embodiment described above, but other specific examples exemplified in the present specification within the scope of the similar effect. It may be replaced with a typical configuration.
　また、当該置き換えは、複数の実施の形態に跨ってなされてもよい。すなわち、異なる実施の形態において例示されたそれぞれの構成が組み合わされて、同様の効果が生じる場合であってもよい。 Also, the replacement may be made across a plurality of embodiments. In other words, the configurations exemplified in different embodiments may be combined to produce the same effect.
　以上に記載された実施の形態によれば、太陽電池は、トンネル酸化物層１０４と、第１の導電型の半導体層と、保護膜１０７と、電極とを備える。ここで、ｎ型の結晶系薄膜シリコン層１０６は、第１の導電型の半導体層に対応するものである。また、裏面電極１１１は、電極に対応するものである。トンネル酸化物層１０４は、半導体基板上、たとえば、半導体基板の裏面に形成される。ここで、ｎ型の単結晶シリコン基板１００は、半導体基板に対応するものである。ｎ型の結晶系薄膜シリコン層１０６は、トンネル酸化物層１０４上、たとえば、トンネル酸化物層１０４の下面に形成される。保護膜１０７は、ｎ型の結晶系薄膜シリコン層１０６上、たとえば、ｎ型の結晶系薄膜シリコン層１０６の下面に形成される。裏面電極１１１は、保護膜１０７上から保護膜１０７を貫通し、かつ、ｎ型の結晶系薄膜シリコン層１０６に接触して形成される。そして、裏面電極１１１は、ガラス粒子を含む焼成電極である。 According to the embodiment described above, the solar cell includes the tunnel oxide layer 104, the first conductive type semiconductor layer, the protective film 107, and the electrode. Here, the n-type crystalline thin film silicon layer 106 corresponds to the first conductive type semiconductor layer. The back electrode 111 corresponds to an electrode. The tunnel oxide layer 104 is formed on the semiconductor substrate, for example, on the back surface of the semiconductor substrate. Here, the n-type single crystal silicon substrate 100 corresponds to a semiconductor substrate. The n-type crystalline thin film silicon layer 106 is formed on the tunnel oxide layer 104, for example, on the lower surface of the tunnel oxide layer 104. The protective film 107 is formed on the n-type crystalline thin film silicon layer 106, for example, on the lower surface of the n-type crystalline thin film silicon layer 106. The back electrode 111 is formed through the protective film 107 from above the protective film 107 and in contact with the n-type crystalline thin film silicon layer 106. The back electrode 111 is a fired electrode containing glass particles.
　このような構成によれば、焼成によって裏面電極１１１を形成する場合において、ｎ型の結晶系薄膜シリコン層１０６上に形成された保護膜１０７が、焼成される裏面電極１１１によってｎ型の結晶系薄膜シリコン層１０６が突き破られること、さらには、ｎ型の結晶系薄膜シリコン層１０６を突き破った裏面電極１１１がｎ型の単結晶シリコン基板１００にまで到達することを防ぐことができる。したがって、トンネル酸化物層１０４、および、ｎ型の結晶系薄膜シリコン層１０６を含むトンネル接合層の浸食ダメージ、印刷ダメージ、または、電流ロスなどの特性低下を抑制することができる。また、保護膜１０７が、熱処理、または、焼成によってｎ型の結晶系薄膜シリコン層１０６、トンネル酸化物層１０４、および、単結晶シリコン基板１００から水素が多量に脱離することを抑制することによって、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果、および、トンネル酸化物層１０４のパッシベーション効果が低下することを抑制する。これらによって、量産性、および、信頼性の高い太陽電池を製造することができる。また、保護膜１０７が高温処理にも耐えうるため、製造プロセスが限定されない。また、焼成によって、信頼性が高く、かつ、低抵抗である銀電極を形成することができるため、太陽電池の変換効率の向上を実現することができる。 According to such a configuration, when the back electrode 111 is formed by firing, the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100. Therefore, deterioration of characteristics such as erosion damage, printing damage, or current loss of the tunnel junction layer including the tunnel oxide layer 104 and the n-type crystalline thin film silicon layer 106 can be suppressed. In addition, the protective film 107 suppresses the release of a large amount of hydrogen from the n-type crystalline thin film silicon layer 106, the tunnel oxide layer 104, and the single crystal silicon substrate 100 by heat treatment or baking. , The passivation effect of the n-type crystalline thin film silicon layer 106 and the passivation effect of the tunnel oxide layer 104 are suppressed from decreasing. By these, a solar cell with high productivity and high reliability can be manufactured. In addition, since the protective film 107 can withstand high temperature treatment, the manufacturing process is not limited. In addition, since the silver electrode having high reliability and low resistance can be formed by firing, the conversion efficiency of the solar cell can be improved.
　なお、これらの構成以外の本願明細書に例示される他の構成については適宜省略することができる。すなわち、これらの構成のみで、以上に記載された効果を生じさせることができる。 It should be noted that other configurations exemplified in the present specification other than these configurations can be omitted as appropriate. In other words, the effects described above can be produced only with these configurations.
　しかしながら、本願明細書に例示される他の構成のうちの少なくとも１つを以上に記載された構成に適宜追加した場合、すなわち、以上に記載された構成としては記載されなかった本願明細書に例示される他の構成を以上に記載された構成に追加した場合でも、同様に以上に記載された効果を生じさせることができる。 However, when at least one of the other configurations exemplified in the present specification is appropriately added to the configuration described above, that is, the configuration described above is not exemplified as the configuration described above. Even when other configurations described above are added to the configurations described above, the effects described above can be similarly produced.
　また、以上に記載された実施の形態によれば、ｎ型の結晶系薄膜シリコン層１０６の膜厚が、５ｎｍ以上、かつ、１００ｎｍ未満である。このような構成によれば、ｎ型の結晶系薄膜シリコン層１０６が適正な膜厚であることによって、電極のｎ型の単結晶シリコン基板１００への浸食を防ぐことができる。また、ｎ型の結晶系薄膜シリコン層１０６が、高いパッシベーション効果を得ることができる。 Further, according to the embodiment described above, the film thickness of the n-type crystalline thin film silicon layer 106 is 5 nm or more and less than 100 nm. According to such a configuration, since the n-type crystalline thin film silicon layer 106 has an appropriate film thickness, erosion of the electrode to the n-type single crystal silicon substrate 100 can be prevented. Further, the n-type crystalline thin film silicon layer 106 can obtain a high passivation effect.
　また、以上に記載された実施の形態によれば、保護膜１０７の膜厚が、５ｎｍ以上、かつ、２００ｎｍ未満である。このような構成によれば、保護膜１０７の膜厚が５ｎｍ以上であることによって、電極が焼成時に、ｎ型の結晶系薄膜シリコン層１０６を突き抜けてｎ型の単結晶シリコン基板１００へ浸食することを抑制することができる。また、保護膜１０７の膜厚が２００ｎｍ未満であることによって、ファイアースルー性を損なわず、直列抵抗の増加を抑えることができる。 Further, according to the embodiment described above, the thickness of the protective film 107 is 5 nm or more and less than 200 nm. According to such a configuration, when the thickness of the protective film 107 is 5 nm or more, the electrode penetrates the n-type crystalline thin film silicon layer 106 and erodes into the n-type single crystal silicon substrate 100 during firing. This can be suppressed. Moreover, when the film thickness of the protective film 107 is less than 200 nm, an increase in series resistance can be suppressed without impairing the fire-through property.
　また、以上に記載された実施の形態によれば、保護膜１０７の硬度が、ｎ型の結晶系薄膜シリコン層１０６の硬度よりも高い。このような構成によれば、保護膜１０７上に電極をスクリーン印刷する際、版との接触または摩擦などによる物理的なダメージからｎ型の結晶系薄膜シリコン層１０６を保護することができる。したがって、ｎ型の結晶系薄膜シリコン層１０６の特性劣化を抑制することができる。 Further, according to the embodiment described above, the hardness of the protective film 107 is higher than the hardness of the n-type crystalline thin film silicon layer 106. According to such a configuration, when the electrode is screen-printed on the protective film 107, the n-type crystalline thin film silicon layer 106 can be protected from physical damage due to contact with the plate or friction. Therefore, characteristic deterioration of the n-type crystalline thin film silicon layer 106 can be suppressed.
　また、以上に記載された実施の形態によれば、ｎ型の単結晶シリコン基板１００の導電型が、第１の導電型である。このような構成によれば、焼成によって裏面電極１１１を形成する場合において、ｎ型の結晶系薄膜シリコン層１０６上に形成された保護膜１０７が、焼成される裏面電極１１１によってｎ型の結晶系薄膜シリコン層１０６が突き破られること、さらには、ｎ型の結晶系薄膜シリコン層１０６を突き破った裏面電極１１１がｎ型の単結晶シリコン基板１００にまで到達することを防ぐことができる。 Further, according to the embodiment described above, the conductivity type of the n-type single crystal silicon substrate 100 is the first conductivity type. According to such a configuration, when the back electrode 111 is formed by firing, the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100.
　また、以上に記載された実施の形態によれば、太陽電池の製造方法において、ｎ型の単結晶シリコン基板１００上、たとえば、ｎ型の単結晶シリコン基板１００の裏面１００Ｂに、トンネル酸化物層１０４を形成する。そして、トンネル酸化物層１０４上、たとえば、トンネル酸化物層１０４の下面に、第１の導電型の半導体層を形成する。ここで、ｎ型の非晶質シリコン層１０５は、この段階、すなわち、熱処理される前の段階の第１の導電型の半導体層に対応するものである。そして、ｎ型の非晶質シリコン層１０５に対し、４００℃以上の温度で熱処理を行う。ここで、ｎ型の結晶系薄膜シリコン層１０６は、熱処理された第１の導電型の半導体層に対応するものである。そして、熱処理されたｎ型の結晶系薄膜シリコン層１０６上、たとえば、ｎ型の結晶系薄膜シリコン層１０６の下面に、保護膜１０７を形成する。そして、保護膜１０７上、たとえば、保護膜１０７の下面に、裏面電極１１１を印刷する。そして、焼成によって、裏面電極１１１とｎ型の結晶系薄膜シリコン層１０６とを電気的に接続させる。 Further, according to the embodiment described above, in the method for manufacturing a solar cell, the tunnel oxide layer is formed on the n-type single crystal silicon substrate 100, for example, on the back surface 100B of the n-type single crystal silicon substrate 100. 104 is formed. Then, a semiconductor layer of the first conductivity type is formed on the tunnel oxide layer 104, for example, on the lower surface of the tunnel oxide layer 104. Here, the n-type amorphous silicon layer 105 corresponds to the first conductivity type semiconductor layer at this stage, that is, before the heat treatment. Then, heat treatment is performed on the n-type amorphous silicon layer 105 at a temperature of 400 ° C. or higher. Here, the n-type crystalline thin film silicon layer 106 corresponds to the heat-treated first conductive type semiconductor layer. Then, a protective film 107 is formed on the heat-treated n-type crystalline thin film silicon layer 106, for example, on the lower surface of the n-type crystalline thin film silicon layer 106. Then, the back electrode 111 is printed on the protective film 107, for example, on the lower surface of the protective film 107. Then, the back electrode 111 and the n-type crystalline thin film silicon layer 106 are electrically connected by baking.
　このような構成によれば、焼成によって裏面電極１１１を形成する場合において、ｎ型の結晶系薄膜シリコン層１０６上に形成された保護膜１０７が、焼成される裏面電極１１１によってｎ型の結晶系薄膜シリコン層１０６が突き破られること、さらには、ｎ型の結晶系薄膜シリコン層１０６を突き破った裏面電極１１１がｎ型の単結晶シリコン基板１００にまで到達することを防ぐことができる。したがって、トンネル酸化物層１０４、および、ｎ型の結晶系薄膜シリコン層１０６を含むトンネル接合層の浸食ダメージ、印刷ダメージ、または、電流ロスなどの特性低下を抑制することができる。また、保護膜１０７が高温処理にも耐えうるため、製造プロセスが限定されない。また、焼成によって、信頼性が高く、かつ、低抵抗である銀電極を形成することができるため、太陽電池の変換効率の向上を実現することができる。 According to such a configuration, when the back electrode 111 is formed by firing, the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100. Therefore, deterioration of characteristics such as erosion damage, printing damage, or current loss of the tunnel junction layer including the tunnel oxide layer 104 and the n-type crystalline thin film silicon layer 106 can be suppressed. In addition, since the protective film 107 can withstand high temperature treatment, the manufacturing process is not limited. In addition, since the silver electrode having high reliability and low resistance can be formed by firing, the conversion efficiency of the solar cell can be improved.
　なお、これらの構成以外の本願明細書に例示される他の構成については適宜省略することができる。すなわち、これらの構成のみで、以上に記載された効果を生じさせることができる。 It should be noted that other configurations exemplified in the present specification other than these configurations can be omitted as appropriate. In other words, the effects described above can be produced only with these configurations.
　しかしながら、本願明細書に例示される他の構成のうちの少なくとも１つを以上に記載された構成に適宜追加した場合、すなわち、以上に記載された構成としては記載されなかった本願明細書に例示される他の構成を以上に記載された構成に追加した場合でも、同様に以上に記載された効果を生じさせることができる。 However, when at least one of the other configurations exemplified in the present specification is appropriately added to the configuration described above, that is, the configuration described above is not exemplified as the configuration described above. Even when other configurations described above are added to the configurations described above, the effects described above can be similarly produced.
　また、特に制限がない限り、それぞれの処理の実施の順序は変更することができる。 Also, unless there is a particular limitation, the order of execution of each process can be changed.
　また、以上に記載された実施の形態によれば、太陽電池の製造方法において、トンネル酸化物層１０４上に、ｎ型の非晶質シリコン層１０５を形成することは、トンネル酸化物層１０４上に、真性半導体層、すなわち、ノンドープの半導体層を形成し、ノンドープの半導体層に対し４００℃以上の温度で熱処理を行うことによって、ノンドープの半導体層内に第１の導電型のドーパントを拡散させて、ｎ型の非晶質シリコン層１０５を形成することである。このような構成によれば、焼成によって裏面電極１１１を形成する場合において、ｎ型の結晶系薄膜シリコン層１０６上に形成された保護膜１０７が、焼成される裏面電極１１１によってｎ型の結晶系薄膜シリコン層１０６が突き破られること、さらには、ｎ型の結晶系薄膜シリコン層１０６を突き破った裏面電極１１１がｎ型の単結晶シリコン基板１００にまで到達することを防ぐことができる。 Further, according to the embodiment described above, in the method for manufacturing a solar cell, the formation of the n-type amorphous silicon layer 105 on the tunnel oxide layer 104 is performed on the tunnel oxide layer 104. In addition, an intrinsic semiconductor layer, that is, a non-doped semiconductor layer is formed, and a heat treatment is performed on the non-doped semiconductor layer at a temperature of 400 ° C. or more to diffuse the first conductivity type dopant in the non-doped semiconductor layer. Thus, the n-type amorphous silicon layer 105 is formed. According to such a configuration, when the back electrode 111 is formed by firing, the protective film 107 formed on the n-type crystalline thin film silicon layer 106 is converted into an n-type crystal system by the fired back electrode 111. It is possible to prevent the thin film silicon layer 106 from being broken through, and further, the back electrode 111 that has broken through the n type crystalline thin film silicon layer 106 from reaching the n type single crystal silicon substrate 100.
　また、以上に記載された実施の形態によれば、太陽電池の製造方法において、トンネル酸化物層１０４上に、ｎ型の非晶質シリコン層１０５を形成し、同時に、ｎ型の非晶質シリコン層１０５に対し、４００℃以上の温度で熱処理を行う。このような構成によれば、ｎ型の結晶系薄膜シリコン層１０６が一工程で形成されるため、工程が簡便となる。 Further, according to the embodiment described above, in the method for manufacturing a solar cell, the n-type amorphous silicon layer 105 is formed on the tunnel oxide layer 104, and at the same time, the n-type amorphous silicon is formed. A heat treatment is performed on the silicon layer 105 at a temperature of 400 ° C. or higher. According to such a configuration, since the n-type crystalline thin film silicon layer 106 is formed in one step, the process becomes simple.
　また、以上に記載された実施の形態によれば、太陽電池の製造方法において、ｎ型の非晶質シリコン層１０５に対して熱処理を行う際のピーク温度、および、焼成によって、裏面電極１１１とｎ型の結晶系薄膜シリコン層１０６とを電気的に接続させる際のピーク温度が、保護膜１０７を形成する際の温度よりも高い。このような構成によれば、熱処理時および電極焼成時に、保護膜１０７に含まれている水素がｎ型の結晶系薄膜シリコン層１０６中に拡散するため、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果が向上する。 Further, according to the embodiment described above, in the method for manufacturing a solar cell, the back surface electrode 111 and the n-type amorphous silicon layer 105 are subjected to the peak temperature when the n-type amorphous silicon layer 105 is heat-treated and the firing. The peak temperature when electrically connecting the n-type crystalline thin film silicon layer 106 is higher than the temperature when forming the protective film 107. According to such a configuration, hydrogen contained in the protective film 107 diffuses into the n-type crystalline thin film silicon layer 106 during the heat treatment and the electrode firing. The passivation effect is improved.
　また、以上に記載された実施の形態によれば、太陽電池の製造方法において、保護膜１０７中の水素濃度が、熱処理されたｎ型の結晶系薄膜シリコン層１０６中の水素濃度よりも高い。このような構成によれば、保護膜１０７中に十分な水素が含まれていることによって、保護膜１０７から脱離した当該水素が、熱処理などによって形成されたｎ型の結晶系薄膜シリコン層１０６中のダングリングボンドを終端する。したがって、ｎ型の結晶系薄膜シリコン層１０６のパッシベーション効果が向上する。また、焼成工程において、ｎ型の結晶系薄膜シリコン層１０６から水素が多量に脱離することを抑制することができる。 Also, according to the embodiment described above, in the method for manufacturing a solar cell, the hydrogen concentration in the protective film 107 is higher than the hydrogen concentration in the heat-treated n-type crystalline thin film silicon layer 106. According to such a configuration, when the protective film 107 contains sufficient hydrogen, the hydrogen desorbed from the protective film 107 is formed into an n-type crystalline thin film silicon layer 106 formed by heat treatment or the like. Terminate the dangling bond inside. Therefore, the passivation effect of the n-type crystalline thin film silicon layer 106 is improved. Further, it is possible to suppress a large amount of hydrogen from being released from the n-type crystalline thin film silicon layer 106 in the baking step.
　＜以上に記載された実施の形態における変形例について＞
　以上に記載された実施の形態では、それぞれの構成要素の材質、材料、寸法、形状、相対的配置関係または実施の条件などについても記載する場合があるが、これらはすべての局面において例示であって、本願明細書に記載されたものに限られることはないものとする。 <Modifications in Embodiments Described above>
In the embodiment described above, the material, material, dimension, shape, relative arrangement relationship, or implementation condition of each component may be described, but these are examples in all aspects. Thus, it is not limited to those described in this specification.
　したがって、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。たとえば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの実施の形態における少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。 Therefore, innumerable modifications that are not illustrated are envisaged within the scope of the technology disclosed in this specification. For example, when deforming, adding or omitting at least one component, extracting at least one component in at least one embodiment, and combining with at least one component in another embodiment Is included.
　また、矛盾が生じない限り、以上に記載された実施の形態において「１つ」備えられるものとして記載された構成要素は、「１つ以上」備えられていてもよいものとする。 Further, as long as no contradiction arises, “one or more” constituent elements described as being provided with “one” in the embodiment described above may be provided.
　さらに、以上に記載された実施の形態におけるそれぞれの構成要素は概念的な単位であって、本願明細書に開示される技術の範囲内には、１つの構成要素が複数の構造物から成る場合と、１つの構成要素がある構造物の一部に対応する場合と、さらには、複数の構成要素が１つの構造物に備えられる場合とを含むものとする。 Further, each component in the embodiment described above is a conceptual unit, and one component is composed of a plurality of structures within the scope of the technique disclosed in this specification. In addition, a case where one component corresponds to a part of a structure and a case where a plurality of components are provided in one structure are included.
　また、以上に記載された実施の形態におけるそれぞれの構成要素には、同一の機能を発揮する限り、他の構造または形状を有する構造物が含まれるものとする。 Further, each component in the embodiment described above includes a structure having another structure or shape as long as the same function is exhibited.
　また、本願明細書における説明は、本技術に関するすべての目的のために参照され、いずれも、従来技術であると認めるものではない。 In addition, the description in the present specification is referred to for all purposes related to the present technology, and neither is admitted to be prior art.
　また、以上に記載された実施の形態において、特に指定されずに材料名などが記載された場合は、矛盾が生じない限り、当該材料に他の添加物が含まれた、たとえば、合金などが含まれるものとする。 Further, in the embodiment described above, when a material name or the like is described without being particularly specified, the material contains other additives, for example, an alloy or the like unless a contradiction arises. Shall be included.
　１００，２００　単結晶シリコン基板、１００Ａ，２００Ａ　受光面、１００Ｂ，２００Ｂ　裏面、１０１，２０１　不純物拡散源、１０２，２０２　ＮＳＧ膜、１０３，２０３　不純物拡散層、１０４，２０４　トンネル酸化物層、１０５，２０５　非晶質シリコン層、１０６，２０６　結晶系薄膜シリコン層、１０７，２０７　保護膜、１０８，２０８　誘電体層、１０９，２０９　反射防止膜、１１０，２１０　受光面電極、１１０Ｂ　バス電極、１１０Ｇ　グリッド電極、１１１，２１１　裏面電極、１１２　不純物拡散領域。 100, 200 single crystal silicon substrate, 100A, 200A light receiving surface, 100B, 200B back surface, 101, 201 impurity diffusion source, 102, 202 NSG film, 103, 203 impurity diffusion layer, 104, 204 tunnel oxide layer, 105, 205 Amorphous silicon layer, 106,206 crystalline thin film silicon layer, 107,207 protective film, 108,208 dielectric layer, 109,209 antireflection film, 110,210 light receiving surface electrode, 110B bus electrode, 110G grid electrode, 111, 211 Back electrode, 112 Impurity diffusion region.

Claims (12)

  1. 　半導体基板（１００、２００）上に形成されるトンネル酸化物層（１０４、２０４）と、
    　前記トンネル酸化物層（１０４、２０４）上に形成される第１の導電型の半導体層（１０６、２０６）と、
    　前記半導体層（１０６、２０６）上に形成される保護膜（１０７、２０７）と、
    　前記保護膜（１０７、２０７）上から前記保護膜（１０７、２０７）を貫通し、かつ、前記半導体層（１０６、２０６）に接触して形成される電極（１１１、２１１）とを備え、
    　前記電極（１１１、２１１）は、ガラス粒子を含む焼成電極である、
    　太陽電池。     A tunnel oxide layer (104, 204) formed on a semiconductor substrate (100, 200);
    A first conductivity type semiconductor layer (106, 206) formed on the tunnel oxide layer (104, 204);
    Protective films (107, 207) formed on the semiconductor layers (106, 206);
    An electrode (111, 211) formed through the protective film (107, 207) from above the protective film (107, 207) and in contact with the semiconductor layer (106, 206),
    The electrodes (111, 211) are fired electrodes containing glass particles,
    Solar cell.
  2. 　前記保護膜（１０７、２０７）の材料は、ケイ化物を含む、
    　請求項１に記載の太陽電池。     The material of the protective film (107, 207) includes silicide.
    The solar cell according to claim 1.
  3. 　前記半導体層（１０６、２０６）の膜厚が、５ｎｍ以上、かつ、１００ｎｍ未満である、
    　請求項１または請求項２に記載の太陽電池。     The semiconductor layer (106, 206) has a thickness of 5 nm or more and less than 100 nm.
    The solar cell according to claim 1 or claim 2.
  4. 　前記保護膜（１０７、２０７）の膜厚が、５ｎｍ以上、かつ、２００ｎｍ未満である、
    　請求項１から請求項３のうちのいずれか１項に記載の太陽電池。     The film thickness of the protective film (107, 207) is 5 nm or more and less than 200 nm.
    The solar cell of any one of Claims 1-3.
  5. 　前記保護膜（１０７、２０７）の硬度が、前記半導体層（１０６、２０６）の硬度よりも高い、
    　請求項１から請求項４のうちのいずれか１項に記載の太陽電池。     The hardness of the protective film (107, 207) is higher than the hardness of the semiconductor layer (106, 206),
    The solar cell of any one of Claims 1-4.
  6. 　前記半導体基板（１００、２００）の導電型が、第１の導電型である、
    　請求項１から請求項５のうちのいずれか１項に記載の太陽電池。     The conductivity type of the semiconductor substrate (100, 200) is the first conductivity type.
    The solar cell of any one of Claims 1-5.
  7. 　半導体基板（１００、２００）上に、トンネル酸化物層（１０４、２０４）を形成し、
    　前記トンネル酸化物層（１０４、２０４）上に、第１の導電型の半導体層（１０５、２０５）を形成し、
    　前記半導体層（１０５、２０５）に対し、４００℃以上の温度で熱処理を行い、
    　熱処理された前記半導体層（１０６、２０６）上に、保護膜（１０７、２０７）を形成し、
    　前記保護膜（１０７、２０７）上に、電極（１１１、２１１）を印刷し、
    　焼成によって、前記電極（１１１、２１１）と前記半導体層（１０６、２０６）とを電気的に接続させる、
    　太陽電池の製造方法。     Forming a tunnel oxide layer (104, 204) on a semiconductor substrate (100, 200);
    Forming a first conductivity type semiconductor layer (105, 205) on the tunnel oxide layer (104, 204);
    The semiconductor layer (105, 205) is heat-treated at a temperature of 400 ° C. or higher,
    A protective film (107, 207) is formed on the heat-treated semiconductor layer (106, 206),
    Electrodes (111, 211) are printed on the protective films (107, 207),
    Electrically connecting the electrodes (111, 211) and the semiconductor layers (106, 206) by firing;
    A method for manufacturing a solar cell.
  8. 　前記トンネル酸化物層（１０４、２０４）上に、第１の導電型の前記半導体層（１０５、２０５）を形成することは、
    　前記トンネル酸化物層（１０４、２０４）上に、真性半導体層を形成し、
    　前記真性半導体層に対し４００℃以上の温度で熱処理を行うことによって、前記真性半導体層内に第１の導電型のドーパントを拡散させて、第１の導電型の前記半導体層（１０５、２０５）を形成することである、
    　請求項７に記載の太陽電池の製造方法。     Forming the semiconductor layer (105, 205) of the first conductivity type on the tunnel oxide layer (104, 204),
    Forming an intrinsic semiconductor layer on the tunnel oxide layer (104, 204);
    The intrinsic semiconductor layer is subjected to a heat treatment at a temperature of 400 ° C. or more to diffuse the first conductivity type dopant in the intrinsic semiconductor layer, thereby the first conductivity type semiconductor layer (105, 205). Is to form a
    The manufacturing method of the solar cell of Claim 7.
  9. 　前記トンネル酸化物層（１０４、２０４）を形成する前に、前記半導体基板（１００、２００）上に、第１の導電型の不純物拡散領域（１１２）を選択的に形成し、
    　前記電極（１１１、２１１）を、前記保護膜（１０７、２０７）上の、平面視において前記不純物拡散領域（１１２）が形成された位置に対応する位置に印刷する、
    　請求項７または請求項８に記載の太陽電池の製造方法。     Before forming the tunnel oxide layer (104, 204), an impurity diffusion region (112) of the first conductivity type is selectively formed on the semiconductor substrate (100, 200).
    Printing the electrodes (111, 211) on the protective film (107, 207) at a position corresponding to the position where the impurity diffusion region (112) is formed in plan view;
    The manufacturing method of the solar cell of Claim 7 or Claim 8.
  10. 　前記トンネル酸化物層（１０４、２０４）上に、第１の導電型の半導体層（１０５、２０５）を形成し、同時に、前記半導体層（１０５、２０５）に対し、４００℃以上の温度で熱処理を行う、
    　請求項７から請求項９のうちのいずれか１項に記載の太陽電池の製造方法。     A first conductive type semiconductor layer (105, 205) is formed on the tunnel oxide layer (104, 204), and at the same time, the semiconductor layer (105, 205) is heat-treated at a temperature of 400 ° C. or higher. I do,
    The manufacturing method of the solar cell of any one of Claims 7-9.
  11. 　前記半導体層（１０５、２０５）に対して熱処理を行う際のピーク温度、および、焼成によって、前記電極（１１１、２１１）と前記半導体層（１０６、２０６）とを電気的に接続させる際のピーク温度が、前記保護膜（１０７、２０７）を形成する際の温度よりも高い、
    　請求項７から請求項１０のうちのいずれか１項に記載の太陽電池の製造方法。     Peak temperature when heat-treating the semiconductor layers (105, 205), and peak when electrically connecting the electrodes (111, 211) and the semiconductor layers (106, 206) by firing The temperature is higher than the temperature when forming the protective film (107, 207),
    The manufacturing method of the solar cell of any one of Claims 7-10.
  12. 　前記保護膜（１０７、２０７）中の水素濃度が、熱処理された前記半導体層（１０６、２０６）中の水素濃度よりも高い、
    　請求項７から請求項１１のうちのいずれか１項に記載の太陽電池の製造方法。     The hydrogen concentration in the protective film (107, 207) is higher than the hydrogen concentration in the heat-treated semiconductor layer (106, 206).
    The manufacturing method of the solar cell of any one of Claims 7-11.
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