WO2017152714A1 - Carrier and manufacturing method therefor, and method for manufacturing core-less package substrate using carrier - Google Patents

Abstract

Provided are a carrier (10) and a manufacturing method therefor, and a method for manufacturing a core-less package substrate using the carrier (10). The method for manufacturing the carrier (10), which is used in the core-less package substrate (100), comprises: step S1, forming a cured resin (12); and step S2, forming an easily-strippable conductor layer (16) on the surface (14) of the cured resin (12), wherein the binding force between the conductor layer (16) and the cured resin (12) is 0.01-0.05 N/mm.

Description

Carrier, manufacturing method thereof and method for manufacturing coreless package substrate using carrier Technical field

The present invention relates to the field of packaging technology, and in particular, to a carrier, a method of manufacturing the same, and a method of manufacturing a coreless package substrate using the carrier. The coreless package substrate can be used in various electronic products to meet the development requirements of multifunctional, miniaturization, and portable.

Background technique

The package substrate or the IC carrier board not only supports the IC chip, but also has a circuit inside to shield the signal between the chip and the PCB circuit board, and has additional functions such as a protection circuit, a dedicated line, a design heat dissipation path, and a modular standard for building components. . As wireless communications, automotive electronics, and other consumer electronics products move toward versatility, thinness, shortness, high frequency, high speed, low power consumption, and high reliability, for rigid package substrates that support and turn on the chip, The lines involved are getting thinner and finer, from 50/50 μm for conventional L/S to 8/8 μm for 25/25 m, 15/15 μm or even smaller.

In the face of fine line requirements, there are mainly three types of substrates (or core boards) currently applied to rigid package substrates. The first type is mainly pressed into a substrate by a copper foil having a surface roughness Rz ≥ 3 μm (12 μm thick to prevent the copper foil from being pressed and creped), and the manufacturer applies a "thinning copper + subtractive etching process" to produce a wiring. The substrate is low in manufacturing cost and high in peeling strength of the substrate. However, it is necessary to reduce the thickness of the copper foil by 12 μm. Therefore, the uniformity of copper thickness is difficult to control, and the yield of the fabricated circuit is low, and the circuit design of L/S>35/35 μm can only be handled. In addition, it is necessary to additionally etch the copper bud portion of 3 μm or more, so the etching amount is large, and more CAM line compensation is required, which ultimately affects the line fabrication capability. The second type is mainly pressed into a substrate by means of a thin copper foil (2 μm thick) having an Rz value of about 2 μm, and the manufacturer uses a modified semi-additive method (MSAP) to fabricate the wiring. Although the L/S production capacity can be increased to ≥25/25μm, the 2μm thin copper foil is more expensive, which limits the large-scale market application of the substrate. The third type mainly deals with L/S<25/25μm line design, mainly with low-roughness thin copper foil (Rz The value is ≤ 1 μm) or the chemical copper is used as the base copper, and the substrate is pressed into a substrate by a Primer coating or ABF resin which increases the peel strength of the line, and the line is processed by a PSAP or SAP semi-additive method. This process requires more expensive low-roughness thin copper foil and Primer and ABF materials, which are extremely expensive to manufacture, and because the bottom copper Rz value is too small, it is prone to line peeling and other process problems (such as the shape of the trailing edge of the adhesive). In short, in order to deal with the different L/S range circuit design of rigid package substrates, different copper foils are used in the industry to fabricate substrates, which leads downstream packaging substrate manufacturers to select different processing processes for different substrates and evaluate them. Stability, etc., it is difficult to find the best substrate between cost and product yield. Especially for products with L/S critical points, the stability of the pass rate has always been a headache.

Compared with the traditional laminated core board process, a new package substrate manufacturing process has been developed in recent years: coreless board technology + buried line ETS and MIS process. By embedding the line in PP (prepreg) or molding compound, it is only necessary to etch the thin copper above the line to avoid side etching or peeling. No additional Primer, ABF and other materials are needed, so the process is cheaper and more expensive. The advantages of thinner lightness, higher electrical performance and high degree of freedom of wiring make it easy to produce a substrate with an L/S of 20/20 μm or even 10/10 μm, showing a good market application prospect. However, since the coreless board is too thin, the manufacturing process exceeds the ability of the board in many processes, so that it is easy to jam and cause the board to be scrapped. In order to improve the yield and productivity of the process, the substrate manufacturer generally adopts a separation process, that is, supporting and increasing the thickness of the plate by means of a carrier, forming a coreless circuit on the upper and lower layers, and then separating the carrier to obtain a package substrate. That is to say, for the "coreless board technology + buried line ETS and MIS process", support and separation must be achieved by means of the key material - "carrier". There are two main types of carriers currently used. The invention relates to a composite carrier made of a separable thin copper foil, which is used in the manufacture of a coreless package substrate, and the chip is packaged after separating the coreless plate from the carrier, and the manufacturing efficiency is high. However, this carrier uses a thin copper foil and a press-bonding process, so the manufacturing process is complicated, the cost is high, and it cannot be reused after the production of the coreless board once, which is wasteful. The other is to apply the thin iron alloy roll to the coil as a carrier and apply it to the MIS process. In the process of manufacturing the coreless plate, it is necessary to perform grinding and window opening of the thin iron alloy. The material and manufacturing cost of the carrier are low, but due to the limitations of the process characteristics and the proprietary grinding equipment, there are shortcomings such as long manufacturing process and low efficiency, which is difficult to be widely applied. And, open The thin iron alloy behind the window cannot be reused and is wasteful. Therefore, there is a need for a reusable, low cost carrier and method of manufacturing the same to address the growing demand for high-end chip flip-chip products such as coreless ETS in the field of package substrates.

In addition, when the coreless package substrate is fabricated in the prior art, the copper foil is usually bonded to the substrate by a high temperature lamination method, and then drilled on the substrate and further subjected to pattern plating or full plate plating. The method removes a portion of the copper foil on the surface of the substrate to obtain the final line. In laser drilling, it is necessary to etch and thin the position where the copper foil needs to be drilled in order to drill holes in the substrate. When the hole is metallized, a conductive seed layer is formed on the hole wall by a process such as electroless copper (PTH) or black hole or black shadow, and a metal conductor layer is formed on the hole wall by electroplating to improve the electrical conductivity. . This process requires the use of finished copper foil and requires multiple etchings, making it difficult to meet the fine line requirements and generating a large amount of wastewater containing metal ions to the environment. Moreover, the bonding force between the conductive seed layer on the wall of the hole and the electroplated copper layer and the substrate is weak, and it is easy to separate from the hole wall and the conductivity of the metallized hole is deteriorated. Therefore, there is a need for a method that is simple in process, easy to control, and capable of ensuring the electrical conductivity of vias therein when fabricating a coreless package substrate.

Summary of the invention

The present invention has been made in view of the above circumstances, and an object thereof is to provide a reusable, low-cost carrier and a method of manufacturing the same, and a process for manufacturing a coreless package substrate using a carrier is simple, easy to control, and capable of ensuring A method of conducting properties of a hole.

A first aspect of the present invention is a method of manufacturing a carrier for a coreless package substrate, the method comprising the steps of: forming a cured resin (S1); and forming a conductor layer which is easily peeled off on a surface of the cured resin, the conductor The bonding force between the layer and the cured resin is from 0.01 to 0.05 N/mm (S2).

In the carrier thus obtained, the bonding force between the conductor layer and the cured resin is as low as 0.01 to 0.05 N/mm. Therefore, when the carrier is used to manufacture the coreless package substrate, the package substrate and the conductor layer are easily peeled off from the cured resin, and the peeled cured resin can be further processed in step S2, and is easily applied repeatedly in the preparation process of the carrier. .

According to a second aspect of the present invention, in the first aspect, the step S1 includes laminating a low-roughness surface of the metal piece with the uncured resin, and removing the metal piece after lamination and heat curing, thereby obtaining a cured resin.

According to a third aspect of the present invention, in the second aspect, the resin comprises one of a bismaleimide triazine resin, an epoxy resin, a cyanate resin, a polyphenylene ether resin, and a modified resin thereof. Or a variety.

According to a fourth aspect of the present invention, in the first aspect, the step S2 includes forming a conductive seed layer on the surface of the cured resin, and then forming a thickened layer of the conductor on the conductive seed layer, and the conductive seed layer and the conductor are added. The thick layer constitutes the conductor layer.

According to a fifth aspect of the present invention, in the fourth aspect, the conductive seed layer is formed by implanting a conductive material under the surface of the cured resin by ion implantation to form an ion implantation layer as a conductive seed layer; Alternatively, a conductive material is deposited on the surface of the cured resin by plasma deposition to form a plasma deposited layer as a conductive seed layer; or, a conductive material is first implanted under the surface of the cured resin by ion implantation to form an ion implantation layer. Then, a plasma deposition layer is formed over the ion implantation layer by plasma deposition, and the ion implantation layer and the plasma deposition layer together constitute a conductive seed layer.

According to a sixth aspect of the present invention, in the fifth aspect, the ion implantation layer is a doped structure formed of a conductive material and a cured resin, the outer surface of which is flush with the surface of the cured resin, and the inner surface is located below the surface of the cured resin. At a depth of 1-100 nm.

According to a seventh aspect of the present invention, in the fifth aspect, the plasma deposition layer includes a metal or metal oxide deposition layer having a thickness of 0 to 500 nm, and a metal or metal oxide deposition layer and a thickness of 0 to 500 nm. The Cu deposit layer, wherein the metal deposit layer comprises Ni or a Ni-Cu alloy, and the metal oxide deposit layer comprises NiO.

According to an eighth aspect of the present invention, in the fourth aspect, the step S2 includes forming a thickened layer of the conductor over the conductive seed layer by one or more of electroplating, electroless plating, vacuum evaporation, and sputtering. .

A ninth technical solution of the present invention is a carrier for a coreless package substrate, the carrier comprising: a cured resin; and a conductor layer which is easily peeled off on a surface of the cured resin, and a conductor The bonding force between the layer and the cured resin is from 0.01 to 0.05 N/mm.

In this carrier, the bonding force between the conductor layer and the cured resin is as low as 0.01 - 0.05 N/mm. Therefore, when the coreless package substrate is manufactured by using the carrier, the package substrate and the conductor layer are easily peeled off from the cured resin, and the peeled cured resin can further form a conductor layer and can be easily reused in the carrier.

According to a tenth aspect of the present invention, in the ninth aspect, the curing resin comprises one of a bismaleimide triazine resin, an epoxy resin, a cyanate resin, a polyphenylene ether resin, and a modified resin thereof. One or more kinds, and the surface roughness of the cured resin is 2.5 μm or less.

According to an eleventh aspect of the present invention, in the ninth aspect, the conductor layer includes a conductive seed layer and a conductor thickening layer over the conductive seed layer.

According to a twelfth aspect of the present invention, in the eleventh aspect, the conductive seed layer includes: an ion implantation layer whose outer surface is flush with the surface of the cured resin and whose inner surface is located inside the cured resin; or a plasma deposition layer above the surface; or an ion implantation layer whose outer surface is flush with the surface of the cured resin and whose inner surface is located inside the cured resin, and a plasma deposition layer located above the ion implantation layer.

According to a thirteenth aspect of the present invention, in the twelfth aspect, the ion-implanted layer is a doped structure formed of a conductive material and a cured resin, the inner surface of which is located at a depth of 1-100 nm below the surface of the cured resin.

According to a fourteenth aspect of the present invention, in the twelfth aspect, the plasma deposition layer includes a metal or metal oxide deposition layer having a thickness of 0 to 500 nm, and a metal or metal oxide deposition layer and a thickness of 0 a 500 nm Cu deposition layer in which the metal deposition layer contains Ni or a Ni-Cu alloy, and the metal oxide deposition layer contains NiO.

According to a fifteenth aspect of the invention, in the eleventh aspect, the conductor thickening layer comprises a Cu layer having a thickness of 0 to 5 μm.

A sixteenth technical solution of the present invention is a method of manufacturing a coreless package substrate, the method comprising the steps of: forming a first wiring structure on a surface of the carrier (S11); laminating the first layer over the first wiring structure a bonding layer (S12); drilling a first bonding layer (S13); forming a conductive seed layer on the surface of the first bonding layer and the wall surface of the hole by, for example, passing Ion implantation implants a conductive material onto the surface of the first bonding layer and below the wall surface of the hole to form an ion implantation layer as a conductive seed layer, or deposits a conductive material onto the surface and hole of the first bonding layer by plasma deposition. On the wall surface, a plasma deposition layer is formed as a conductive seed layer, or a conductive material is first implanted into the surface of the first bonding layer and below the wall surface of the hole by ion implantation to form an ion implantation layer, and then deposited by plasma deposition. Forming a plasma deposition layer above the ion implantation layer, the ion implantation layer and the plasma deposition layer together forming a conductive seed layer (S14); forming a second line structure on the surface of the first bonding layer (S15); and, stripping The package substrate is obtained by the carrier (S16).

By forming a conductive seed layer on the surface of the bonding layer and the wall surface of the hole, the metallization of the surface of the bonding layer and the metallization of the hole walls can be simultaneously performed. Therefore, the metallized via and the surface of the bonding layer with the conductive seed layer can be directly formed by one molding, without the need to previously coat the substrate with a thick metal foil and then the metal foil as in the prior art. Etching and thinning can be used to drill holes in the substrate, and it is not necessary to form a conductive layer on the hole walls by chemical copper or black holes, black shadow, or the like to obtain metallized via holes. Compared with the prior art, the process of the above method can be significantly shortened, and the use of the etching liquid can be reduced, which is beneficial to environmental protection. In addition, by adjusting various process parameters, such as voltage, current, and plating solution concentration during plating, the above method can easily produce a very thin wiring structure layer, which is easy to meet the fine line requirements of narrow line width and line spacing. In addition, when the ion implantation layer is formed, a high bonding force can be generated between the hole wall and the conductive seed layer, and the metal layer of the hole wall is thus not easily peeled off or drawn in various subsequent processing or application processes. hurt. Therefore, it is advantageous to improve the conductivity of the via holes, and it is convenient to obtain a package substrate having good conductivity.

According to a seventeenth aspect of the present invention, in the sixteenth aspect, the steps S12 to S15 are repeated to form a multilayer package substrate having the first, second, third, ... Nth line structures.

According to an eighteenth aspect of the present invention, in the seventeenth aspect, when one or more of the intermediate circuit structures of the multilayer package substrate, that is, the second, third, ..., N-1th line structures are formed First, the copper foil is laminated on the bonding layer, the copper foil and the bonding layer are drilled, and then the copper foil is etched to obtain an intermediate wiring structure.

According to a nineteenth aspect of the present invention, in the sixteenth aspect, the carrier is a carrier manufactured by any one of the first to eighth aspects, or any of the ninth to fifteenth aspects A carrier.

According to a twentieth aspect of the present invention, in the sixteenth aspect, the step S11 includes forming the first wiring structure on both sides of the carrier, and the step S16 includes stripping the carrier from both sides to obtain two separate package substrates.

According to a twenty-first aspect of the present invention, in the sixteenth aspect, in the steps S11 and S15, the first and second line structures are formed by a full-plate plating or a pattern plating method.

According to a twenty-second aspect of the present invention, in the sixteenth aspect, the ion implantation layer is a doped structure formed by the conductive material and the first bonding layer, and the outer surface thereof and the surface or the hole of the first bonding layer The wall is flush and the inner surface is located at the surface of the first conforming layer or at a depth of 1-500 nm below the wall surface of the hole.

According to a twenty-third aspect of the present invention, in the sixteenth aspect, the step S14 further includes forming one or more of electroplating, electroless plating, vacuum evaporation plating, and sputtering on the conductive seed layer. The conductor is thickened and the thickened layer of the conductor contains Cu.

DRAWINGS

These and other features, aspects and advantages of the present invention will become more readily apparent to those skilled in the <RTI For the sake of clarity, the figures are not necessarily to scale, and some parts may be exaggerated to show specific details. Throughout the drawings, the same reference numerals will be given to the

1 is a flow chart showing a method of manufacturing a carrier for a coreless package substrate according to the present invention;

2(a)-(d) are schematic cross-sectional views showing various carriers produced by the method shown in Fig. 1;

3 is a flow chart showing a method of manufacturing a coreless package substrate according to the present invention;

4(a)-(f) are schematic cross-sectional views showing structures corresponding to the respective steps of the method of FIG. 3 in producing a two-layer package substrate;

5(a)-(j) are schematic cross-sectional views showing structures corresponding to the respective steps of the method shown in Fig. 3 when producing a three-layer package substrate.

Reference number:

10 carrier

12 curing resin

14 cured resin surface

16 conductor layer

17 conductive seed layer

18 ion implantation layer

20 plasma deposition layer

201 metal or metal oxide deposit

202 Cu deposit

22 conductor thickening layer

100 package substrate

102 first line structure

104 first bonding layer

106 surface of the first bonding layer

108 holes

110 hole wall

116 conductor layer

117 conductive seed layer

118 ion implantation layer

120 plasma deposition layer

122 conductor thickening layer

124 second line structure

126 second bonding layer

128 third line structure

130 release film

132 copper foil

134 prepreg.

detailed description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Those skilled in the art should understand that the description is merely illustrative of exemplary embodiments of the invention and is not intended to limit the scope of the invention. In addition, in order to facilitate the description of the positional relationship between the layers of materials, spatially relative terms such as "above" and "below", and "inside" and "outside" are used herein, and the terms are relative to the carrier or For the surface of the laminate layer. If the layer A material is in a direction toward the outside of the carrier or the bonding layer relative to the layer B material, then the layer A material is considered to be above the layer B material and vice versa. In addition, the terms "double layer", "three layers" and "multilayer" used when referring to a package substrate actually refer to the number of layers of the wiring structure in the package substrate.

1 is a flow chart showing a method of manufacturing a carrier for a coreless package substrate in accordance with the present invention. The method includes the steps of: forming a cured resin (step S1); and forming a conductor layer which is easily peeled off on the surface of the cured resin, and a bonding force between the conductor layer and the cured resin is 0.01 to 0.05 N/mm (step S2). In the carrier thus obtained, the bonding force between the conductor layer and the cured resin is as low as 0.01 to 0.05 N/mm. Therefore, when the carrier is used to manufacture the coreless package substrate, the package substrate is easily peeled off from the cured resin together with the conductor layer, and the peeled cured resin can be further processed in step S2, and can be easily applied to the preparation of the carrier. In the process.

When the cured resin is formed, the metal sheet can be removed by laminating and heat-curing the low-frost surface of the metal sheet to the uncured resin to obtain a cured resin. The resin raw material to be used may include one or more of a bismaleimide triazine resin, an epoxy resin, a cyanate resin, a polyphenylene ether resin, and a modified resin thereof. The metal sheet used may be a common metal foil such as a stainless steel sheet, an aluminum sheet or a copper sheet, or may be a thick metal plate or the like. The low-roughness surface of the metal sheet preferably has a surface roughness Rz value of 2.5 μm or less (ie, ≤2.5 μm, for example, 2.0 μm, 1.0 μm, 0.5 μm, etc.), so that the final solid is obtained. The resin also has a correspondingly low surface roughness to facilitate the formation of a flat conductor layer. Further, the heat curing process can be performed in a vacuum press, and the removal of the metal piece can be achieved by etching or the like. In fact, in addition to the cured resin, other insulating rigid sheets having stable properties can also be used in the production of the carrier in the present invention. For example, an organic polymer rigid plate, a ceramic plate (such as a silica plate), a glass plate, or the like may be used, wherein the organic polymer rigid plate may further include LCP, PTFE, CTFE, FEP, PPE, synthetic rubber sheet, and glass fiber. Cloth/ceramic filler reinforcement board, etc. In addition, a prepreg may be used instead of the cured resin, not in the manufacturing process of the carrier, but the prepreg may be cured in a subsequent process of manufacturing the package substrate using the carrier.

The step S2 of forming the conductor layer may include first forming a conductive seed layer on the surface of the cured resin, and then forming a conductor thickened layer on the conductive seed layer. When the conductive seed layer is formed, a conductive material may be implanted under the surface of the cured resin by ion implantation to form an ion implantation layer as a conductive seed layer. Alternatively, a conductive material may be deposited on the surface of the cured resin by plasma deposition to form a plasma deposited layer as a conductive seed layer. Alternatively, a conductive material may be injected under the surface of the cured resin by ion implantation to form an ion implantation layer, and then a plasma deposition layer is formed over the ion implantation layer by plasma deposition, the ion implantation layer and the plasma. The bulk deposits together form a conductive seed layer. Further, not limited to the two methods of ion implantation and plasma deposition, it is also possible to form a conductor layer which is easily peeled off on the surface of the cured resin by a method such as sputtering deposition, chemical vapor deposition or the like. By adjusting the operating parameters of the various methods, the bonding force between the conductor layer and the cured resin can be stably controlled to be between 0.01 and 0.05 N/mm.

Ion implantation can be carried out by using a conductive material as a target, ionizing a conductive material in a target by an arc in a vacuum environment to generate ions, and then accelerating the ions under an electric field to obtain a certain energy. The energetic conductive material ions then impinge directly onto the surface of the cured resin at a rate and are implanted to a depth below the surface. A relatively stable chemical bond (for example, an ionic bond or a covalent bond) is formed between the implanted conductive material ions and the resin molecules, which together constitute a doped structure. The outer surface of the doped structure (ie, the ion implantation layer) is flush with the surface of the cured resin, and the inner surface thereof The surface penetrates deep into the interior of the cured resin, that is, under the surface of the cured resin. Before the ion implantation, the surface of the cured resin may be subjected to decontamination, surface cleaning, pore sealing agent treatment, vacuum environment Hall source treatment, surface deposition treatment, etc., in order to facilitate the smooth progress of the ion implantation process.

Various metals, alloys, conductive oxides, conductive carbides, conductive organic substances, and the like can be used as the conductive material for ion implantation, such as Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, and the like. One or more of the alloys interposed, such as NiCr, TiCr, VCr, CuCr, MoV, NiCrV, TiNiCrNb, and the like. Moreover, the ion implantation layer may include one or more layers such as a Ni layer and a Cu layer which are sequentially arranged from the inside to the outside. In the ion implantation process, the depth of ion implantation and the bonding force between the cured resin and the conductive seed layer can be easily adjusted by controlling various parameters such as voltage, current, degree of vacuum, ion implantation dose, and the like. For example, the depth of ion implantation (ie, the distance between the inner surface of the ion implantation layer and the surface of the cured resin) may be adjusted to be between 0 and 100 nm, while the bonding force between the cured resin and the conductive seed layer may be It is adjusted to 0.01-0.05 N/mm, for example, 0.02, 0.03, 0.04 N/mm, and the like. The conductive material ions used in the ion implantation process generally have a nanometer size, are uniformly distributed during ion implantation, and have a small difference in incident angle to the surface of the cured resin. Therefore, it is ensured that the obtained ion implantation layer has good uniformity and density, and pinhole phenomenon is less likely to occur.

Plasma deposition can be performed in a manner similar to ion implantation as described above, except that a lower voltage is applied during deposition. That is, the conductive material is also used as a target, and in a vacuum environment, the conductive material in the target is ionized by an arc to generate ions, and then the ions are accelerated under an electric field to obtain a certain energy and deposited on the surface of the cured resin. Upper, thereby forming a plasma deposition layer. At this time, a conductive material which is the same as or different from the ion implantation may be used as the target. Preferably, the conductive material for the plasma deposition layer can be selected depending on the composition and thickness of the resin material or the ion implantation layer (if present) selected or the like. Further, the plasma deposition layer may also include one or more layers, such as a metal or metal oxide deposition layer and a Cu layer arranged in order from the inside to the outside. In a preferred embodiment, the metal deposition layer is a Ni layer having a thickness of 0 to 500 nm, and the metal oxide deposition layer is a thickness of The Ni-Cu alloy layer is 0-500 nm, and the thickness of Cu may also be 0-500 nm. The conductive material ions used for plasma deposition also have nanometer-scale dimensions, are more uniformly distributed during deposition, and have a small difference in incident angle to the surface of the cured resin. Therefore, it is possible to ensure that the obtained plasma deposited layer has good uniformity and density, and pinhole phenomenon is less likely to occur.

As described above, ion implantation or plasma deposition may be separately employed to form a conductive seed layer on the surface of the cured resin, or a conductive seed layer may be simultaneously formed by ion implantation and plasma deposition. For example, in the example shown in FIG. 2(a), the conductive seed layer 17 formed on the surface 14 of the cured resin 12 is composed only of the ion implantation layer 18, and the outer surface of the ion implantation layer 18 is cured with the cured resin 12. The surface 14 is flush and the inner surface is located below the surface 14 of the cured resin 12, i.e., inside the cured resin 12. In the example shown in FIG. 2(d), the conductive seed layer 17 is composed only of the plasma deposition layer 20, the inner surface of which is flush with the surface 14 of the cured resin 12, and the outer surface is located. The exterior of the cured resin 12 is cured. In other words, the plasma deposited layer 20 is directly above the surface 14 of the cured resin 12. Further, in the examples shown in FIGS. 2(b) and (c), the conductive seed layer 17 formed on the surface 14 of the cured resin 12 includes the ion implantation layer 18 and plasma deposition over the ion implantation layer 18. The layer 20 in which the outer surface of the ion implantation layer 18 is flush with the surface 14 of the cured resin 12, and the inner surface is located below the surface 14 of the cured resin 12, and the plasma deposition layer 20 is attached above the ion implantation layer 18. In a preferred embodiment, as shown in FIG. 2(c), the plasma deposition layer 20 further includes a metal or metal oxide deposition layer 201 directly above the ion implantation layer 18 and the surface 14 of the cured resin, and the metal is located thereon. Or a Cu deposition layer 202 over the metal oxide deposition layer 201.

The thickened layer of the conductor above the conductive seed layer may be treated by one or more of electroplating, electroless plating, vacuum evaporation, sputtering, etc., using, for example, Al, Mn, Fe, Ti, Cr, Co, One or more of Ni, Cu, Ag, Au, V, Zr, Mo, Nb, and an alloy therebetween are formed. Electroplating is preferred because of its high plating speed, low cost, and a wide range of materials that can be plated, especially for Cu, Ni, Sn, Ag and alloys between them. For certain conductive materials, especially metals and alloys (such as Al, Cu, Ag and their alloys), the sputtering speed can reach 100 nm/min, so that the conductor can be quickly plated on the conductive seed layer using sputtering. Thickened layer. Since a uniform, dense conductive seed layer has been formed on the surface of the cured resin by ion implantation and/or plasma deposition, it is easy to form a uniform, dense conductor thickening on the conductive seed layer by the above method. The layer, which in turn forms a conductor layer together with the conductive seed layer.

The conductor thickened layer 22 formed over the conductive seed layer 17 is clearly shown in FIGS. 2(a) to 2(d). In order to facilitate the use in the subsequent process of manufacturing the coreless package substrate, thickening the initial structure thickness of the package substrate processing to improve the yield, and avoiding the occurrence of substrate warpage, the carrier 10 includes a conductive seed layer 17 and a conductor. The conductor layer 16 of the thickened layer 22 preferably has a thickness of 5 μm or less (i.e., ≤ 5 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.).

After the carrier is formed, the carrier can then be used to form a coreless package substrate. 3 is a flow chart showing a method of manufacturing a coreless package substrate in accordance with the present invention. The method comprises the steps of: forming a first wiring structure on a surface of the carrier (step S11); laminating a first bonding layer over the first wiring structure (step S12); drilling the first bonding layer (step S13) forming a conductive seed layer on the surface of the first bonding layer and the wall surface of the hole (step S14); forming a second wiring structure on the surface of the first bonding layer (step S15); and, peeling off the carrier A coreless package substrate is obtained (step S16).

Through the above steps S11 to S16, a two-layer package substrate having a surface layer and a bottom line structure can be obtained. It should be easily understood that the above steps S12 to S15 can be repeated in the case where it is desired to form a multilayer wiring structure. For example, the second conforming layer can be continuously laminated over the second wiring structure, and then the second bonding layer is drilled, and then formed on the surface of the second bonding layer and in the second bonding layer. A conductive seed layer is formed on the wall of the hole, and then a third line structure is formed on the surface of the second bonding layer, and finally the carrier is peeled off to obtain a package substrate having a three-layer wiring structure. By analogy, a multilayer package substrate having first, second, third, ... Nth line structures can be formed. In forming one or more of the intermediate circuit structures of the multilayer package substrate, that is, the second, third, ..., N-1th line structures, The copper foil can be laminated to the bonding layer, the copper foil and the bonding layer can be drilled, and then the copper foil can be etched to obtain the desired intermediate wiring structure. Since the intermediate circuit structure is not exposed, a circuit pattern with less wireframe and wire pitch requirements can be obtained by this simple method. In addition, when forming a multi-layer package substrate, each of the bonding layers may not be drilled separately in each cycle, but one or more of the plurality of bonding layers laminated together may be drilled in a certain cycle. Through holes to electrically connect the corresponding line structure at one time.

As the carrier for manufacturing the coreless package substrate, in addition to the carrier 10 shown in Figs. 2(a) to 2(d) obtained by the above method, a carrier commonly used in the art can be used, for example, via a release film. A carrier sheet formed by pressing an ultra-thin copper foil onto a prepreg at a high temperature. In addition, in the manufacture of the coreless package substrate, the line structure may be formed only on one side of the carrier, or the line structure may be formed on both sides of the carrier. In this case, two separate ones may be separated from the carrier at one time. Coreless package substrate.

As a method of forming the wiring structure, full-plate plating or pattern plating known in the art can be employed. For example, the photoresist film may be overlaid on the conductor layer of the carrier or on the conductive seed layer on the surface of the bonding layer and exposed, developed, and then etched to remove the non-circuit portion and fading, thereby forming a wiring structure. Alternatively, the photoresist film may be coated on the conductor layer of the carrier or on the conductive seed layer on the surface of the bonding layer, exposed and developed, and then subjected to integral plating, and then the film is removed and the non-circuit portion is quickly etched to form a portion. Line structure. Here, the conductor layer may be any one of the conductor layers 16 shown in FIGS. 2(a) to 2(d).

As a material for the bonding layer, a common prepreg is typically used, and PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, PPA can also be used. Such as organic polymer film, or pure resin film without fiberglass cloth (such as epoxy film). When drilling, mechanical drilling, punching, laser drilling, plasma etching, reactive ion etching, etc. may be used, wherein laser drilling may include infrared laser drilling, YAG laser drilling, and ultraviolet laser drilling. Micropores having a pore diameter of 2 to 5 μm can be formed on the substrate. The shape of the holes may be various shapes such as a circular shape, a rectangular shape, and a terrace shape, and a hole having an inverted trapezoidal cross section is usually formed in laser drilling. In addition, during laser drilling, a resin partially volatilized after vaporization of the resin may be deposited on the wall of the hole in the presence of cold. Fragments generated during cutting may also remain in the holes. Therefore, before the holes are metallized (the conductive seed layer is formed in step S14), a desmear removal process is required to avoid problems in interlayer interconnection and reliability, and to achieve good electrical contact between the electrodes. The desmear removal treatment can be carried out by plasma cleaning or chemical etching. While the slag is removed, the wall surface of the hole can be slightly corroded to roughen the wall surface, which helps the conductor layer to adhere to the wall surface of the hole. The agent used for the roughening may be sulfuric acid or basic potassium permanganate.

In step S14, when a conductive seed layer is formed on the surface of the first bonding layer and the wall surface of the hole, the method described above can be employed. For example, a conductive material may be implanted into the surface of the first bonding layer and below the wall surface of the hole by ion implantation to form an ion implantation layer as a conductive seed layer. Alternatively, a conductive material may be deposited by plasma deposition onto the surface of the first conformal layer and the wall of the hole to form a plasma deposited layer as a conductive seed layer. Optionally, a conductive material may be first implanted into the surface of the first bonding layer and below the wall surface of the hole by ion implantation to form an ion implantation layer, and then a plasma deposition layer is formed on the ion implantation layer by plasma deposition. The plasma deposition layer together with the ion implantation layer constitutes a conductive seed layer.

Specifically, ion implantation is performed using the method described above. It should be noted that when forming the carrier, it is desirable that the conductor layer on the carrier can be easily peeled off from the surface of the cured resin, thereby adjusting the parameters of the ion implantation process during the implantation process, especially using a lower acceleration voltage to obtain a comparison. The low ion flying speed is such that the predetermined bonding force between the conductor layer and the cured resin is as low as 0.01-0.05 N/mm. However, when the holes are metallized and the wiring structure is formed, it is desirable to have a large bonding force between the formed conductor layer and the bonding layer material. At this time, it is necessary to apply a higher voltage in the ion implantation apparatus, so that the conductive material ions obtain higher energy and directly hit the surface of the bonding layer and the wall surface of the hole at a higher speed, and are injected below it. The depth is, for example, 1-500 nm (e.g., 50, 100, 200, 300, 400 nm, etc.). In this way, the conductive material ions are forcibly injected into the interior of the bonding layer to form a stable chemical bond with the material molecules constituting the bonding layer to form a doping structure, which is equivalent to forming a quantity below the surface of the bonding layer and the wall surface of the hole. Numerous "base piles". The outer surface of the doped structure (ie, the ion implantation layer) is flush with the surface of the conforming layer or the wall surface of the hole, The inner surface is located at the surface of the conforming layer or at a depth of 1-500 nm below the wall surface of the hole. The bonding force between the "base pile" and the bonding layer is relatively high, and can reach 0.5 N/mm or more, for example, between 0.7-1.5 N/mm, more specifically between 0.8-1.2 N/mm, which is far large. The bonding force that can be obtained by conventional magnetron sputtering. Further, as described above, the conductive material ions for ion implantation generally have a nano-scale particle size, are more uniformly distributed during ion implantation, and have little difference in incident angles to the surface of the conforming layer and the pore walls. Therefore, it is ensured that the ion implantation layer has good uniformity and density, and pinhole phenomenon is less likely to occur. Moreover, the thickness ratio of the conductor layer on the surface of the hole wall and the surface of the bonding layer can reach 1:1, and problems such as uneven plating and holes or cracks do not occur in the subsequent plating process, and the conductive property of the metallized hole can be effectively improved. .

In addition to the ion implantation layer, the conductive seed layer formed on the surface of the bonding layer and the wall surface of the hole may further include a plasma deposition layer located above the ion implantation layer. Further, it is also possible to form a plasma deposition layer directly on the surface of the bonding layer and the wall surface of the hole by a plasma deposition method as the conductive seed layer. Each of the ion implantation layer and the plasma deposition layer may include one or more layers composed of the same or different materials. For example, the conductive seed layer 17 shown in FIGS. 2(a) to 2(d) may be formed on the wall surface of the hole drilled in the bonding layer. Of course, in the case of forming a plasma deposited layer, the drilled holes may be filled with the plasma deposited layer, that is, the entire hole is filled with a conductive material and the pore structure is no longer macroscopically present.

In any case, by forming a conductive seed layer on the surface of the bonding layer and the wall surface of the hole, the metallization of the surface of the bonding layer and the metallization of the hole walls can be simultaneously performed. Therefore, the metallized via and the surface of the bonding layer with the conductive seed layer can be directly formed by one molding, without the need to previously coat the substrate with a thick metal foil and then the metal foil as in the prior art. Etching and thinning can be used to drill holes in the substrate, and it is not necessary to form a conductive layer on the hole walls by chemical copper or black holes, black shadow, or the like to obtain metallized via holes. Compared with the prior art, the method of the invention can significantly shorten the process flow, and can reduce the use of the etching liquid and is beneficial to environmental protection. In addition, by adjusting various process parameters, such as voltage, current, and plating solution concentration during plating, the above method is easy to produce extremely thin thickness (for example, A circuit structure layer of 12 μm or less, such as 5 μm, 7 μm, 9 μm, etc., is easy to meet the fine line requirements of narrow line width and line spacing. In addition, when the ion implantation layer is formed as at least a part of the conductive seed layer, a high bonding force is generated between the hole wall and the conductive seed layer due to the presence of the ion implantation layer in the hole wall (for example, 0.5 N/mm or more, Between 0.7-1.5 N/mm, and more specifically between 0.8-1.2 N/mm), the metal layer of the cell walls will not easily fall off or scratch during subsequent processing or application. Therefore, it is advantageous to improve the conductivity of the via hole, and it is convenient to manufacture a package substrate having good conductivity.

When the wiring structure is formed in step S15, a conductor thickening layer may be formed over the conductive seed layer on the surface of the bonding layer, such that the entire conductive seed layer is thickened. Next, a photoresist film is overlaid over the conductor thickened layer and exposed and developed to expose a non-circuit portion (ie, a region where a conductive layer is not required to be formed). Then, etching is performed to remove the conductive seed layer and the conductor thickened layer in the non-circuit portion. Finally, the photoresist film is removed to form a wiring structure with a conductive seed layer and a conductor thickened layer only in the circuit portion (i.e., the region where the conductive layer needs to be formed). Alternatively, the photoresist film may be overlaid on the surface of the bonding layer and exposed and developed to expose the circuit portion. Next, electroplating is performed to form a conductor thickened layer over the conductive seed layer. Then, the photoresist film is removed and subjected to rapid etching to remove the conductive seed layer of the non-circuit portion, thereby obtaining a wiring structure. At this time, the thickened layer of the conductor is also etched away to a thickness at least equal to the thickness of the conductive seed layer, but this does not greatly affect the electrical conductivity of the wiring structure. The formation of the thickened layer of the conductor can be carried out by the method described above. For example, a plating solution composed of copper sulfate 100-200 g/L, sulfuric acid 50-100 g/L, chloride ion concentration 30-90 mg/L, and a small amount of additives may be used to form a thickness of 1 above the conductive seed layer by electroplating. a thick copper layer of -1000 μm (for example, 2 μm, 5 μm, 10 μm, 12 μm, 50 μm, 100 μm, 500 μm, etc.). Further, it is also possible to press the copper foil onto the surface of the bonding layer, and remove the non-circuit portion of the copper foil by etching, thereby obtaining a wiring structure.

In step S16, the entire line structure on the carrier is separated from the carrier to obtain a desired coreless package substrate. When the carrier 10 shown in Figs. 2(a) to 2(d) is used, this separation process will combine the wiring structure together with the conductor layer 16 including the conductive seed layer 17 and the conductor thickening layer 22 formed on the carrier 10. Stripped together because the conductor layer 16 and the cured resin 12 The bond between the two is as low as 0.01-0.05 N/mm. The peeled cured resin 12 no longer has the conductor layer 16 on the surface, and can be further used for the production of the carrier by further processing. In addition, when a common high-temperature pressure-bonding carrier plate is used as a carrier, since the surface of the prepreg is press-fitted with a release film, the wire structure can be peeled off together with the copper foil on the release film by applying an external force to form a coreless body. Package substrate. In both cases, it is desirable to quickly etch the side of the package substrate adjacent the carrier to remove the existing conductor layer or copper foil to avoid shorting of the first line structure. In the case where the thicker conductor layer 16 on the carrier 10 is directly removed by etching to form the first wiring structure, although the conductor layer of the non-circuit portion is no longer present on the lower surface of the package substrate, it may be necessary to perform rapid etching. Get a relatively flat surface.

After the separation and rapid etching, a solder resist layer may be formed on the surface of the package substrate, a window is formed on the solder resist layer after exposure and development, and a solder resist layer formed with a window is cured. The solder resist layer is a protective layer that prevents physical disconnection of the wiring structure on the package substrate, and prevents short circuits caused by bridging during the soldering process and prevents contamination due to external factors such as water vapor and dust. Insulation deteriorates and corrodes the line structure. By opening the solder mask, the electrodes that require the patch and the plug-in can be exposed to access other circuits or electronic components.

The coreless package substrate obtained by the above method is composed of a first line structure, a first bonding layer, a second line structure, a second bonding layer, a third bonding layer, ..., an Nth line structure, wherein The first circuit structure is embedded in the first bonding layer, the coreless package substrate is formed with a hole and a conductive seed layer is formed on the wall surface of the hole, and the conductive seed layer includes ion implantation injected below the wall surface of the hole. A layer and/or a plasma deposited layer formed over the wall of the aperture. The outer surface of the first wiring structure is flush with the outer surface of the first bonding layer, and the inner surface is located inside the first bonding layer. The ion implantation layer (if present) is a doped structure formed by the conductive material and the bonding layer, the outer surface of which is flush with the wall surface of the hole or the surface of the bonding layer, and the inner surface is located below the surface of the hole or the surface of the bonding layer. At a depth of 1-500 nm. The inner surface of the plasma deposited layer, if present, is flush with the wall surface of the aperture or the surface of the conforming layer, while the outer surface is external to the conforming layer.

The method of manufacturing a coreless package substrate according to the present invention is generally described above. In the following, several specific embodiments for carrying out the method will be exemplified in order to enhance the understanding of the invention.

(First Embodiment)

4(a) to 4(f) are cross-sectional views showing the structure corresponding to the respective steps of the method shown in Fig. 3 in the production of a two-layer package substrate in accordance with a first embodiment of the present invention.

First, as shown in FIG. 4(a), a coreless package substrate including an outer surface and a cured resin 12 is prepared using the carrier 10 as shown in FIG. 2(a) obtained by the method described above. The surface 14 is flush and the inner surface is located below the surface 14 of the ion implantation layer 18 and the conductor thickened layer 22 above the ion implantation layer 18. On the upper and lower surfaces of the carrier 10, a conventional pattern plating or full-plate plating method is used to form the first wiring structure 102. In the present embodiment, the copper foil is directly pressed onto the surface of the carrier 10, and the non-circuit portion of the copper foil is removed by etching, thereby obtaining the first wiring structure 102. In the case where the conductor layer 16 on the carrier 10 is sufficiently thick, the first circuit structure 102 can also be obtained by directly removing the non-circuit portion of the conductor layer 16 by etching. This eliminates the need for copper foil and high temperature compression, which shortens the process and reduces costs.

Next, as shown in FIG. 4(b), the first bonding layer 104 is laminated over the first wiring structure 102. In this step, a first conformal laminate composed of a prepreg may be laminated over the first wiring structure 102 in a high temperature laminator at a temperature of 210-220 °C. After the heat curing, the prepreg becomes a cured state, and the warpage of the double-layer package substrate can be avoided. Thereafter, as shown in FIG. 4(c), a hole 108 is drilled in the first bonding layer 104 by laser drilling. The hole 108 leads directly to the circuit pattern in the first line structure 102 to electrically connect the circuit patterns on both sides of the first bonding layer 104. Although a hole 108 having a rectangular cross section is illustrated in FIG. 4(c), it should be readily understood that the illustration is merely exemplary. The holes formed by laser drilling generally have a longitudinal section of an inverted trapezoid, and the shapes of the holes may be various shapes such as a cylindrical shape, a rectangular shape, and a terrace shape.

Then, as shown in FIG. 4(d), a conductive material is implanted under the surface 106 of the first bonding layer 104 and below the hole wall 110 of the hole 108 by ion implantation to form an ion implantation layer. 118, and a conductive material is deposited by plasma deposition, and a plasma deposition layer 120 is formed over the ion implantation layer 118, which together with the ion implantation layer 118 constitutes a conductive seed layer 117. A conductive seed layer 117 composed of both the ion implantation layer 118 and the plasma deposition layer 120 is shown in FIG. 4(d), but it should be readily understood that the conductive seed layer 117 may also include only the ion implantation layer 118 and Any of the structures in the plasma deposition layer 120, as described above.

Next, a conductive thick layer 122 is formed over the conductive seed layer 117 on the surface 106 of the bonding layer, and the photoresist film is overlaid on the conductive thick layer 122 and exposed and developed to expose the non-circuit portion. . Then, etching is performed to remove the conductive seed layer 117 and the conductor thickening layer 122 in the non-circuit portion. Finally, the photoresist film is removed to form a wiring structure having the conductive seed layer 117 and the conductor thickening layer 122 only in the circuit portion. As shown in FIG. 4(e), the resulting second wiring structure 124 includes an ion implantation layer 118 implanted below the surface 106 of the first bonding layer 104, a plasma deposition layer 120 over the ion implantation layer 118, and A conductor thickened layer 122 is disposed over the plasma deposition layer 120. This method is the "full-plate plating" described above.

Finally, the entire wiring structure on the upper and lower surfaces of the carrier 10 is peeled off from the carrier 10 by applying an external force, thereby obtaining two separate coreless package substrates 100 as shown in Fig. 4(f). In the carrier 10, the bonding force between the conductor layer and the cured resin can be controlled to be as low as 0.01 to 0.05 N/mm, and thus the conductor layer is easily separated from the cured resin during the peeling process. After stripping, the conductor layer 16 will adhere below the first line structure 124. At this time, the conductor layer 16 needs to be removed by means of rapid etching or the like, and then a solder resist layer is formed on the surface of the resulting package substrate 100 and fenestrated to protect the wiring structure on the package substrate and form a desired electrical connection.

Ion implantation and/or plasma deposition may be performed again on the peeled cured resin 12, and a conductor layer which is easily peeled off is formed again on the surface of the cured resin 12. By adjusting various parameters of the ion implantation and/or plasma deposition process (eg, voltage, current, vacuum, implant dose, etc.), a desired lower bonding force can be easily obtained between the cured resin and the conductor layer, for example, 0.01. Between -0.05 N/mm, such binding force can be repeated and Obtained steadily. That is, the cured resin after peeling can easily repeat the carrier for preparing the coreless package substrate.

(Second embodiment)

5(a) to 5(j) are cross-sectional views showing the structure corresponding to the respective steps of the method shown in Fig. 3 in the production of a three-layer package substrate in accordance with a second embodiment of the present invention.

First, as shown in FIG. 5(a), the carrier 10 formed by press-bonding the thin copper foil 132 to the prepreg 134 via the release film 130 is used. Alternatively, the prepreg, the copper support plate, the release film, and the thin copper foil may be sequentially pressed together at a high temperature to obtain a desired carrier. High temperature pressing refers to the use of high temperature and high pressure to melt the prepreg and convert it into a solidified sheet, thereby pressing the prepreg copper plate or copper foil on both sides. The carrier thus obtained greatly increases the thickness of the initial structure of the three-layer package substrate, thereby improving the operability of the process and making the subsequent process easy to control, and improving the fabrication yield of the package substrate. The cross-sectional structures shown in Figs. 5(a) to 5(e) correspond to Figs. 4(a) to 4(e), respectively, except for the carrier used. It should be noted that, when the second wiring structure 124 is formed, the copper foil may be simply laminated onto the first bonding layer, then the copper foil and the first bonding layer are drilled, and then the copper foil is etched. Obtain the desired line structure.

In order to form a three-layer wiring structure, it is necessary to continue laminating the second bonding layer 126 over the second wiring structure 124 after forming the second wiring structure 124, as shown in FIG. 5(f). When the second bonding layer 126 is laminated, the second bonding layer 126 composed of the prepreg may be pressed at a high temperature to the second line in a high temperature laminator at a temperature of 210-220 ° C as described above. Above the structure 124. In the case of forming a three-layer package substrate, two bonding layers 104 and 126 are used. Thus, preferably, the first bonding layer 104 is pressed at a low temperature at a temperature of 110-130 ° C for 5-20 minutes, at which time the first bonding layer 104 remains in a semi-cured state. When the second bonding layer 126 is subsequently laminated, high temperature bonding is performed at a temperature of 210 to 220 ° C. At this time, the first bonding layer 104 is pressed together with the second bonding layer 126 at a high temperature to be in a cured state. Since the conditions of the first and second bonding layers are the same when cured, the internal stress between them is uniform, and the warpage of the three-layer package substrate can be avoided.

Holes 108 are then drilled into the second conforming layer 126 by laser drilling. The The hole 108 leads directly to the circuit pattern in the second line structure 124 to facilitate electrical connection of the circuit pattern on both sides of the second bonding layer 126, as shown in Figure 5(g). In this embodiment, the first bonding layer 104 may not be drilled in advance, but after the second bonding layer 126 is laminated, the first and second bonding layers 104 and 126 are respectively drilled. The through hole of the person and the through hole penetrating only the second bonding layer 126. In this way, the drilling process can be reduced, but the electrical connections required between only the line structures on both sides of the first bonding layer 104 may not be realized. When drilling through the two bonding layers, two or more laser drillings may be performed in succession so that the holes successively penetrate the second bonding layer 126 and the first bonding layer 104.

Next, a conductive material is implanted under the surface of the second bonding layer 126 and under the hole wall 110 of the hole 108 by ion implantation by the method described above to form the ion implantation layer 118 as the conductive seed layer 117. As shown in Figure 5 (h). Of course, as described above, the conductive seed layer 117 may also include the plasma deposited layer 120 over the ion implantation layer 118, or may include only the surface directly above the surface of the second conforming layer 126 and the wall 110 of the aperture 108. Plasma deposited layer 120.

Then, a third wiring structure 128 is formed on the surface of the second bonding layer 126 by pattern plating. That is, the photoresist film is first overlaid on the ion implantation layer 118 (that is, the conductive seed layer 117) formed under the surface of the second bonding layer 126, and exposed and developed to expose the circuit portion. Next, electroplating is performed to form the conductor thickened layer 122 only over the circuit portion of the conductive seed layer 117. Then, the photoresist film is removed and subjected to rapid etching to remove the conductive seed layer 117 of the non-circuit portion, thereby obtaining the third wiring structure 128. At this time, the conductor thickening layer 122 located above the conductive seed layer 117 in the circuit portion is also etched away to a thickness at least equal to the thickness of the conductive seed layer 117, but does not cause a large electrical conductivity of the wiring structure. The negative impact.

Finally, the entire wiring structure on both sides of the carrier 10 is peeled off from the carrier 10 by applying an external force, thereby obtaining two separate three-layer wiring structures (i.e., the first, second and third wiring structures 102, 124 and The coreless package substrate 100 of 128) is as shown in Fig. 5(j). After the peeling, the release film 130 may adhere to the lower surface of the first wiring structure 102 along with the copper foil 132. At this time, it is necessary to remove the release film 130 in advance, and then pass the fast The copper foil 132 attached to the lower surface of the first wiring structure is etched away to obtain a desired package substrate. Of course, the release film 130 may remain adhered to the prepreg 134 after peeling, at which time its adhesion is greatly reduced, and it is necessary to replace it with a new release film to continue to be used for preparing a new carrier. In any event, the carrier comprising the release film is more complicated to handle than the carrier obtained by ion implantation and/or plasma deposition in the present invention, and cannot be conveniently reused.

The above description refers only to the preferred embodiment of the invention. However, the invention is not limited to the specific embodiments described herein. It will be readily apparent to those skilled in the art that various modifications, adaptations and substitutions may be made to these embodiments to adapt to a particular situation without departing from the scope of the invention. Indeed, the scope of the invention is defined by the claims, and may include other examples that are contemplated by those skilled in the art. If such other examples have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements that are not significantly different from the literal language of the claims, they are intended to fall within the scope of the appended claims .

Claims (23)

1. A method of manufacturing a carrier for a coreless package substrate, comprising the steps of:

   S1: forming a cured resin;

   S2: forming a conductor layer which is easily peeled off on the surface of the cured resin, and a bonding force between the conductor layer and the cured resin is 0.01 to 0.05 N/mm.
2. The method according to claim 1, wherein the step S1 comprises laminating a low-roughness surface of the metal sheet with the uncured resin, and removing the metal sheet after lamination and heat curing, thereby obtaining the cured resin. .
3. The method according to claim 2, wherein said resin comprises one of a bismaleimide triazine resin, an epoxy resin, a cyanate resin, a polyphenylene ether resin, and a modified resin thereof. Or a variety.
4. The method according to claim 1, wherein the step S2 comprises first forming a conductive seed layer on the surface of the cured resin, and then forming a conductor thickening layer on the conductive seed layer, the conductive seed crystal The layer and the thickened layer of the conductor constitute the conductor layer.
5. The method of claim 4 wherein said conductive seed layer is formed by:

   A conductive material is injected under the surface of the cured resin by ion implantation to form an ion implantation layer as the conductive seed layer; or

   Depositing a conductive material on the surface of the cured resin by plasma deposition to form a plasma deposited layer as the conductive seed layer; or

   First, a conductive material is injected under the surface of the cured resin by ion implantation to form an ion implantation layer, and then a plasma deposition layer is formed over the ion implantation layer by plasma deposition, the ion implantation layer and the plasma The bulk deposited layers together constitute the conductive seed layer.
6. The method according to claim 5, wherein the ion implantation layer is a doped structure formed by the conductive material and the cured resin, the outer surface of which is flush with the surface of the cured resin, and the inner surface Located at a depth of 1-100 nm below the surface of the cured resin Degree.
7. The method according to claim 5, wherein said plasma deposited layer comprises a metal or metal oxide deposited layer having a thickness of 0 to 500 nm, and is located above said metal or metal oxide deposited layer and having a thickness of 0 a 500 nm Cu deposition layer, wherein the metal deposition layer comprises Ni or a Ni-Cu alloy, and the metal oxide deposition layer contains NiO.
8. The method according to claim 4, wherein the step S2 comprises forming the conductor plus the conductive seed layer by one or more of electroplating, electroless plating, vacuum evaporation plating, and sputtering. Thick layer.
9. A carrier for a coreless package substrate, comprising:

   Curing resin; and

   A conductor layer which is easily peeled off on the surface of the cured resin, and a bonding force between the conductor layer and the cured resin is 0.01 to 0.05 N/mm.
10. The carrier according to claim 9, wherein the cured resin comprises one of a bismaleimide triazine resin, an epoxy resin, a cyanate resin, a polyphenylene ether resin, and a modified resin thereof. One or more kinds, and the cured resin has a surface roughness of 2.5 μm or less.
11. The carrier according to claim 9, wherein said conductor layer comprises a conductive seed layer and a conductor thickening layer over said conductive seed layer.
12. The carrier according to claim 11, wherein the conductive seed layer comprises:

    An ion implantation layer whose outer surface is flush with the surface of the cured resin and whose inner surface is located inside the cured resin; or

    a plasma deposition layer located above the surface of the cured resin; or

    An ion implantation layer whose outer surface is flush with the surface of the cured resin and whose inner surface is located inside the cured resin, and a plasma deposition layer located above the ion implantation layer.
13. The carrier according to claim 12, wherein the ion implantation layer is a doped structure formed of a conductive material and the cured resin, the inner surface of which is located in the curing The surface of the resin is at a depth of 1-100 nm below.
14. The carrier according to claim 12, wherein the plasma deposition layer comprises a metal or metal oxide deposition layer having a thickness of 0 to 500 nm, and is located above the metal or metal oxide deposition layer and has a thickness of 0. a 500 nm Cu deposition layer, wherein the metal deposition layer comprises Ni or a Ni-Cu alloy, and the metal oxide deposition layer contains NiO.
15. The carrier according to claim 11, wherein said conductor thickening layer comprises a Cu layer having a thickness of 0 to 5 μm.
16. A method of manufacturing a coreless package substrate, comprising the steps of:

    S11: forming a first line structure on a surface of the carrier;

    S12: laminating a first bonding layer over the first line structure;

    S13: drilling the first bonding layer;

    S14: forming a conductive seed layer on the surface of the first bonding layer and the wall surface of the hole by:

    A conductive material is implanted into the surface of the first bonding layer and below the wall surface of the hole by ion implantation to form an ion implantation layer as the conductive seed layer; or

    Depositing a conductive material onto the surface of the first bonding layer and the wall surface of the hole by plasma deposition to form a plasma deposition layer as the conductive seed layer; or

    First, a conductive material is injected into the surface of the first bonding layer and below the wall surface of the hole by ion implantation to form an ion implantation layer, and then a plasma deposition layer is formed over the ion implantation layer by plasma deposition. The ion implantation layer and the plasma deposition layer together constitute the conductive seed layer;

    S15: forming a second line structure on a surface of the first bonding layer;

    S16: peeling off the carrier to obtain a coreless package substrate.
17. The method according to claim 16, wherein steps S12 to S15 are repeated to form a multi-layer package substrate having a first, second, third, ... Nth line structure.
18. The method according to claim 17, wherein in forming one or more of the intermediate circuit structures of the multilayer package substrate, that is, the second, third, ..., N-1th line structures, A copper foil was laminated to the bonding layer, the copper foil and the bonding layer were drilled, and then the copper foil was etched to obtain the intermediate wiring structure.
19. The method according to claim 16, wherein the carrier is a carrier manufactured by the method according to any one of claims 1-8, or according to any one of claims 9-15 Carrier.
20. The method of claim 16 wherein step S11 comprises forming a first line structure on both sides of the carrier, and step S16 comprises stripping the carrier from both sides to obtain two separate package substrates.
21. The method according to claim 16, wherein in said steps S11, S15, said first and second wiring structures are formed by a full-plate plating or a pattern plating method.
22. The method according to claim 16, wherein the ion implantation layer is a doped structure formed by the conductive material and the first bonding layer, and an outer surface thereof and a surface of the first bonding layer Or the wall surface of the hole is flush, and the inner surface is located at a depth of 1-500 nm below the surface of the first bonding layer or the wall surface of the hole.
23. The method according to claim 16, wherein the step S14 further comprises forming a conductor thickening over the conductive seed layer by one or more of electroplating, electroless plating, vacuum evaporation plating, and sputtering. a layer, the conductor thickening layer comprising Cu.

Images