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WO2017145473A1 - Module device - Google Patents

Module device Download PDF

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Publication number
WO2017145473A1
WO2017145473A1 PCT/JP2016/085137 JP2016085137W WO2017145473A1 WO 2017145473 A1 WO2017145473 A1 WO 2017145473A1 JP 2016085137 W JP2016085137 W JP 2016085137W WO 2017145473 A1 WO2017145473 A1 WO 2017145473A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
bump
module
substrate
main surface
Prior art date
Application number
PCT/JP2016/085137
Other languages
French (fr)
Japanese (ja)
Inventor
彰 道上
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2017145473A1 publication Critical patent/WO2017145473A1/en
Priority to US16/057,841 priority Critical patent/US10581401B2/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders or supports
    • H03H9/058—Holders or supports for surface acoustic wave devices
    • H03H9/059—Holders or supports for surface acoustic wave devices consisting of mounting pads or bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02559—Characteristics of substrate, e.g. cutting angles of lithium niobate or lithium-tantalate substrates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders or supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0542—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a lateral arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders or supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1092—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/145—Driving means, e.g. electrodes, coils for networks using surface acoustic waves
    • H03H9/14544—Transducers of particular shape or position
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/64—Filters using surface acoustic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

Definitions

  • the present invention relates to a module device in which a filter chip is mounted on a module substrate.
  • Patent Document 1 describes a structure in which a surface acoustic wave chip is mounted on a circuit board as a module board.
  • This surface acoustic wave chip has a columnar conductor that is not electrically connected to the IDT electrode.
  • This columnar conductor is exposed to the module substrate side. That is, the columnar conductor in an electrically floating state is exposed on the side facing the circuit board of the surface acoustic wave chip.
  • the columnar conductor is joined to the ground pad on the circuit board by solder or the like. Thereby, the bonding strength of the surface acoustic wave chip to the circuit board is increased.
  • Patent Document 1 a columnar conductor that is not electrically connected to an IDT electrode needs to be bonded to a ground pad on a circuit board. For this reason, in the module substrate, there is a restriction on the arrangement of the signal wiring in the surface acoustic wave chip mounting region. Therefore, the module device cannot be sufficiently reduced in size.
  • An object of the present invention is to provide a module device in which the degree of freedom of arrangement of signal wirings in the mounting area on the module substrate is enhanced and the size can be reduced.
  • a module device comprises a module substrate having an electrode land provided on one main surface, a signal wiring, and a filter chip mounted on the module substrate, wherein the filter chip is A chip substrate having a main surface facing the one main surface of the module substrate; and provided on the chip substrate, having a functional electrode portion and a plurality of bumps, the plurality of bumps having a signal potential A first bump connected to a ground potential; a second bump connected to a ground potential; and a third bump not electrically connected to the functional electrode portion; and the first bump of the filter chip.
  • a third bump is bonded to the module substrate, and the third bump is disposed in a mounting region in which the filter chip is projected onto the one main surface of the module substrate.
  • the one said electrode lands and the signal wiring provided on the main surface of the module substrate, and is electrically connected to the signal line.
  • the filter chip is an elastic wave filter chip
  • the chip substrate is a piezoelectric substrate.
  • the third bump is between the first bumps, between the second bumps, or between the first bumps and the second bumps. Is arranged. In this case, the module device can be further reduced in size.
  • a chip-side electrode land bonded to the third bump is provided on the main surface of the chip substrate.
  • a chip-side electrode land bonded to the third bump is laminated on the main surface of the chip substrate via another material layer. ing.
  • the other material layer is made of a dielectric having a dielectric constant lower than that of the chip substrate. In this case, the electrical characteristics of the module device are more unlikely to deteriorate.
  • the signal wiring is electrically connected to the first bump and extends outside the mounting area.
  • the module device further includes an electronic component chip that is mounted on the one main surface of the module substrate and is different from the filter chip, and the signal wiring is the other It is electrically connected to the electronic component chip.
  • the module device further includes first and second electronic component chips that are mounted on the one main surface of the module substrate and different from the filter chip, The first and second electronic component chips are electrically connected by the signal wiring.
  • the module device can be further reduced in size.
  • the mounting region has a rectangular shape, and the signal wiring extends outside the mounting region across different sides of the rectangle.
  • the module device can be further miniaturized.
  • the elastic wave filter chip has an IDT electrode as the functional electrode unit, and the elastic wave filter chip has the IDT electrode on the piezoelectric substrate.
  • a support layer provided to surround the cover layer and a cover member provided to seal a facing portion of the support layer, and the cover member side faces the one main surface of the module substrate.
  • the acoustic wave filter chip is mounted on the one main surface of the module substrate.
  • the module device of the present invention it is possible to increase the degree of freedom of the arrangement of signal wirings in the mounting area where the filter chip is mounted on the module substrate. Therefore, it is possible to reduce the size of the module device.
  • FIG. 1 is a schematic plan view of a module device according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the module device according to the first embodiment of the present invention, corresponding to the portion along line AA in FIG.
  • FIG. 3 is a bottom view showing the electrode structure on the first main surface of the filter chip in the module device according to the first embodiment of the present invention.
  • FIG. 4 is a schematic plan view for explaining a module device according to the second embodiment of the present invention.
  • FIG. 5 is a front sectional view showing the main part of the filter chip mounted on the module substrate in the third embodiment of the present invention.
  • FIG. 6 is a diagram illustrating the filter characteristics of the module device according to the third embodiment of the present invention and no dielectric layer.
  • FIG. 1 is a schematic plan view of a module device according to a first embodiment of the present invention.
  • the module device 1 has a module substrate 2.
  • the module substrate 2 has an upper surface 2a as one main surface.
  • a plurality of electrode lands 3 and 4 connected to the ground potential are provided on the upper surface 2a.
  • signal wirings 5 and 6 are also provided on the upper surface 2a.
  • the module substrate 2 is made of an appropriate insulating material or semiconductor material.
  • the electrode lands 3 and 4 and the signal wirings 5 and 6 are made of a metal film.
  • the metal film may be a laminated metal film in which a plurality of metal films are laminated.
  • the filter chip 11 is mounted on the module substrate 2.
  • the mounting area in which the filter chip 11 is mounted is indicated by a broken line.
  • the mounting region refers to a region where the filter chip 11 is projected onto the upper surface 2a of the module substrate 2.
  • An electronic component chip 12 other than the filter chip 11 is also mounted on the module substrate 2.
  • the mounted part is schematically shown by a broken line.
  • the filter chip 11 is an elastic wave filter chip.
  • the acoustic wave filter chip has a plurality of bumps 11a to 11f indicated by circles in FIG.
  • the bumps 11a to 11f are bonded to the electrode lands 3 and 4 or the signal wirings 5 and 6 on the upper surface 2a of the module substrate 2.
  • the bumps 11a and 11c are the first bumps in the present invention
  • the bumps 11d, 11e and 11f are the second bumps connected to the ground potential
  • the bumps 11b are the floating bumps described later. It becomes a bump. This will be described more specifically with reference to FIG.
  • FIG. 2 is a cross-sectional view of the module device 1 corresponding to the line AA in FIG.
  • FIG. 2 shows a cross section of a portion where the bumps 11b, 11c, and 11f are provided among the plurality of bumps 11a to 11f described above.
  • Bumps 11 f are joined to the electrode lands 4.
  • the bumps 11 b are connected to the signal wiring 5.
  • Bumps 11 c are joined to the signal wiring 6.
  • the filter chip 11 has a piezoelectric substrate 13 as a chip substrate.
  • the piezoelectric substrate 13 is made of a piezoelectric single crystal such as LiTaO 3 or LiNbO 3 .
  • piezoelectric ceramics may be used.
  • the electrode structure provided on the main surface 13a on the side facing the module substrate 2 of the piezoelectric substrate 13 is shown in a bottom view in FIG.
  • a functional electrode portion 14 is provided on the main surface 13a.
  • the functional electrode unit 14 includes a plurality of IDT electrodes and constitutes a band-pass surface acoustic wave filter.
  • the electrode structure of the functional electrode portion 14 is not particularly limited, and an appropriate electrode structure constituting the filter circuit can be used.
  • One end of each of the extraction electrodes 16a, 16c to 16f is connected to the functional electrode portion 14.
  • the other ends of the extraction electrodes 16a and 16c to 16f are connected to the chip side electrode lands 17a and 17c to 17f.
  • the aforementioned bumps 11a, 11c to 11f are joined to the chip side electrode lands 17a and 17c to 17f.
  • the bumps 11 a and 11 c are first bumps that are electrically connected to the signal wiring 5 or 6.
  • the first bumps 11a and 11c are connected to the functional electrode portion 14 via chip-side electrode lands 17a and 17c.
  • the second bumps 11d, 11e, and 11f are connected to the ground potential of the functional electrode portion 14 through the extraction electrodes 16d, 16e, and 16f and the chip-side electrode lands 17d, 17e, and 17f.
  • the chip-side electrode land 17b is not electrically connected to the functional electrode portion 14.
  • the third bump 11b is provided on the chip side electrode land 17b. Therefore, the third bump 11 b is a so-called floating bump that is not electrically connected to the functional electrode portion 14.
  • the floating bump is a bump which is not electrically connected to the signal potential or the ground potential in the filter chip 11 and is in an electrically floating state. As shown in FIGS. 1 and 2, the third bump 11 b is bonded to the signal wiring 5 in the mounting region described above.
  • the support layer 18 made of an insulating material is provided on the main surface 13a of the piezoelectric substrate 13 in the portion where the chip side electrode lands 17b, 17c, and 17f are provided.
  • a through hole is provided so as to penetrate the support layer 18.
  • the support layer 18 is made of a synthetic resin or an inorganic insulating material.
  • a cover member 20 is provided on the front end side of the support layer 18.
  • the cover member 20 is made of a synthetic resin or an inorganic insulating material.
  • a portion surrounded by the cover member 20 and the support layer 18 is a hollow portion and sealed.
  • the functional electrode portion 14 described above is located in this hollow portion.
  • a through hole is provided so as to penetrate the support layer 18 and the cover member 20.
  • An under bump metal layer 19 is provided in the through hole.
  • the under bump metal layer 19 is provided on the chip side electrode lands 17b, 17c, and 17f.
  • the under bump metal layer 19 is made of a metal or an alloy.
  • the filter chip 11 has a so-called WLP type package structure including the piezoelectric substrate 13, the support layer 18, and the cover member 20.
  • the filter chip 11 is mounted on the module substrate 2 in a face-down manner using the bumps 11a to 11f.
  • the filter chip is not limited to one having a WLP structure.
  • a filter chip having an appropriate package structure such as a CSP structure can be used.
  • the feature of this embodiment is that the third bump 11b which is the floating bump is joined to the signal wiring 5 in the mounting region. This will be described in more detail with reference to FIG.
  • the signal wiring 5 is provided on the upper surface 2 a of the module substrate 2 so as to electrically connect the filter chip 11 and the electronic component chip 12.
  • the signal wiring 5 is a wiring through which a signal current flows.
  • the first bump 11a is electrically connected to the functional electrode portion 14, and a signal flows from the first bump 11a to the signal wiring 5 to reach the bump 12a connected to the electronic component chip 12.
  • the third bump 11b which is a floating bump is not connected to the functional electrode portion 14 and the ground potential.
  • the third bump 11 b that is a floating bump is also bonded to the signal wiring 5. That is, the third bump 11 b that is a floating bump is joined to the signal wiring 5 in a rectangular mounting region in which the filter chip 11 is projected onto the upper surface 2 a of the module substrate 2.
  • the third bump 11b which is the floating bump, is provided at a position sandwiched between the second bump 11f and the first bump 11c. Accordingly, the signal wiring 5 passes between the second bump 11f and the first bump 11c from the side bonded to the first bump 11a in the rectangular mounting region, and is on the electronic component chip 12 side. It is extended to.
  • the signal wiring 5 can be arranged so that the third bump 11b, which is the floating bump, is joined to the signal wiring 5 in the mounting region. Therefore, the degree of freedom of arrangement of the signal wiring 5 in the mounting area is increased, and it is possible to effectively reduce the size.
  • the third bump 11b which is the floating bump, is also bonded to the signal wiring 5, in this embodiment, the bonding strength of the filter chip 11 to the module substrate 2 by the large number of bumps 11a to 11f. Is also raised enough.
  • FIG. 4 is a schematic plan view of a module device according to the second embodiment of the present invention.
  • the filter chip 11 is mounted on the upper surface 2a of the module substrate 2 in the same manner as in the first embodiment.
  • the filter chip 11 is the same as the filter chip 11 used in the first embodiment, and includes first bumps 11a and 11c, second bumps 11d, 11e, and 11f, and a third bump 11b.
  • a plurality of electronic component chips 32 and 33 are mounted on the upper surface 2 a of the module substrate 2.
  • the electronic component chip 32 has bumps 32a connected to the signal potential.
  • the electronic component chip 33 has bumps 33a connected to the signal potential.
  • electrode lands 3 and 4 connected to the ground potential and signal wirings 34 to 36 connected to the signal potential are provided on the upper surface 2a of the module substrate 2.
  • the first bump 11 a is bonded to the signal wiring 35
  • the first bump 11 c is bonded to the signal wiring 36.
  • the third bump 11 b that is a floating bump is joined to the signal wiring 34.
  • the signal wiring 34 is not electrically connected to the filter chip 11.
  • the signal wiring 34 electrically connects the electronic component chip 32 and the electronic component chip 33. That is, the bump 32 a and the bump 33 a are connected by the signal wiring 34.
  • the third bump 11 b that is a floating bump may be joined to the signal wiring 34 that is not electrically connected to the filter chip 11. Even in this case, the degree of freedom of arrangement of the signal wirings 34 in the mounting region in which the filter chip 11 is projected onto the upper surface 2a of the module substrate 2 can be increased. Therefore, since no extra space is required for routing the signal wiring 34, the size can be reduced. In addition, since the filter chip 11 is bonded to the module substrate 2 also by the third bump 11b that is the floating bump, the bonding strength between the filter chip 11 and the module substrate 2 is sufficiently increased.
  • the signal wiring 34 to which the third bump 11 b that is a floating bump is joined may be one that joins the other electronic component chips 32 and 33 to each other in the filter chip 11.
  • signal wirings 34 are provided so as to connect two different sides of the rectangular mounting area. That is, the signal wiring 34 has a portion extending in the mounting area, a portion extending outside one side of the mounting region, and a portion extending outside the other side. By shortening the connection length between the electronic component chips 32 and 33 by the signal wiring 34, the size can be further reduced.
  • the signal wiring 34 does not necessarily have to be extended outward from two adjacent sides of the mounting area. It may be extended outside any two sides. Alternatively, it may be extended outside the mounting area from the same side of the mounting area. That is, a position where the signal wiring 34 reaches outside the mounting area may be selected according to the position of the electronic component chips 32 and 33 positioned outside the mounting area.
  • FIG. 5 is a front sectional view showing the main part of the filter chip mounted on the module substrate of the third embodiment of the present invention.
  • the filter chip 41 has a piezoelectric substrate 13. Similar to the filter chip 11, the functional electrode portion 14 is provided on the main surface 13 a of the piezoelectric substrate 13 on the side facing the module substrate 2 described above. In FIG. 5, only a part of the electrode portion of the functional electrode portion 14 is illustrated. A support layer 43 is provided on the electrode land 42 joined to the functional electrode portion 14. The electrode land 44 is provided on the main surface 13a with the dielectric layer 45 interposed therebetween. The dielectric constant of the dielectric layer 45 is lower than the dielectric constant of the piezoelectric substrate 13. As a material for constituting such a dielectric layer 45, a synthetic resin such as polyimide or an inorganic insulating material such as silicon oxide can be appropriately used.
  • the electrode land 44 is not electrically connected to the functional electrode portion 14, that is, is provided as a floating electrode land.
  • a support layer 43 is provided so as to cover the electrode land 44.
  • the cover member 20 is provided on the support layer 43.
  • a hollow portion B is provided by the support layer 43 and the cover member 20.
  • the functional electrode portion 14 faces the hollow portion B.
  • a through hole is provided so as to penetrate the support layer 43 and the cover member 20.
  • An under bump metal layer 46 is provided in the through hole.
  • a third bump 11 b as a floating bump is provided on the under bump metal layer 46 on the electrode land 44.
  • the first bump 11 a connected to the signal potential is provided so as to be electrically connected to the electrode land 42.
  • the electrode land 44 to which the third bump 11b, which is a floating bump, is bonded may not be in direct contact with the main surface 13a of the piezoelectric substrate 13. That is, the electrode land 44 may be provided on the main surface 13a of the piezoelectric substrate 13 via the dielectric layer 45 as another material layer. Further, preferably, the dielectric layer 45 is used as another material layer as in the present embodiment. However, a material layer other than the dielectric layer 45 may be used as the other material layer.
  • the filter characteristics in the module device can be improved. This will be described with reference to FIG.
  • FIG. 6 is a diagram showing the filter characteristics by the filter chip in the module device of the third embodiment, and the solid line shows the result of the third embodiment.
  • the broken lines indicate the filter characteristics of the module device configured in the same manner as in the third embodiment except that the dielectric layer 45 is not provided.
  • the solid line in FIG. 6 is the result when polyimide is used as the dielectric layer 45.
  • the attenuation outside the passband can be made sufficiently smaller than when the dielectric layer 45 is not provided. This is presumably because the dielectric constant of the dielectric layer 45 is lower than the dielectric constant of the piezoelectric substrate 13, thereby suppressing the influence of capacitive coupling of the signal that has entered the third bump 11 b that is a floating bump. Therefore, it is preferable to provide the dielectric layer 45 as described above.

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

To provide a module device whereby a degree of freedom in disposing a signal wiring line in a mounting region can be improved, and size reduction can be achieved. On an upper surface 2a, i.e., one main surface of a module substrate 2, a plurality of electrode lands 3, 4, and signal wiring lines 5, 6 are provided. On the module substrate 2, a filter chip 11 is mounted. The filter chip 11 has a plurality of bumps 11a-11f. The bumps 11a-11f have: first bumps 11a, 11c connected to a signal potential; second bumps 11d, 11e, 11f connected to a ground potential; and a third bump 11b not electrically connected to a functional electrode section 14. In a mounting region, the third bump 11b, i.e., a floating bump, is electrically connected to the signal wiring line 5.

Description

モジュール装置Modular equipment
　本発明は、モジュール基板上にフィルタチップが実装されているモジュール装置に関する。 The present invention relates to a module device in which a filter chip is mounted on a module substrate.
　従来、モジュール基板上に、１以上の電子部品チップを搭載してなるモジュール装置が種々提案されている。下記の特許文献１では、弾性表面波チップを、モジュール基板としての回路基板上に実装した構造が記載されている。この弾性表面波チップは、ＩＤＴ電極と電気的に接続されていない柱状導体を有する。この柱状導体がモジュール基板側に露出している。すなわち、電気的に浮いた状態の柱状導体が、弾性表面波チップの回路基板に対向している側において露出している。そして、この柱状導体が、回路基板上のグラウンドパッドと半田などにより接合されている。それによって、弾性表面波チップの回路基板への接合強度が高められている。 Conventionally, various module devices in which one or more electronic component chips are mounted on a module substrate have been proposed. Patent Document 1 below describes a structure in which a surface acoustic wave chip is mounted on a circuit board as a module board. This surface acoustic wave chip has a columnar conductor that is not electrically connected to the IDT electrode. This columnar conductor is exposed to the module substrate side. That is, the columnar conductor in an electrically floating state is exposed on the side facing the circuit board of the surface acoustic wave chip. The columnar conductor is joined to the ground pad on the circuit board by solder or the like. Thereby, the bonding strength of the surface acoustic wave chip to the circuit board is increased.
特開２０１１－４９９９１号公報JP 2011-49991 A
　特許文献１では、ＩＤＴ電極と電気的に接続されていない柱状導体は、回路基板上のグラウンドパッドに接合される必要がある。そのため、モジュール基板において、弾性表面波チップの実装領域内における信号配線の配置に制約があった。よって、モジュール装置の小型化を十分に図ることができなかった。 In Patent Document 1, a columnar conductor that is not electrically connected to an IDT electrode needs to be bonded to a ground pad on a circuit board. For this reason, in the module substrate, there is a restriction on the arrangement of the signal wiring in the surface acoustic wave chip mounting region. Therefore, the module device cannot be sufficiently reduced in size.
　本発明の目的は、モジュール基板上の実装領域内における信号配線の配置の自由度が高められており、小型化を進めることができる、モジュール装置を提供することである。 An object of the present invention is to provide a module device in which the degree of freedom of arrangement of signal wirings in the mounting area on the module substrate is enhanced and the size can be reduced.
　本発明に係るモジュール装置は、一方主面上に設けられた電極ランドと、信号配線とを有するモジュール基板と、前記モジュール基板上に実装されているフィルタチップと、を備え、前記フィルタチップが前記モジュール基板の前記一方主面に対向している主面を有するチップ基板と、前記チップ基板に設けられており、機能電極部と、複数のバンプとを有し、前記複数のバンプは、信号電位に接続される第１のバンプと、グラウンド電位に接続される第２のバンプと、前記機能電極部に電気的に接続されていない第３のバンプとを有し、前記フィルタチップの前記第１～第３のバンプが前記モジュール基板に接合されており、前記第３のバンプは、前記フィルタチップを前記モジュール基板の前記一方主面に投影した実装領域内において、前記モジュール基板の前記一方主面に設けられた前記電極ランド及び前記信号配線のうち、前記信号配線に電気的に接続されている。 A module device according to the present invention comprises a module substrate having an electrode land provided on one main surface, a signal wiring, and a filter chip mounted on the module substrate, wherein the filter chip is A chip substrate having a main surface facing the one main surface of the module substrate; and provided on the chip substrate, having a functional electrode portion and a plurality of bumps, the plurality of bumps having a signal potential A first bump connected to a ground potential; a second bump connected to a ground potential; and a third bump not electrically connected to the functional electrode portion; and the first bump of the filter chip. A third bump is bonded to the module substrate, and the third bump is disposed in a mounting region in which the filter chip is projected onto the one main surface of the module substrate. Among the one said electrode lands and the signal wiring provided on the main surface of the module substrate, and is electrically connected to the signal line.
　本発明に係るモジュール装置のある特定の局面では、前記フィルタチップが、弾性波フィルタチップであり、前記チップ基板が圧電基板である。 In a specific aspect of the module device according to the present invention, the filter chip is an elastic wave filter chip, and the chip substrate is a piezoelectric substrate.
　本発明に係るモジュール装置の他の特定の局面では、前記第１のバンプ間、前記第２のバンプ間、または前記第１のバンプと前記第２のバンプとの間に、前記第３のバンプが配置されている。この場合には、モジュール装置の小型化をより一層進めることができる。 In another specific aspect of the module device according to the present invention, the third bump is between the first bumps, between the second bumps, or between the first bumps and the second bumps. Is arranged. In this case, the module device can be further reduced in size.
　本発明に係るモジュール装置のさらに他の特定の局面では、前記第３のバンプと接合されているチップ側電極ランドが、前記チップ基板の前記主面に設けられている。 In still another specific aspect of the module device according to the present invention, a chip-side electrode land bonded to the third bump is provided on the main surface of the chip substrate.
　本発明に係るモジュール装置のさらに他の特定の局面では、前記第３のバンプに接合されているチップ側電極ランドが、前記チップ基板の前記主面上に、他の材料層を介して積層されている。 In still another specific aspect of the module device according to the present invention, a chip-side electrode land bonded to the third bump is laminated on the main surface of the chip substrate via another material layer. ing.
　本発明に係るモジュール装置のさらに他の特定の局面では、前記他の材料層が、前記チップ基板の誘電率よりも低い誘電率を有する誘電体からなる。この場合には、モジュール装置の電気的特性の劣化がより一層生じ難い。 In still another specific aspect of the module device according to the present invention, the other material layer is made of a dielectric having a dielectric constant lower than that of the chip substrate. In this case, the electrical characteristics of the module device are more unlikely to deteriorate.
　本発明に係るモジュール装置のさらに他の特定の局面では、前記信号配線が前記第１のバンプに電気的に接続されており、かつ前記実装領域外に延ばされている。 In yet another specific aspect of the module device according to the present invention, the signal wiring is electrically connected to the first bump and extends outside the mounting area.
　本発明に係るモジュール装置の別の特定の局面では、前記モジュール基板の前記一方主面上に実装されており、前記フィルタチップとは異なる他の電子部品チップをさらに備え、前記信号配線が前記他の電子部品チップに電気的に接続されている。 In another specific aspect of the module device according to the present invention, the module device further includes an electronic component chip that is mounted on the one main surface of the module substrate and is different from the filter chip, and the signal wiring is the other It is electrically connected to the electronic component chip.
　本発明に係るモジュール装置のさらに他の特定の局面では、前記モジュール基板の前記一方主面上に搭載されており、前記フィルタチップとは異なる第１及び第２の電子部品チップをさらに備え、前記第１及び第２の電子部品チップが前記信号配線により電気的に接続されている。この場合には、モジュール装置のより一層の小型化を図ることができる。 In still another specific aspect of the module device according to the present invention, the module device further includes first and second electronic component chips that are mounted on the one main surface of the module substrate and different from the filter chip, The first and second electronic component chips are electrically connected by the signal wiring. In this case, the module device can be further reduced in size.
　本発明に係るモジュール装置の別の特定の局面では、前記実装領域が矩形の形状を有し、前記信号配線が該矩形の異なる辺を横切って、前記実装領域外に延ばされている。この場合には、モジュール装置のさらなる小型化を図ることができる。 In another specific aspect of the module device according to the present invention, the mounting region has a rectangular shape, and the signal wiring extends outside the mounting region across different sides of the rectangle. In this case, the module device can be further miniaturized.
　本発明に係るモジュール装置のさらに他の特定の局面では、前記弾性波フィルタチップが、前記機能電極部としてＩＤＴ電極を有し、前記弾性波フィルタチップが、前記圧電基板上に、前記ＩＤＴ電極を囲むように設けられた支持層と、前記支持層の対向部を封止するように設けられたカバー部材とを有し、前記カバー部材側が、前記モジュール基板の前記一方主面に対向するように、前記弾性波フィルタチップが、前記モジュール基板の前記一方主面に実装されている。 In still another specific aspect of the module device according to the present invention, the elastic wave filter chip has an IDT electrode as the functional electrode unit, and the elastic wave filter chip has the IDT electrode on the piezoelectric substrate. A support layer provided to surround the cover layer and a cover member provided to seal a facing portion of the support layer, and the cover member side faces the one main surface of the module substrate. The acoustic wave filter chip is mounted on the one main surface of the module substrate.
　本発明に係るモジュール装置によれば、モジュール基板上における、フィルタチップが搭載されている実装領域において、信号配線の配置の自由度を高めることができる。従って、モジュール装置の小型化を図ることが可能となる。 According to the module device of the present invention, it is possible to increase the degree of freedom of the arrangement of signal wirings in the mounting area where the filter chip is mounted on the module substrate. Therefore, it is possible to reduce the size of the module device.
図１は、本発明の第１の実施形態に係るモジュール装置の略図的平面図である。FIG. 1 is a schematic plan view of a module device according to a first embodiment of the present invention. 図２は、図１のＡ－Ａ線に沿う部分に相当する、本発明の第１の実施形態のモジュール装置の断面図である。FIG. 2 is a cross-sectional view of the module device according to the first embodiment of the present invention, corresponding to the portion along line AA in FIG. 図３は、本発明の第１の実施形態のモジュール装置におけるフィルタチップの第１の主面上の電極構造を示す底面図である。FIG. 3 is a bottom view showing the electrode structure on the first main surface of the filter chip in the module device according to the first embodiment of the present invention. 図４は、本発明の第２の実施形態に係るモジュール装置を説明するための略図的平面図である。FIG. 4 is a schematic plan view for explaining a module device according to the second embodiment of the present invention. 図５は、本発明の第３の実施形態において、モジュール基板に搭載されるフィルタチップの要部を示す正面断面図である。FIG. 5 is a front sectional view showing the main part of the filter chip mounted on the module substrate in the third embodiment of the present invention. 図６は、本発明の第３の実施形態及び誘電体層が設けられていないモジュール装置のフィルタ特性を示す図である。FIG. 6 is a diagram illustrating the filter characteristics of the module device according to the third embodiment of the present invention and no dielectric layer.
　以下、図面を参照しつつ、本発明の具体的な実施形態を説明することにより、本発明を明らかにする。 Hereinafter, the present invention will be clarified by describing specific embodiments of the present invention with reference to the drawings.
　なお、本明細書に記載の各実施形態は、例示的なものであり、異なる実施形態間において、構成の部分的な置換または組み合わせが可能であることを指摘しておく。 It should be pointed out that each embodiment described in this specification is an example, and a partial replacement or combination of configurations is possible between different embodiments.
　図１は、本発明の第１の実施形態に係るモジュール装置の略図的平面図である。 FIG. 1 is a schematic plan view of a module device according to a first embodiment of the present invention.
　モジュール装置１は、モジュール基板２を有する。モジュール基板２は、一方主面としての上面２ａを有する。上面２ａ上にグラウンド電位に接続される複数の電極ランド３，４が設けられている。上面２ａ上においては、信号配線５，６も設けられている。 The module device 1 has a module substrate 2. The module substrate 2 has an upper surface 2a as one main surface. A plurality of electrode lands 3 and 4 connected to the ground potential are provided on the upper surface 2a. On the upper surface 2a, signal wirings 5 and 6 are also provided.
　モジュール基板２は、適宜の絶縁性材料や半導体材料からなる。電極ランド３，４及び信号配線５，６は、金属膜からなる。金属膜は、複数の金属膜を積層した積層金属膜であってもよい。 The module substrate 2 is made of an appropriate insulating material or semiconductor material. The electrode lands 3 and 4 and the signal wirings 5 and 6 are made of a metal film. The metal film may be a laminated metal film in which a plurality of metal films are laminated.
　モジュール基板２上には、フィルタチップ１１が搭載される。図１では、フィルタチップ１１が搭載されている実装領域を破線で示す。 The filter chip 11 is mounted on the module substrate 2. In FIG. 1, the mounting area in which the filter chip 11 is mounted is indicated by a broken line.
　なお、実装領域とは、フィルタチップ１１をモジュール基板２の上面２ａに投影した領域をいうものとする。モジュール基板２上には、フィルタチップ１１とは別の電子部品チップ１２も搭載されている。電子部品チップ１２についても、搭載されている部分を破線で略図的に示すこととする。 Note that the mounting region refers to a region where the filter chip 11 is projected onto the upper surface 2a of the module substrate 2. An electronic component chip 12 other than the filter chip 11 is also mounted on the module substrate 2. As for the electronic component chip 12, the mounted part is schematically shown by a broken line.
　本実施形態では、フィルタチップ１１は、弾性波フィルタチップである。弾性波フィルタチップは、図１に円で示す複数のバンプ１１ａ～１１ｆを有する。バンプ１１ａ～１１ｆが、モジュール基板２の上面２ａ上の電極ランド３，４、または信号配線５，６に接合されている。バンプ１１ａ，１１ｃが、本発明における第１のバンプであり、バンプ１１ｄ，１１ｅ，１１ｆが、グラウンド電位に接続される第２のバンプであり、バンプ１１ｂが、後述する浮きバンプとなる第３のバンプとなる。これを、図２を参照してより具体的に説明する。図２は、図１のＡ－Ａ線に相当する部分のモジュール装置１の断面図である。 In the present embodiment, the filter chip 11 is an elastic wave filter chip. The acoustic wave filter chip has a plurality of bumps 11a to 11f indicated by circles in FIG. The bumps 11a to 11f are bonded to the electrode lands 3 and 4 or the signal wirings 5 and 6 on the upper surface 2a of the module substrate 2. The bumps 11a and 11c are the first bumps in the present invention, the bumps 11d, 11e and 11f are the second bumps connected to the ground potential, and the bumps 11b are the floating bumps described later. It becomes a bump. This will be described more specifically with reference to FIG. FIG. 2 is a cross-sectional view of the module device 1 corresponding to the line AA in FIG.
　図２では、前述した複数のバンプ１１ａ～１１ｆのうち、バンプ１１ｂ，１１ｃ，１１ｆが設けられている部分の断面が示されている。バンプ１１ｆが電極ランド４に接合されている。バンプ１１ｂが、信号配線５に接続されている。バンプ１１ｃが信号配線６に接合されている。 FIG. 2 shows a cross section of a portion where the bumps 11b, 11c, and 11f are provided among the plurality of bumps 11a to 11f described above. Bumps 11 f are joined to the electrode lands 4. The bumps 11 b are connected to the signal wiring 5. Bumps 11 c are joined to the signal wiring 6.
　フィルタチップ１１は、チップ基板としての圧電基板１３を有する。圧電基板１３は、ＬｉＴａＯ３やＬｉＮｂＯ３などの圧電単結晶からなる。圧電単結晶に代えて、圧電セラミックスが用いられてもよい。 The filter chip 11 has a piezoelectric substrate 13 as a chip substrate. The piezoelectric substrate 13 is made of a piezoelectric single crystal such as LiTaO 3 or LiNbO 3 . Instead of the piezoelectric single crystal, piezoelectric ceramics may be used.
　圧電基板１３のモジュール基板２と対向している側の主面１３ａ上に設けられている電極構造を図３に底面図で示す。主面１３ａ上には、機能電極部１４が設けられている。機能電極部１４は、本実施形態では、複数のＩＤＴ電極を有し、帯域通過型の弾性表面波フィルタを構成している。もっとも、本発明において、機能電極部１４の電極構造は特に限定されず、フィルタ回路を構成する適宜の電極構造を用いることができる。 The electrode structure provided on the main surface 13a on the side facing the module substrate 2 of the piezoelectric substrate 13 is shown in a bottom view in FIG. A functional electrode portion 14 is provided on the main surface 13a. In the present embodiment, the functional electrode unit 14 includes a plurality of IDT electrodes and constitutes a band-pass surface acoustic wave filter. However, in the present invention, the electrode structure of the functional electrode portion 14 is not particularly limited, and an appropriate electrode structure constituting the filter circuit can be used.
　機能電極部１４に、引き出し電極１６ａ，１６ｃ～１６ｆの一端が接続されている。引き出し電極１６ａ，１６ｃ～１６ｆの他端は、チップ側電極ランド１７ａ，１７ｃ～１７ｆに接続されている。チップ側電極ランド１７ａ，１７ｃ～１７ｆに、前述したバンプ１１ａ，１１ｃ～１１ｆが接合されている。ここで、バンプ１１ａ，１１ｃは、信号配線５又は６に電気的に接続されている第１のバンプである。この第１のバンプ１１ａ，１１ｃは、チップ側電極ランド１７ａ，１７ｃを介して、機能電極部１４に接続されている。 , One end of each of the extraction electrodes 16a, 16c to 16f is connected to the functional electrode portion 14. The other ends of the extraction electrodes 16a and 16c to 16f are connected to the chip side electrode lands 17a and 17c to 17f. The aforementioned bumps 11a, 11c to 11f are joined to the chip side electrode lands 17a and 17c to 17f. Here, the bumps 11 a and 11 c are first bumps that are electrically connected to the signal wiring 5 or 6. The first bumps 11a and 11c are connected to the functional electrode portion 14 via chip-side electrode lands 17a and 17c.
　他方、第２のバンプ１１ｄ，１１ｅ，１１ｆは、機能電極部１４のグラウンド電位に上述した引き出し電極１６ｄ，１６ｅ，１６ｆ及びチップ側電極ランド１７ｄ，１７ｅ，１７ｆを介して接続されている。 On the other hand, the second bumps 11d, 11e, and 11f are connected to the ground potential of the functional electrode portion 14 through the extraction electrodes 16d, 16e, and 16f and the chip-side electrode lands 17d, 17e, and 17f.
　これに対して、チップ側電極ランド１７ｂは、機能電極部１４に電気的に接続されていない。第３のバンプ１１ｂは、チップ側電極ランド１７ｂ上に設けられている。従って、第３のバンプ１１ｂは、機能電極部１４に電気的に接続されていない、いわゆる浮きバンプである。ここで、浮きバンプとは、フィルタチップ１１において、信号電位やグラウンド電位に電気的に接続されておらず、電気的に浮いた状態にあるバンプをいうものとする。第３のバンプ１１ｂは、図１及び図２に示したように、上述した実装領域内において、信号配線５に接合されている。 On the other hand, the chip-side electrode land 17b is not electrically connected to the functional electrode portion 14. The third bump 11b is provided on the chip side electrode land 17b. Therefore, the third bump 11 b is a so-called floating bump that is not electrically connected to the functional electrode portion 14. Here, the floating bump is a bump which is not electrically connected to the signal potential or the ground potential in the filter chip 11 and is in an electrically floating state. As shown in FIGS. 1 and 2, the third bump 11 b is bonded to the signal wiring 5 in the mounting region described above.
　図２に戻り、チップ側電極ランド１７ｂ，１７ｃ，１７ｆが設けられている部分においては、圧電基板１３の主面１３ａ上に、絶縁性材料からなる支持層１８が設けられている。この支持層１８を貫通するように貫通孔が設けられている。支持層１８は、合成樹脂や無機絶縁性材料からなる。 2, the support layer 18 made of an insulating material is provided on the main surface 13a of the piezoelectric substrate 13 in the portion where the chip side electrode lands 17b, 17c, and 17f are provided. A through hole is provided so as to penetrate the support layer 18. The support layer 18 is made of a synthetic resin or an inorganic insulating material.
　上記支持層１８の先端側には、カバー部材２０が設けられている。カバー部材２０は、合成樹脂や、無機絶縁性材料からなる。上記カバー部材２０と、支持層１８とに囲まれた部分が、中空部分とされ、封止されている。この中空部分内に、前述した機能電極部１４が位置している。 A cover member 20 is provided on the front end side of the support layer 18. The cover member 20 is made of a synthetic resin or an inorganic insulating material. A portion surrounded by the cover member 20 and the support layer 18 is a hollow portion and sealed. The functional electrode portion 14 described above is located in this hollow portion.
　他方、図２に示すように、支持層１８及びカバー部材２０を貫通するように貫通孔が設けられている。この貫通孔内に、アンダーバンプメタル層１９が設けられている。アンダーバンプメタル層１９は、チップ側電極ランド１７ｂ，１７ｃ，１７ｆ上に設けられている。アンダーバンプメタル層１９は、金属もしくは合金からなる。 On the other hand, as shown in FIG. 2, a through hole is provided so as to penetrate the support layer 18 and the cover member 20. An under bump metal layer 19 is provided in the through hole. The under bump metal layer 19 is provided on the chip side electrode lands 17b, 17c, and 17f. The under bump metal layer 19 is made of a metal or an alloy.
　アンダーバンプメタル層１９上に、前述した第３のバンプ１１ｂ，第１のバンプ１１ｃ及び第２のバンプ１１ｆが設けられている。 On the under bump metal layer 19, the above-described third bump 11b, first bump 11c, and second bump 11f are provided.
　フィルタチップ１１は、上述したように、圧電基板１３と、支持層１８と、カバー部材２０とを有する、いわゆるＷＬＰ型のパッケージ構造を有する。そして、バンプ１１ａ～１１ｆを用いて、フェイスダウン方式で、フィルタチップ１１はモジュール基板２上に実装されている。 As described above, the filter chip 11 has a so-called WLP type package structure including the piezoelectric substrate 13, the support layer 18, and the cover member 20. The filter chip 11 is mounted on the module substrate 2 in a face-down manner using the bumps 11a to 11f.
　もっとも、本発明において、フィルタチップは、ＷＬＰ構造を有するものに限らない。ＣＳＰ構造などの適宜のパッケージ構造を有するフィルタチップを用いることができる。 However, in the present invention, the filter chip is not limited to one having a WLP structure. A filter chip having an appropriate package structure such as a CSP structure can be used.
　本実施形態の特徴は、上記浮きバンプである第３のバンプ１１ｂが、実装領域内において信号配線５に接合されていることにある。これを、図１を参照してより詳細に説明する。 The feature of this embodiment is that the third bump 11b which is the floating bump is joined to the signal wiring 5 in the mounting region. This will be described in more detail with reference to FIG.
　信号配線５は、フィルタチップ１１と、電子部品チップ１２とを電気的に接続するように、モジュール基板２の上面２ａ上に設けられている。信号配線５は、信号電流が流れる配線である。 The signal wiring 5 is provided on the upper surface 2 a of the module substrate 2 so as to electrically connect the filter chip 11 and the electronic component chip 12. The signal wiring 5 is a wiring through which a signal current flows.
　第１のバンプ１１ａは、機能電極部１４に電気的に接続されており、信号が、第１のバンプ１１ａから信号配線５に流れ、電子部品チップ１２に接続されているバンプ１２ａに至る。 The first bump 11a is electrically connected to the functional electrode portion 14, and a signal flows from the first bump 11a to the signal wiring 5 to reach the bump 12a connected to the electronic component chip 12.
　他方、浮きバンプである第３のバンプ１１ｂは、機能電極部１４及びグラウンド電位に接続されていない。しかしながら、浮きバンプである第３のバンプ１１ｂもまた、信号配線５に接合されている。すなわち、フィルタチップ１１をモジュール基板２の上面２ａに投影した矩形の実装領域内において、浮きバンプである第３のバンプ１１ｂが信号配線５に接合されている。 On the other hand, the third bump 11b which is a floating bump is not connected to the functional electrode portion 14 and the ground potential. However, the third bump 11 b that is a floating bump is also bonded to the signal wiring 5. That is, the third bump 11 b that is a floating bump is joined to the signal wiring 5 in a rectangular mounting region in which the filter chip 11 is projected onto the upper surface 2 a of the module substrate 2.
　本実施形態では、この浮きバンプである第３のバンプ１１ｂが、第２のバンプ１１ｆと第１のバンプ１１ｃとの間に挟まれた位置に設けられている。従って、信号配線５は、この矩形の実装領域内において、第１のバンプ１１ａに接合されている側から、第２のバンプ１１ｆと第１のバンプ１１ｃとの間を通り、電子部品チップ１２側に延ばされている。 In the present embodiment, the third bump 11b, which is the floating bump, is provided at a position sandwiched between the second bump 11f and the first bump 11c. Accordingly, the signal wiring 5 passes between the second bump 11f and the first bump 11c from the side bonded to the first bump 11a in the rectangular mounting region, and is on the electronic component chip 12 side. It is extended to.
　従来、浮きバンプはグラウンド電位に接続される電極ランドに接合されているのが普通であった。そのため、図１の第３のバンプ１１ｂを電極ランド４や電極ランド３の延長部分に接合することが考えられる。しかしながら、そのような構成では、信号配線５を上記実装領域内において引き回すことが困難となる。例えば、信号配線５を、実装領域外において引き回さねばならなかった。そのため、小型化が困難であった。 Conventionally, floating bumps are usually joined to electrode lands connected to the ground potential. Therefore, it is conceivable to join the third bump 11 b of FIG. 1 to the electrode land 4 or the extended portion of the electrode land 3. However, with such a configuration, it is difficult to route the signal wiring 5 in the mounting area. For example, the signal wiring 5 has to be routed outside the mounting area. Therefore, downsizing has been difficult.
　これに対して、モジュール装置１では、実装領域内において信号配線５に上記浮きバンプである第３のバンプ１１ｂを接合するように、信号配線５を配置することができる。従って、上記実装領域内における信号配線５の配置の自由度が高められ、小型化を効果的に図ることが可能とされている。 On the other hand, in the module device 1, the signal wiring 5 can be arranged so that the third bump 11b, which is the floating bump, is joined to the signal wiring 5 in the mounting region. Therefore, the degree of freedom of arrangement of the signal wiring 5 in the mounting area is increased, and it is possible to effectively reduce the size.
　加えて、上記浮きバンプである第３のバンプ１１ｂは、信号配線５にも接合されているため、本実施形態においては、多数のバンプ１１ａ～１１ｆにより、フィルタチップ１１のモジュール基板２に対する接合強度も十分に高められている。 In addition, since the third bump 11b, which is the floating bump, is also bonded to the signal wiring 5, in this embodiment, the bonding strength of the filter chip 11 to the module substrate 2 by the large number of bumps 11a to 11f. Is also raised enough.
　図４は、本発明の第２の実施形態に係るモジュール装置の略図的平面図である。 FIG. 4 is a schematic plan view of a module device according to the second embodiment of the present invention.
　モジュール装置３１では、モジュール基板２の上面２ａ上に、第１の実施形態と同様に、フィルタチップ１１が搭載される。フィルタチップ１１は、第１の実施形態で用いたフィルタチップ１１と同様であり、第１のバンプ１１ａ，１１ｃ、第２のバンプ１１ｄ，１１ｅ，１１ｆ及び第３のバンプ１１ｂを有する。モジュール装置３１では、フィルタチップ１１以外に、複数の電子部品チップ３２，３３がモジュール基板２の上面２ａ上に実装されている。電子部品チップ３２は、信号電位に接続されるバンプ３２ａを有する。電子部品チップ３３は、信号電位に接続されるバンプ３３ａを有する。 In the module device 31, the filter chip 11 is mounted on the upper surface 2a of the module substrate 2 in the same manner as in the first embodiment. The filter chip 11 is the same as the filter chip 11 used in the first embodiment, and includes first bumps 11a and 11c, second bumps 11d, 11e, and 11f, and a third bump 11b. In the module device 31, in addition to the filter chip 11, a plurality of electronic component chips 32 and 33 are mounted on the upper surface 2 a of the module substrate 2. The electronic component chip 32 has bumps 32a connected to the signal potential. The electronic component chip 33 has bumps 33a connected to the signal potential.
　モジュール基板２の上面２ａ上には、グラウンド電位に接続される電極ランド３，４と、信号電位に接続される信号配線３４～３６とが設けられている。このうち、信号配線３５に、第１のバンプ１１ａが接合されており、信号配線３６に第１のバンプ１１ｃが接合されている。他方、浮きバンプである第３のバンプ１１ｂは、信号配線３４に接合されている。信号配線３４は、フィルタチップ１１には電気的には接続されていない。信号配線３４は、電子部品チップ３２と電子部品チップ３３とを電気的に接続している。すなわち、バンプ３２ａとバンプ３３ａとが、信号配線３４により接続されている。 On the upper surface 2a of the module substrate 2, electrode lands 3 and 4 connected to the ground potential and signal wirings 34 to 36 connected to the signal potential are provided. Among these, the first bump 11 a is bonded to the signal wiring 35, and the first bump 11 c is bonded to the signal wiring 36. On the other hand, the third bump 11 b that is a floating bump is joined to the signal wiring 34. The signal wiring 34 is not electrically connected to the filter chip 11. The signal wiring 34 electrically connects the electronic component chip 32 and the electronic component chip 33. That is, the bump 32 a and the bump 33 a are connected by the signal wiring 34.
　このように、本発明において、浮きバンプである第３のバンプ１１ｂは、フィルタチップ１１に電気的に接続されていない信号配線３４に接合されていてもよい。この場合においても、フィルタチップ１１をモジュール基板２の上面２ａに投影した実装領域内における信号配線３４の配置の自由度を高めることができる。従って、信号配線３４の引き回しに余分なスペースを必要としないため、小型化を図ることができる。加えて、上記浮きバンプである第３のバンプ１１ｂによっても、フィルタチップ１１がモジュール基板２に接合されているため、フィルタチップ１１とモジュール基板２の接合強度も十分に高められている。 Thus, in the present invention, the third bump 11 b that is a floating bump may be joined to the signal wiring 34 that is not electrically connected to the filter chip 11. Even in this case, the degree of freedom of arrangement of the signal wirings 34 in the mounting region in which the filter chip 11 is projected onto the upper surface 2a of the module substrate 2 can be increased. Therefore, since no extra space is required for routing the signal wiring 34, the size can be reduced. In addition, since the filter chip 11 is bonded to the module substrate 2 also by the third bump 11b that is the floating bump, the bonding strength between the filter chip 11 and the module substrate 2 is sufficiently increased.
　モジュール装置３１のように、浮きバンプである第３のバンプ１１ｂが接合される信号配線３４は、フィルタチップ１１の他の電子部品チップ３２，３３同士を接合するものであってもよい。 As in the module device 31, the signal wiring 34 to which the third bump 11 b that is a floating bump is joined may be one that joins the other electronic component chips 32 and 33 to each other in the filter chip 11.
　モジュール装置３１では、矩形の実装領域の異なる２辺を結ぶように信号配線３４が設けられている。すなわち、信号配線３４は、上記実装領域内と、実装領域の一辺の外側に延ばされている部分と、他の一辺の外側に延ばされている部分とを有する。電子部品チップ３２，３３間の、信号配線３４による接続長を短くすることによって、小型化をより一層進めることができる。もっとも、信号配線３４は、上記実装領域の隣り合う２辺からそれぞれ外側に延ばされている必要は必ずしもない。任意の２辺の外側に延ばされていてもよい。あるいは、実装領域の同じ辺から実装領域外に延ばされていてもよい。すなわち、実装領域の外側に位置する電子部品チップ３２や３３の位置に応じて、信号配線３４が実装領域外に至る位置を選択すればよい。 In the module device 31, signal wirings 34 are provided so as to connect two different sides of the rectangular mounting area. That is, the signal wiring 34 has a portion extending in the mounting area, a portion extending outside one side of the mounting region, and a portion extending outside the other side. By shortening the connection length between the electronic component chips 32 and 33 by the signal wiring 34, the size can be further reduced. However, the signal wiring 34 does not necessarily have to be extended outward from two adjacent sides of the mounting area. It may be extended outside any two sides. Alternatively, it may be extended outside the mounting area from the same side of the mounting area. That is, a position where the signal wiring 34 reaches outside the mounting area may be selected according to the position of the electronic component chips 32 and 33 positioned outside the mounting area.
　図５は、本発明の第３の実施形態のモジュール基板に搭載されるフィルタチップの要部を示す正面断面図である。 FIG. 5 is a front sectional view showing the main part of the filter chip mounted on the module substrate of the third embodiment of the present invention.
　フィルタチップ４１は、圧電基板１３を有する。圧電基板１３の前述したモジュール基板２に対向する側の主面１３ａ上に、フィルタチップ１１と同様に機能電極部１４が設けられている。図５では、機能電極部１４の一部の電極部分のみが図示されている。この機能電極部１４に接合される電極ランド４２上に支持層４３が設けられている。また、電極ランド４４が、誘電体層４５を介して主面１３ａ上に設けられている。誘電体層４５の誘電率は、圧電基板１３の誘電率よりも低い。このような誘電体層４５を構成するための材料としては、ポリイミドなどの合成樹脂や、酸化ケイ素などの無機絶縁性材料を適宜用いることができる。 The filter chip 41 has a piezoelectric substrate 13. Similar to the filter chip 11, the functional electrode portion 14 is provided on the main surface 13 a of the piezoelectric substrate 13 on the side facing the module substrate 2 described above. In FIG. 5, only a part of the electrode portion of the functional electrode portion 14 is illustrated. A support layer 43 is provided on the electrode land 42 joined to the functional electrode portion 14. The electrode land 44 is provided on the main surface 13a with the dielectric layer 45 interposed therebetween. The dielectric constant of the dielectric layer 45 is lower than the dielectric constant of the piezoelectric substrate 13. As a material for constituting such a dielectric layer 45, a synthetic resin such as polyimide or an inorganic insulating material such as silicon oxide can be appropriately used.
　この電極ランド４４は、機能電極部１４に電気的に接続されていない、すなわち浮き電極ランドとして設けられている。 The electrode land 44 is not electrically connected to the functional electrode portion 14, that is, is provided as a floating electrode land.
　上記電極ランド４４を覆うように、支持層４３が設けられている。支持層４３上にカバー部材２０が設けられている。上記支持層４３とカバー部材２０とにより、中空部Ｂが設けられている。機能電極部１４は中空部Ｂに臨んでいる。 A support layer 43 is provided so as to cover the electrode land 44. The cover member 20 is provided on the support layer 43. A hollow portion B is provided by the support layer 43 and the cover member 20. The functional electrode portion 14 faces the hollow portion B.
　本実施形態においても、支持層４３及びカバー部材２０を貫通するように貫通孔が設けられている。この貫通孔内にアンダーバンプメタル層４６が設けられている。そして、電極ランド４４上のアンダーバンプメタル層４６上に、浮きバンプとしての第３のバンプ１１ｂが設けられている。また、信号電位に接続される第１のバンプ１１ａが電極ランド４２に電気的に接続されるように設けられている。このように、浮きバンプである第３のバンプ１１ｂが接合されている電極ランド４４は、圧電基板１３の主面１３ａに直接接触されておらずともよい。すなわち、他の材料層としての誘電体層４５を介して、電極ランド４４が圧電基板１３の主面１３ａ上に設けられていてもよい。また、好ましくは、本実施形態のように、誘電体層４５が他の材料層として用いられる。もっとも、他の材料層としては、誘電体層４５以外の材料層を用いてもよい。 Also in this embodiment, a through hole is provided so as to penetrate the support layer 43 and the cover member 20. An under bump metal layer 46 is provided in the through hole. A third bump 11 b as a floating bump is provided on the under bump metal layer 46 on the electrode land 44. Further, the first bump 11 a connected to the signal potential is provided so as to be electrically connected to the electrode land 42. As described above, the electrode land 44 to which the third bump 11b, which is a floating bump, is bonded may not be in direct contact with the main surface 13a of the piezoelectric substrate 13. That is, the electrode land 44 may be provided on the main surface 13a of the piezoelectric substrate 13 via the dielectric layer 45 as another material layer. Further, preferably, the dielectric layer 45 is used as another material layer as in the present embodiment. However, a material layer other than the dielectric layer 45 may be used as the other material layer.
　本実施形態のように、誘電体層４５が設けられている場合、モジュール装置におけるフィルタ特性を改善することができる。これを、図６を参照して説明する。 When the dielectric layer 45 is provided as in this embodiment, the filter characteristics in the module device can be improved. This will be described with reference to FIG.
　図６は、第３の実施形態のモジュール装置におけるフィルタチップによるフィルタ特性を示す図であり、実線が第３の実施形態の結果を示す。また、破線は、上記誘電体層４５が設けられていないことを除いては、第３の実施形態と同様に構成されたモジュール装置のフィルタ特性を示す。 FIG. 6 is a diagram showing the filter characteristics by the filter chip in the module device of the third embodiment, and the solid line shows the result of the third embodiment. The broken lines indicate the filter characteristics of the module device configured in the same manner as in the third embodiment except that the dielectric layer 45 is not provided.
　なお、図６の実線は、誘電体層４５としてポリイミドを用いた場合の結果である。図６から明らかなように、誘電体層４５としてポリイミドを用いた場合、誘電体層４５が設けられていない場合に比べて、通過帯域外における減衰量を十分に小さくし得ることがわかる。これは、誘電体層４５の誘電率が圧電基板１３の誘電率より低いため、浮きバンプである第３のバンプ１１ｂ中に侵入した信号の容量結合による影響を抑制することによると考えられる。よって、好ましくは、上記のように誘電体層４５を設けることが望ましい。 The solid line in FIG. 6 is the result when polyimide is used as the dielectric layer 45. As can be seen from FIG. 6, when polyimide is used as the dielectric layer 45, the attenuation outside the passband can be made sufficiently smaller than when the dielectric layer 45 is not provided. This is presumably because the dielectric constant of the dielectric layer 45 is lower than the dielectric constant of the piezoelectric substrate 13, thereby suppressing the influence of capacitive coupling of the signal that has entered the third bump 11 b that is a floating bump. Therefore, it is preferable to provide the dielectric layer 45 as described above.
１…モジュール装置
２…モジュール基板
２ａ…上面
３，４…電極ランド
５，６…信号配線
１１…フィルタチップ
１１ａ，１１ｃ…第１のバンプ
１１ｂ…第３のバンプ
１１ｄ，１１ｅ，１１ｆ…第２のバンプ
１２…電子部品チップ
１２ａ…バンプ
１３…圧電基板
１３ａ…主面
１４…機能電極部
１６ａ，１６ｃ～１６ｆ…引き出し電極
１７ａ～１７ｆ…チップ側電極ランド
１８…支持層
１９…アンダーバンプメタル層
２０…カバー部材
３１…モジュール装置
３２，３３…電子部品チップ
３２ａ，３３ａ…バンプ
３４～３６…信号配線
４１…フィルタチップ
４２…電極ランド
４３…支持層
４４…電極ランド
４５…誘電体層
４６…アンダーバンプメタル層 DESCRIPTION OF SYMBOLS 1 ... Module apparatus 2 ... Module board | substrate 2a ... Upper surface 3, 4 ... Electrode land 5, 6 ... Signal wiring 11 ... Filter chip 11a, 11c ... 1st bump 11b ... 3rd bump 11d, 11e, 11f ... 2nd Bump 12 ... Electronic component chip 12a ... Bump 13 ... Piezoelectric substrate 13a ... Main surface 14 ... Functional electrode portions 16a, 16c to 16f ... Lead electrodes 17a to 17f ... Chip-side electrode land 18 ... Support layer 19 ... Under bump metal layer 20 ... Cover member 31 ... Module devices 32, 33 ... Electronic component chips 32a, 33a ... Bumps 34-36 ... Signal wiring 41 ... Filter chip 42 ... Electrode land 43 ... Support layer 44 ... Electrode land 45 ... Dielectric layer 46 ... Under bump metal layer

Claims (11)

  1. 　一方主面上に設けられた電極ランドと、信号配線とを有するモジュール基板と、
    　前記モジュール基板上に実装されているフィルタチップと、を備え、
    　前記フィルタチップが前記モジュール基板の前記一方主面に対向している主面を有するチップ基板と、前記チップ基板に設けられており、機能電極部と、複数のバンプとを有し、前記複数のバンプは、信号電位に接続される第１のバンプと、グラウンド電位に接続される第２のバンプと、前記機能電極部に電気的に接続されていない第３のバンプとを有し、
    　前記フィルタチップの前記第１～第３のバンプが前記モジュール基板に接合されており、前記第３のバンプは、前記フィルタチップを前記モジュール基板の前記一方主面に投影した実装領域内において、前記モジュール基板の前記一方主面に設けられた前記電極ランド及び前記信号配線のうち、前記信号配線に電気的に接続されている、モジュール装置。     On the other hand, a module substrate having electrode lands provided on the main surface and signal wiring,
    A filter chip mounted on the module substrate,
    The filter chip includes a chip substrate having a main surface facing the one main surface of the module substrate, the chip chip substrate, a functional electrode portion, and a plurality of bumps. The bump has a first bump connected to the signal potential, a second bump connected to the ground potential, and a third bump not electrically connected to the functional electrode unit,
    The first to third bumps of the filter chip are bonded to the module substrate, and the third bumps are formed in the mounting region in which the filter chip is projected onto the one main surface of the module substrate. A module device that is electrically connected to the signal wiring among the electrode land and the signal wiring provided on the one main surface of the module substrate.
  2. 　前記フィルタチップが、弾性波フィルタチップであり、前記チップ基板が圧電基板である、請求項１に記載のモジュール装置。 The module device according to claim 1, wherein the filter chip is an elastic wave filter chip, and the chip substrate is a piezoelectric substrate.
  3. 　前記第１のバンプ間、前記第２のバンプ間、または前記第１のバンプと前記第２のバンプとの間に、前記第３のバンプが配置されている、請求項１または２に記載のモジュール装置。 3. The third bump according to claim 1, wherein the third bump is disposed between the first bumps, between the second bumps, or between the first bump and the second bump. Modular device.
  4. 　前記第３のバンプと接合されているチップ側電極ランドが、前記チップ基板の前記主面に設けられている、請求項１～３のいずれか１項に記載のモジュール装置。 The module device according to any one of claims 1 to 3, wherein a chip-side electrode land bonded to the third bump is provided on the main surface of the chip substrate.
  5. 　前記第３のバンプに接合されているチップ側電極ランドが、前記チップ基板の前記主面上に、他の材料層を介して積層されている、請求項１～３のいずれか１項に記載のモジュール装置。 The chip-side electrode land bonded to the third bump is laminated on the main surface of the chip substrate via another material layer. Modular equipment.
  6. 　前記他の材料層が、前記チップ基板の誘電率よりも低い誘電率を有する誘電体からなる、請求項５に記載のモジュール装置。 6. The module device according to claim 5, wherein the other material layer is made of a dielectric having a dielectric constant lower than that of the chip substrate.
  7. 　前記信号配線が前記第１のバンプに電気的に接続されており、かつ前記実装領域外に延ばされている、請求項１～６のいずれか１項に記載のモジュール装置。 7. The module device according to claim 1, wherein the signal wiring is electrically connected to the first bump and extends outside the mounting area.
  8. 　前記モジュール基板の前記一方主面上に実装されており、前記フィルタチップとは異なる他の電子部品チップをさらに備え、前記信号配線が前記他の電子部品チップに電気的に接続されている、請求項７に記載のモジュール装置。 The electronic device further includes another electronic component chip that is mounted on the one main surface of the module substrate and is different from the filter chip, and the signal wiring is electrically connected to the other electronic component chip. Item 8. The module device according to Item 7.
  9. 　前記モジュール基板の前記一方主面上に搭載されており、前記フィルタチップとは異なる第１及び第２の電子部品チップをさらに備え、前記第１及び第２の電子部品チップが前記信号配線により電気的に接続されている、請求項１～６のいずれか１項に記載のモジュール装置。 The module board further includes first and second electronic component chips mounted on the one main surface of the module substrate and different from the filter chip, and the first and second electronic component chips are electrically connected by the signal wiring. The module device according to any one of claims 1 to 6, wherein the module devices are connected to each other.
  10. 　前記実装領域が矩形の形状を有し、前記信号配線が該矩形の異なる辺を横切って、前記実装領域外に延ばされている、請求項９に記載のモジュール装置。 10. The module device according to claim 9, wherein the mounting area has a rectangular shape, and the signal wiring extends outside the mounting area across different sides of the rectangle.
  11. 　前記弾性波フィルタチップが、前記機能電極部としてＩＤＴ電極を有し、前記弾性波フィルタチップが、前記圧電基板上に、前記ＩＤＴ電極を囲むように設けられた支持層と、前記支持層の対向部を封止するように設けられたカバー部材とを有し、
    　前記カバー部材側が、前記モジュール基板の前記一方主面に対向するように、前記弾性波フィルタチップが、前記モジュール基板の前記一方主面に実装されている、請求項１～９のいずれか１項に記載のモジュール装置。     The elastic wave filter chip has an IDT electrode as the functional electrode part, and the elastic wave filter chip is provided on the piezoelectric substrate so as to surround the IDT electrode, and the support layer is opposed to the support layer. A cover member provided to seal the part,
    10. The elastic wave filter chip is mounted on the one main surface of the module substrate so that the cover member side faces the one main surface of the module substrate. The module apparatus as described in.
PCT/JP2016/085137 2016-02-22 2016-11-28 Module device WO2017145473A1 (en)

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