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WO2017140615A1 - Composant semi-conducteur optoélectronique et procédé de fabrication d'un composant semi-conducteur optoélectronique - Google Patents

Composant semi-conducteur optoélectronique et procédé de fabrication d'un composant semi-conducteur optoélectronique Download PDF

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Publication number
WO2017140615A1
WO2017140615A1 PCT/EP2017/053133 EP2017053133W WO2017140615A1 WO 2017140615 A1 WO2017140615 A1 WO 2017140615A1 EP 2017053133 W EP2017053133 W EP 2017053133W WO 2017140615 A1 WO2017140615 A1 WO 2017140615A1
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WO
WIPO (PCT)
Prior art keywords
layer
active
areas
current spreading
electrically insulating
Prior art date
Application number
PCT/EP2017/053133
Other languages
German (de)
English (en)
Inventor
Tansen Varghese
Adrian Stefan Avramescu
Tilman SCHIMPKE
Martin Mandl
Original Assignee
Osram Opto Semiconductors Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2017140615A1 publication Critical patent/WO2017140615A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the invention relates to an optoelectronic
  • active areas which may be formed in particular as micro or nanorods, and a method for producing such an optoelectronic
  • Upper side regions may also be a semi-polar one different from side facets of the active regions
  • An object to be solved is to provide an improved optoelectronic semiconductor component having a plurality of juxtaposed active regions, which can be improved by an improved efficiency and / or a
  • the optoelectronic component comprises
  • Current spreading layer which at least partially covers and electrically connects the plurality of active regions.
  • the active areas are each for generation
  • the active areas generate light during operation
  • Semiconductor device can be two or more active
  • Areas in particular a hundred and more active areas or thousands and more active areas include.
  • the active ones include a hundred and more active areas or thousands and more active areas include.
  • regions are so electrically conductive connected to each other that at least 50% of the active
  • Areas in particular at least 75%, for example, all active areas that generate electromagnetic radiation during operation simultaneously.
  • the active regions are arranged at least partially spaced from one another. That is, the active areas do not touch each other at least in some areas, but are at least partially as from each other
  • the active areas may be, for example, in lateral directions parallel to a main plane of extension of the optoelectronic
  • Semiconductor device run, at least partially spaced from each other to be arranged.
  • the active regions can be connected to each other, for example, at their bottom surfaces or their top surfaces by a common material or the substrate.
  • the regions of the active regions which in the operation of the optoelectronic semiconductor component electromagnetic radiation
  • the active areas can each have one
  • Main extension direction extends, for example, transversely or perpendicular to the lateral directions in which the active regions are spaced from each other.
  • the active regions preferably have a core region which may comprise a first semiconductor material. about This first semiconductor material, the active regions may be connected to each other, for example, on a bottom surface of the active regions. Furthermore, the active regions may comprise an active layer covering the core region at least in directions transverse to the main extension direction of the active region. That is, the active layer may be formed on lateral surfaces and possibly also on top surfaces of the active regions and cover the core region there.
  • the bottom surfaces and / or top surfaces of the active regions are each free of the active layer and only lateral surfaces of the active regions are covered by the active layer.
  • the active areas can be a cover layer
  • the cover layer may be formed, for example, with a second semiconductor material, which differs from the first semiconductor material, in particular by its doping
  • Main extension direction of the active region is in each case covered by an active layer, which in turn, in particular in directions transverse to the main extension direction of the active region, each covered by a cover layer.
  • the active regions may in particular be so-called micro- or nanorods in which a shell with an active layer is applied around a core which extends in all three spatial directions.
  • core-shell nanorods or micro-rods also known as core-shell nanorods or core-shell microrods.
  • the semiconductor material with which the active regions are formed is, for example, a nitridic compound semiconductor material.
  • the active regions may be based on InGaN.
  • the optoelectronic semiconductor component is characterized in particular by the fact that, due to the multiplicity of active regions which extend along a main extension direction, the radiation-emitting surface of the
  • the active regions may be coated with a II-VI material or III-V material, in particular a III-nitride material, e.g. InAlGaN, are manufactured and emit depending on
  • Material composition in the active layer for example, light having a peak wavelength in a wavelength range of at least 210 nm to at most 550 nm.
  • the peak wavelength in particular the wavelength is maximum
  • the active areas in the beam path of the electromagnetic radiation can be any one of the beam path of the electromagnetic radiation.
  • the optoelectronic component comprises
  • a current spreading layer which the plurality of active areas on their outer surfaces at least covered in places and electrically conductively connected together.
  • the current spreading layer is in direct contact with the cover layer of the active regions.
  • the current spreading layer may partially or completely cover the active regions at their exposed outer surface.
  • the current spreading layer is preferable
  • Current spreading layer may be formed in such a case with a semiconductor material or with a transparent, conductive oxide.
  • ITO indium tin oxide
  • the current spreading layer is formed with a semi-transparent conductive material which is applied thinly.
  • the current spreading layer may in this case be formed, for example, with graphene or consist of graphene.
  • the active regions on a side facing away from the substrate advantageously on top side portions which are not electrically connected to the current spreading layer.
  • the active regions on a side facing away from the substrate advantageously on top side portions which are not electrically connected to the current spreading layer.
  • Areas may be micro- or nanorods where the
  • the electrical contacting of the micro- or nanorod preferably takes place via the lateral surfaces of the active regions.
  • This has the particular advantage that no current flow in the typically defective Top areas of the active areas, in particular in the side facets of the active areas different facets of the upper side areas occurs. In this way, emission of unwanted wavelength radiation from the top areas can be reduced. Furthermore, the number of non-radiative recombinations is reduced in the top areas and in this way the
  • the active regions preferably each have one
  • the active regions have a length which is greater than the diameter.
  • the length of the active regions is at least twice as large as the diameter, in particular at least five times the diameter or even at least 20 times the diameter of the active regions.
  • the top side regions are covered by an electrically insulating layer.
  • the electrically insulating layer may in particular be an oxide layer, such as a silicon oxide layer.
  • the electrically insulating layer may be a SiO 2 layer.
  • the current spreading layer can be guided over the electrically insulating layer on the upper side regions at least in regions.
  • Optoelectronic semiconductor device are the
  • top areas of the active areas free.
  • the top areas of the active areas may in this case directly adjoin an ambient medium such as air.
  • the ambient medium such as air.
  • Stream spreading layer for example, be arranged on the side surfaces of the active areas, while the
  • Optoelectronic semiconductor device are the
  • the Stromaufweitungstik covers the top areas at least partially or even the entire surface, but in the
  • electrical conductivity of the top portions may be reduced by ion bombardment be that essentially no current flow in the
  • Optoelectronic semiconductor device disclosed features are also disclosed for the method and vice versa.
  • Semiconductor device comprises according to at least one
  • the plurality of active regions may be core-shell nanorods or core-shell microstrips.
  • the use of core-shell nanorods or microfibers as active regions increases the active volume and thus the luminance of the optoelectronic semiconductor component.
  • the method comprises applying a
  • an electrically insulating layer is applied to the upper side regions before the application of the current spreading layer.
  • the application of the electrically insulating layer preferably takes place selectively on the upper side regions.
  • the upper side regions of the active regions and optionally at least part of them are bonded to the substrate
  • the method comprises the directed deposition of the electrically insulating layer such that the electrically insulating layer on the
  • Top areas are deposited with a greater layer thickness than on side surfaces of the active areas.
  • the side surfaces can in particular lateral surfaces of the
  • Method is subsequently preferably carried out an etching process in which the electrically insulating layer is removed from the side surfaces again.
  • Etching process is advantageously chosen such that the applied to the side surfaces electrically insulating layer with a smaller layer thickness is completely removed, while in the top side areas due to there
  • the electrically insulating layer is not completely removed.
  • the electrically insulating layer can be applied in particular by chemical vapor deposition (CVD method).
  • the electrically insulating layer may be, for example, by thermal evaporation, sputtering or laser beam evaporation (PLD, Pulsed Laser Deposition). be applied.
  • the electrically insulating layer may in particular be an oxide layer.
  • the electrically insulating layer is a SiO 2 layer.
  • the current spreading layer is removed from the upper side regions after application to the active regions. In other words, the current spreading layer is first applied to the active areas over the whole area, including the upper areas, and then removed again in the upper areas. After removing the
  • the etching process is carried out, in which the current spreading layer is removed from the upper side regions.
  • Regions applied a transparent dielectric layer which preferably forms a planar surface over the plurality of active regions.
  • the transparent dielectric layer thus advantageously completely fills the interspaces between the active regions and has a planar surface above the active regions.
  • this embodiment is preferably a
  • the material removing process performed by the parts of the transparent dielectric layer, the Current spreading layer and the active areas are removed so that upper side areas of the active areas are exposed.
  • the material-removing process can in particular a
  • the material-removing process may include, in particular, grinding, lapping and / or polishing.
  • Chemical-mechanical polishing (CMP) can also be used for material removal.
  • the exposed after the execution of the material-removing process upper side areas are preferably electrically
  • the electrically insulating layer may be made of the same material as before
  • the transparent dielectric layer and the electrically insulating layer may be one
  • Silicon oxide such as S1O 2 have.
  • the upper side regions of the active regions are advantageously replaced by a layer before the current spreading layer is applied
  • Ion bombardment passivated.
  • the electrical conductivity of the top areas is reduced by the ion bombardment so that they are substantially electrically insulating.
  • the ion bombardment is preferably directed, in particular substantially parallel to the main direction of extension of the active regions. This has the advantage that the
  • the current spreading layer can be applied over the whole area to the active areas.
  • the upper side regions advantageously produces no electrical contact, since these are essentially electrically insulating.
  • FIG. 1A shows a schematic representation of a cross section through an optoelectronic semiconductor component according to a first exemplary embodiment
  • FIG. 1B is an enlarged view of an active area in the first embodiment
  • Figure IC is a simplified schematic plan view of the
  • FIGS. 2A to 2C schematically illustrated intermediate steps in an embodiment of a method for producing the optoelectronic
  • Figures 3A to 3C schematically illustrated intermediate steps in a further embodiment of a
  • FIGS. 4A to 4F schematically illustrated intermediate steps in a further embodiment of a
  • FIGS. 5A to 5D schematically illustrated intermediate steps in a further embodiment of a
  • FIGS. 6A to 6C schematically illustrated intermediate steps in a further embodiment of a
  • the optoelectronic semiconductor component 20 shown schematically in cross section in accordance with a first exemplary embodiment in FIG. 1A has a multiplicity of active regions 10 which are arranged next to one another above a common substrate 1. To simplify the illustration, only three active areas 10 are shown in FIG. The
  • Actual number of active areas 10 in the Optoelectronic semiconductor device 20 may be substantially larger, for example, the optoelectronic
  • Semiconductor device 20 have at least 50, at least 100 or even at least 500 active areas 10.
  • the active regions 10 may be arranged in a matrix-like arrangement over the substrate 1.
  • the plurality of active regions 10 is preferably connected to one another via a first semiconductor layer 2, which may be grown epitaxially on the substrate 1.
  • the first semiconductor layer 2 may in particular be an n-type
  • Be semiconductor layer For example, the first one
  • the active regions 10 are in particular formed as micro- or nanorods. An active region 10 is shown enlarged in FIG. 1B. Each active region 10 includes a core region 11 formed with a first semiconductor material. The core region is enveloped by an active layer 12, which is used to generate electromagnetic
  • the active layer 12 is enveloped by a cover layer 13, which is formed, for example, with a second semiconductor material.
  • a cover layer 13 is formed, for example, with a second semiconductor material.
  • Arrangement of the layers in the micro- or nanorods is also called core-shell structure.
  • the semiconductor layers 2, 11, 12, 13 of the optoelectronic semiconductor component 20 are preferably based on a nitride compound semiconductor.
  • a nitride compound semiconductor in the present context means that the semiconductor layers or at least one layer thereof is a III-nitride Compound semiconductor material, preferably In x Al y Gai x - y N includes, where 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 and x + y ⁇ 1. This material does not necessarily have a mathematically exact
  • composition according to the above formula may contain one or more dopants as well as additional
  • the above formula contains only the essential constituents of the crystal lattice (In, Al, Ga, N), even if these may be partially replaced by small amounts of other substances.
  • the core region 11 comprises n-doped GaN, the active layer 12 InGaN, and the cap layer p-doped GaN. It is also conceivable that the core region 11, the active layer 12 and / or the cover layer 13 of several
  • Partial layers are composed.
  • the active layer 12 may comprise a single or multiple quantum well structure.
  • the active region 10 has a main extension direction Z, along which it extends.
  • the active region 10 is preferably formed longer along the main extension direction z than it is in lateral directions, transverse or perpendicular to the main extension direction Z, broad.
  • the active regions 10 may have hexagonal bases, for example. Alternatively, however, other shapes of the base are possible.
  • the top portions 14 of the active areas 10 may be in
  • Main extension direction have tapered cross-section and in particular have a tip.
  • the Top portions 14 may be in the form of, for example, hexagonal pyramids or hexagonal truncated pyramids.
  • the electrical contacting of the active regions 10 takes place, for example, on the one hand via the first semiconductor layer 2, to which an n-contact 6 is applied.
  • the core regions 11 are electrically conductively connected to the first semiconductor layer 2 and can in particular directly to the first
  • the current spreading layer 4 adjoins, in particular in regions, the cover layers 13 of the active regions 10.
  • the current spreading layer 4 and the p-contact 5 are electrically or by one or more
  • the p-contact 5 and the n-contact 6 may be embodied, for example, as metal layers.
  • the current spreading layer 4, which is arranged above the active regions 10, is preferably a transparent one
  • Semiconductor device 20 emitted radiation through the
  • Current spreading layer 4 are coupled out.
  • the current spreading layer 4 can be transparent
  • TCO conductive oxide
  • ITO indium tin oxide
  • Insulation layer 3 On the bottoms of the active regions 10, where they are interconnected by the semiconductor layer 2, is a Insulation layer 3 is formed, which also serves as a mask for
  • the insulation layer 3 does not have to correspond to a growth mask and can also
  • the insulating layer 3 is, for example, with a semiconductor oxide or a
  • Semiconductor nitride such as silicon oxide or silicon nitride
  • the insulating layer 3 is electrically insulating and insulates the core region 10 as well as the first semiconductor layer 2 from the cover layer 13 and
  • the active regions 10 advantageously have top areas 14, which are not electrically conductively connected to the current spreading layer 4. This will be at the here shown
  • Embodiment achieved in that an electrically insulating layer 7 on the upper side regions 14th
  • the electrically insulating layer 7 covers the active regions 10 only partially, preferably only at the upper side regions 14. It is possible that in addition to lower side regions 16 of the active regions 10, a further electrically insulating layer 7A is applied, for example, the same material as the electrically has insulating layer 7 and in the same
  • Process step can be produced.
  • the side surfaces 15 of the active regions 10 are at least partially not of the electrically insulating layer 7 or the other for producing the electrical contact between the current spreading layer 4 and the cover layers 13
  • the electrically insulating layer 7 and / or the other electrically Insulating layer 7A are preferably each one
  • Oxide layer in particular a Si0 2 layer.
  • top side portions 14 are insulated from the StromaufWeitungs für 4 by the electrically insulating layer 7, during operation of the optoelectronic
  • Top areas 14 embossed. This is advantageous because the upper side regions 14 of the active regions 10
  • optoelectronic semiconductor region 20 can be reduced. In order to avoid such unwanted effects, it has been found advantageous to provide electrical contact between the current spreading layer 4 and the
  • Top areas 14 of the active areas 10 to avoid.
  • FIGS. 2A to 2C schematically show intermediate steps of an exemplary embodiment of a method for producing an optoelectronic semiconductor component, with which, for example, the optoelectronic semiconductor component is illustrated
  • Semiconductor device can be produced.
  • an electrically insulating layer 7 has been applied to the active regions 10.
  • the electrically insulating layer 7 is preferably an oxide layer, in particular a Si0 2 layer.
  • the electrically insulating layer 7 is replaced by a
  • Coating process preferably by a CVD method, applied to the active regions 10.
  • the coating is preferably carried out such that on the top side regions 14, the active regions 10 are deposited a greater layer thickness than on the side surfaces 15.
  • the layer thickness of the electrically insulating layer 7 on the upper side regions 14 about 500 nm, in the range of
  • Precursor materials pressure or temperature
  • an etching process is carried out, by which the electrically insulating layer is at least partially removed.
  • the etching process may be an isotropic etching process by which the layer thicknesses of the electrically insulating layer 7 in the different regions are substantially the same
  • Amount be reduced. Due to the variation of the layer thickness after the coating remains on the top sides 14 of the active regions 10 after the
  • the electrically insulating layer 7 is at least partially completely removed. It is possible that the electrically insulating layer partially covers the side surfaces 15 in the upper region, but the side surfaces 15 are at least not completely separated from the electrically insulating layer 7 covered. It is also possible that in the
  • the insulating layer remains.
  • the insulating layer remains.
  • Etching process are thus removed, for example, about 200 nm of the electrically insulating layer 7.
  • FIG. 2C schematically illustrates a subsequent process step in which the current spreading layer 4 has been applied to the active regions 10.
  • Top portions 14 and bottom portions 16 are the active regions 10 through the electrically insulating ones
  • FIGS. 3A, 3C A modification of the embodiment shown in FIGS. 2A to 2C is schematically illustrated in FIGS. 3A, 3C. As in the previous embodiment, after the fabrication of the active regions 10 in an intermediate step shown in FIGS. 3A, 3C.
  • the process parameters in the coating are set, for example, such that in the field of
  • FIGS. 4A to 4F show a further exemplary embodiment of the method for producing an optoelectronic device
  • the active regions 10 are those which have an n-type conductivity
  • Semiconductor layer 2 are interconnected, have been prepared on a common substrate 1.
  • the substrate 1 may be, for example, a sapphire substrate. Furthermore, an electrically insulating layer 3 has been applied.
  • a mask layer 8 for example, a
  • the mask layer 8 has been removed so far that it ends in a vertical direction below the upper side regions 14 of the active regions 10.
  • the removal of the mask layer 8 can be achieved, for example, by an etching process, in particular by an etching process with an oxygen plasma,
  • Current spreading layer 4 to be removed from the upper side regions 14 not covered by the mask layer 8. This can be carried out by means of a wet-chemical etching process or by means of a dry etching process.
  • the top side regions 14 of the active regions are advantageously exposed, that is to say they are adjacent directly to the surrounding medium such as air.
  • the upper side regions 14 are not covered by the current spreading layer 4, so that no current is impressed into the upper side regions 14 during operation of the optoelectronic semiconductor component 20. This results in the same advantages as in the previous ones
  • FIGS. 5A to 5D show a further exemplary embodiment of the method for producing an optoelectronic device
  • the n-type semiconductor layer 2, the insulating layer 3, the active areas 10 and the current spreading layer 4 have been produced on a substrate 1. This can be done analogously to the previous embodiment, wherein the
  • Embodiments of the active regions 10 and the further layers can in turn correspond to the first embodiment and therefore will not be explained again in more detail.
  • a transparent dielectric layer 9 has been applied to the current spreading layer 4, which preferably completely planarizes these.
  • the transparent dielectric layer 9 fills the interspaces between the active regions 10 connected to the
  • the transparent dielectric layer 9 may in particular be an oxide layer, for example a Si0 2 layer.
  • CMP chemical-mechanical polishing
  • Material removal takes place so far that upper side regions 14 of the active regions 10 are freed from the current spreading layer 4.
  • the tips of the micro- or nanorods, which form the active regions 10, can be removed here.
  • the electrically insulating layer 7 has been applied.
  • the electrically insulating layer 7 may have the same material as the transparent dielectric layer 9. In this case, no optically effective interface between the electrically insulating layer 7 and the transparent dielectric layer 9 is formed.
  • the electrically insulating layer 7 may be an oxide layer such as a SiO 2 layer.
  • Embodiment of the optoelectronic Semiconductor device 20 to complete The electrically insulating layer 7 and the transparent dielectric layer 9 have been partially removed laterally from the active regions 10 to form the n-type semiconductor layer 2 and the current spreading layer 4 for deposition
  • Embodiment of the method for producing an optoelectronic semiconductor device illustrated by means of schematically illustrated intermediate steps.
  • the n-type semiconductor layer 2, the insulating layer 3 and the active regions 10 have been produced on a substrate 1. This can be done analogously to the previous embodiments, wherein the embodiments of the active regions 10 and the other layers in turn the first
  • an ion bombardment is carried out, which is indicated by the arrows 19.
  • the ion bombardment is carried out by means of an ion source, preferably in such a way that the ions impinge thereon substantially parallel to the main extension direction of the active regions 10.
  • the ions therefore advantageously strike substantially only the
  • the top areas 14 are with others
  • Carrying out the ion bombardment for example, a hydrogen plasma and / or an oxygen plasma can be used.
  • a hydrogen plasma and / or an oxygen plasma can be used.
  • FIG. 6C further process steps have been carried out in order to obtain another
  • a current spreading layer 4 which may preferably be an ITO layer, has been applied to the active regions 10. Further, a part of the insulating layer 3 was removed from the n-type semiconductor layer 2 to apply an n-type contact 6 thereon. Furthermore, a p-type contact 5 was applied to a portion of the current spreading layer 4.
  • top portions 14 of the active regions 10 are not adjacent to the current spreading layer 4 connected. Rather, the upper side regions 14 are not electrically conductive due to the passivation by the ion bombardment, so that during operation of the

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Abstract

La présente invention concerne un composant semi-conducteur optoélectronique (20) comportant un substrat (1), une pluralité des zones actives (10, de préférence microtiges ou nanotiges) disposés côte à côte, et une couche d'élargissement de courant (4) qui recouvre au moins partiellement les zones actives (10) et les relie électriquement. Les zones actives (10) sont au moins partiellement espacées l'une de l'autre et comportent une direction d'extension principale (z), une zone centrale (11), une couche d'émission de rayonnement (12) et une couche de recouvrement (13). La couche d'émission de rayonnement (12) recouvre la zone centrale (11) au moins dans des directions transversales à la direction d'extension principale (z) de la zone active (10). La couche de recouvrement (13) recouvre la couche d'émission de rayonnement (12) au moins dans des directions transversales à la direction d'extension principale (z) de la zone active (10). Les zones actives (10) comportent, à un côté opposé au substrat (1), des zones de surface (14) qui ne sont pas reliées électriquement à la couche d'élargissement de courant (4). La présente invention concerne en outre un procédé de fabrication d'un composant semi-conducteur optoélectronique (20).
PCT/EP2017/053133 2016-02-18 2017-02-13 Composant semi-conducteur optoélectronique et procédé de fabrication d'un composant semi-conducteur optoélectronique WO2017140615A1 (fr)

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DE102016102876.2A DE102016102876A1 (de) 2016-02-18 2016-02-18 Optoelektronisches Halbleiterbauelement und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauelements
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DE102019114169A1 (de) * 2019-05-27 2020-12-03 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronisches halbleiterbauelement mit verbindungsbereichen und verfahren zur herstellung des optoelektronischen halbleiterbauelements

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