WO2017092617A1

WO2017092617A1 - Error estimation method, base station and terminal

Info

Publication number: WO2017092617A1
Application number: PCT/CN2016/107298
Authority: WO
Inventors: 蔺同宇; 王浩; 望育梅; 田春长
Original assignee: 华为技术有限公司
Priority date: 2015-11-30
Filing date: 2016-11-25
Publication date: 2017-06-08
Also published as: CN106817192B; CN106817192A

Abstract

An embodiment of the invention discloses an error estimation method, comprising: constructing a first code block by a base station, the first code block comprising information bits, error-correcting code (EEC) check bits and cyclic redundancy check (CRC) check bits; configuring a CRC generator polynomial to generate a CRC check code according to the CRC generator polynomial, both the first and last coefficients of the CRC generator polynomial being 1 and the number of terms having a coefficient of 1 in the CRC generator polynomial being an even number; performing a CRC check according to the CRC check code and forming a second code block after channel coding, and modulating and sending the second code block to a terminal for error estimation by the terminal according to the EEC check bits and the CRC check code. By using the invention, utilization of transmission resources in video data service can be improved and reliability of data transmission is ensured.

Description

Method, base station and terminal for error estimation

This application claims priority to Chinese Patent Application No. 201510859520.2, entitled "A Method of Error Estimation, Base Station and Terminal", filed on November 30, 2015, the entire contents of In this application.

Technical field

The present invention relates to the field of communications technologies, and in particular, to a method, a base station, and a terminal for error estimation.

Background technique

With the rise of the mobile wave, the commercialization of 4G, the rapid expansion of the number of users and the diversification of service types, the demand for data traffic has exploded, especially for video data services, which have bits compared to other services. A feature with a higher rate. The core idea of the current video compression coding technology is to remove the correlation, reduce the redundant information in the video content, and represent the most video content with the least number of bits, thereby achieving compression. However, video compression coding technology reduces the ability of video stream to be fault-tolerant while reducing redundant information. In the compressed video bitstream, each bit is very important. Therefore, bit errors that occur during transmission can significantly affect the decoded video effect. Forward Error Correction (FEC) and data interleaving can only correct transmission errors to a certain extent; automatic retransmission techniques such as Hybrid Automatic Repeat Quest (HARQ) can guarantee the reliability of data transmission. However, retransmission of the entire codeword undoubtedly wastes additional transmission resources, and in multimedia applications with high real-time requirements, excessive retransmission may affect the user experience. If the wrong position of the coded bits can be located, the error can be corrected by transmitting the relevant data in a targeted manner. Compared with automatic retransmission, the latter can guarantee the reliability of data transmission with a small amount of redundancy.

Summary of the invention

The embodiment of the invention provides a method, a base station and a terminal for erroneous estimation, so as to solve the problem that the transmission resource utilization and the transmission reliability are unbalanced in the video data service.

A first aspect of the present invention provides a method of erroneous estimation, comprising:

The base station constructs a first code block, the first code block including information bits, error estimation coding EEC check Bit and cyclic redundancy CRC check bits;

Configuring a CRC generator polynomial, generating a CRC check code according to the CRC generation polynomial, wherein the CRC generation polynomial first coefficient and the last bit coefficient are both 1 and the number of items having a coefficient of 1 in the CRC generation polynomial is an even number;

Performing a CRC check according to the CRC check code and completing channel coding to form a second code block, and the second code block is modulated and sent to the terminal, so that the terminal is based on the EEC check bit and the CRC. The code is evaluated for errors.

With reference to the implementation of the first aspect, in a first possible implementation manner of the first aspect, the performing, by the base station, the first code block includes:

Determining the EEC packet size according to the preset accuracy of the EEC error estimate;

Determining the number of the EEC packets according to a highest index of the CRC generator polynomial and a number of bytes of the EEC check bit;

Performing a CRC check calculation on the information bit, configuring the CRC check bit after the information bit, and performing the total length of the information bit and the CRC check bit according to the number of the EEC packets. Equally, the EEC check bits of each EEC packet are inserted at the equally divided positions.

With reference to the first aspect, or the first possible implementation manner of the first aspect, in the second possible implementation manner of the first aspect, the highest index of the CRC generating polynomial is 8, and the sequence of the CRC generating polynomial is the following Any one:

[1,1,1,0,1,0,0,0,1], [1,1,1,0,0,0,1,0,1], [1,1,0,1,1 , 0,0,0,1], [1,1,0,1,0,1,0,0,1], [1,0,1,1,1,0,0,0,1], [1,0,1,1,0,0,1,0,1], [1,0,1,0,0,1,1,0,1], [1,0,0,1,1 ,1,0,0,1],[1,0,0,1,1,0,1,0,1], [1,0,0,1,0,1,0,1,1], [1,0,0,0,1,1,1,0,1], [1,0,0,0,1,0,1,1,1], [1,1,1,1,0 , 1, 1, 0, 1], [1, 1, 1, 0, 1, 0, 1, 1, 1], [1, 1, 0, 1, 1, 1, 1, 0, 1], [1,0,1,1,0,1,1,1,1].

A second aspect of the present invention provides a method of erroneous estimation, comprising:

Receiving, by the terminal, a second code block sent by the base station;

Demodulating the second code block to obtain an error estimation coded EEC check bit and a cyclic redundancy CRC check bit included in the second code block, where the CRC check code is determined by the base station according to a first bit coefficient and a last bit coefficient a CRC generator polynomial with an even number of 1 and a coefficient of 1;

The terminal performs error estimation on the corresponding data according to the EEC check bit and the CRC check code.

In conjunction with the implementation of the second aspect, in a first possible implementation manner of the second aspect, the method further includes:

After the EEC decoding, the EEC packet miss detection is checked based on the absolute value of the soft information generated by the decision at the time of channel decoding.

A third aspect of the embodiments of the present invention provides a base station, including:

a constructing unit, configured to construct a first code block, where the first code block includes an information bit, an error estimation coding EEC check bit, and a cyclic redundancy CRC check bit;

a configuration unit, configured to configure a CRC generator polynomial, generate a CRC check code according to the CRC generation polynomial, the CRC generation polynomial first coefficient and the last bit coefficient are both 1 and the number of items in the CRC generation polynomial with a coefficient of 1 is even;

a modulating unit, configured to perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and the second code block is modulated and sent to a terminal, so that the terminal is configured according to the EEC The bit check and the CRC check code are used for error estimation.

In conjunction with the implementation of the third aspect, in a first possible implementation manner of the third aspect, the constructing unit is specifically configured to:

With reference to the third aspect, or the first possible implementation manner of the third aspect, in a second possible implementation manner of the third aspect, the highest index of the CRC generating polynomial is 8, and the sequence of the CRC generating polynomial is Any one:

A fourth aspect of the embodiments of the present invention provides a terminal, including:

a receiving unit, configured to receive a second code block sent by the base station;

a demodulation unit, configured to demodulate the second code block to obtain an error estimate included in the second code block a coded EEC check bit and a cyclic redundancy CRC check bit, wherein the CRC check code is generated by the base station according to a CRC generator polynomial whose first coefficient and the last bit coefficient are both 1 and the number of terms of the coefficient is even;

And an estimating unit, configured to perform error estimation on the corresponding data according to the EEC check bit and the CRC check code.

With reference to the fourth aspect, in a first possible implementation manner of the fourth aspect, the terminal further includes:

The checking unit is configured to check the condition of the EEC packet miss detection according to the absolute value of the soft information generated by the decision at the time of channel decoding after the EEC decoding.

Embodiments of the present invention have the following beneficial effects:

By constructing a new first code block, the EEC coded parity is added on the basis of the conventional CRC check, and by configuring a new CRC generator polynomial, the redundant information can be reduced, and the probability of CRC miss detection is further reduced. Therefore, data retransmission can be reduced, and the reliability of data transmission is ensured on the basis of improving the utilization of transmission resources.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work.

1 is a schematic flow chart of a first embodiment of a method for erroneous estimation according to the present invention;

2 is a schematic flow chart of a second embodiment of a method for erroneous estimation according to the present invention;

3 is a schematic structural diagram of a MAC frame constructed according to an embodiment of the present invention;

4 is a schematic flow chart of a third embodiment of a method for erroneous estimation according to the present invention;

FIG. 5 is a schematic structural diagram of a first embodiment of a base station according to the present invention; FIG.

6 is a schematic structural diagram of a second embodiment of a base station according to the present invention;

7 is a schematic structural diagram of a first embodiment of a terminal according to the present invention;

FIG. 8 is a schematic diagram of the composition of a second embodiment of a terminal according to the present invention.

detailed description

The technical solution in the embodiment of the present invention will be clarified in the following with reference to the accompanying drawings in the embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is apparent that the described embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The network element involved in the embodiment of the present invention mainly includes a MAC layer and a physical layer (PHY) layer in the mobile communication system.

MAC layer: Between the PHY layer and the Radio Link Control (RLC) layer, it is the bridge between the PHY layer and the RLC layer. The MAC layer implements many functions related to data processing, including channel management and mapping, packet encapsulation and decapsulation of data packets, HARQ process, data scheduling, and priority management of logical channels.

PHY layer: Taking the Long Term Evolution (LTE) system as an example, the LTE PHY layer mainly provides the following functional services for data transmission at the MAC layer: Transport Block (TB) error checking and error correction, rate matching, and HARQ. Soft combining, mapping of transport channels to physical channels, power control or allocation, modulation and demodulation, frequency domain time domain synchronization, physical layer measurement, multi-antenna space-time signal processing, radio frequency processing, etc.

CRC check: When using CRC check, the sender and receiver use the same generator polynomial g(x), and the first and last bits of g(x) must have a coefficient of 1. The processing method of the CRC is that the sender removes (modulo di-division) g(x) with the information data to be transmitted, and the obtained remainder is added as check data to the original data. The receiver removes the received data with g(x). If the remainder is zero, it means that the transmission process has no error; if the remainder is not zero, there must be an error during the transmission.

The LTE system uses four formats of CRC: CRC-24A, CRC-24B, CRC-l6, and CRC-8. Its generator polynomial is as follows:

CRC-24A: g(x)=x ²⁴ +x ²³ +x ¹⁸ +x ¹⁷ +x ¹⁴ +x ¹¹ +x ¹⁰ +x ⁷ +x ⁶ +x ⁵ +x ⁴ +x ³ +x+1;

CRC-24B: g(x)=x ²⁴ +x ²³ +x ⁶ +x ⁵ +x+1;

CRC-16: g(x)=x ¹⁶ +x ¹² +x ⁵ +1;

CRC-8: g(x)=x ⁸ +x ⁷ +x ⁴ +x ³ +x+1;

The CRC-24A and CRC-24B of length 24 are mainly used for shared channel data transmission. The CRC-l6 of length 16 is mainly used for downlink control channel and broadcast channel data transmission, and the CRC-8 of length 8 is mainly used for channel. Transmission of Channel Quality Information (CQI) information.

First, for TB (length A), a 24 (L=24) bit CRC is added according to the generator polynomial of CRC-24A, and the length of the transport block after adding the CRC check is B=A+L.

After the TB data is added with the 24-bit check code, if the length exceeds Z=6144, it must be segmented and divided into several code blocks, and the CRC processing is performed again by using the generator polynomial CRC-24B for each code block. The segments are all CRC added.

In the network, the video data is taken as an example for video data, and the video data sequence needs to be compressed and encoded before the network transmission. The video compression coding standard currently used is H. .264/Advanced Video Coding (AVC) or Scalable Video Coding (SVC). The general transmission process of packaging the video data into a Media Access Control (MAC) Protocol Data Unit (PDU) and transmitting the feedback to the receiving end includes:

First, the video data is framed by the MAC layer, and then Cyclic Redundancy Check (CRC) and channel coding are performed at the physical layer (PHY), and then physical layer framing, modulation mapping, and then transmitted through the antenna. The receiving end demodulates the data, performs channel decoding and CRC check, and determines feedback Acknowledgement (ACK) or Not-Acknowledgement (NACK) information. The CRC check + channel coding is used for error detection and error correction, and the feedback ACK/NACK is used to indicate whether the current MAC PDU is successfully transmitted.

Since the traditional CRC check mode can only detect errors, the location of the error cannot be determined, and there is a certain probability of missed detection. The information fed back by the receiving end is only ACK/NACK, and it is impossible to retransmit the error in a targeted manner, which may cause excessive redundant information transmission and waste bandwidth resources. The invention provides an Error Estimating Coding (EEC) and CRC joint error location estimation mechanism. In the current CRC check for missed detection, the CRC generator polynomial is redesigned, and the video data is better satisfied. The need to retransmit.

1 is a schematic flowchart of a first embodiment of a method for estimating a fault according to the present invention. In this embodiment, the method includes:

S101. The base station constructs a first code block.

The first code block includes an information bit, an error estimation coded EEC check bit, and a cyclic redundancy CRC check bit.

The first code block may be included in a MAC frame. S102, configuring a CRC generator polynomial according to The CRC generation polynomial generates a CRC check code.

The CRC generation polynomial first coefficient and the last coefficient are both 1 and the number of terms having a coefficient of 1 in the CRC generation polynomial is an even number.

Since EEC coding is added in the embodiment of the present invention, and CRC-24 is used for verification in LTE, in order to reduce redundancy overhead, the present embodiment re-generates the polynomial design of the CRC check:

The probability of misjudgment in the actual environment is related to the bit error rate. The CRC-24A and CRC-24B used in LTE contain the least error pattern with an even number of 1, due to the low bit error rate (10 ^-5 ). The more the error pattern contains 1, the lower the probability of occurrence, the false positive probability is negligible, so do not consider these error patterns too much here. However, for security reasons, the CRC polynomial used in this scheme is based on the principle of the smallest even maximum odd number, that is, the odd number 1 error pattern can be detected by the EEC, and only the even number of 1 error patterns can be considered. The less the probability that the number 1 error pattern occurs, the more the following error pattern is considered: For CRC-8, the minimum error pattern with 1 has 6 1s, and the CRC-24 has 1 minimum. The error pattern has 10 ones. In order to reduce the redundancy overhead by replacing CRC-24 with CRC-8, the overall error probability of CRC-8 and CRC-24 is calculated first: under CRC-8, the probability of occurrence of 6-bit error is about 0.1%, assuming 32 packets, if a codeword has 3200 bits, then all cases of a 6-bit error are

Then the probability of a 6-bit error misjudgment is

The overall error probability is on the order of 10-17. Under the CRC-24 condition, the probability of a 10-bit error occurring is about 0.01%, and the probability of a 10-bit error misjudging is

The overall error probability is on the order of 10-25. By adding EEC coding, combined with CRC-8, the overall error probability can be reduced, which is sufficient compared with the degree of error probability of CRC-24.

Based on the above conditions, the present embodiment obtains some CRC-8 generator polynomials by ensuring that the coefficients of the first and last bits of the generator polynomial g(x) must be 1, and the intermediate items can be 0 or 1. Make them have a minimum of 1 error pattern with 6 1s, so the recommended generator polynomial is:

[1,1,1,0,1,0,0,0,1], [1,1,1,0,0,0,1,0,1], [1,1,0,1,1 ,0,0,0,1],[1,1,0,1,0,1,0,0,1], [1,0,1,1,1,0,0,0,1], [1,0,1,1,0,0,1,0,1], [1,0,1,0,0 ,1,1,0,1],[1,0,0,1,1,1,0,0,1], [1,0,0,1,1,0,1,0,1], [1,0,0,1,0,1,0,1,1], [1,0,0,0,1,1,1,0,1], [1,0,0,0,1 , 0, 1, 1, 1], [1, 1, 1, 1, 0, 1, 1, 0, 1], [1, 1, 1, 0, 1, 0, 1, 1, 1], [1,1,0,1,1,1,1,0,1], [1,0,1,1,0,1,1,1,1].

Taking [1,1,1,0,1,0,0,0,1] and [1,1,1,1,0,1,1,0,1] as an example, the generator polynomial is g(x )=x ⁸ +x ⁷ +x ⁶ +x ⁴ +1 and g(x)=x ⁸ +x ⁷ +x ⁶ +x ⁵ +x ³ +x ² +1.

S104: Perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and then modulate the second code block and send the second code block to the terminal, so that the terminal according to the EEC check bit and The CRC check code is error estimated.

In this embodiment, by constructing a new first code block, the EEC coded parity is added on the basis of the conventional CRC check, and by configuring a new CRC generator polynomial, the redundant information can be reduced and further reduced. The probability of CRC miss detection can reduce data retransmission and ensure the reliability of data transmission on the basis of improving the utilization of transmission resources.

2 is a schematic flowchart of a second embodiment of a method for estimating errors according to the present invention. In this embodiment, the method includes:

S201: Determine an EEC packet size according to a preset accuracy of the EEC error estimation.

S202. Determine a quantity of the EEC packet according to a highest index of the CRC generation polynomial and a number of bytes of the EEC check bit.

After the data is packaged into a MAC PDU, before the CRC check, the EEC code is added. This embodiment redesigns the corresponding first code block, corresponding to the new MAC frame structure. The first code block is composed of three parts, the information bit, The CRC check bit and the EEC check bit are shown in Figure 9. Before channel coding, in order to ensure byte alignment and not to fill a large number of null bits, the present invention provides a typical calculation method for EEC packet byte alignment:

Assume that the amount of data that this transmission can carry is x, x = MAC PDU + CRC + EEC. The MAC PDU size is n bytes (Byte), the CRC check bit c = 1 byte, and the EEC check bit is m bytes.

First, determine the EEC packet size s. Under the premise of ensuring a certain EEC error estimation accuracy, the value range of s is set to s∈(0,512) bits, and each packet contains a 1-bit EEC check bit. s take the maximum value that can be taken in the above range (if you want to make the EEC estimation more accurate, you can take s smaller), thus reducing the EEC check overhead, and the number of EEC packets is 8*m, the EEC packet size is known. The relationship between s and the number of EEC packets is

The length of the MAC PDU is: n=s*mmc, and the new transmittable length is x'. From the above calculation, x' may be smaller than x, and the extra bits of x-x' may be used for channel coding redundancy. Overhead.

S203. Perform CRC check calculation on the information bit, configure the CRC check bit after the information bit, and compare the information bit and the CRC check bit according to the number of the EEC packets. The lengths are equally divided, and the EEC check bits of each EEC packet are inserted at the equally divided positions.

At this point, the configuration of the first code block and the MAC frame is completed. The specific composition can be seen in FIG. 3 , which is a schematic diagram of the composition of the MAC frame constructed by the embodiment of the present invention, including information bits, CRC check bits, and shadows. 1-bit EEC check digit.

S204. Configure a CRC generator polynomial, and generate a CRC check code according to the CRC generation polynomial.

S205: Perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and then modulate the second code block and send the second code block to the terminal, so that the terminal according to the EEC check bit and The CRC check code is error estimated.

Optionally, after performing the CRC check and the EEC check according to the MAC and the CRC check code, the terminal may further check the EEC packet leak according to the absolute value of the soft information generated by the channel decoding after performing the EEC decoding. The situation of the inspection.

Specifically, after the EEC decoding, the soft information generated by the decision when using channel decoding is used.

(where p(X=0) and p(X=1) indicate that X takes a probability of 0,1) can further aid in the detection of EEC packet miss detection. The value of the soft information is generally 100 or more or -100 or less. A value close to 0 indicates that the soft information of this bit is unreliable, so a threshold (such as an absolute value of 1) can be determined to determine which bits are in error. The information bit soft information SI of the decoding error in the code word is close to 0, and the information bit of the error in the packet and the packet for estimating the EEC check miss may be determined according to this feature. The specific judgment is as follows:

If the EEC is error-free, the CRC is wrong, and if there are even errors in the decoding, you can choose soft. Two packets in which the minimum value of information exists are considered to be in error;

If the EEC finds less than or equal to an error and finds that there are a small number of errors during decoding, the packet with the error is reported;

If the EEC has more than one error and it is found that there may be a missed packet when decoding, then whether the absolute soft packet contains the absolute value smaller than the absolute value of the error packet, if there are multiple such packets in the packet. The soft information bit is considered to be wrong.

This embodiment combines the CRC checksum EEC algorithm to reduce the probability of false positives. The theoretical verification is as follows:

There is a miss check on the CRC check (the error codeword is considered to be correct): there are 2n kinds of CRC coding results, and n is the information bit length, which are multiples of g(x). The error that appears in the defined codeword is the error pattern E. For example, if the correct codeword is 10101010101 and the transmitted codeword is 10101010011, the error pattern E is 00000000110. The non-all 0 error pattern that may occur in the channel has 2 ^x -1=2 ^n+r -1, where x = length of the information bit plus CRC, r = CRC check digit, when the error pattern can be g ( x) Divisibility, that is, when the error pattern itself is a codeword, such an error will fool the receiver, causing the decoder to report no problem, saying that the situation is a missed detection. Missing test example:

Let the transmission data bit sequence be F(x)=110011 (ie, x ⁵ +x ⁴ +x+1), and the generated polynomial bit sequence is g(x)=11001, by the formula (F(x)*x ^r )%g (x)=R(x), which can be obtained as R(x)=1001, and the information bit sequence finally transmitted by the transmitting end is F(x)=1100111001. Assume that the sequence of information received at the receiving end is 1100100000 or 1100111001+11001 (modulo 2 operation), divided by g(x)=11001, and the remainder is zero, and no transmission error is considered, so the detection is missed.

Assume that the code length is n, the CRC check bit length is r, and the number of different error patterns is 2 ^x = 2 ^{n + r} , and the number of error patterns that can be divisible by g (x) is 2 ⁿ , except An all-zero error pattern indicates no error, and the remaining error patterns can cause missed detection. The number of these error patterns is 2 ⁿ -1, and the probability of CRC miss detection is

For example, the error pattern that cannot be detected by CRC-24 only accounts for the total possible error pattern.

The longer the CRC number, the stronger the error detection capability, but the lower the coding efficiency. If the EEC (parity) length is m, the EEC divides the codeword into m equal length segments. If the EEC is independent of the CRC check, the missed detection probability is

It can be seen that the insertion of PCE<<PCRC, EEC check digit can effectively improve the accuracy of CRC check.

The embodiment of the invention performs CRC check on the information bits first, then performs EEC packet parity check, combines the advantages of the two coding methods, reduces the false positive rate, and determines the approximate location of the error by the result of each group check. The length of the information bit, the CRC check bit, and the EEC check bit are reasonably allocated by determining the EEC packet size and the number of EEC packets, thereby ensuring that the MAC PDU can perform CRC check and EEC encoding simultaneously. Make full use of the characteristics and advantages of EEC and CRC check, improve the reliability of transmission; at the same time give the basic principle of generator polynomial construction and optional 8-bit CRC generator polynomial, reduce redundancy and reduce CRC miss detection Probability; optionally, at the receiving end, the soft information can be fully utilized to determine the missed packet, and the EEC and CRC are assisted to improve the accuracy of the error estimation.

Referring to FIG. 4, it is a schematic flowchart of a third embodiment of a method for estimating errors according to the present invention. In this embodiment, the method includes:

S401. The terminal receives a second code block sent by the base station.

The first code block includes an information bit, a cyclic redundancy CRC check bit, and an error estimation coding EEC check bit. The CRC check code is determined by the base station according to the first bit coefficient and the last bit coefficient, and the coefficient is 1. The number of items is an even number of CRC generator polynomial generation.

Optionally, the highest index of the CRC generator polynomial is 8, and the sequence of the CRC generator polynomial is any one of the following:

S402. Demodulate the second code block to obtain an error estimation coded EEC check bit and a cyclic redundancy CRC check bit included in the second code block.

S403. The terminal performs error estimation on the corresponding data according to the EEC check bit and the CRC check code.

S404. After performing EEC decoding, check the case of the EEC packet miss detection according to the absolute value of the soft information generated by the decision at the time of channel decoding.

Optionally, after the EEC decoding, the soft information generated by the decision when using channel decoding is used.

If the EEC is error-free, the CRC is wrong, and an even number of errors are found during decoding, the two packets in which the soft information minimum value exists may be selected as an error;

In this embodiment, the EEC check bit and the CRC check code in the first code block are obtained by demodulation to ensure the smooth progress of the EEC and the CRC check, and the CRC generator polynomial adapted to the joint mechanism is redesigned, and finally received. The soft information on the side further improves the accuracy of the error estimate.

FIG. 5 is a schematic structural diagram of a first embodiment of a base station according to the present invention. In this embodiment, the base station includes:

The constructing unit 100 is configured to construct a first code block, where the first code block includes an information bit, an error estimation coding EEC check bit, and a cyclic redundancy CRC check bit;

The configuration unit 200 is configured to configure a CRC generation polynomial, and generate a CRC check code according to the CRC generation polynomial, where the CRC generation polynomial first coefficient and the last coefficient are both 1 and the number of the coefficient in the CRC generation polynomial is 1. Even number;

The modulating unit 300 is configured to perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and the second code block is modulated and sent to the terminal, so that the terminal according to the EEC The check digit and the CRC check code are used for error estimation.

Optionally, the constructing unit 100 is specifically configured to:

It should be noted that the foregoing configuration unit 100, the configuration unit 200, and the modulation unit 300 may exist independently or may be integrated, and the configuration unit 100, the configuration unit 200, or the modulation unit 300 in the above base station embodiment may be independent of hardware. The processor of the base station is separately provided and can be in the form of a microprocessor; it can also be embedded in the processor of the base station in hardware, or can be stored in the memory of the base station in software to facilitate the processor of the base station. The operations corresponding to the above construction unit 100, configuration unit 200, and modulation unit 300 are invoked.

For example, in the first embodiment of the base station of the present invention (the embodiment shown in FIG. 5), the construction unit 100 may be a processor of the base station, and the functions of the configuration unit 200 and the modulation unit 300 may be embedded in the processor. It can also be set independently of the processor, or it can be stored in the memory in the form of software, and its function can be called by the processor. The above processor may be a central processing unit (CPU), a microprocessor, a single chip microcomputer, or the like.

6 is a schematic diagram of a composition of a second embodiment of a base station according to the present invention. In this embodiment, the base station includes:

The input device 110, the output device 120, the memory 130, and the processor 140. The memory 130 is configured to store a set of program codes, and the processor 140 is configured to invoke program code stored in the memory 130, perform the method of error estimation according to the present invention, and perform any operation in the first and second embodiments. Work.

FIG. 7 is a schematic structural diagram of a first embodiment of a terminal according to the present invention. In this embodiment, the terminal includes:

The receiving unit 400 is configured to receive a second code block sent by the base station;

Demodulation unit 500, configured to demodulate the second code block to obtain an error estimation coded EEC check bit included in the second code block, and a cyclic redundancy CRC check bit, where the CRC check code is used by the base station A CRC generator polynomial is generated according to an even number of items whose first coefficient and last bit coefficient are both and whose coefficient is 1;

The estimating unit 600 is configured to perform error estimation on the corresponding data according to the EEC check bit and the CRC check code.

Optionally, the terminal may further include a checking unit 700 (not shown in FIG. 7), for performing an EEC packet miss check according to an absolute value of the soft information generated by the decision at the time of channel decoding after performing EEC decoding. .

It should be noted that the foregoing receiving unit 400, the demodulating unit 500, the estimating unit 600, and the checking unit 700 may exist independently or may be integrated, and the receiving unit 400, the demodulating unit 500, the estimating unit 600 or the above terminal embodiment The verification unit 700 can be separately set in the form of hardware independently of the processor of the base station, and can be in the form of a microprocessor; it can also be embedded in the processor of the terminal in hardware, or can be stored in the terminal in software. In the memory, the processor of the terminal is called to perform operations corresponding to the above receiving unit 400, demodulating unit 500, estimating unit 600, and verifying unit 700.

For example, in the first embodiment of the terminal of the present invention (the embodiment shown in FIG. 7), the estimating unit 600 may be a processor of the terminal, and the functions of the receiving unit 400, the demodulating unit 500, and the checking unit 700 may be embedded. In the processor, it can also be set separately from the processor, or can be stored in the memory in the form of software, and the function is called by the processor. The above processor may be a central processing unit (CPU), a microprocessor, a single chip microcomputer, or the like.

The receiving unit 400 can also be used as a transceiver circuit of the estimating unit 600, and is integrated with the estimating unit 600.

FIG. 8 is a schematic structural diagram of a fourth embodiment of a terminal according to the present invention. In this embodiment, the base station includes:

The input device 210, the output device 220, the memory 230, and the processor 240. The memory 230 is configured to store a set of program codes, and the processor 240 is configured to invoke the program code stored in the memory 230 to perform any operation in the third embodiment of the method for estimating the error of the present invention.

It should be noted that the various embodiments in the present specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same similar parts between the various embodiments are mutually referred to. can. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

Through the description of the above embodiments, the present invention has the following advantages:

Performing CRC check on the information bits first, then performing EEC packet parity check, combining the advantages of the two encoding methods, reducing the false positive rate, and determining the approximate location of the error by the result of each group check; by determining the EEC The packet size and the number of EEC packets are used to reasonably allocate the length of the information bits, the CRC check bits, and the EEC check bits, thereby ensuring that the MAC PDU can perform both CRC check and EEC encoding. Make full use of the characteristics and advantages of EEC and CRC check, improve the reliability of transmission; at the same time give the basic principle of generator polynomial construction and optional 8-bit CRC generator polynomial, reduce redundancy and reduce CRC miss detection Probability; optionally, at the receiving end, the soft information can be fully utilized to determine the missed packet, and the EEC and CRC are assisted to improve the accuracy of the error estimation.

One of ordinary skill in the art can understand that all or part of the process of implementing the foregoing embodiments can be completed by a computer program to instruct related hardware, and the program can be stored in a computer readable storage medium. When executed, the flow of an embodiment of the methods as described above may be included. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

Claims

A method for erroneous estimation, comprising:

The base station constructs a first code block, where the first code block includes an information bit, an error estimation coding EEC check bit, and a cyclic redundancy CRC check bit;

Configuring a CRC generator polynomial, generating a CRC check code according to the CRC generation polynomial, wherein the CRC generation polynomial first coefficient and the last bit coefficient are both 1 and the number of items having a coefficient of 1 in the CRC generation polynomial is an even number;

Performing a CRC check according to the CRC check code and completing channel coding to form a second code block, and the second code block is modulated and sent to the terminal, so that the terminal is based on the EEC check bit and the CRC. The code is evaluated for errors.
The method of claim 1, wherein the base station constructs the first code block, comprising:

Determining the EEC packet size according to the preset accuracy of the EEC error estimate;

Determining the number of the EEC packets according to a highest index of the CRC generator polynomial and a number of bytes of the EEC check bit;

Performing a CRC check calculation on the information bit, configuring the CRC check bit after the information bit, and performing the total length of the information bit and the CRC check bit according to the number of the EEC packets. Equally, the EEC check bits of each EEC packet are inserted at the equally divided positions.
The method according to claim 1 or 2, wherein the highest index of the CRC generator polynomial is 8, and the sequence of the CRC generator polynomial is any one of the following:

[1,1,1,0,1,0,0,0,1], [1,1,1,0,0,0,1,0,1], [1,1,0,1,1 , 0,0,0,1], [1,1,0,1,0,1,0,0,1], [1,0,1,1,1,0,0,0,1], [1,0,1,1,0,0,1,0,1], [1,0,1,0,0,1,1,0,1], [1,0,0,1,1 ,1,0,0,1],[1,0,0,1,1,0,1,0,1], [1,0,0,1,0,1,0,1,1], [1,0,0,0,1,1,1,0,1], [1,0,0,0,1,0,1,1,1], [1,1,1,1,0 , 1, 1, 0, 1], [1, 1, 1, 0, 1, 0, 1, 1, 1], [1, 1, 0, 1, 1, 1, 1, 0, 1], [1,0,1,1,0,1,1,1,1].
A method for erroneous estimation, comprising:

Receiving, by the terminal, a second code block sent by the base station;

Demodulating the second code block to obtain an error estimation coding EEC check bit and a cyclic redundancy CRC check code included in the second code block, wherein the CRC check code is determined by the base station according to a first bit coefficient and a last bit coefficient a CRC generator polynomial with an even number of 1 and a coefficient of 1;

The terminal performs error estimation on the corresponding data according to the EEC check bit and the CRC check code.
The method of claim 4, further comprising:

After the EEC decoding, the EEC packet miss detection is checked based on the absolute value of the soft information generated by the decision at the time of channel decoding.
A base station, comprising:

a constructing unit, configured to construct a first code block, where the first code block includes an information bit, an error estimation coding EEC check bit, and a cyclic redundancy CRC check bit;

a configuration unit, configured to configure a CRC generator polynomial, generate a CRC check code according to the CRC generation polynomial, the CRC generation polynomial first coefficient and the last bit coefficient are both 1 and the number of items in the CRC generation polynomial with a coefficient of 1 is even;

a modulating unit, configured to perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and the second code block is modulated and sent to a terminal, so that the terminal is configured according to the EEC The bit check and the CRC check code are used for error estimation.
The base station according to claim 6, wherein the construction unit is specifically configured to:

Determining the EEC packet size according to the preset accuracy of the EEC error estimate;

Determining the number of the EEC packets according to a highest index of the CRC generator polynomial and a number of bytes of the EEC check bit;

Performing a CRC check calculation on the information bit, configuring the CRC check bit after the information bit, and performing the total length of the information bit and the CRC check bit according to the number of the EEC packets. Equally, the EEC check bits of each EEC packet are inserted at the equally divided positions.
A base station according to claim 6 or 7, wherein said CRC generates a polynomial The highest index is 8, and the sequence of the CRC generator polynomial is any one of the following:

[1,1,1,0,1,0,0,0,1], [1,1,1,0,0,0,1,0,1], [1,1,0,1,1 , 0,0,0,1], [1,1,0,1,0,1,0,0,1], [1,0,1,1,1,0,0,0,1], [1,0,1,1,0,0,1,0,1], [1,0,1,0,0,1,1,0,1], [1,0,0,1,1 ,1,0,0,1],[1,0,0,1,1,0,1,0,1], [1,0,0,1,0,1,0,1,1], [1,0,0,0,1,1,1,0,1], [1,0,0,0,1,0,1,1,1], [1,1,1,1,0 , 1, 1, 0, 1], [1, 1, 1, 0, 1, 0, 1, 1, 1], [1, 1, 0, 1, 1, 1, 1, 0, 1], [1,0,1,1,0,1,1,1,1].
A terminal, comprising:

a receiving unit, configured to receive a second code block sent by the base station;

a demodulation unit, configured to demodulate the second code block to obtain an error estimation coded EEC check bit included in the second code block, and a cyclic redundancy CRC check bit, where the CRC check code is determined by the base station a CRC generator polynomial in which the first coefficient and the last coefficient are both 1 and the number of terms of the coefficient is even;

And an estimating unit, configured to perform error estimation on the corresponding data according to the EEC check bit and the CRC check code.
The terminal according to claim 9, wherein the terminal further comprises:

The checking unit is configured to check the condition of the EEC packet miss detection according to the absolute value of the soft information generated by the decision at the time of channel decoding after the EEC decoding.