WO2017081796A1 - Semiconductor device - Google Patents

Abstract

To improve the performance of a semiconductor device including an optical waveguide. In order to achieve the purpose, a semiconductor device of the present invention is provided with: an optical waveguide layer formed of a semiconductor layer having a front surface and a rear surface; a first stress film that applies a tensile strain to the front surface side of the optical waveguide layer; and a second stress film that applies a tensile strain to the rear surface side of the optical waveguide layer.

Description

Semiconductor device

The present invention relates to a semiconductor device, for example, a technique effective when applied to a semiconductor device including an optical waveguide.

Japanese Patent Laid-Open No. 2003-207660 (Patent Document 1) describes a technique for reducing stress applied to a waveguide by a plurality of stress films having different thermal expansion coefficients.

Non-Patent Document 1 describes a technique for improving luminous efficiency by applying local local stress to a germanium light-emitting layer by internal stress of a silicon nitride film.

Non-Patent Document 2 describes a technique in which an indirect transition semiconductor is changed to a direct transition semiconductor by applying a tensile strain to the thin film layer by causing a stress film to warp the thin film layer.

JP 2003-207660 A

For example, optical communication is used in broadband networks that support the Internet industry. A laser diode using a compound semiconductor such as a III-V group or a II-VI group is used for transmission / reception of light in this optical communication.

On the other hand, LSI (Large Scale Integration) based on silicon is used for information processing and information storage. In order to connect this LSI to a broadband network, silicon and compounds that are different materials from each other are used. It is necessary to consider the connection with the semiconductor. In this regard, in recent years, research has been actively conducted to realize short-distance optical wiring between silicon semiconductor chips and in semiconductor chips with an optical waveguide using silicon. It is called “Silicon Photonics”. This “silicon photonics” is a technique for making an optical element typified by an optical waveguide using a sophisticated silicon line widely spread worldwide.

At present, LSIs are being produced on silicon lines based on CMOS (Complementary Metal Oxide Semiconductor) circuits, but in the future, photonics and electronics integrating optical circuits and CMOS circuits based on silicon photonics will be integrated. It is believed that circuit technology will be realized.

Here, the most challenging issue in “Silicon Photonics” is the light source. This is because silicon and germanium in a bulk state are indirect transition semiconductors and thus have extremely low luminous efficiency. That is, in “silicon photonics”, it is desired to improve the performance of indirect transition semiconductors made of silicon, germanium, etc., and particularly when an indirect transition semiconductor made of silicon, germanium, etc. is used as a light emitting element. It is important to improve luminous efficiency.

An object of the present invention is to provide a technique capable of improving performance in a semiconductor device including an optical waveguide.

Other issues and novel features will become clear from the description of the present specification and the accompanying drawings.

In one embodiment, a semiconductor device includes an optical waveguide layer formed of a semiconductor layer having a first surface and a second surface opposite to the first surface, and a first strain applied to the first surface side of the optical waveguide layer. 1 stress film | membrane and the 2nd stress film | membrane which gives a tensile strain to the 2nd surface side of an optical waveguide layer are provided.

In one embodiment, a semiconductor device includes an optical waveguide layer formed of a semiconductor layer having a first surface and a second surface opposite to the first surface, and a first surface provided on the first surface side of the optical waveguide layer. 1 film and the 2nd film | membrane provided in the 1st surface side of the optical waveguide layer so that the 1st film | membrane may be included and it may cover a 1st film | membrane in planar view. At this time, the first film includes a silicon oxide film or a first silicon nitride film, and the second film includes an aluminum nitride film or a second silicon nitride film. The bond density between nitrogen and hydrogen in the second silicon nitride film is larger than the bond density between nitrogen and hydrogen in the first silicon nitride film.

According to one embodiment, a semiconductor device includes a thin-walled portion, an optical waveguide layer including a semiconductor layer formed in the thin-walled portion and having a first surface and a second surface opposite to the first surface, and an optical waveguide The first film formed on the first surface of the layer and the back surface provided on the second surface side of the optical waveguide layer among the surfaces of the thin portion, and larger in size than the first film A second film. At this time, the first film includes a silicon nitride film that is a silicon oxide film or a compressive stress film, and the second film includes a silicon nitride film that is a silicon oxide film or a compressive stress film.

According to one embodiment, the performance of a semiconductor device including an optical waveguide can be improved.

It is a figure which shows the typical band structure of a direct transition semiconductor. It is a figure which shows the typical band structure of an indirect transition semiconductor. (A) is a figure which shows typically the band structure of germanium which is an indirect transition semiconductor, (b) is a schematic diagram which shows the band structure at the time of giving an extension strain to the crystal | crystallization of germanium. (A) is a figure which shows typically the structural example which gives a local stress to the core layer which is an optical waveguide layer, (b) is the figure which visualized the extension distortion added to a core layer. (A) is a figure which shows typically the structural example which gives global stress to the core layer which is an optical waveguide layer, (b) is the figure which visualized the extension distortion added to a core layer. 2 is a diagram for explaining a basic idea in Embodiment 1. FIG. (A) is a figure which shows typically the structural example which gives both global stress and local stress to the core layer which is a light emitting layer, (b) is the figure which visualized the extensional strain added to a core layer. . It is a figure explaining the mode gain in the structural example which forms a compressive-stress film | membrane locally directly on the core layer CRL. It is a figure explaining the mode gain in the structural example which implement | achieves the basic thought in Embodiment 1. FIG. 2 is a diagram illustrating a planar configuration of the semiconductor device according to the first embodiment, and FIG. 3B is a cross-sectional view taken along line AA in FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device in a second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; (A) is a figure which shows the planar structure of the semiconductor device in Embodiment 3, (b) is sectional drawing cut | disconnected by the AA of FIG. 26 (a).

In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

In all the drawings for explaining the embodiments, the same members are, in principle, given the same reference numerals, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
Semiconductors can be distinguished into direct transition semiconductors and indirect transition semiconductors due to differences in band structures. In the following, first, a direct transition semiconductor and an indirect transition semiconductor will be described.

<Direct transition semiconductor>
FIG. 1 is a diagram showing a schematic band structure of a direct transition semiconductor. In FIG. 1, the horizontal axis indicates the wave number (k) corresponding to the momentum, and the vertical axis indicates energy (E). In FIG. 1, the valence band and the conduction band constituting the band structure are shown, and the upper end of the valence band is shown as Ev, and the lower end of the conduction band is shown as Ec. Here, in the direct transition semiconductor, the upper end (Ev) of the valence band and the lower end (Ec) of the conduction band have the same wave number. Here, for example, consider that electrons transition from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band. In this case, first, since the wave numbers of the lower end (Ec) of the conduction band and the upper end (Ev) of the valence band are equal, the electrons transition from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band. Save momentum. Therefore, in a direct transition semiconductor, an electron can transit independently from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band. In this transition, the energy of the electron is changed from “Ec” to “Ev”. Therefore, light having an energy of “Ec−Ev = hν” is emitted according to the energy conservation law. That is, in the direct transition semiconductor, the upper end (Ev) of the valence band and the lower end (Ec) of the conduction band have the same wavenumber, so that the valence band from the lower end (Ec) of the conduction band. An electron transition to the upper end (Ev) occurs. For this reason, when a direct transition semiconductor is used as a light emitting element, the luminous efficiency is increased. That is, in the direct transition semiconductor, a light emitting element with high light emission efficiency can be manufactured due to the band structure. As the direct transition semiconductor, there are compound semiconductors represented by GaAs and GaN.

<Indirect transition semiconductor>
On the other hand, FIG. 2 is a diagram showing a schematic band structure of an indirect transition semiconductor. In FIG. 2, the horizontal axis represents the wave number (k) corresponding to the momentum, and the vertical axis represents energy (E). In FIG. 2, the valence band and the conduction band constituting the band structure are shown, the upper end of the valence band is shown as Ev, and the lower end of the conduction band is shown as Ec. Here, in the indirect transition semiconductor, unlike the direct transition semiconductor, the upper end (Ev) of the valence band and the lower end (Ec) of the conduction band have different wave numbers. Therefore, for example, considering that electrons transition from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band, in the indirect transition semiconductor, the lower end (Ec) of the conduction band and the upper end of the valence band (Ev) ) Are different from each other, the momentum is not preserved when an electron transits alone from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band. That is, in an indirect transition semiconductor, the transition of electrons alone from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band does not satisfy the conservation of momentum. For this reason, in an indirect transition semiconductor, in order to preserve momentum by the transition of electrons from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band, interaction with components other than electrons is required. Become. That is, in the indirect transition semiconductor, the transition of electrons from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band requires interaction with the lattice vibration (phonon) of the crystal lattice. In other words, in an indirect transition semiconductor, in order for electrons to transition from the lower end (Ec) of the conduction band to the upper end (Ev) of the valence band, phonon intervention that satisfies the conservation law of momentum is required. Therefore, indirect transition semiconductors require this phonon intervention, so that when the indirect transition semiconductor is used as a light emitting element, the light emission efficiency is lowered. That is, in the indirect transition semiconductor, the light emission efficiency is lowered due to the band structure. Such indirect transition semiconductors include Si (silicon) and Ge (germanium).

From the above, it is desirable to use a direct transition semiconductor as the light emitting element, but silicon and germanium used in “silicon photonics” are indirect transition semiconductors, and light emitting elements with high luminous efficiency in “silicon photonics” It can be seen that ingenuity is required to realize Therefore, in the first embodiment, first, a light-emitting element having high light emission efficiency in “silicon photonics” is realized by using the knowledge described below.

<Knowledge used in Embodiment 1>
FIG. 3A is a diagram schematically showing a band structure of germanium which is an indirect transition semiconductor. As shown in FIG. 3A, in the band structure of germanium, the energy of the conduction band at the Γ point is higher than the energy of the conduction band at the L point. Therefore, it can be seen that germanium is an indirect transition semiconductor. However, when germanium is subjected to an extension strain, the band gap is reduced, and as the band gap is reduced, the energy of the conduction band at the Γ point becomes lower than the energy of the conduction band at the L point.

Specifically, FIG. 3B is a schematic diagram showing a band structure in the case where a tensile strain is applied to a germanium crystal. As shown in FIG. 3B, it can be seen that when the germanium crystal is stretched, the energy of the conduction band at the Γ point is lower than the energy of the conduction band at the L point. This means that germanium, which is an indirect transition semiconductor in a normal crystal state, functions as a direct transition semiconductor when it is given an extensional strain. Therefore, even if germanium, which is an indirect transition semiconductor, is used as a light-emitting element in “silicon photonics”, germanium can be made to function as a direct transition semiconductor if a structure that imparts tensile strain to germanium crystals can be realized. Thus, in “silicon photonics”, a light emitting element with high luminous efficiency can be realized. In other words, in the first embodiment, for example, light emission in “silicon photonics” is based on the knowledge that an indirect transition semiconductor such as germanium or silicon can be made to function as a direct transition semiconductor by applying an extension strain. A highly efficient light-emitting element is realized.

In particular, in germanium, the energy of the conduction band at the Γ point is higher than the energy of the conduction band at the L point in a normal state where no tensile strain is applied, but the difference is slight, and it is easy to apply the tensile strain. There is a characteristic that the energy of the conduction band at the Γ point is lower than the energy of the conduction band at the L point. That is, germanium easily changes from an indirect transition semiconductor to a direct transition semiconductor by applying an extension strain. Therefore, in consideration of this point, the present specification pays particular attention to germanium. However, the technical idea in the first embodiment is not limited to germanium, and can be widely applied to, for example, other indirect transition semiconductors represented by silicon.

The present inventor newly found that there is a matter to be solved as shown below when applying the above-described knowledge that the indirect transition semiconductor can function as a direct transition semiconductor when tensile strain is applied to the indirect transition semiconductor, Since the improvement of the matter to be solved has been examined, the following will describe the improvement.

<Examination of improvement>
The above-mentioned approach for improving the performance by applying stress to the crystal, for example, in the so-called strained channel structure that applies strain to the channel in order to improve the mobility of the MOSFET formed in silicon, has so far been the principle And manufacturing technology is being researched. However, this technology is an approach to improving the performance of electronic devices such as MOSFETs formed on silicon. According to a new study by the inventor, an approach to improve the performance by applying stress to crystals has been proposed. When applied to devices, there are new improvements.

Here, as a classification of how to give stress, there are local stress that gives stress locally to the device and global stress that gives stress to the whole structure such as a semiconductor substrate (wafer). First, focusing on the local stress, the matters to be improved found by the present inventor will be described.

FIG. 4 is a diagram for explaining matters to be improved with respect to local stress. In particular, FIG. 4A is a diagram schematically illustrating a configuration example in which local stress is applied to the core layer, which is an optical waveguide layer, and FIG. 4B is a diagram visualizing tensile strain applied to the core layer. It is. In FIG. 4A, for example, a clad layer CLD made of silicon is formed on the insulating film IF, and a core layer CRL made of germanium is formed so as to be sandwiched between the clad layers CLD. At this time, since the refractive index of germanium constituting the core layer CRL is larger than the refractive index of silicon constituting the cladding layer CLD, the light propagating through the core layer CRL is confined in the core layer CRL. In this way, the core layer CRL that is an optical waveguide layer is configured.

As shown in FIG. 4A, a compressive stress film 10 is formed on the surface of the core layer CRL sandwiched between the clad layers CLD. At this time, the compressive stress film 10 is a film that tends to stretch as a result of applying compressive stress to the film itself. Therefore, a tensile strain is applied to the core layer CRL in contact with the compressive stress film 10. Specifically, as shown in FIG. 4B, it can be seen that an extension strain is applied to the surface side of the core layer CRL.

The tensile strain applied by the compressive stress film 10 is maximum at the interface between the compressive stress film 10 and the core layer CRL, and decreases as the distance from the compressive stress film 10 increases. Therefore, the tensile strain in the core layer CRL is reduced. The distribution of is non-uniform. As a result, the effect of effective stretching strain by the compressive stress film 10 is limited to a region from the surface of the core layer CRL to a depth of several tens of nm. Accordingly, the tensile strain due to the compressive stress film 10 is effectively applied to a portion formed near the surface (depth of about several tens to 100 nm), for example, like a channel region of a MOSFET. It does not effectively apply to a portion having a depth of several hundred nm or more. In particular, since the thickness of the core layer made of germanium targeted in the first embodiment is about several hundred nm, the local stress caused by the compressive stress film 10 gives tensile strain to the entire core layer CRL made of germanium. It becomes difficult. In other words, from the viewpoint of causing an indirect transition semiconductor to function as a direct transition semiconductor, it is necessary to give the entire core layer CRL an extension strain, but the local stress due to the compressive stress film 10 has a thickness of about several hundred nm. It is difficult to give an extension strain to the entire core layer CRL having a thickness.

In this regard, it is conceivable to reduce the thickness of the core layer CRL made of germanium in order to give the entire core layer CRL a tensile strain. However, it is appropriate to reduce the thickness of the core layer CRL made of germanium. There is no. The reason for this will be described below.

The core layer CRL serving as the optical waveguide layer needs to have a thickness of about (wavelength / refractive index) as the core layer CRL in order to confine propagating light in the core layer CRL. Furthermore, it is necessary to increase the thickness of the core layer CRL from the viewpoint of maintaining the physical properties and quality of germanium. This is because, when germanium is formed on silicon, germanium formed on silicon due to a mismatch in lattice constant between germanium and silicon, in principle, has a large defect density and dislocation density. This is because the core layer CRL (germanium layer) needs to be thickened in order to reduce the dislocation density. In other words, in order to improve the crystallinity by reducing the defect density and the dislocation density, it is necessary to increase the thickness of the entire core layer CRL including the buffer layer of several tens of nm to several hundred nm or more. Furthermore, since germanium has a smaller material gain than a compound semiconductor, it is necessary to compensate for the small material gain and increase the mode gain indicating the luminous efficiency by the volume effect by increasing the thickness of the core layer CRL as the light emitting layer. There is. From the above, it is difficult to reduce the thickness of the core layer CRL.

The emission wavelength of germanium is about 1600 nm, and the refractive index of germanium is about 4. Further, in order to increase the mode gain and distribute the electric field of propagating light in the core layer CRL (light emitting layer), a thickness of (wavelength / refractive index) = about 400 nm is required. Here, the electric field peak of the propagation light propagating through the core layer CRL of about (wavelength / refractive index) is located near the center of the core layer CRL. For this reason, the ratio that the material gain near the center of the core layer CRL contributes to the amplification of the propagation light becomes high. In other words, the influence of the material properties near the front surface and near the back surface of the core layer CRL on the light emission properties is small. That is, in the local stress caused by the compressive stress film 10 shown in FIG. 4A, the surface of the core layer CRL can be locally stretched, but the entire core layer CRL cannot be stretched. The contribution to the parameter called mode gain indicating the luminous efficiency is also small. Therefore, it is difficult to sufficiently improve the light emission efficiency with the local stress by the compressive stress film 10 shown in FIG.

In this regard, another technique for applying stress is global stress that deforms the entire structure (for example, the entire semiconductor substrate). For example, as the global stress, there is a method of warping the entire semiconductor substrate (wafer). This global stress has an advantage that a strong and uniform stress can be applied to the entire semiconductor substrate compared to the local stress. On the other hand, in the method of applying global stress, there is a concern that the semiconductor substrate may be warped or the semiconductor substrate may be damaged due to excessive stress. Furthermore, as shown below, it is difficult to sufficiently improve the light emission efficiency even in the method of applying global stress.

FIG. 5 is a diagram for explaining matters to be improved regarding global stress. In particular, FIG. 5A is a diagram schematically showing a configuration example in which global stress is applied to the core layer which is an optical waveguide layer, and FIG. 5B is a diagram visualizing the extension strain applied to the core layer. It is. In FIG. 5A, for example, a clad layer CLD made of silicon is formed on the insulating film IF, and a core layer CRL made of germanium is formed so as to be sandwiched between the clad layers CLD. At this time, since the refractive index of germanium constituting the core layer CRL is larger than the refractive index of silicon constituting the cladding layer CLD, the light propagating through the core layer CRL is confined in the core layer CRL. In this way, the core layer CRL that is an optical waveguide layer is configured.

Then, as shown in FIG. 5A, an extension stress film 11 is formed so as to cover the surface of the core layer CRL from the surface of the cladding layer CLD. At this time, the extension stress film 11 is a film to be compressed as a result of extension stress being applied to the film itself. Therefore, compressive strain is applied to the core layer CRL in contact with the tensile stress film 11. Specifically, as shown in FIG. 5B, it can be seen that compressive strain is applied to the surface side of the core layer CRL.

Here, when the structure is distorted by the global stress, as shown in FIG. 5B, there are a portion where the structure is extended (back side) and a portion where the structure is contracted (front side). . That is, with global stress, it is difficult to impart distortion in the same direction (same characteristics) to the entire structure. As a result, the global stress cannot give the entire core layer CRL an extensional strain. In other words, when global stress is applied to the core layer CRL, the light emission efficiency is increased at the location where the extension strain is applied, while the light emission efficiency is decreased at the location where the compression strain is applied. For this reason, it is difficult to sufficiently improve the light emission efficiency of the core layer CRL even by the global stress.

From the above, according to the study of the present inventor, in order to improve the light emission efficiency of the entire core layer CRL by applying a tensile strain to the entire core layer CRL having a thickness of about several hundreds of nanometers, a device is devised. You can see that it is needed. Therefore, in the first embodiment, it is possible to improve the light emission efficiency of the entire core layer CRL by applying a device for imparting tensile strain to the entire core layer CRL having a thickness of about several hundred nm. In the following, the basic idea in the first embodiment to which this device has been applied will be described with reference to the drawings.

<Basic idea in Embodiment 1>
FIG. 6 is a diagram for explaining the basic idea in the first embodiment. As shown in FIG. 6, a clad layer CLD and a core layer CRL are formed on the insulating film IF, and the core layer CRL is arranged so as to be sandwiched between the clad layers CLD. A compressive stress film 10 is formed on the surface of the core layer CRL, and an extension stress film 11 is formed over the compressive stress film 10 and over the cladding layer CLD. That is, the basic idea in the first embodiment is a technical idea of using the compressive stress film 10 and the tensile stress film 11 in combination, in particular, forming the compressive stress film 10 on the surface of the core layer CRL, and This is a technical idea of covering the compressive stress film 10 and forming the tensile stress film 11 over the clad layer CLD.

Thereby, first, the tensile stress film 11 formed from the core layer CRL to the clad layer CLD applies global stress to the entire structure including the core layer CRL and the clad layer CLD to give a downward convex distortion. Can do. Specifically, the tensile stress film 11 applies a compressive stress to the surface side of the cladding layer CLD with which the tensile stress film 11 is in contact. As a result, as shown in FIG. 6, the front surface side of the cladding layer CLD and the core layer CRL contracts relative to the back surface side of the cladding layer CLD and the core layer CRL. Therefore, as shown in FIG. 6, stretch distortion occurs in the area AR <b> 2 on the back surface side of the cladding layer CLD and the core layer CRL. In this way, the tensile stress can be applied to the core layer CRL from the back side of the core layer CRL by the global stress resulting from the tensile stress film 11.

On the other hand, in the global stress caused by the tensile stress film 11, compressive strain is applied to the surface side of the core layer CRL. Therefore, the global strain alone cannot apply the tensile strain to the surface side of the core layer CRL. Therefore, in the first embodiment, as shown in FIG. 6, the compressive stress film 10 is interposed between the core layer CRL and the extension stress film 11 on the core layer CRL. As a result, the region AR1 on the surface side of the core layer CRL can be given tensile strain by the compressive stress film 10 in contact with the core layer CRL. That is, in the first embodiment, the compressive stress film 10 is interposed between the core layer CRL and the extension stress film 11, so that an extension strain can be applied to the surface side of the core layer CRL.

From the above, according to the first embodiment, as shown in FIG. 6, the tensile stress film 11 formed over the entire structure including the core layer CRL and the cladding layer CLD warps the entire structure. It is possible to generate an extension strain on the back side (region AR2) of the core layer CRL. Furthermore, according to the first embodiment, the compressive stress film 10 locally formed on the core layer CRL can give a tensile strain to the surface side (region AR1) of the core layer CRL. As a result, according to the first embodiment, since the extension strain can be applied from both the front surface side and the back surface side of the core layer CRL, the extension strain can be applied to the entire thick core layer CRL. . Therefore, according to the first embodiment, the entire germanium forming the core layer CRL is stretched and strained. As a result, the entire germanium can be directly functioned as a transition semiconductor. Luminous efficiency when using as a light emitting layer can be improved.

That is, the feature point of the basic idea in the first embodiment is that the global stress and the local stress are used together, and in particular, the tensile stress is applied to the core layer CRL from the back side of the core layer CRL by the global stress. In addition, it is possible to give an extension strain to the core layer CRL from the surface side of the core layer CRL by local stress. That is, with the single global stress and the single local stress, it is difficult to give an extension strain to the entire core layer CRL. On the other hand, according to the basic idea in the first embodiment that combines the global stress and the local stress, It can be said that the basic idea in the first embodiment is an excellent technical idea in that an extension strain can be applied to the entire core layer CRL.

FIG. 7A is a diagram schematically illustrating a configuration example in which both the global stress and the local stress are applied to the core layer which is the light emitting layer, and FIG. 7B visualizes the extension strain applied to the core layer. FIG. In FIG. 7A, for example, a clad layer CLD and a core layer CRL made of silicon are formed on the insulating film IF, and a core layer CRL made of germanium is formed so as to be sandwiched between the clad layers CLD. ing. At this time, since the refractive index of germanium constituting the core layer CRL is larger than the refractive index of silicon constituting the cladding layer CLD, the light propagating through the core layer CRL is confined in the core layer CRL. In this way, the core layer CRL that is an optical waveguide layer is configured. Then, as shown in FIG. 7A, an extensional stress film 11 is formed so as to cover the surface of the core layer CRL from the surface of the cladding layer CLD, and the local compressive stress film 10 is directly above the core layer CRL. Is formed. At this time, the compressive stress film 10 is a film that tends to stretch as a result of applying compressive stress to the film itself. On the other hand, the extension stress film 11 is a film to be compressed as a result of extension stress being applied to the film itself. Accordingly, the surface side of the core layer CRL that is in contact with the compressive stress film 10 is subjected to tensile strain due to local stress caused by the compressive stress film 10 and is formed from the cladding layer CLD to the surface side of the core layer CRL. Due to the global stress resulting from the stretch stress film 11, stretch strain is applied to the back side of the core layer CRL. That is, according to the configuration example shown in FIG. 7A, it is possible to apply an extension strain to the entire core layer CRL. Specifically, as shown in FIG. 7B, it can be seen that tensile strain is applied to the entire core layer CRL by applying tensile strain from both the front and back sides of the core layer CRL.

Next, the effect by the basic idea in this Embodiment 1 is demonstrated. First, FIG. 8 is a diagram illustrating a mode gain in a configuration example in which the compressive stress film 10 is locally formed immediately above the core layer CRL. In FIG. 8, the mode gain (G _mod (x, z)) is an index indicating the light emission efficiency, and means that the light emission efficiency increases as the mode gain increases. As shown in FIG. 8, the mode gain is the product of the light intensity distribution (Γ (x, z)) and the material gain (g _mat (ε (x, z))) in the core layer CRL. It can be obtained by integrating with.

At this time, the material gain is a function of the extension strain (function of ε) applied to the core layer CRL. For example, the greater the extension strain, the greater the material gain. Therefore, in order to increase the mode gain, it is necessary to increase the material gain. For example, the material gain of germanium to which normal stretch strain is not applied is smaller than that of the compound semiconductor.

Therefore, in order to increase the material gain of the core layer CRL made of germanium, it is effective to increase the tensile strain applied to the core layer CRL. In other words, it is important to increase the material gain by applying a tensile strain to the germanium constituting the core layer CRL and causing it to function directly as a transition semiconductor.

In this regard, in the configuration example shown in FIG. 8, stretch distortion is applied only to a partial area (area with dots) on the surface side of the core layer CRL. Therefore, in the configuration example shown in FIG. 8, a portion with a small light intensity (region with dots) in the light intensity distribution, and a portion with a large expansion strain (dots) in the material gain corresponding to this portion. Only the product of the region marked with) contributes to the mode gain. That is, in the configuration example shown in FIG. 8, the mode gain does not increase due to the fact that only a part of the surface side of the core layer CRL is subjected to an extensional strain. In other words, it is difficult to improve the light emission efficiency in the configuration example shown in FIG. That is, in the configuration example shown in FIG. 8, the product of the light intensity and the material gain cannot be increased because it is not possible to give an extension strain to the central portion of the core layer CRL where the light intensity is high.

On the other hand, FIG. 9 is a diagram for explaining the mode gain in the configuration example for realizing the basic idea in the first embodiment. In FIG. 9, in the basic idea in the first embodiment, the compressive stress film 10 is locally provided immediately above the core layer CRL, and the compressive stress film 10 is provided on the surface side of the core layer CRL extending from the core layer CRL to the cladding layer. An extending stress film 11 is provided. As a result, in the configuration example shown in FIG. 9, the tensile strain caused by the compressive stress film 10 is applied to the core layer CRYL from the surface side of the core layer CRL, and the tensile stress film is applied to the core layer CRL from the back surface side of the core layer CRL. 11 is added to the stretching strain. As a result, in the configuration example that embodies the basic idea in the first embodiment shown in FIG. 9, an expansion strain is applied to the entire core layer CRL (dots are attached). Therefore, in the configuration example in which the basic idea in the first embodiment shown in FIG. 9 is realized, the material gain (corresponding to the tensile strain) is increased in the entire core layer CRL by adding the tensile strain to the entire core layer CRL. This makes it possible to increase the contribution to the mode gain from the portion of the light intensity distribution where the light intensity is high. That is, in the configuration example in which the basic idea in the first embodiment shown in FIG. 9 is realized, a tensile strain can be applied to the entire core layer CRL, so that the product of the light intensity contributing to the mode gain and the material gain is increased. It can be done. Thereby, in the configuration example that realizes the basic idea in the first embodiment shown in FIG. 9, the mode gain can be significantly increased. This means that in the configuration example that realizes the basic idea in the first embodiment shown in FIG. 9, the light emission efficiency in the core layer CRL that functions as the light emitting layer can be improved. In spite of the use of germanium, it is possible to obtain an excellent effect that light emission efficiency at the level of a direct transition semiconductor can be realized.

<Configuration of a semiconductor device that embodies the basic idea>
Next, the configuration of the semiconductor device that embodies the basic idea of the first embodiment will be described with reference to the drawings. Specifically, in the first embodiment, the structure of a semiconductor device including an optical waveguide that functions as a light emitting layer will be described.

FIG. 10A is a diagram showing a planar configuration of the semiconductor device according to the first embodiment. As shown in FIG. 10A, the semiconductor device according to the first embodiment includes, for example, an n-type germanium layer 20a, a p-type germanium layer 20b, an n-type silicon layer 30a, and a p-type silicon layer 30b. Have. At this time, the n-type germanium layer 20a and the p-type germanium layer 20b are formed so as to be sandwiched between the n-type silicon layer 30a and the p-type silicon layer 30b. That is, the core layer CRL is formed by the n-type germanium layer 20a and the p-type germanium layer 20b, and each of the n-type silicon layer 30a and the p-type silicon layer 30b forms a cladding layer CLD. That is, the core layer CLD is formed so as to be sandwiched between the clad layers CLD. The compressive stress film 10 is formed on the core layer CRL including the n-type germanium layer 20a and the p-type germanium layer 20b, and further includes the compressive stress film 10 in a plan view. An extensional stress film 11 is formed so as to cover 10. A plurality of holes HL are formed in each of the n-type silicon layer 30a and the p-type silicon layer 30b functioning as the cladding layer CLD.

FIG. 10B is a cross-sectional view taken along the line AA in FIG. In FIG. 10B, the microbridge structure MBS is formed above the SOI substrate composed of the substrate layer 1a, the insulating layer 1b, and the silicon layer 1c via the gap SP. Specifically, as shown in FIG. 10B, an insulating film IF is formed on the silicon layer 1c of the SOI substrate, and a hole HL is formed so as to penetrate the insulating film IF and the silicon layer 1c. ing. A protective film PF is formed on the inner wall of the hole HL. In the SOI substrate, a gap SP connected to the hole HL is formed in the insulating layer 1b, and the microbridge structure MBS is formed above the gap SP. Although not shown in FIG. 10B, the insulating layer 1b and the silicon layer 1c of the SOI substrate remain so as to surround the gap SP in a plan view, and the microbridge structure MBS is formed on the SOI substrate by this remaining portion. It is supported by.

In the microbridge structure MBS, an insulating film IF is formed on the silicon layer 1c, and a core layer CRL and a cladding layer CLD are formed on the insulating film IF. At this time, the core layer CRL is disposed so as to be sandwiched between the clad layers CLD. In the first embodiment, the core layer CRL is, for example, an indirect transition semiconductor when no extension strain is applied, and is composed of a semiconductor layer that functions as a direct transition semiconductor when the extension strain is applied. . As a specific example, the core layer CRL includes an n-type germanium layer 20a and a p-type germanium layer 20b. In FIG. 10B, the cladding layer CLD disposed on the left side of the core layer CRL is composed of an n-type silicon layer 30a, and the cladding layer CLD disposed on the right side of the core layer CRL is a p-type. It is composed of a silicon layer 30b. Further, an insulating film IF1 is formed on the surface of the p-type silicon layer 30b. As shown in FIG. 10 (b), the compressive stress film 10 is formed on the surface side (first surface side) of the core layer CRL, and the core is formed so as to cover the compressive stress film in plan view. An extension stress film 11 is formed over the entire surface side of the layer CRL and the cladding layer CLD. From this, the microbridge structure MBS in the first embodiment includes the core layer CRL that is an optical waveguide functioning as a light emitting layer, the compressive stress film 10 formed on the surface of the core layer CRL, and a plan view. The tensile stress film 11 is formed on the surface side of the core layer CRL so as to include the compressive stress film 10 and to cover the compressive stress film 10. According to the microbridge structure MBS configured as described above, the core layer CRL, which is a semiconductor layer having a front surface and a back surface opposite to the front surface, and a compressive stress that gives a tensile strain to the front surface side of the core layer CRL. A configuration including the film 10 and the extension stress film 11 that applies extension strain to the back surface side of the core layer CRL is realized. This point will be described below.

First, as shown in FIG. 10B, in the microbridge structure MBS in the first embodiment, the compressive stress film 10 is formed so as to be in direct contact with the surface of the core layer CRL. Here, the compressive stress film 10 is a film in which a compressive stress is applied to the film itself. As a reaction, the compressive stress film 10 tends to expand. Accordingly, an extension strain is applied to the surface side of the core layer CRL that is in contact with the compressive stress film 10. That is, according to the microbridge structure MBS in the present first embodiment, the surface layer of the core layer CRL is stretched by the local stress caused by the compressive stress film 10 formed on the surface of the core layer CRL. be able to. For example, the width in the x direction of the core layer CRL is, for example, about 3 μm, and the width in the x direction of the compressive stress film 10 formed on the surface of the core layer CRL is also about 3 μm.

In the first embodiment, for example, as shown in FIG. 10B, the compressive stress film 10 is formed so as to be in direct contact with the surface of the core layer CRL. The idea is not limited to this configuration, and an intermediate layer may be interposed between the core layer CRL and the compressive stress film 10. For example, from the viewpoint of increasing the tensile strain applied to the surface side of the core layer CRL, it is desirable to form the compressive stress film 10 so as to be in direct contact with the surface of the core layer CRL. On the other hand, from the viewpoint of adding a function of protecting the core layer CRL, a protective film made of a GeO film or a GeO ₂ film can be used as an intermediate layer and interposed between the core layer CRL and the compressive stress film 10. At this time, the thickness of the protective film can be, for example, 100 nm or less.

As shown in FIG. 10B, the core layer CRL is composed of an n-type germanium layer 20a and a p-type germanium layer 20b, and both the n-type germanium layer 20a and the p-type germanium layer 20b are compressed. Covered with a membrane 10. Therefore, in the first embodiment, the pn junction portion between the n-type germanium layer 20a and the p-type germanium layer 20b is necessarily covered with the compressive stress film 10. Thereby, the light emission efficiency of the core layer CRL which is a light emitting layer can be improved. This is because a depletion layer is formed at the pn junction between the n-type germanium layer 20a and the p-type germanium layer 20b, and electrons are supplied to the depletion layer from the n-type germanium layer 20a and positive from the p-type germanium layer 20b. This is because, as a result of supplying the holes, light emission mainly occurs due to the combination of electrons and holes in the depletion layer. In other words, by applying a tensile strain, the light emission efficiency can be improved by making the band structure in the depletion layer in which light emission occurs directly a band structure of a transition semiconductor.

Furthermore, the fact that the n-type germanium layer 20a is covered with the compressive stress film 10 together with the pn junction portion between the n-type germanium layer 20a and the p-type germanium layer 20b also contributes to improving the light emission efficiency. That is, for example, in a germanium laser using the core layer CRL as a light emitting layer, the n-type germanium layer 20a is used as an optical gain medium.

Subsequently, as shown in FIG. 10B, in the microbridge structure MBS in the first embodiment, the core layer includes the compressive stress film 10 and covers the compressive stress film 10 in plan view. An extensional stress film 11 is formed over the surface side of the CRL and the surface side of the cladding layer CLD. Here, the extension stress film 11 is a film in which extension stress is applied to the film itself. As a reaction, the extension stress film 11 attempts to compress. Therefore, compressive strain is applied to the surface side of the core layer CRL and the surface side of the cladding layer CLD that are in contact with the tensile stress film 11. This means that the front surface side of the core layer CRL shrinks relatively than the back surface side of the core layer CRL, whereby the microbridge structure MBS warps in a downwardly convex shape. As a result, an extension strain is applied to the back side of the core layer CRL. That is, according to the microbridge structure MBS in the first embodiment, the microbridge structure is caused by the global stress caused by the tensile stress film 11 formed from the surface side of the core layer CRL to the surface side of the cladding layer CLD. A downwardly convex warp occurs in the MBS, and as a result, an extension strain can be applied to the back surface side of the core layer CRL.

For example, in FIG. 10B, the total thickness of the silicon layer 1c, the insulating film IF, and the core layer CRL of the microbridge structure MBS is about 5 μm or less and is formed in the microbridge structure MBS. The thickness of the tensile stress film 11 is about 3 μm or less. In particular, from the viewpoint of giving a large tensile strain to the back surface side of the core layer CRL by generating a downward convex warp with respect to the microbridge structure MBS, the thickness of the microbridge structure MBS is reduced, and It is desirable to increase the thickness of the tensile stress film 11. In FIG. 10B, from the viewpoint of ensuring the mechanical strength of the SOI substrate, for example, the gap SP can be filled with an insulating material.

In the first embodiment, it is possible to give a convex warp only to the microbridge structure MBS without giving a convex warp downward to the entire SOI substrate. This is because, as shown in FIG. 10B, the microbridge structure MBS according to the first embodiment is arranged above the SOI substrate via the gap SP. As a result, according to the first embodiment, the microbridge structure MBS can be warped downward to generate a tensile warp on the back side of the core layer CRL, while the entire SOI substrate is flat. Therefore, the SOI substrate can be damaged and the yield in the assembly process can be improved.

From the above, according to the first embodiment, the core layer CRL, which is a semiconductor layer having a front surface and a back surface opposite to the front surface, and the compressive stress film 10 that applies tensile strain to the front surface side of the core layer CRL. And a microbridge structure MBS including the tensile stress film 11 that applies tensile strain to the back surface side of the core layer CRL. That is, according to the microbridge structure MBS in the first embodiment, the surface side of the core layer CRL that is in contact with the compressive stress film 10 is subjected to tensile strain due to local stress caused by the compressive stress film 10, and A tensile stress is applied to the back side of the core layer CRL by the global stress caused by the tensile stress film 11 formed from the cladding layer CLD to the surface side of the core layer CRL. As a result, according to the microbridge structure MBS in the first embodiment, the tensile strain is applied to the entire core layer CRL by applying the tensile strain from both the front side and the back side of the core layer CRL. Thus, it can be seen that the basic idea of the first embodiment is embodied.

Next, a typical material configuration will be described. In FIG. 10B, attention is paid to the x direction. In the x direction, the core layer CRL is sandwiched between the cladding layers CLD. The core layer CRL is composed of an n-type germanium layer 20a and a p-type germanium layer 20b, and the cladding layer CLD is composed of an n-type silicon layer 30a and a p-type silicon layer 30b. Therefore, considering that the refractive index of germanium is higher than the refractive index of silicon, the light generated in the core layer CRL is confined by the cladding layer CLD. On the other hand, focusing on the z direction, the core layer CRL is sandwiched between the compressive stress film 10 and the insulating film IF. Here, considering that the compressive stress film 10 is formed of, for example, a silicon oxide film or a silicon nitride film, and the insulating film IF is also formed of a silicon oxide film or the like, the refractive index of the compressive stress film 10 or the insulating film The refractive index of IF is smaller than the refractive index of the core layer CRL. Therefore, the light generated in the core layer CRL is confined also in the z direction. As described above, in the first embodiment, the light generated in the core layer CRL is confined in both the x direction and the z direction. As a result, the light generated in the core layer CRL extends in the y direction. It propagates in the existing core layer CRL. That is, the core layer CRL functions as an optical waveguide.

As described above, the compressive stress film 10 is made of, for example, a silicon oxide film or a silicon nitride film. On the other hand, the tensile stress film 11 is made of, for example, an aluminum nitride film or a silicon nitride film. Here, it may be questioned that the silicon nitride film is used as the compressive stress film 10 and also as the extension stress film 11, but the silicon nitride film depends on the composition. 10 or the tensile stress film 11. Specifically, the silicon nitride film becomes the compressive stress film 10 or the tensile stress film 11 depending on the bond density between nitrogen and hydrogen in the silicon nitride film. It may seem that the silicon nitride film is composed only of silicon and nitrogen. However, in the actual manufacturing process of the silicon nitride film, since hydrogen is mixed, hydrogen is mixed in the silicon nitride film. There is a bond of nitrogen and hydrogen. Qualitatively speaking, when the bond density of nitrogen and hydrogen in the silicon nitride film is low, the silicon nitride film becomes a compressive stress film. On the other hand, when the bond density of nitrogen and hydrogen in the silicon nitride film increases, the silicon nitride film becomes an extensional stress film. Therefore, by changing the film formation conditions of the silicon nitride film, for example, a silicon nitride film having a low bond density of nitrogen and hydrogen can be used as the compressive stress film 10, and nitrogen and hydrogen can be used as the extension stress film 11. A silicon nitride film having a high hydrogen bond density can be used. That is, when a silicon nitride film is used for both the compressive stress film 10 and the tensile stress film 11, the composition of the silicon nitride film used for the compressive stress film 10 and the tensile stress film 11 are used. This is different from the composition of the silicon nitride film. Specifically, the bond density of nitrogen and hydrogen of the silicon nitride film used for the tensile stress film 11 is larger than the bond density of nitrogen and hydrogen of the silicon nitride film used for the compressive stress film 10. it can.

<Method for Manufacturing Semiconductor Device>
The semiconductor device according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

First, as shown in FIG. 11, an SOI (Silicon On On Insulator) substrate including a substrate layer 1a, an insulating layer (buried insulating layer) 1b, and a silicon layer (SOI layer) 1c is prepared. In the SOI substrate, for example, the thickness of the insulating layer 1b is about 1 μm, and the thickness of the silicon layer 1c made of single crystal silicon is about 50 nm.

Next, after the SOI substrate is cleaned, an insulating film IF made of a silicon oxide film is formed by using, for example, a thermal oxidation method. However, the insulating film IF is not limited to this. For example, a silicon oxide film or a silicon nitride film formed by using a CVD (Chemical Vapor Deposition) method can also be used. Then, the opening OP1 is formed in the insulating film IF by using a photolithography technique and an etching technique. The opening OP1 is formed to expose a part of the silicon layer 1c. This is because in order to grow the germanium layer, the silicon layer 1c serving as the nucleus of growth is necessary. Specifically, the opening OP1 can be formed by the following process. That is, after a resist film is applied to the surface of the insulating film IF, the resist film is patterned by a photolithography technique (exposure and development). Thereby, the silicon layer 1c can be partially exposed from the opening OP1.

Subsequently, as shown in FIG. 12, a seed film (not shown) made of germanium is selectively formed on the silicon layer 1c exposed from the opening OP1, and then this seed film is used as a nucleus of crystal growth. Then, the n-type germanium layer 20a is formed over the insulating film IF from the inside of the opening OP1. For example, the seed film has many defects due to lattice mismatch between silicon and germanium, but the defect density of defects is reduced because the interface between silicon and germanium does not exist on the insulating film IF. . Note that an n-type impurity serving as a light emitting medium is introduced into the n-type germanium layer 20a. Furthermore, as shown in FIG. 12, by forming the p-type germanium layer 20b and the p-type silicon layer 30b, a junction structure (n-Ge / p-Ge / p-Si) that becomes a part of the pn diode is formed. The At this time, for example, the thickness in the z direction of the silicon layer 1c and the junction structure is about 5 μm. Then, for example, by using a chemical mechanical polishing method (CMP method: ChemicalCMechanical） Polishing), the n-type germanium layer 20a, the p-type germanium layer 20b, and the p-type silicon layer 30b formed on the insulating film IF Flatten the surface. As a result, the thickness in the z direction of the connection structure formed on the insulating film IF is, for example, about 500 nm. In the following process, the subsequent manufacturing process will be described focusing on the area AR surrounded by the dotted line in FIG.

As shown in FIG. 13, a part of the p-type silicon layer 30b is etched by using a photolithography technique and an etching technique. Thereafter, as shown in FIG. 14, an insulating film IF1 is formed on a part of the etched p-type silicon layer 30b, and the insulating film IF2 extending over the insulating film IF1 and on the p-type germanium layer 20b and the n-type germanium layer 20a. Form. At this time, the width in the x direction of a part of the p-type germanium layer 20b and the n-type germanium layer 20a covered with the insulating film IF2 is, for example, about 2 μm to satisfy the single mode condition of the optical waveguide.

Next, as shown in FIG. 15, the n-type germanium layer 20a exposed from the insulating film IF2 is removed by an etching technique using the insulating film IF2 as a mask. Thereafter, as shown in FIG. 16, an n-type silicon layer 30a is formed in the removed n-type germanium layer 20a. As a result, an n-Si / n-Ge junction structure is formed. As described above, an n-Si / n-Ge / p-Ge / p-Si junction structure can be formed on the insulating film IF in the x direction. Here, since germanium has a higher refractive index than silicon, a germanium region (n-type germanium layer 20a + p-type germanium) sandwiched between silicon regions (n-type silicon layer 30a and p-type silicon layer 30b) with respect to the x direction. A structure in which light is confined in the layer 20b) is realized. That is, the n-type germanium layer 20a and the p-type germanium layer 20b function as a core layer, and the n-type silicon layer 30a and the p-type silicon layer 30b function as a cladding layer.

Subsequently, a multilayer structure of stress films is formed in order to give a tensile strain to the core layer composed of the n-type germanium layer 20a and the p-type germanium layer 20b. Specifically, as shown in FIG. 17, after removing the insulating film IF2, the compressive stress film 10 having an internal stress of about 1 GPa and a film thickness of about 200 nm is formed by using, for example, a CVD method. After the film formation, the compressive stress film 10 having a width in the x direction of about 3 μm, for example, is left on the n-type germanium layer 20a and the p-type germanium layer 20b. As a result, tensile strain is applied to the n-type germanium layer 20a and the p-type germanium layer 20b formed immediately below the compressive stress film 10.

Next, as shown in FIG. 18, the tensile stress film 11 having an internal stress of about 0.5 GPa and a film thickness of about 1 μm is larger than the compressive stress film 10 so as to include the compressive stress film 10. Form over the area. Thereafter, although not shown, a metal electrode is connected to each of the n-type silicon layer 30a and the p-type silicon layer 30b to form a structure for injecting a current into the pn diode. Note that the compressive stress film 10 can be formed by leaving portions of the insulating film IF2 shown in FIG. 16 formed on the n-type germanium layer 20a and the p-type germanium layer 20b. In this case, since the process of newly forming the compressive stress film 10 can be omitted, the manufacturing process can be simplified.

After that, as shown in FIG. 19, by using a photolithography technique and an etching technique, a hole HL that penetrates the n-type silicon layer 30a, the insulating film IF, and the silicon layer 1c and reaches the insulating layer 1b, and the insulating film A hole HL that penetrates through IF1, the p-type silicon layer 30b, the insulating film IF, and the silicon layer 1c to reach the insulating layer 1b is formed.

Then, as shown in FIG. 20, after forming a protective film PF resistant to hydrofluoric acid on the inner wall of the hole HL, for example, by using hydrofluoric acid, the silicon oxide film is formed through the hole HL. The insulating layer 1b is removed. As a result, as shown in FIG. 10B, the microbridge structure MBS can be formed above the SOI substrate via the gap SP. At this time, the tensile stress film 11 causes the microbridge structure MBS to warp downward. As a result, tensile strain is applied to the back side of the core layer CRL shown in FIG. On the other hand, due to the compressive stress film 10, an extension strain is also applied to the surface side of the core layer CRL. Therefore, according to the semiconductor device in the first embodiment, the tensile strain is applied from both the front surface side and the back surface side of the core layer CRL, and the entire core layer CRL is subjected to the tensile strain. As described above, the semiconductor device according to the first embodiment can be manufactured.

In FIG. 10B, the gap SP for floating the microbridge structure MBS from the SOI substrate may be filled with an insulating material (inorganic insulating film or organic resin film), for example. In this case, the mechanical strength can be improved. However, it is a condition that the material has a low coefficient of thermal expansion and low viscosity so that no upward warping occurs in the microbridge structure MBS.

(Embodiment 2)
<Configuration of a semiconductor device that embodies the basic idea>
FIG. 21 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. As shown in FIG. 21, the semiconductor device according to the second embodiment has an SOI substrate including a substrate layer 1a, an insulating layer 1b, and a silicon layer 1c. An insulating film IF is formed on the silicon layer 1c of the SOI substrate, and a core layer CRL and a cladding layer CLD sandwiching the core layer CRL are formed on the insulating film IF. The core layer CRL is composed of an n-type germanium layer 20a and a p-type germanium layer 20b. The cladding layer CLD provided on the left side of the core layer CRL is composed of the n-type silicon layer 30a, while the cladding layer CLD provided on the right side of the core layer CRL is composed of the p-type silicon layer 30b. It is configured. An insulating film IF1 is formed on a portion of the surface of the cladding layer CLD made of the p-type silicon layer 30b. Further, also in the second embodiment, the compressive stress film 10 is formed so as to be in direct contact with the surface of the core layer CRL. The compressive stress film 10 is made of, for example, a silicon oxide film or a silicon nitride film. Here, the compressive stress film 10 is a film in which a compressive stress is applied to the film itself. As a reaction, the compressive stress film 10 tends to expand. Accordingly, an extension strain is applied to the surface side of the core layer CRL that is in contact with the compressive stress film 10. That is, also in the semiconductor device according to the second embodiment, it is possible to give a tensile strain to the surface side of the core layer CRL by local stress caused by the compressive stress film 10 formed on the surface side of the core layer CRL.

Subsequently, as shown in FIG. 21, an insulating film IF3 is partially formed on the back surface of the SOI substrate. The back surface of the SOI substrate exposed from the insulating film IF3 penetrates the SOI substrate to pass through the insulating film. A groove DIT reaching IF is formed. As a result, a thin portion is formed above the groove DIT, and the core layer CRL is formed in the thin portion. A compressive stress film 12 is formed so as to be in contact with the insulating film IF exposed from the trench DIT. The compressive stress film 12 is also composed of, for example, a silicon oxide film or a silicon nitride film. In particular, in the second embodiment, the size of the compressive stress film 12 is larger than the size of the compressive stress film 10 as shown in FIG. Therefore, the tensile strain applied to the back side of the thin portion by the compressive stress film 12 is larger than the tensile strain applied to the front surface side of the thin portion by the compressive stress film 10. As a result, according to the second embodiment, the back surface side of the thin portion extends more than the front surface side, so that a downwardly convex warp occurs in the thin portion. As a result, a tensile stress is applied to the back surface side of the core layer CRL due to the global stress caused by the downwardly convex warp generated in the thin portion. As a result, according to the semiconductor device in the second embodiment, the tensile strain is applied to the entire core layer CRL by applying the tensile strain from both the front side and the back side of the core layer CRL. It can be seen that the idea is embodied.

From the above, according to the second embodiment, the thin portion, the core layer CRL formed on the thin portion, the compressive stress film 10 formed on the surface of the core layer CRL, and the surface of the thin portion Among them, a structure having a compressive stress film 12 formed on the back surface provided on the back surface side of the core layer CRL and a size of the compressive stress film 12 larger than the size of the compressive stress film 10 is realized. In other words, in the second embodiment, a core layer CRL formed of a semiconductor layer formed in a thin portion and having a front surface and a back surface, and a small-sized silicon oxide film formed on the surface of the core layer CRL or A structure having a silicon nitride film and a large-sized silicon oxide film or silicon nitride film formed on the back side of the core layer CRL is realized. That is, according to the semiconductor device in the present second embodiment, the surface side of the core layer CRL that is in contact with the small-sized compressive stress film 10 is subjected to tensile strain due to local stress caused by the compressive stress film 10, and A tensile stress is applied to the back surface side of the core layer CRL by the global stress caused by the convex warpage below the thin portion formed by the large compressive stress film 12 formed on the bottom surface of the groove DIT. As a result, according to the semiconductor device in the present second embodiment, the tensile strain is applied from both the front surface side and the back surface side of the core layer CRL, and the entire core layer CRL is subjected to the tensile strain. Thus, the light emission efficiency in the core layer CRL functioning as the light emitting layer can be improved.

<Method for Manufacturing Semiconductor Device>
The semiconductor device according to the second embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

First, the structure shown in FIG. 22 is formed through the same steps as those in the first embodiment shown in FIGS. Next, as shown in FIG. 23, an insulating film IF3 is formed on the back surface of the substrate layer 1a. The insulating film IF3 is formed of, for example, a silicon oxide film, and can be formed by using, for example, a CVD method.

Subsequently, as shown in FIG. 24, by using a photolithography technique and an etching technique, the insulating film IF3 is patterned to form an opening OP2 in the insulating film IF3. Thereafter, as shown in FIG. 25, the substrate layer 1a exposed from the opening OP2 is etched using the patterned insulating film IF3 as a mask. This etching can be, for example, wet etching using TMAH (Tetra Methyl Ammonium Hydroxide). This TMAH is an anisotropic etching solution in which the (111) plane of silicon appears. For this reason, the size of the bottom surface of the trench DIT is smaller than the size of the opening OP2 formed in the insulating film IF3. Therefore, it is necessary to make the size of the opening OP2 larger than the size of the thin portion, for example, about 70 μm larger than the size of the thin portion to be formed. In this way, after etching the substrate layer 1a, the exposed insulating layer 1b is etched, and further, the exposed silicon layer 1c is etched by etching the insulating layer 1b. As a result, as shown in FIG. 25, a trench DIT that penetrates the SOI substrate and reaches the insulating layer IF can be formed. As a result, a thin portion can be formed above the trench DIT.

Next, as shown in FIG. 21, a compressive stress film 12 that contacts the insulating film IF exposed from the bottom surface of the trench DIT is formed. The compressive stress film 12 is formed of, for example, a silicon oxide film or a silicon nitride film, and can be formed by using, for example, a CVD method.

At this time, the compressive stress film 12 is formed so that the size of the compressive stress film 12 is larger than the size of the compressive stress film 10 as shown in FIG. As a result, the tensile strain applied to the back side of the thin portion by the compressive stress film 12 is larger than the tensile strain applied to the front surface side of the thin portion by the compressive stress film 10. Therefore, since the back surface side of the thin wall portion extends more than the front surface side, the thin wall portion is warped downward. As a result, a tensile stress is applied to the back surface side of the core layer CRL due to the global stress caused by the downwardly convex warp generated in the thin portion. As a result, according to the semiconductor device in the second embodiment, the tensile strain can be applied from both the front surface side and the back surface side of the core layer CRL, and the entire core layer CRL can be applied with the tensile strain.

Note that the internal stress and optical characteristics of the silicon nitride film vary greatly depending on the bond density and distribution state between the elements in the film. Therefore, in the second embodiment, the silicon nitride film functioning as a compressive stress film is formed by adjusting the film formation temperature and the supply amount of the material gas. For example, when the bond density of nitrogen and hydrogen (NH bond) in the silicon nitride film is low, the silicon nitride film becomes a compressive stress film, while the bond between nitrogen and hydrogen (NH bond) in the silicon nitride film When the density is high, the silicon nitride film becomes a tensile stress film. Therefore, since the silicon nitride film used in Embodiment 2 needs to be a compressive stress film, by adjusting the film forming conditions, nitrogen and hydrogen (N—H) A silicon nitride film having a low bond density is formed as the compressive stress film 10 or the compressive stress film 12.

As described above, the semiconductor device according to the second embodiment can be manufactured.

(Embodiment 3)
In the first embodiment, an example in which the basic idea of the present invention is applied to a light emitting element has been described. In the third embodiment, an example in which the basic idea of the present invention is applied to a light receiving element will be described. That is, in the first embodiment, the configuration example of the core layer functioning as the light emitting layer has been described. In the third embodiment, the configuration example of the core layer functioning as the light receiving layer (light absorption layer) will be described. Since the configuration of the semiconductor device in the first embodiment and the configuration of the semiconductor device in the third embodiment are substantially the same, the description will focus on the differences.

FIG. 26A shows a planar configuration of the semiconductor device according to the third embodiment. In FIG. 26A, the core layer CRL that functions as a light absorption layer (light receiving layer) is composed of a germanium layer 20 that is an intrinsic semiconductor layer, and the core layer CRL is composed of, for example, an amorphous silicon layer 21. Connected to the optical waveguide. At this time, by adding a diffraction grating or a mode converter to the optical waveguide, the core layer CRL functioning as a light receiving portion of the light receiving element (semiconductor device) in the third embodiment is optically connected to another optical circuit. can do.

FIG. 26 (b) is a cross-sectional view taken along line AA in FIG. 26 (a). As shown in FIG. 26B, the core layer CRL made of the germanium layer 20 is surrounded by the clad layer CLD made of the n-type silicon layer 30a and the clad layer CLD made of the p-type silicon layer 30b. Also in the third embodiment, as in the first embodiment, the core layer CRL, which is an intrinsic semiconductor layer having a front surface and a back surface opposite to the front surface, and a tensile strain on the front surface side of the core layer CRL. A micro-bridge structure MBS is realized that includes a compressive stress film 10 that imparts a tensile stress and a tensile stress film 11 that imparts a tensile strain to the back side of the core layer CRL. That is, also in the third embodiment, the surface side of the core layer CRL in contact with the compressive stress film 10 is subjected to tensile strain due to local stress caused by the compressive stress film 10, and from the clad layer CLD to the core layer CRL. Due to the global stress caused by the tensile stress film 11 formed over the front surface side, the tensile strain is applied to the back surface side of the core layer CRL. As a result, also in the third embodiment, the tensile strain is applied from both the front surface side and the back surface side of the core layer CRL so that the entire core layer CRL is stretched. Is embodied.

Here, in the third embodiment, the core layer CRL functions as a light absorption layer. In the third embodiment, the core layer CRL is formed from the germanium layer 20 that is an intrinsic semiconductor layer, and the entire core layer CRL is stretched to improve the light absorption efficiency in the core layer CRL. Can do. This point will be described below.

First, when the core layer CRL is composed of the germanium layer 20 which is an intrinsic semiconductor layer, the core layer CRL is formed in the core layer CRL sandwiched between the clad layer CLD made of the n-type silicon layer 30a and the clad layer made of the p-type silicon layer 30b. The depletion layer becomes larger. For this reason, the fact that light is absorbed in the core layer CRL means that light is absorbed in the depletion layer. Then, when light is absorbed in the depletion layer, electrons are excited from the valence band to the conduction band. This means that holes are generated in the valence band and electrons transition to the conduction band. At this time, when light is absorbed in the depletion layer and hole / electron pairs are generated, electrons excited in the conduction band are accelerated toward the n-type silicon layer 30a by the electric field in the depletion layer. The holes generated in the valence band are accelerated toward the p-type silicon layer 30b. Therefore, since electrons and holes move in opposite directions, the probability of recombination of electrons and holes decreases. This means that when light is absorbed in the depletion layer, recombination of electrons and holes is less likely to occur, thereby increasing light absorption efficiency. That is, in the third embodiment, the light absorption efficiency in the core layer CRL can be improved by configuring the core layer CRL functioning as the light absorption layer from the germanium layer 20 which is an intrinsic semiconductor layer.

Further, in the present third embodiment, as shown in FIG. 26B, the surface side of the core layer CRL is subjected to tensile strain due to local stress caused by the compressive stress film 10, and from the cladding layer CLD to the core layer. A tensile stress is applied to the back surface side of the core layer CRL by the global stress caused by the tensile stress film 11 formed over the surface side of the CRL. As a result, also in the third embodiment, the tensile strain is applied from both the front surface side and the back surface side of the core layer CRL, and the entire core layer CRL is subjected to the tensile strain. This means that the band gap of the germanium layer 20 constituting the core layer CRL is reduced over the entire core layer CRL. Then, considering that the energy for exciting electrons from the valence band to the conduction band decreases as the band gap decreases, even the light having a longer wavelength is absorbed by the core layer CRL. This means that according to the third embodiment, the light absorption efficiency in the core layer CRL is improved.

From the above, according to the semiconductor device (light receiving element) in the present third embodiment, the core layer CRL is formed from the germanium layer 20 which is an intrinsic semiconductor layer, and the entire core layer CRL is subjected to tensile strain. By this synergistic effect, it is possible to obtain an excellent effect that the light absorption efficiency in the core layer CRL can be greatly improved.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

10 Compressive stress film 11 Tensile stress film AR1 region AR2 region CLD Clad layer CRL Core layer IF Insulating film

Claims (15)

1. An optical waveguide layer comprising a semiconductor layer having a first surface and a second surface opposite to the first surface;
   A first stress film for applying an extension strain to the first surface side of the optical waveguide layer;
   A second stress film for applying an extension strain to the second surface side of the optical waveguide layer;
   A semiconductor device comprising:
2. The semiconductor device according to claim 1,
   The semiconductor device has a structure provided on a substrate via a gap,
   The structure is
   The optical waveguide layer;
   The first stress film comprising a compressive stress film formed on the first surface of the optical waveguide layer;
   In plan view, the second stress film including the first stress film and made of an extensional stress film formed on the first surface side of the optical waveguide layer so as to cover the first stress film;
   A semiconductor device.
3. The semiconductor device according to claim 2,
   A semiconductor device in which an insulating film is embedded in the gap.
4. The semiconductor device according to claim 1,
   The semiconductor device includes:
   Thin part,
   The optical waveguide layer formed in the thin portion;
   The first stress film comprising a compressive stress film formed on the first surface of the optical waveguide layer;
   Of the surface of the thin portion, the second stress film made of a compressive stress film formed on the back surface provided on the second surface side of the optical waveguide layer;
   Have
   The size of the second stress film is a semiconductor device larger than the size of the first stress film.
5. The semiconductor device according to claim 1,
   The optical waveguide layer is an indirect transition semiconductor when the extension strain is not applied, and includes the semiconductor layer that functions as a direct transition semiconductor when the extension strain is applied.
6. The semiconductor device according to claim 1,
   The optical waveguide layer is a semiconductor device that functions as a light emitting layer.
7. The semiconductor device according to claim 6.
   The optical waveguide layer is a semiconductor device having an n-type semiconductor layer.
8. The semiconductor device according to claim 6.
   The optical waveguide layer is a semiconductor device including a junction between an n-type semiconductor layer and a p-type semiconductor layer.
9. The semiconductor device according to claim 1,
   The optical waveguide layer is a semiconductor device that functions as a light absorption layer.
10. The semiconductor device according to claim 1,
    The semiconductor device, wherein the first stress film is in direct contact with the optical waveguide layer.
11. The semiconductor device according to claim 1,
    A semiconductor device, wherein an intermediate layer is interposed between the optical waveguide layer and the first stress film.
12. The semiconductor device according to claim 1,
    The optical waveguide layer is a semiconductor device containing germanium.
13. An optical waveguide layer comprising a semiconductor layer having a first surface and a second surface opposite to the first surface;
    A first film provided on the first surface side of the optical waveguide layer;
    A second film provided on the first surface side of the optical waveguide layer so as to enclose the first film and cover the first film in plan view;
    With
    The first film includes a silicon oxide film or a first silicon nitride film,
    The second film includes an aluminum nitride film or a second silicon nitride film,
    The semiconductor device, wherein a bond density between nitrogen and hydrogen in the second silicon nitride film is larger than a bond density between nitrogen and hydrogen in the first silicon nitride film.
14. The semiconductor device according to claim 13,
    The semiconductor device has a structure provided on a substrate via a gap,
    The structure includes
    The optical waveguide layer;
    The first film;
    The second film;
    A semiconductor device in which is formed.
15. Thin part,
    An optical waveguide layer formed of a semiconductor layer formed in the thin portion and having a first surface and a second surface opposite to the first surface;
    A first film formed on the first surface of the optical waveguide layer;
    Of the surface of the thin portion, a second film formed on the back surface provided on the second surface side of the optical waveguide layer and having a size larger than the first film,
    With
    The first film includes a silicon nitride film that is a silicon oxide film or a compressive stress film,
    The second film includes a silicon oxide film or a silicon nitride film that is a compressive stress film.

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