WO2017052594A1

WO2017052594A1 - Semiconductor device wafer bonding integration techniques

Info

Publication number: WO2017052594A1
Application number: PCT/US2015/052253
Authority: WO
Inventors: Glenn A. Glass; Il-Seok Son; Anand S. Murthy; Paul B. Fischer
Original assignee: Intel Corporation
Priority date: 2015-09-25
Filing date: 2015-09-25
Publication date: 2017-03-30
Also published as: TW201724276A; TWI715614B

Abstract

Techniques are disclosed for semiconductor device wafer bonding integration. The wafer bonding integration employs device-quality embedded epitaxial layers (e.g., high-quality single-crystal semiconductor material layers) from which one or more devices (e.g., transistors) can be formed, enabling vertical 3D integration schemes. The integration techniques include the ability to produce transistors and back-end stacks on very thin substrates, where the substrate is of device-level quality. The techniques include forming a multilayer substrate including a bulk wafer, a sacrificial layer, and a device-quality layer from which one or more transistors are formed. After back-end processing, the transistors can be bonded to a host wafer that also includes transistors, such that the transistors are stacked in a vertical fashion. After the bonding process, the bulk wafer of the multilayer substrate can be removed from the transistor that was bonded, by at least partially removing the sacrificial layer of the multilayer substrate.

Description

SEMICONDUCTOR DEVICE WAFER BONDING INTEGRATION TECHNIQUES

BACKGROUND

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon, germanium, and gallium arsenide. A FinFET is a transistor built around a thin strip of semiconductor material (generally referred to as the fin). The transistor includes the standard field-effect transistor (FET) nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). A nanowire transistor (sometimes referred to as a gate-all-around or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used and the gate material generally surrounds each nanowire.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a method of forming an integrated circuit, in accordance with one or more embodiments of the present disclosure.

Figures 2A-C illustrate forming at least one transistor on a multilayer substrate including a bulk wafer, a sacrificial layer, and a device-quality layer, in accordance with some embodiments of the present disclosure.

Figure 3 illustrates the structure of Figure 2C being bonded to a host wafer including at least one transistor, in accordance with an embodiment of the present disclosure.

Figures 4-4' illustrate an integrated circuit structure including a first transistor vertically integrated over a second transistor, the first transistor formed on a multilayer substrate, in accordance with some embodiments of the present disclosure.

Figures 5A-B illustrate various resulting structures during removal of the bulk wafer layer of the multilayer substrate, in accordance with some embodiments of the present disclosure. Figure 6 illustrates an example structure after backside back-end processing is performed on the structure of Figure 5B, in accordance with an embodiment of the present disclosure.

Figure 7 illustrates an example structure after an additional level of transistors is bonded to the structure of Figure 6, in accordance with an embodiment of the present disclosure.

Figure 8 illustrates a computing system implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

Techniques are disclosed for semiconductor device wafer bonding integration. The wafer bonding integration employs device-quality embedded epitaxial layers (e.g., high-quality single- crystal semiconductor material layers) from which one or more devices (e.g., transistors) can be formed, enabling vertical 3D integration schemes. The integration techniques include the ability to produce transistors with metal-oxide-semiconductor (MOS) single-crystal channel regions of any suitable material, type, or configuration and back-end stacks on very thin substrates, where the substrate is of device-level quality for purposes of contamination, doping levels, defect levels, roughness, and wafer bow, for example. The techniques include forming a multilayer substrate including a bulk wafer, a sacrificial layer, and a device-quality layer from which one or more transistors are formed. After back-end processing, the transistors can be bonded to a host wafer that also includes transistors, such that the transistors are stacked in a vertical fashion. After the bonding process, the bulk wafer of the multilayer substrate can be removed from the transistor that was bonded, by at least partially removing the sacrificial layer of the multilayer substrate. In some instances, the sacrificial layer is an etch-stop layer and removal of the bulk wafer may include a backside grind followed by etch and/or polish processes. In some instances, the sacrificial layer is a fast-etch layer and removal of the bulk wafer may include a lateral etch of the fast-etch layer. The integration techniques can be repeated as desired to achieve as many transistor stack levels as desired. Numerous variations and configurations will be apparent in light of this disclosure.

General Overview

The microelectronics technology industry has maintained Moore's law for transistor scaling for over fifty years. As patterning and fundamental quantum limits of conventional scaling are approached, it makes sense to scale devices vertically with multiple layers of front- end devices sandwiched between layers of back-end interconnects. A subsequent layer of front- end effectively doubles the number of active transistors and maintains the progress toward higher functionality within a fixed die size. Also, a stacked device can provide the power of a dual core in the footprint of a single core. Repeating the process can give the processing power of a triple core in the footprint of a single core, and so on. However, enabling such vertical integration requires the ability to cleanly produce a transistor and back-end stack on a very thin substrate. Further, the substrate would have to be of device level quality from the standpoint of contamination, doping levels, point and line and bulk defect levels (e.g., to achieve single-crystal structures), roughness, and wafer bow, to name a few requirements. Moreover, lack of thickness uniformity of the stacked devices would cause non-trivial problems.

Thus, and in accordance with one or more embodiments of the present disclosure, techniques are disclosed for semiconductor device wafer bonding integration. In some embodiments, the techniques include forming a multilayered substrate including a bulk wafer (e.g., a bulk silicon or silicon on insulator (SOI) wafer), an etch-stop and/or fast-etch layer deposited on the wafer, and a device-quality layer deposited on the etch-stop or fast-etch layer. As will be apparent in light of the present disclosure, a buffer layer may be present between the etch-stop and fast-etch layers when both are present in the multilayered substrate. Standard front-end processing can then be performed on the multilayered substrate to form as many semiconductor devices (e.g., transistors) as desired using the device-quality layer. Standard back-end processing can then be performed to form the metal contacts and as many metal back- end layers as desired. The resulting fully integrated wafer can then be bonded to another wafer that is also fully integrated with one or more transistor devices (the other wafer is referred to herein as a host wafer). The bonding may occur by turning a fully integrated guest wafer upside down to invert it and then connecting the metal back-end and/or insulator material (e.g., oxide material) of the fully integrated guest wafer to the metal back-end and/or insulator material on the host wafer. Such bonding can be performed using heat, pressure, and/or force, in presence of a controlled environment such as a forming gas or ammonia while taking care to align and connect the respective features of both wafers, for example.

As will be apparent in light of the present disclosure, after the fully integrated guest wafer formed on the multilayer substrate is inverted and bonded to the host wafer, the integration techniques can be used to remove the bulk wafer (e.g., the majority of the multilayer substrate thickness that is not populated with active device elements) from the multilayer substrate. In embodiments including an etch-stop layer in the multilayer substrate, a backside grind can be performed to get close to the etch-stop layer and then a wet etch and/or polish process can be performed until the etch/polish is effectively stopped at the etch-stop layer. In some such embodiments, only the device-quality layer (including transistors formed therefrom) and possibly some of the etch-stop layer will remain on the guest wafer, thereby enabling 3D vertical scaling. In embodiments including a fast-etch layer in the multilayer substrate, a lateral wet etch can be performed to remove the fast-etch layer and allow for the release (liftoff) of the bulk wafer from the device-quality layer. In some such embodiments, only the device -quality layer (including transistors formed therefrom) and possibly some of the fast-etch layer will remain on the host wafer, significantly reducing the thickness of the guest wafer and thereby enabling 3D vertical scaling. In some embodiments, the multilayer substrate may include both a fast-etch and an etch-stop layer. In some such embodiments, the lateral etch can be performed to release the bulk wafer and then an etch and/or polish can be performed until the etch/polish is effectively stopped at the etch-stop layer.

Note that "device-quality" as used herein (e.g., device-quality layer or device-quality material) denotes high-quality single-crystal semiconductor material. The high-quality component may be representative of defect levels (e.g., less than 1E8 defects per square cm), contamination levels, dopant levels, roughness, and/or any other suitable property of the material, as will be apparent in light of the present disclosure. As will be apparent, vertically integrating levels of transistors above other levels of transistors on a host wafer cannot be achieved without using the integration techniques variously described herein. This is because the device-quality material from which one or more transistors are formed for additional vertical transistor levels needs to have a single-crystal structure of sufficiently high-quality from the standpoint of contamination, doping, defect, roughness, etc. Without having the crystal structure defined by a bulk wafer, such high-quality single-crystal material cannot be achieved and thus the device-quality layer for vertically integrated transistor levels would not be achievable. Therefore, the integration techniques include forming the additional level of transistors on a guest bulk wafer and including a sacrificial layer that allows that guest bulk wafer to eventually be removed after the level of transistors is bonded to a fully formed host wafer (e.g., a host wafer with a level of transistors formed thereon, including back-end processing, etc.). The integration techniques can be repeated as many times as desired to achieve as many vertical transistor levels as desired, depending on the end use or target application.

As will be apparent in light of the present disclosure, the integration techniques can be used with various different configurations, including numerous transistor geometries and materials. For instance, device-quality layer material may include various semiconductor materials, such as silicon (Si), germanium (Ge), SiGe, or at least one III-V material (e.g., indium gallium arsenide (InGaAs)), graphene, molybdenum disulfide (MoS₂), carbon nanotubes, or any other material that forms a three dimensional or a two dimensional crystal capable of forming a transistor. In embodiments where the device-quality layer includes Si, an example etch-stop material is carbon (C) doped Si (Si:C) with C doping content in the range of 1-30% and example fast-etch materials are SiGe and boron (B) doped SiGe (SiGe:B). In embodiments where the device-quality layer includes Ge or SiGe with greater than 80% Ge alloy content, example etch- stop materials are Ge or Ge:C with C doping content in the range of 1-30% and example fast- etch materials are germanium tin (GeSn) and B:GeSn. In embodiments where the device-quality layer includes SiGe with Ge alloy content in the range of 10-80%, an example etch-stop material is SiGe:C with C doping content in the range of 1-30% and an example fast-etch material is SiGe with approximately 10% or more higher Ge content than the SiGe device-quality layer (which may be boron doped). In embodiments where the device-quality layer includes the III-V material InGaAs, an example etch-stop material is indium phosphate (InP) and an example fast- etch material is gallium arsenide (GaAs). In all cases, practical limitations may exist on the combinations of materials and fast/slow etch layers in terms of sustainability to maintain high- quality single-crystal device quality over-layers, as will be apparent in light of the present disclosure.

Numerous benefits of the integration techniques variously described herein will be apparent in light of this disclosure. For example, the techniques provide the ability to cleanly produce a transistor and back-end stack on a very thin device-quality substrate, such as a substrate having a thickness of less than 500, 250, 100, or 50 nm, or some other suitable maximum thickness, depending on the end use or target application. As previously described, such a thin substrate would have to be of device level quality for integration purposes in areas such as contamination, doping levels, defect levels (e.g., point, line, and bulk defect levels), roughness, and wafer bow, just to name a few example areas. Use of the etch-stop and/or fast- etch layers in the integration techniques described herein provides built-in self-alignment capabilities such that every wafer can be made to the desired specifications, including the ability to achieve device level quality substrates and enable vertical scaling with multiple layers of front-end devices. The integration techniques variously described herein provide benefits over standard grinding and etching techniques currently used for integration, as such standard techniques do not include a built-in etch stop layer or fast etch layer, resulting in thickness uniformity problems that can affect performance and reliability. The integration techniques variously described herein demonstrate control over the thickness of the substrate of the stacked layer and also allow for very thin device-quality layers to be vertically stacked.

Upon analysis (e.g., using scanning/transmission electron microscopy (SEM/TEM), composition mapping, secondary ion mass spectrometry (SIMS), time-of-flight SIMS (ToF- SIMS), atom probe imaging, local electrode atom probe (LEAP) techniques, 3D tomography, high resolution physical or chemical analysis, etc.), an integrated circuit structure configured in accordance with one or more embodiments will effectively show stacked transistor devices on a single wafer as variously described herein. For example, in some embodiments, detection may be performed by detecting the 3D integration scheme variously described herein. In some cases, the etch-stop and/or fast-etch layers may be undetectable or absent from the final structure, as they are primarily used to assist with removal of the bulk wafer after bonding. However, any 3D integration scheme that has good control over the thickness of a stacked device-quality layer would have to employ an etch-stop and/or fast-etch layer as variously described herein. Good control over the thickness of the device-quality layer may be observed based on the material (e.g., functionally a transistor channel element) being a single-crystal material (e.g., as compared to surrounding amorphous and non-crystalline materials, such as the back-end metal and oxide materials), the nominal thickness of the layer (e.g., if the layer is less than 500, 250, 100, 50, or 25 nm, or some other suitable maximum amount), the amount of defects in the layer (e.g., if the layer has defects, such as grain boundaries or dislocations, on the order of less than 1E8 defects per square cm), and/or based on the flatness/surface roughness of the backside of the device- quality layer across the die and across the wafer. Further, as the integration techniques include bonding the tops of the transistor devices together (e.g., the metal lines and/or overlying oxide material), it can be understood that the transistor device formed on the host wafer will be formed in a standard orientation, while the bonded transistor device (from the guest wafer) will be stacked in a substantially inverted orientation above the first transistor device. A substantially inverted orientation may include planar variations within 5 degrees and determination of whether two transistors are substantially inverted relative to each other may be determined using the transistor gates, for example, or any other suitable method. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

Figure 1 illustrates a method of forming an integrated circuit, in accordance with one or more embodiments of the present disclosure. Figures 2A-C, 3, 4-4', and 5A-B illustrate example integrated circuit structures that are formed when carrying out the method 100 of Figure 1, in accordance with various embodiments. As will be apparent in light of the structures formed, method 100 discloses techniques for 3D vertical semiconductor device integration, which will be demonstrated with transistor devices. The structures are primarily depicted using transistor devices including a finned configuration (e.g., FinFET or tri-gate) for ease of illustration. However, the techniques can be used to integrate transistors of any suitable geometry, depending on the end use or target application. Various example transistor device geometries that can benefit from the integration techniques described herein include, but are not limited to, field- effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), tunnel-FETs (TFETs), planar transistor configurations, dual-gate transistor configurations, finned transistor configurations (e.g., fin-FET, tri-gate), vertical channel configurations, and nanowire (or nanoribbon or gate-all-around) transistor configurations. In addition, the techniques may be used to vertically integrate p-type transistor devices (e.g., p-MOS or p-TFET) and/or n-type transistor devices (e.g., n-MOS or n-TFET). Further, the techniques may be used to vertically integrate complementary MOS (CMOS) or complementary TFET (CTFET) devices or few to single electron quantum transistor devices. Further yet, such devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example.

As can be seen in Figure 1, method 100 includes providing 102 a bulk wafer, depositing 104a an etch-stop layer or depositing 104b a fast-etch layer, and depositing a device-quality semiconductor layer 106 to form an example multilayer substrate illustrated in Figure 2A, in accordance with an embodiment. The multilayer substrate, in this example embodiment, includes bulk wafer layer 200, etch-stop or fast-etch layer 210 and device-quality semiconductor layer 220. Bulk wafer layer 200 may be a substrate including, e.g., Si, SiGe, Ge, and/or at least one III-V material or wafer layer 200 may be an X on insulator (XOI) structure where X is Si, SiGe, Ge, and/or at least one III-V material, for example, and the insulator material is an oxide material or dielectric material or some other electrically insulating material. As the devices formed on bulk wafer 200 are to be integrated to another host wafer, bulk wafer 200 may be referred to herein as a guest wafer. For ease of description, the present disclosure will be described primarily in the context of bulk wafer 200 being a bulk Si or SOI wafer. In some cases, the thickness Tl of bulk wafer layer 200 may be, for example, 0.5-2 mm, such as 0.75 mm for 8 inch diameter wafers, as is standard. However, the thickness Tl of bulk wafer layer 200 may be any suitable thickness, depending on the end use or target application.

In this example embodiment, layer 210 is either an etch-stop layer or a fast-etch layer that has been deposited 104a or 104b on the bulk wafer layer 200. As will be apparent in light of the present disclosure, layer 210 is a sacrificial layer that assists with the removal of bulk wafer layer 200. Accordingly, as is described in more detail herein, sacrificial layer 210 is either completely or partially removed during performance of the integration techniques. Deposition 104a or 104b may include a blanket deposition of sacrificial layer 210 or a selective growth of sacrificial layer 210 on layer 200 using chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and/or any other suitable process, depending on the end use or target application. In some embodiments, the top surface of wafer layer 200 may be treated (e.g., chemical treatment, thermal treatment, etc.) prior to deposition of sacrificial layer 210. In some embodiments, where sacrificial layer 210 is an etch-stop layer, the thickness T2 of the etch-stop layer 210 may be in the range of 50-200 nm, for example, or any suitable thickness that allows etch/polish 115a hitting the valleys caused by backside grind 114a to withstand the etch/polish 115a process until all peaks (made as a result of the backside grind) are consumed, as will be described in more detail with reference to Figure 5A. In some embodiments, where sacrificial layer 210 is a fast-etch layer, the thickness T2 of the fast-etch layer 210 may be at least 500 nm, for example, or any suitable thickness that allows lateral etch 114b to etch in from the edges of the wafer and allow a liftoff or removal of the wafer, as will be described in more detail with reference to Figure 5B. However, the thickness T2 of sacrificial layer 210 may be any suitable thickness, depending on the end use or target application.

In this example embodiment, device-quality layer 220 includes Si, Ge, SiGe, at least one III-V material, graphene, MoS₂, and/or carbon nanotubes. In some embodiments, layer 220 may include a plurality of multilayer materials, which may be used for nanowire transistor configuration applications, for example. In addition, layer 220 may be doped with one or more other materials, depending on the end use or target application. Deposition 106 of layer 220 can be performed using any deposition process described herein (e.g., CVD, ALD, MBE, etc.) or any other suitable deposition process. In some embodiments, the thickness T3 of device-quality layer 220 may be in the range of 300-500 nm, for example, or any other suitable thickness depending on the end use or target application. As will be apparent in light of the present disclosure, one or more transistor devices will be formed from device-quality layer 220, and those devices will be bonded to a host wafer including one or more transistor devices.

Any suitable material may be used for sacrificial layer 210, depending on the selected configuration. In some embodiments, the material selected for sacrificial layer 210 may be based on whether layer 210 is an etch-stop layer or a fast-etch layer, the material of bulk wafer layer 200, and/or the material of device-quality layer 220. For instance, in the case of a Si bulk wafer 200 and an Si device-quality layer 220, an example etch-stop material includes Si:C with C doping content in the range of 1-30% and example fast-etch materials include SiGe and SiGe:B. In the case of a Si bulk wafer 200 and a Ge or SiGe with greater than 80% Ge alloy content device-quality layer 220, for layer 210, example etch-stop materials include Ge or Ge:C with C doping content in the range of 1-30% and example fast-etch materials include GeSn and B:GeSn. In the case of a Si bulk wafer 200 and a SiGe with Ge alloy content in the range of 10- 80% device-quality layer 220, for layer 210, an example etch-stop material includes SiGe:C with C doping content in the range of 1-30% and an example fast-etch material includes SiGe with approximately 10% or more higher Ge content than the SiGe device-quality layer (which may or may not be boron doped). In the case of a Si bulk wafer 200 and an InGaAs device -quality layer 220, for layer 210, an example etch-stop material includes InP and an example fast-etch material includes GaAs. In embodiments including a fast-etch layer, the fast-etch material may be selected based on the ability to remove that fast-etch material at a rate of at least 2, 5, 10, 50, 100, or 200 times faster than the material of one or more of the surrounding layers. Numerous variations on the materials of sacrificial layer 210, whether the layer is an etch- stop layer or a fast-etch layer, as will be apparent in light of the present disclosure.

Figure 2A' illustrates another example multilayer substrate, in accordance with an embodiment. In this example embodiment, bulk wafer 200 and device-quality layer 220 are the same as described with reference to the example structure of Figure 2A, but additional layers are included between them. As can be seen in method 100 of Figure 1, some embodiments include both an etch-stop layer and a fast-etch layer, which is the case in the example structure of Figure 2A', where layer 212 is a fast-etch layer and layer 214 is an etch-stop layer. The previous relevant discussion with respect to layer 210 is equally applicable to this structure. For example, the relevant thicknesses and materials discussed with reference to layer 210 as a fast-etch layer apply to fast-etch layer 212 (having a thickness T4). Further, the relevant thicknesses and materials discussed with reference to layer 210 as an etch-stop layer apply to etch-stop layer 214 (having a thickness T6). As can also be seen in Figure 2A, layer 205 is sandwiched between fast-etch layer 212 and etch- stop layer 214. Layer 205 may be included as a transitional layer that assists with the etch and removal of layer 212 and/or assists with the etch/polish performed to etch-stop layer 214, as will be apparent in light of the present disclosure. In some embodiments, layer 205 may include the same material as bulk wafer 200 or layer 205 may include the same material of layer 220, for example. Further, in some embodiments, layer 205 may have a thickness T5 in the range of 50-300 nm, for example, or any other suitable thickness depending on the end use or target application. Note that the deposition of any of layers 212, 205, 214, and 220 can be performed using any deposition process described herein (e.g., CVD, ALD, MBE, etc.) or any other suitable deposition process.

Method 100 of Figure 1 continues with performing 108 front-end processing using the example multilayer substrate of Figure 2A to form the resulting example structure shown in Figure 2B, in accordance with an embodiment. As can be seen in Figure 2B, after front-end processing 108, the device-quality layer 220 was formed into fins 222, shallow trench isolation (STI) material 230 was deposited and recessed, and gate 240 was formed on fins 222 to define channel regions (where source/drain (S/D) regions are adjacent to the channel regions). The formation of fins 222 may have been performed using any suitable processes, such as a wet or dry etch process. Fins 222 may be formed to have varying widths and heights. For example, the height to width ratio (h/w) of the fins may be greater than 1, such as 1.5 to 3, in some instances. Note that fins 222 and the trenches formed between the fins 222 are shown as having the same width and depth/height in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited. Also note that although three fins 222 are shown in the example structure, any number of fins may be formed, such as one, two, ten, hundreds, thousands, millions, etc., depending on the end use or target application. Further note that although a portion of the device-quality layer 220 was formed into fins 222, the maximum thickness of the layer is still the same as (or approximately the same as) the original thickness of the deposited layer 220 shown in Figure 2A (where the thickness may be measured from the bottom of layer 220 to the top of fins 222).

In the example structure of Figure 2B, STI material 230 is present between fins 222 formed from device-quality layer 220. In some embodiments, deposition of the STI material 230 may include any deposition process described herein (e.g., CVD, ALD, MBE, etc.), or any other suitable deposition process. STI material 230 may include any suitable insulating material, such as one or more dielectric, oxide (e.g., silicon dioxide), or nitride (e.g., silicon nitride) materials. In some embodiments, the STI material 230 may selected based on the material of fins 222. For example, in the case of a Si device-quality layer 220 (and thus, Si fins 222, in this example embodiment), STI material 220 may be silicon dioxide or silicon nitride. As can also be seen in the structure of Figure 2B, a gate 240 was formed on fins 222. In some embodiments, the formation of gate 240 may include a gate first flow (also called up-front hi-k gate). In some embodiments, the gate may be formed in a gate last flow (also called replacement metal gate (RMG)). In such gate last processing, the process includes dummy gate oxide deposition, dummy gate electrode (e.g., poly-Si) deposition, and patterning hardmask deposition. Additional processing may include patterning the dummy gates and depositing/etching spacer material. Following such processes, the method may continue with insulator deposition, planarization, and then dummy gate electrode and gate oxide removal to expose the channel region of the transistors. Following opening the channel region, the dummy gate oxide and electrode may be replaced with, for example, a hi-k dielectric and a replacement metal gate, respectively.

In this example embodiment, the gate includes a gate electrode 240 and a gate dielectric (not shown for ease of illustration) formed directly under the gate electrode 240. The gate dielectric may be, for example, any suitable oxide such as silicon dioxide or high-k gate dielectric materials. Examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used. The gate electrode 240 may comprise a wide range of materials, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example. Spacers may be formed adjacent to the gate and/or hardmask may be formed on the gate to, for example, assist with replacement gate processing and/or protect the gate during subsequent processing.

In some embodiments, front-end processing 108 may also include S/D processing, such as doping the S/D regions based on the end use or target application. Note that any suitable front- end processing 108 may be used and variations to the specific structure of Figure 2B may be possible in other embodiments, depending on the end use or target application. For example, in some embodiments, fins 222 may have been removed and replaced by another semiconductor material to form fins of that other semiconductor material (e.g., as opposed to being native to the device-quality layer 220 as shown in Figure 2B). In another example embodiment, for transistor devices having a planar configuration, STI material 230 may not have been recessed to expose fins 222, resulting in the STI material 230 being level with the top of fins 222. Also note that front end-processing is also referred to as front-end-of-line (FEOL) and generally includes processes up to (but not including) the deposition of metal interconnect layers. As previously described, the front-end processing may include the formation of one or more transistor devices including any of the following: field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), tunnel-FETs (TFETs), planar configurations, dual-gate configurations, finned configurations (e.g., fin-FET, tri-gate), vertical channel configurations, and/or nanowire (or nanoribbon or gate-all-around) configurations (having any number of nano wires). In addition, the devices formed may include p-type transistor devices (e.g., p-MOS or p-TFET) and/or n-type transistor devices (e.g., n-MOS or n-TFET). Further, the devices may include complementary MOS (CMOS) or complementary TFET (CTFET) or quantum devices (few to single electron). Numerous variations and configurations will be apparent in light of the present disclosure. Method 100 of Figure 1 continues with performing 110 back-end processing using the example structure of Figure 2B to form the resulting example structure 20 shown in Figure 2C, in accordance with an embodiments. The back-end processing 110 primarily includes formation of metal contacts 260, metal line 270, and insulator layer(s) 250. Contacts 260 can be formed for the S/D regions and the gate using any suitable processes, such as forming contact trenches in insulator material over the respective regions and depositing metal contact material in the trenches. In some embodiments, contact formation may include silicidation, germination, or annealing processes. The material of contacts 260 may include aluminum or tungsten, although any suitable conductive metal or alloy can be used, such as silver, nickel-platinum, or nickel- aluminum, for example. Metal line 270 may be formed using any suitable processes and may be formed of any suitable material, such as copper or aluminum, for example. In this example embodiment, only one metal line/level 270 is shown for ease of illustration; however, any number of back end layers may be formed. Insulator 250 may be formed using any suitable processes and may be formed of any suitable material, such as a dielectric material, for example. In this example embodiment, insulator layer 250 is shown as a single transparent layer to allow the other device components to be seen, such as metal contacts 260; however, the layer would not be transparent in practice and may include multiple layers of insulating material that were deposited at various points of the device formation process. Note that back-end processing is also referred to as back-end-of-line (BEOL) where individual devices (e.g., transistors, capacitors, resistors, etc.) get interconnected with wiring.

Method 100 of Figure 1 continues with inverting the device(s) 20 to be bonded as illustrated in Figure 3 and bonding 112 the device(s) 20 on the guest wafer 200 to host wafer structure 30 to form the resulting example structure illustrated in Figure 4, in accordance with an embodiment. As can be understood, structure 20 (including the device(s) to be bonded) is the same structure as shown in Figure 2C, where the one or more transistors/de vices are formed on a multilayer substrate as variously described herein. Bonding 112 may be performed using any suitable techniques, such as using any combination of heat, pressure, and/or force to physically connect structure 20 to structure 30. In some cases, the insulator/oxide layers 250 and 350 may be bonded together. In some cases, the metal lines 270 and 370 will be bonded together. And in some cases, the insulator oxide/layers 250 and 350 and the metal lines 270 and 370 will be bonded together. Although the example resulting structure after bonding 112 illustrated in Figure 4 shows metal lines 270 and 370 as separate lines, they may be fused together into one line, in some cases. Note that although the transistor(s) of structure 20 from the guest wafer 200 are exactly above the transistor(s) of host wafer structure 30, the present disclosure is not intended to be so limited. For example, in some embodiments, there may be a lateral offset between the transistors/devices, such that the vertically integrated ones are not exactly above or over the host ones; however, even with such a lateral offset, the bonded transistors/de vices will be considered as being "above" the transistors/devices on the host wafer 300. Figure 4' illustrates the example resulting structure after bonding 112 is performed, where the one or more transistors/de vices to be bonded were formed on the example multilayer substrate of Figure 2A'. Recall that such an example multilayer substrate includes both a fast-etch layer 212 and an etch- stop layer 214 (as well as a transitional layer 205) between the bulk wafer 200 and the device- quality layer 220.

The host wafer 30 includes its own one or more transistors/devices, where the structure 30 shown is similar to structure 20 for ease of illustration and the relevant description provided herein with reference to structure 20 having components numbered in the 200s is equally applicable to structure 30 having numbers in the 300s. However, note that the transistor(s) formed on the host wafer in structure 30 are formed from the host wafer/substrate 300 in this example case. For example, fins 322 are formed from the bulk wafer/substrate 300, as there are no intervening layers present to assist with removing the bulk wafer 300 for the integration techniques described herein, due to structure 30 receiving the devices for vertical integration (as indicated by the arrows in Figure 3). Note that in some embodiments, the transistors formed on host wafer 300 may include any suitable variations or configurations. For example, although fins 322 are shown as being native to substrate 300, in some cases, they may be removed and replaced with a different semiconductor material. In another example case, a different semiconductor material may have been deposited on bulk wafer 300 and used as the device - quality layer from which one or more transistors/devices are formed. The one or more devices formed in host structure 30 can include any of the following: field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), tunnel-FETs (TFETs), planar transistor configurations, dual-gate transistor configurations, finned transistor configurations (e.g., fin- FET, tri-gate), vertical channel transistor configurations, and/or nanowire (or nanoribbon or gate- all-around) transistor configurations (having any number of nano wires). In addition, the devices formed may include p-type transistor devices (e.g., p-MOS or p-TFET) and/or n-type transistor devices (e.g., n-MOS or n-TFET). Further, the devices may include complementary MOS (CMOS) or complementary TFET (CTFET) or quantum devices (few to single electron). The materials or device types included in the device layer of the host and guest wafers may be the same or they may be different. In an example embodiment, it may be desired to fabricate the host wafer including InGaAs wires for n-MOS transistors, while a first guest wafer includes Ge tri-gate fin p-MOS devices, and a second guest wafer includes graphene planar quantum (e.g., few to single electron) transistors, for example. Numerous transistor device material combinations, device geometries, and device type variations and configurations will be apparent in light of this disclosure.

Method 100 of Figure 1 continues with removing the bulk wafer layer 200 via either backside grind 114a and etch/polish 115a processes in the case of sacrificial layer 210 being an etch- stop layer or via a lateral etch 114b in the case of sacrificial layer 210 being a fast-etch layer, in accordance with some embodiments. As can be understood, bulk wafer layers 200 and 300 would be significantly thicker than the other layers in the structure of Figure 4 (e.g., on the order of at least 1000 times thicker in some cases) and removal of bulk wafer layer 200 would significantly reduce the thickness of the entire structure, thereby enabling a 3D vertical integration scheme. In configurations where sacrificial layer 210 in the example structure of Figure 4 is an etch-stop layer, removal of bulk wafer layer 200 may include initially performing a backside grind 114a of the bulk wafer layer 200 to form the resulting example structure of Figure 5 A, in accordance with an embodiment. Backside grind 114a may be performed using any suitable techniques, and in some cases, the backside grind may be performed to as close to the active transistors (e.g., as close to device-quality layer 220) as practical, owing, for example, to within-wafer process grind thickness uniformity constraints. As can be seen in Figure 5 A, the resulting structure would typically include a rough backside surface 201 of bulk wafer layer 200 after grind 114a has been performed. After backside grind 114a has been performed to remove bulk wafer material to a point that is near or very close to etch-stop layer 210, method 100 can continue by performing an etch and/or polish process 115a to remove the remainder of bulk wafer layer 200.

The etch/polish 115a may be performed using any suitable process, based on the material and/or thickness of etch-stop layer 210 (and optionally based on the material/thickness of other layers, such as device-quality layer 220), for example. In some embodiments, etch/polish 115a will remove the entirety of etch-stop layer 210, leaving an example structure such as is illustrated in Figure 5B. In other embodiments, etch/polish 115a may only partially remove etch-stop layer 210, and thus some of the layer's material may remain on the backside of device-quality layer 220. In some such embodiments, the remaining material of layer 210 may not be present in all locations of the backside of layer 220, as it may be completely removed in some areas and only partially removed in others. In embodiments where bulk wafer layer 200 is Si, an example etchant for etch/polish 115a includes ammonium hydroxide. For example, where bulk wafer layer 200 is Si, an example etch stop material is carbon doped Si (Si:C) with C alloying concentration in the range of 1 to 30%. Numerous different etch-stop materials for layer 210 will be apparent in light of the present disclosure.

In configurations where sacrificial layer 210 in the example structure of Figure 4 is a fast- etch layer, method 100 may continue from inversion and bonding process 112 by laterally etching 114b the fast-etch layer 210 to release the bulk wafer layer 200, in accordance with an embodiment. Lateral etch 114b can be performed using any suitable process, and in this example embodiment, includes performing a wet etch from the side of the structure to remove fast-etch layer 210, thereby enabling the clean release/liftoff of bulk wafer layer 200. In some embodiments, lateral etch 114b will remove the entirety of fast-etch layer 210, leaving an example structure such as is illustrated in Figure 5B. In other embodiments, lateral etch 114b may only partially remove fast-etch layer 210, and thus some of the layer's material may remain on the backside of device-quality layer 220. In some such embodiments, the remaining material of layer 210 may not be present in all locations of the backside of layer 220, as it may be completely removed in some areas and only partially removed in others. In any case, use of a fast-etch layer for sacrificial layer 210 may provide the benefit of allowing a clean liftoff of the bulk wafer 200, thereby preserving the wafer for other future uses, for example. In embodiments where the device-quality layer 220 is Si and the guest wafer layer 200 to be removed is also Si, an example fast-etch layer 210 is SiGe or SiGe:B and an example etchant for lateral etch 114b is peroxide containing concentrated sulfuric or nitric acid. In embodiments where the device- quality layer 220 is Ge or SiGe with Ge alloy content greater than 80% and the guest wafer layer 200 to be removed is Si, an example fast-etch layer 210 is GeSn or GeSn:B and an example etchant for lateral etch 114b is buffered dilute nitric or sulfuric acid. In embodiments, where the device-quality layer 220 is SiGe with Ge alloy content of 10-80%) and the guest wafer layer 200 to be removed is Si, an example fast-etch layer 210 is SiGe with approximately 10% or more greater Ge content than the Ge content of the device-quality layer and an example etchant is peroxide containing concentrated sulfuric or nitric acid. In embodiments where the device- quality layer 220 is InGaAs, an example fast-etch layer 210 is GaAs and an example etchant for lateral etch 114b includes a strong base, such as potassium hydroxide or sodium hydroxide. Numerous different fast-etch materials for layer 210 will be apparent in light of the present disclosure.

In the example embodiment illustrated in Figure 4', recall that the guest wafer includes a multilayer substrate including both a fast-etch layer 212 and an etch- stop layer 214. In such an example embodiment, removal of bulk wafer layer 200 may include performing lateral etch 114b as previously described to partially or completely remove fast-etch layer 212 and allow for the clean release/liftoff of bulk wafer layer 200. An example resulting structure after the lateral etch 114b is performed is shown in Figure 5 A' (where fast-etch layer 212 was completely removed). The method can then continue with performing etch/polish 115a as previously described to completely remove transitional layer 205 and partially or completely remove etch-stop layer 214. An example resulting structure after the etch/polish 115a is performed is shown in Figure 5B (where etch- stop layer 214 was completely removed).

Method 100 optionally continues with performing 116 additional back-end processing (e.g., to form the example structure of Figure 6) and/or bonding an additional transistor level (e.g., to form the example structure of Figure 7), in accordance with some embodiments of the present disclosure. As can be seen in the example structure of Figure 6, the additional back-end processing 116 was performed on the backside of the structure 20 added to the host wafer. Such additional processing, in this example embodiment, included etching and/or polishing to the level of STI material 230, which is also to the base of fins 222, followed by depositing a layer of back-end materials, which includes oxide 280 and metal contacts/lines 290. These processes may be performed using any suitable techniques. As can be seen in Figure 6, the active device portion of fins 222 (e.g., the portion including the channel region and the source and drain regions) has a thickness indicated as T7. In some cases, thickness T7 may be less than 200, 100, 50, or 25 nm, or any other suitable maximum thickness, depending on the end use or target application.

Figure 7 illustrates an example structure after an additional level of transistors (a second guest wafer) is bonded to the structure of Figure 6, in accordance with an embodiment. As can be understood, the next device wafer would result in a third level of vertical device integration and the process may include bonding a device formed on a multilayer substrate as variously described herein, such that the host wafer and levels of devices formed thereon can maintain a relatively thin profile to, for example, allow all layers to be electrically connected regardless of scale. The previous relevant discussion with reference to figure component identifying numbers in the 200s is equally applicable to the components in the 400s. For example, the previous relevant discussion with respect to: fins 222 applies to fins 422, STI 230 applies to STI 430, gate 240 applies to gate 440, and so on. As can be seen in the structure of Figure 7, there are three levels/layers LI, L2, L3 of transistors on host bulk wafer 300, with LI being the first level of transistors formed from bulk wafer 300, L2 being the second level of transistors (initially fabricated on the first guest wafer) located above the first level LI of transistors, and L3 being the third level of transistors (initially fabricated on the second guest wafer) located above the second level L2 of transistors. Note that brackets identifying levels LI, L2, and L3 in Figure 7 are shown bracketing the device-quality layer of the transistor levels (e.g., the channel region and the source and drain regions). Also note that between each bracketed level are non- single-crystal materials, such as various polycrystalline or amorphous/non-crystalline materials, such as the metal contacts and lines and the insulating materials (e.g., the oxide material). In addition, process 116 can be repeated as desired to achieve any desired amount of vertical integration of transistor levels, depending on the end use or target application.

Recall that various example transistor device geometries that can benefit from the integration techniques described herein include, but are not limited to, field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), tunnel-FETs (TFETs), planar transistor configurations, dual-gate transistor configurations, finned transistor configurations (e.g., fm- FET, tri-gate), vertical channel configurations, and nanowire (or nanoribbon or gate-all-around) transistor configurations. In addition, the techniques may be used to vertically integrate p-type transistor devices (e.g., p-MOS or p-TFET) and/or n-type transistor devices (e.g., n-MOS or n- TFET). Further, the techniques may be used to vertically integrate complementary MOS (CMOS) or complementary TFET (CTFET) devices or quantum devices (few to single electron). Numerous variations and configurations on method 100 and the integration techniques and structures described herein will be apparent in light of the present disclosure.

Example System

Figure 8 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the techniques disclosed herein, in accordance with an example embodiment. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit including: a substrate; a first transistor including a first layer of single-crystal semiconductor material, wherein the first layer of semiconductor material is at least one of native to and above the substrate; and a second transistor including a second layer of single-crystal semiconductor material, the second layer of semiconductor material located above the first layer of semiconductor material, wherein the first and second layers of semiconductor material are separated by non-single-crystal materials.

Example 2 includes the subject matter of Example 1, wherein at least one of the first and second layers of semiconductor material includes less than 1E8 dislocation or grain boundary defects per square cm.

Example 3 includes the subject matter of any of Examples 1-2, wherein the non-single- crystal materials include amorphous or polycrystalline materials.

Example 4 includes the subject matter of any of Examples 1-3, wherein the substrate is a bulk silicon or silicon on insulator (SOI) wafer.

Example 5 includes the subject matter of any of Examples 1-4, wherein at least one of the first and second layers of semiconductor material includes silicon.

Example 6 includes the subject matter of any of Examples 1-5, wherein at least one of the first and second layers of semiconductor material includes germanium or silicon germanium.

Example 7 includes the subject matter of any of Examples 1-6, wherein at least one of the first and second layers of semiconductor material includes at least one III-V material. Example 8 includes the subject matter of any of Examples 1-7, wherein at least one of the first and second layers of semiconductor material includes graphene or molybdenum disulfide.

Example 9 includes the subject matter of any of Examples 1-8, wherein at least one of the first and second transistors has a finned configuration.

Example 10 includes the subject matter of any of Examples 1-9, wherein at least one of the first and second transistors has a nanowire configuration.

Example 11 includes the subject matter of any of Examples 1-10, wherein at least one of the first and second transistors has a metal-oxide-semiconductor field-effect transistor (MOSFET) or tunnel FET (TFET) configuration.

Example 12 includes the subject matter of any of Examples 1-11, wherein the first and second transistors are each one of a p-type transistor and an n-type transistor.

Example 13 includes the subject matter of any of Examples 1-12, wherein at least one of the first and second transistors are included in a complementary metal-oxide-semiconductor (CMOS) device or a complementary tunnel field-effect transistor (CTFET) device or a few to single electron quantum transistor device.

Example 14 includes the subject matter of any of Examples 1-13, further including a third transistor including a third layer of single-crystal semiconductor material, the third layer of semiconductor material located above the second layer of semiconductor material, wherein the second and third layers of semiconductor material are separated by non-single-crystal materials.

Example 15 is a computing system including the subject matter of any of Examples 1-14.

Example 16 is an integrated circuit including: a substrate; a first transistor including a gate defining a channel, the first transistor channel in a first layer of single-crystal semiconductor material, wherein the first layer of semiconductor material is at least one of native to and above the substrate; and a second transistor including a gate defining a channel, the second transistor channel in a second layer of single-crystal semiconductor material, the second layer of semiconductor material located above the first layer of semiconductor material; wherein the second transistor gate has a substantially inverted orientation relative to the first transistor gate.

Example 17 includes the subject matter of Example 16, wherein at least one of the first and second layers of semiconductor material includes less than 1E8 dislocation or grain boundary defects per square cm.

Example 18 includes the subject matter of any of Examples 16-17, wherein the first and second layers of semiconductor material are separated by non-single-crystal materials. Example 19 includes the subject matter of any of Examples 16-18, wherein the substrate is a bulk silicon or silicon on insulator (SOI) wafer.

Example 20 includes the subject matter of any of Examples 16-19, wherein at least one of the first and second layers of semiconductor material includes silicon.

Example 21 includes the subject matter of any of Examples 16-20, wherein at least one of the first and second layers of semiconductor material includes germanium or silicon germanium.

Example 22 includes the subject matter of any of Examples 16-21, wherein at least one of the first and second layers of semiconductor material includes at least one III-V material.

Example 23 includes the subject matter of any of Examples 16-22, wherein at least one of the first and second layers of semiconductor material includes graphene or molybdenum disulfide.

Example 24 includes the subject matter of any of Examples 16-23, wherein at least one of the first and second transistors has a finned configuration.

Example 25 includes the subject matter of any of Examples 16-24, wherein at least one of the first and second transistors has a nanowire configuration.

Example 26 includes the subject matter of any of Examples 16-25, wherein at least one of the first and second transistors has a metal-oxide-semiconductor field-effect transistor (MOSFET) or tunnel FET (TFET) configuration.

Example 27 includes the subject matter of any of Examples 16-26, wherein the first and second transistors are each one of a p-type transistor and an n-type transistor.

Example 28 includes the subject matter of any of Examples 16-27, wherein at least one of the first and second transistors are included in a complementary metal-oxide-semiconductor (CMOS) device or a complementary tunnel field-effect transistor (CTFET) device or a few to single electron quantum transistor device.

Example 29 includes the subject matter of any of Examples 16-28, further including a third transistor including a third layer of single-crystal semiconductor material, the third layer of semiconductor material located above the second layer of semiconductor material, wherein the second and third layers of semiconductor material are separated by non-single-crystal materials.

Example 30 is a computing system including the subject matter of any of Examples 16-29. Example 31 is a method of forming an integrated circuit, the method including: providing a first substrate; depositing a sacrificial layer on the first substrate; forming a single-crystal semiconductor material layer on the sacrificial layer; forming a first transistor including the semiconductor material layer, the first transistor including at least one back-end layer; bonding a back-end layer of the first transistor to a back-end layer of a second transistor, the second transistor formed on a second substrate; and at least partially removing the sacrificial layer to remove the first substrate from the first transistor.

Example 32 includes the subject matter of Example 31, wherein the sacrificial layer is an etch-stop layer and wherein at least partially removing the sacrificial layer includes grinding the first substrate to near the etch-stop layer followed by at least one of an etch and polish process used to remove the remainder of the first substrate material.

Example 33 includes the subject matter of Example 31, wherein the sacrificial layer is a fast-etch layer and wherein at least partially removing the sacrificial layer includes a lateral etch of the fast-etch layer to allow for liftoff of the first substrate.

Example 34 includes the subject matter of Example 31, wherein the sacrificial layer is a multilayer stack including a fast-etch layer and an etch-stop layer and wherein at least partially removing the sacrificial layer includes a lateral etch of the fast-etch layer to allow for liftoff of the first substrate followed by at least one of an etch and polish process used to at least partially remove the etch-stop layer.

Example 35 includes the subject matter of any of Examples 31-34, wherein the semiconductor material layer has a thickness of less than 500 nm.

Example 36 includes the subject matter of any of Examples 31-35, wherein the semiconductor material layer has less than 1E8 dislocation or grain boundary defects per square cm.

Example 37 includes the subject matter of any of Examples 31-36, wherein the semiconductor material layer includes one of silicon, germanium, silicon germanium, a III-V material, graphene or molybdenum disulfide.

Example 38 includes the subject matter of any of Examples 31-37, wherein the sacrificial layer includes carbon doped silicon with carbon in the range of 1-30%.

Example 39 includes the subject matter of any of Examples 31-37, wherein the sacrificial layer includes carbon doped germanium with carbon in the range of 1-30%.

Example 40 includes the subject matter of any of Examples 31-37, wherein the sacrificial layer includes one of silicon germanium, germanium tin, and gallium arsenide.

Example 41 includes the subject matter of any of Examples 31-40, further including bonding a third transistor to a back-end layer above the second transistor. Example 42 includes the subject matter of any of Examples 31-41, wherein the first and second transistor geometry includes at least one of a field-effect transistor (FET), metal-oxide- semiconductor FET (MOSFET), tunnel-FET (TFET), planar configuration, finned configuration, FinFET configuration, trigate configuration, vertical channel configuration, nanowire configuration, nanoribbon configuration, and gate-all-around configuration.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit comprising:

a substrate;

a first transistor including a first layer of single-crystal semiconductor material, wherein the first layer of semiconductor material is at least one of native to and above the substrate; and

a second transistor including a second layer of single-crystal semiconductor material, the second layer of semiconductor material located above the first layer of semiconductor material, wherein the first and second layers of semiconductor material are separated by non-single-crystal materials.

2. The integrated circuit of claim 1, wherein at least one of the first and second layers of semiconductor material includes less than 1E8 dislocation or grain boundary defects per square cm.

3. The integrated circuit of claim 1, wherein the non-single-crystal materials include amorphous or polycrystalline materials.

4. The integrated circuit of claim 1 , wherein the substrate is a bulk silicon or silicon on insulator (SOI) wafer.

5. The integrated circuit of claim 1 , wherein at least one of the first and second layers of semiconductor material includes silicon.

6. The integrated circuit of claim 1 , wherein at least one of the first and second layers of semiconductor material includes germanium or silicon germanium.

7. The integrated circuit of claim 1 , wherein at least one of the first and second layers of semiconductor material includes at least one III-V material.

8. The integrated circuit of claim 1 , wherein at least one of the first and second layers of semiconductor material includes graphene or molybdenum disulfide.

9. The integrated circuit of claim 1 , wherein at least one of the first and second transistors has a finned configuration.

10. The integrated circuit of claim 1 , wherein at least one of the first and second transistors has a nanowire configuration.

11. The integrated circuit of claim 1 , wherein at least one of the first and second transistors has a metal-oxide-semiconductor field-effect transistor (MOSFET) or tunnel FET (TFET) configuration.

12. The integrated circuit of claim 1, wherein the first and second transistors are each one of a p-type transistor and an n-type transistor.

13. The integrated circuit of claim 1 , wherein at least one of the first and second transistors are included in a complementary metal-oxide-semiconductor (CMOS) device or a complementary tunnel field-effect transistor (CTFET) device or a few to single electron quantum transistor device.

14. The integrated circuit of claim 1 , further comprising a third transistor including a third layer of single-crystal semiconductor material, the third layer of semiconductor material located above the second layer of semiconductor material, wherein the second and third layers of semiconductor material are separated by non-single-crystal materials.

15. A computing system comprising the integrated circuit of any of claims 1-14.

16. An integrated circuit comprising:

a substrate;

a first transistor including a gate defining a channel, the first transistor channel in a first layer of single-crystal semiconductor material, wherein the first layer of semiconductor material is at least one of native to and above the substrate; and a second transistor including a gate defining a channel, the second transistor channel in a second layer of single-crystal semiconductor material, the second layer of semiconductor material located above the first layer of semiconductor material; wherein the second transistor gate has a substantially inverted orientation relative to the first transistor gate.

17. The integrated circuit of claim 16, wherein at least one of the first and second layers of semiconductor material includes less than 1E8 dislocation or grain boundary defects per square cm.

18. The integrated circuit of any of claims 16-17, wherein the first and second layers of semiconductor material are separated by non-single-crystal materials.

19. A method of forming an integrated circuit, the method comprising:

providing a first substrate;

depositing a sacrificial layer on the first substrate;

forming a single-crystal semiconductor material layer on the sacrificial layer;

forming a first transistor including the semiconductor material layer, the first transistor including at least one back-end layer;

bonding a back-end layer of the first transistor to a back-end layer of a second transistor, the second transistor formed on a second substrate; and

at least partially removing the sacrificial layer to remove the first substrate from the first transistor.

20. The method of claim 19, wherein the sacrificial layer is an etch-stop layer and wherein at least partially removing the sacrificial layer includes grinding the first substrate to near the etch-stop layer followed by at least one of an etch and polish process used to remove the remainder of the first substrate material.

21. The method of claim 19, wherein the sacrificial layer is a fast-etch layer and wherein at least partially removing the sacrificial layer includes a lateral etch of the fast-etch layer to allow for liftoff of the first substrate.

22. The method of claim 19, wherein the sacrificial layer is a multilayer stack including a fast-etch layer and an etch-stop layer and wherein at least partially removing the sacrificial layer includes a lateral etch of the fast-etch layer to allow for liftoff of the first substrate followed by at least one of an etch and polish process used to at least partially remove the etch-stop layer.

23. The method of claim 19, wherein the semiconductor material layer has a thickness of less than 500 nm.

24. The method of claim 19, wherein the semiconductor material layer includes one of silicon, germanium, silicon germanium, a III-V material, graphene or molybdenum disulfide.

25. The method of any of claims 19-24, further comprising bonding a third transistork-end layer above the second transistor.