WO2016127600A1

WO2016127600A1 - Exception handling method and apparatus

Info

Publication number: WO2016127600A1
Application number: PCT/CN2015/086164
Authority: WO
Inventors: 蒋习旺
Original assignee: 中兴通讯股份有限公司
Priority date: 2015-02-12
Filing date: 2015-08-05
Publication date: 2016-08-18
Also published as: CN105988905A

Abstract

An exception handling method and apparatus. The method comprises: detecting whether an exception has occurred in a process of accessing a PCI-E memory space (S102); if so, setting a return value corresponding to an exception instruction causing the exception as an illegal value (S104); and taking the next address of the exception instruction as a return address of the current exception (S106). Using the technical solution solves the problems in the related art that the occurrence of an exception in the process of accessing a pcie memory address causes the procedure to stop and a system halts due to an endless loop, thereby improving the robustness and survivability of the system.

Description

Abnormal processing method and device

Technical field

The present invention relates to the field of communications, and in particular to an exception handling method and apparatus.

Background technique

Peripheral Component Interconnect Express (PCI-E) is a new type of bus standard and interface. It is a third-generation PCI bus called "3GIO" announced by Intel in 2001. PCI-E is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices allocate exclusive channel bandwidth and do not share bus bandwidth. They mainly support active power management, error reporting, end-to-end reliability transmission, hot swap and service. Features such as Quality of Service (QoS).

Four address spaces are specified in PCI-E, which are memory, I/O, configuration, and message space. In the PCI-E architecture, an exception occurs when accessing a memory address that does not have a bank. For different processor platforms, there will be some differences in how to handle such anomalies.

Under the PerPerformance Optimization With Enhanced-Performance Computing (POWERPC) processor platform, the Central Processing Unit (CPU) issues a read command to access the PCI-E memory space. The processor first maps the local address of the instruction to the PCI-E controller through local access windows. Then uses outbound ATMU windows to map the processor address to the address of the PCI-E domain. The transaction layer of the PCI-E controller will be based on The access type of the processor and the mapped PCI-E address constitute one or more TLPs. Finally, these TLPs are sent to the opposite end of the bus through the link layer and physical layer of the PCI-E, and wait for the completion message of the opposite end. End this thing.

When the processor sends a read access and the address of the read access does not correspond to the bank, the PCI-E controller will generate an exception due to waiting for the completion message to time out. During the exception handling process, the handler will determine whether the instruction that triggered the exception is in the home state or in the kernel state. In the user mode, exception handling will send a SIGBUS signal to the user mode process. After the process receives the SIGBUS signal, the default processing method is to end the process. If it is in kernel mode, the user will print out the current processor environment information and exit the exception. The PCI-E memory access instruction was not successfully executed, and the kernel will re-execute the instruction after the exception is returned. The memory access instruction will access the PCI-E address corresponding to the bank, so the exception will be thrown again, which will eventually cause the kernel to enter an infinite loop state.

In systems that support PCI-E hot plugging, PCI-E devices may be powered down or unplugged at any time. It is assumed that the processor continuously reads and accesses the memory space of the PCI-E device at a certain time. The PCI-E device suddenly loses power during the visit. If the access is initiated by a user-mode process, the process will be killed. If the access is initiated by the kernel mode, the system will fall into an infinite loop because of this access failure, so that the whole machine is down.

In the related art, an effective solution has not been proposed for the process stoppage caused by an abnormality in accessing the pcie memory address and the system hangs due to an infinite loop.

Summary of the invention

In order to solve the above technical problem, an embodiment of the present invention provides an abnormal processing method and apparatus.

According to an embodiment of the present invention, an exception processing method is provided, including: detecting whether an abnormality occurs in a process of accessing a fast peripheral interconnection standard PCI-E storage memory space; if so, an abnormal instruction corresponding to an abnormality is generated The return value is set to an illegal value; the next address of the exception instruction is used as the return address of the current exception.

In the embodiment of the present invention, detecting whether an abnormality occurs during the process of accessing the PCI-E storage memory space includes: detecting whether the following occurs: when accessing the PCI-E storage memory space, the PCI-E storage memory space is not An abnormality caused by the corresponding storage entity, and whether the operation address of the abnormal instruction to be accessed is located in an address range of the PCI-E storage memory space; wherein, if the detection result is yes, determining to access the An exception occurred during PCI-E memory memory space.

In the embodiment of the present invention, the operation address is obtained by one of the following manners: when determining that the current abnormality is an exception caused by loading a load class instruction, acquiring the operation address from the load class instruction; or checking from a machine The operation address is read in the interrupt status register MCSR.

In the embodiment of the present invention, the obtaining the operation address from the load class instruction includes: acquiring, according to a format type of the load class instruction, a specified location from the load class instruction corresponding to the format type. Operation address.

In the embodiment of the present invention, setting the return value corresponding to the abnormal instruction that causes the current abnormality to an illegal value includes: writing the illegal value in a data register corresponding to the abnormal instruction.

In the embodiment of the present invention, the abnormality includes at least one of the following: an exception caused by loading a load class instruction, and a data bus abnormality read on the bus.

According to another embodiment of the present invention, there is also provided an exception processing apparatus, comprising: a detecting module configured to detect whether an abnormality occurs during access to a standard PCI-E memory memory space; and a setting module is set to When an abnormality occurs, the return value corresponding to the abnormal command causing the abnormality is set to an illegal value; and the determining module is set to use the next address of the abnormal command as the return address of the current abnormality.

In the embodiment of the present invention, the detecting module is configured to detect whether an abnormality occurs when the PCI-E storage memory space does not have a corresponding storage entity when accessing the PCI-E storage memory space. And whether the operation address of the abnormal instruction to be accessed is located in an address range of the PCI-E storage memory space; wherein, if the detection result is yes, determining that the access to the PCI-E storage memory space occurs abnormal.

In the embodiment of the present invention, the device further includes: an acquiring module, configured to acquire the operation address, wherein the acquiring module is further configured to: when determining that the current abnormality is an abnormality caused by loading a load class instruction, The load class instruction acquires the operation address; or reads the operation address from a machine check interrupt status register MCSR.

In the embodiment of the present invention, the acquiring module is further configured to acquire the operation address from a specified location corresponding to the format type in the load class instruction according to a format type of the load class instruction.

According to the embodiment of the present invention, when the abnormality occurs, the next address of the abnormal instruction is used as the return address of the current abnormality, and the return value of the abnormal instruction is set as the illegal value. The process caused by an abnormality in the pcie memory address process and the system hangs due to an infinite loop, thereby improving the robustness and survivability of the system.

DRAWINGS

The drawings described herein are intended to provide a further understanding of the invention, and are intended to be a part of the invention. In the drawing:

1 is a flowchart of an exception handling method according to an embodiment of the present invention;

2 is a block diagram showing the structure of an exception handling apparatus according to an embodiment of the present invention;

3 is a block diagram showing another structure of an exception processing apparatus according to an embodiment of the present invention;

4 is a flowchart of a processing method for processing a read pcie memory exception using a method of analyzing an instruction according to a preferred embodiment of the present invention;

FIG. 5 illustrates exception handling of pcie memory using registers provided by the powerpc platform architecture in accordance with a preferred embodiment of the present invention.

detailed description

The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.

Other features and advantages of the invention will be set forth in the description which follows, The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is an embodiment of the invention, but not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of the present invention.

An exception handling method is provided in this embodiment. FIG. 1 is a flowchart of an exception processing method according to an embodiment of the present invention. As shown in FIG. 1, the flow includes the following steps:

Step S102, detecting whether an abnormality occurs during the process of accessing the standard peripheral PCI-E memory memory space.

Step S104, if yes, setting a return value corresponding to the abnormal instruction causing the abnormality to an illegal value;

In step S106, the next address of the abnormal command is used as the return address of the current abnormality.

Through the above-mentioned various steps, in the related art, the next address of the abnormal command is used as the return address of the current abnormality, and the return value of the abnormal command is set to an illegal value. The problem caused by an abnormality in the access to the pcie memory address and the system hangs due to an infinite loop, thereby improving the robustness and survivability of the system.

Optionally, the illegal value may be preset, and is preferably a hexadecimal F in the embodiment of the present invention.

Whether an abnormality occurs during the process of detecting the access to the PCI-E memory memory space may be detected by detecting whether an abnormality occurs due to the absence of a corresponding storage entity in the PCI-E storage memory space when accessing the PCI-E storage memory space. And whether the operation address to be accessed of the abnormal instruction is located in an address range of the PCI-E storage memory space; wherein, if the detection result is yes, determining that an abnormality occurs during access to the PCI-E storage memory space.

The operation address may be obtained by one of the following methods: when determining that the current abnormality is an exception caused by loading a load class instruction, acquiring the operation address from the load class instruction; or reading the above from the machine check interrupt status register MCSR The operation address is different in the format type of the load class instruction. Therefore, in the implementation of the present invention, the operation address is obtained from the specified location corresponding to the format type in the load class instruction according to the format type of the load class instruction.

In summary, the technical solution of the embodiment of the present invention solves the abnormal problem caused by the powerpc architecture processor reading and accessing the pcie memory address corresponding to the memoryless body, thereby achieving the process of not killing the user state, and does not cause the system to cause The method of hanging out of the dead loop improves the robustness and survivability of the system.

The exception processing method provided in the above embodiment is described below with reference to an example, but is not used to limit the embodiment of the present invention:

Step 1) Determine the cause of the abnormality

First, the cause of the exception is determined in the exception handling flow: that is, the processor accesses the exception caused by the pcie memory address corresponding to the bank. If this is not the case, the exception continues as originally. Otherwise, this exception will be further processed

Step 2) Determine whether the abnormal address is within the range of the pcie memory address.

After determining the cause of the abnormality, it is necessary to further obtain the operation address that caused the abnormal instruction and record the address. And obtain the range of memory addresses governed by all pcie controllers in the system. Finally, it is judged whether the recorded abnormal instruction operation address belongs to the pcie memory space. If so, it is stated that this condition satisfies the conditions to be handled by the embodiment of the present invention. Otherwise, it is executed according to the original exception handling process.

Step 3) Fill the return value to full F

When the above two conditions and conditions are met, the return value of the load memory instruction is filled with all Fs. Change the address returned by the exception to the address under the instruction that caused the exception, and skip the subsequent printing of the kernel exception or send the SIGBUS signal. Give the user process an operation and return directly.

The above technical solution provided by the embodiment of the present invention can easily and effectively prevent the problem that the process caused by the abnormality of the read access PCIe is killed or the system hangs.

It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should understand that the present invention is not limited by the described action sequence. Because certain steps may be performed in other sequences or concurrently in accordance with the present invention. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

An exception processing apparatus is also provided in the embodiment to implement the above-mentioned embodiments and preferred embodiments. The descriptions of the modules involved in the apparatus are described below. As used below, the term "module" may implement a combination of software and/or hardware of a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated. 2 is a block diagram showing the structure of an exception handling apparatus according to an embodiment of the present invention. As shown in Figure 2, the device comprises:

The detecting module 20 is configured to detect whether an abnormality occurs during the process of accessing the standard peripheral PCI-E memory memory space;

The setting module 22 is connected to the detecting module 20, and is configured to set a return value corresponding to the abnormal command that causes the abnormality to an illegal value when an abnormality occurs;

The determining module 24 is connected to the setting module 22 and is configured to set the next address of the abnormal command as the return address of the current abnormality.

Through the integrated application of each of the above modules, when the abnormality occurs, the next address of the abnormal instruction is used as the return address of the current abnormality, and the technical means for causing the return value corresponding to the abnormal command to be set to an illegal value is adopted. The related art has solved the problem that the process stops due to an abnormality in accessing the pcie memory address and the system hangs due to an infinite loop, thereby improving the robustness and survivability of the system.

FIG. 3 is a block diagram of another structure of an exception processing apparatus according to an embodiment of the present invention, wherein the detecting module 20 is configured to detect whether a PCI-E memory memory space is accessed due to the PCI-E memory memory space when accessing the PCI-E memory memory space. An exception caused by the absence of the corresponding storage unit, and whether the operation address of the abnormal instruction to be accessed is located in the address range of the PCI-E storage memory space; wherein, in the case of the detection result being YES, determining to access the PCI- An exception occurred during the storage of the memory space.

Optionally, the device further includes: an obtaining module 26, configured to obtain the operation address, wherein the obtaining module 26 is further configured to: obtain the foregoing from the load class instruction when determining that the current abnormality is an abnormality caused by loading a load type instruction The operation address; or read the above operation address from the machine check interrupt status register MCSR.

Further, the obtaining module 26 is further configured to acquire the operation address from a specified location corresponding to the format type in the load class instruction according to a format type of the load class instruction.

In order to better understand the above abnormal processing procedure, the following description will be made in conjunction with the preferred embodiments, but is not intended to limit the present invention. The scope of protection of the embodiments.

The method for solving the read pcie memory exception using the method of analyzing the instruction is further described in detail below with reference to FIG. 4:

Step S402, the exception entry, the powerpc architecture instruction belongs to the reduced instruction set, adopts a unified instruction encoding manner, the lengths of the instructions are equal, and the op-code in all the instructions is always in the same position. According to this instruction feature, the judgment of the cause of the abnormality can be implemented by analyzing the instruction op-code.

In step S404, the instruction regs->nip causing the abnormality is extracted by retaining the lower structure struct pt_regs when entering the abnormality. Take the [0:5] bits of the instruction and determine if the instruction belongs to the load class instruction. If so, the processing in step S406 is performed, otherwise step S410.

In order to obtain the operation address of the instruction causing the exception, the Load instruction is further analyzed. The address to be accessed by the instruction can be extracted according to the specific Load instruction. Each load instruction is stored in a different format, so the address is extracted according to different instructions.

In step S406, the address range covered by the pcie is obtained by the linux kernel structure variable struct pci_controller hose_head. It is also checked whether the address extracted in step S404 belongs to this range. If so, the operation in step S410 is performed, otherwise step S410 is performed.

Step S408, the information struct pt_regs retained when the abnormality is acquired is filled in the data register regs->gpr[0] of the load instruction causing the abnormality to be all F. The address returned by the exception is pointed to the next address regs->nip=(regs->nip)+4; which causes the exception instruction. When you return to the program again, the program will not perceive the exception, just as the load instruction gets the illegal value of the full F in the pcie memory space.

In step S410, the original exception processing flow is executed.

Another implementation is to obtain and analyze exception information based on the powerpc core cache. The processing of the read access pcie memory exception implemented using the core register will be further described below with reference to FIG.

Step S502, at the abnormal entry, the type of the abnormality is determined by acquiring the MCSR register. If the Machine Check Syndrome Register, referred to as MCSR)[60]=1, it indicates that a "Bus read data bus error" exception has occurred. This type of exception;

Step S504, in the powerpc architecture, when an exception occurs, the Machine Check Address Register (MCAR) register contains the address of the instruction that caused the exception.

In step S506, by reading the MCAR register, the operation address to be accessed by the instruction causing the abnormality can be obtained, and it is determined whether the operation address is located in the address range covered by pcie. If yes, the operation in step S506 is performed, otherwise step S508 is performed.

Step S508, the information struct pt_regs retained when the abnormality is acquired is filled with the data register regs->gpr[0] of the load instruction causing the abnormality as the full F. The address returned by the exception is pointed to the next address regs->nip=(regs->nip)+4; which causes the exception instruction. When you return to the program again, the program will not perceive the exception, just as the load instruction gets the illegal value of the full F in the pcie memory space.

In step S508, the original exception processing flow is executed.

In summary, the embodiment of the present invention achieves the following technical effects: the related art stops the process caused by an abnormality in accessing the pcie memory address and the system hangs due to an infinite loop, thereby improving the robustness of the system. Sex and survivability.

In another embodiment, software is also provided for performing the technical solutions described in the above embodiments and preferred embodiments.

In another embodiment, a storage medium is further provided, wherein the software includes the above-mentioned software, including but not limited to: an optical disk, a floppy disk, a hard disk, an erasable memory, and the like.

It is to be understood that the terms "first", "second" and the like in the specification and claims of the present invention are used to distinguish similar objects, and are not necessarily used to describe a particular order or order. It is to be understood that the objects so used are interchangeable, where appropriate, so that the embodiments of the invention described herein can be carried out in a sequence other than those illustrated or described herein. In addition, the terms "comprises" and "comprises" and "the" and "the" are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to Those steps or units may include other steps or units not explicitly listed or inherent to such processes, methods, products or devices.

It will be apparent to those skilled in the art that the various modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Industrial applicability

The above technical solution provided by the present invention can be applied to an exception processing process, and when an abnormality occurs, the next address of the abnormal instruction is used as the return address of the current abnormality, and the return value of the abnormal instruction is set to an illegal value. The technical means solves the problem that the process stops due to an abnormality in accessing the pcie memory address and the system hangs due to an infinite loop, thereby improving the robustness and survivability of the system.

Claims

An exception handling method, including:

Detecting whether an exception occurs during access to the standard peripheral PCI-E memory memory space.

If yes, the return value corresponding to the exception instruction that caused the exception is set to an illegal value;

The next address of the exception instruction is taken as the return address of the current exception.
The method of claim 1, wherein detecting whether an abnormality occurs during access to the PCI-E storage memory space comprises:

Detecting whether: when accessing the PCI-E storage memory space, an exception caused by the PCI-E storage memory space having no corresponding storage entity, and whether the operation address of the abnormal instruction to be accessed is located The PCI-E stores the address range of the memory space; wherein, if the detection result is YES, it is determined that an abnormality occurs during access to the PCI-E storage memory space.
The method of claim 2, wherein the operation address is obtained by one of:

When it is determined that the current abnormality is an exception caused by loading a load class instruction, acquiring the operation address from the load class instruction; or

The operation address is read from the machine check interrupt status register MCSR.
The method of claim 3, wherein the obtaining the operation address from the load class instruction comprises:

And obtaining, according to a format type of the load class instruction, the operation address from a specified location corresponding to the format type in the load class instruction.
The method according to claim 1, wherein setting a return value corresponding to the abnormal instruction causing the current abnormality to an illegal value comprises:

The illegal value is written in a data register corresponding to the abnormal instruction.
The method according to any one of claims 1 to 5, wherein the abnormality comprises at least one of the following:

The exception caused by loading the load class instruction and the error of reading the data bus on the bus.
An abnormal processing device includes:

The detecting module is configured to detect whether an abnormality occurs during the process of accessing the standard peripheral PCI-E memory memory space;

Set the module to set the return value corresponding to the exception instruction that caused the exception to an illegal value when an exception occurs;

The determining module is set to use the next address of the abnormal instruction as the return address of the current abnormality.
The apparatus of claim 7, wherein the detection module is configured to detect if the following occurs: access When the PCI-E stores the memory space, the abnormality caused by the PCI-E storage memory space does not have a corresponding storage entity, and whether the operation address of the abnormal instruction to be accessed is located in the PCI-E storage memory space. Within the address range; wherein, in the case where the detection result is YES, it is determined that an abnormality occurs during access to the PCI-E storage memory space.
The device according to claim 8, wherein the device further comprises: an obtaining module, configured to acquire the operation address, wherein the obtaining module is further configured to determine that the current abnormality is caused by loading a load class instruction When the exception occurs, the operation address is obtained from the load class instruction; or the operation address is read from the machine check interrupt status register MCSR.
The apparatus according to claim 9, wherein the obtaining module is further configured to acquire the operation address from a specified location corresponding to the format type in the load class instruction according to a format type of the load class instruction. .