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WO2016119380A1 - 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 - Google Patents

薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 Download PDF

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WO2016119380A1
WO2016119380A1 PCT/CN2015/081992 CN2015081992W WO2016119380A1 WO 2016119380 A1 WO2016119380 A1 WO 2016119380A1 CN 2015081992 W CN2015081992 W CN 2015081992W WO 2016119380 A1 WO2016119380 A1 WO 2016119380A1
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Prior art keywords
pattern
oxide semiconductor
metal oxide
thin film
active layer
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PCT/CN2015/081992
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English (en)
French (fr)
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姜春生
李旭远
刘威
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京东方科技集团股份有限公司
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Priority to US14/785,816 priority Critical patent/US9899532B2/en
Priority to EP15790814.6A priority patent/EP3252802B1/en
Publication of WO2016119380A1 publication Critical patent/WO2016119380A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device.
  • CTR cathode ray tube
  • AMLCD Active Matrix Liquid Crystal Display
  • AMOLED Active Matrix Organic Light Emitting Diode
  • TFTs Thin Film Transistors
  • the TFT can be classified into an amorphous silicon TFT, a polycrystalline silicon TFT, a metal oxide TFT, or the like, depending on the material of the active layer in the TFT.
  • Metal oxide TFTs and polysilicon TFTs have higher mobility than amorphous silicon TFTs; whereas with respect to polysilicon TFTs, the fabrication process of metal oxide TFTs is simpler due to the limitations of devices such as ion implantation and laser crystallization, and thus Metal oxide TFTs are widely used in LCD, OLED, and Polymer Light Emitting Diodes (PLEDs).
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device to provide a novel method for preparing a metal oxide semiconductor active layer.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor, the method comprising forming a gate, a gate insulating layer, a metal oxide semiconductor active layer, a source and a drain on a substrate;
  • the forming the metal oxide semiconductor active layer includes: forming the metal oxide semiconductor active layer by an electrochemical reaction.
  • At least one embodiment of the present invention provides a thin film transistor including a gate, a gate insulating layer, a metal oxide semiconductor active layer, a source and a drain; in the thin film transistor, the metal oxide semiconductor active layer is formed by an electrochemical reaction.
  • At least one embodiment of the present invention provides an array substrate including the thin film transistor described above.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising forming a thin film transistor on a substrate, and the method of fabricating the thin film transistor is the method for preparing the thin film transistor described above.
  • At least one embodiment of the present invention provides a display device including the above array substrate.
  • FIG. 1a is a schematic structural view 1 of a thin film transistor according to an embodiment of the present invention.
  • 1b is a schematic structural view 2 of a thin film transistor according to an embodiment of the present invention.
  • 1c is a schematic structural view 3 of a thin film transistor according to an embodiment of the present invention.
  • FIGS. 2a-2e are schematic diagrams showing processes for preparing a metal oxide semiconductor active layer, a source and a drain according to an embodiment of the present invention
  • FIG. 3 is a schematic structural view 1 of an array substrate according to an embodiment of the invention.
  • FIG. 4 is a schematic structural view 2 of an array substrate according to an embodiment of the invention.
  • FIG. 5 is a third schematic structural diagram of an array substrate according to an embodiment of the invention.
  • the metal oxide semiconductor active layer in the preparation of the metal oxide TFT is coated with a metal oxide semiconductor thin film on the substrate, and is patterned by a process other than the active region.
  • the metal oxide semiconductor film is etched away to form a metal oxide semiconductor active layer located in the active region. This makes the preparation method relatively simple.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, the method comprising: forming a gate, a gate insulating layer, a metal oxide semiconductor active layer, a source and a drain on a substrate; and forming the metal oxide
  • the semiconductor active layer includes: forming the metal oxide semiconductor active layer by an electrochemical reaction.
  • the substrate is a substrate, does not belong to a thin film transistor structure, may be a substrate substrate that does not form any other structure, or may form a film structure.
  • the substrate may of course be any substrate of any material or shape, and these embodiments of the invention are not limited in any way.
  • a bottom gate type thin film transistor such as that shown in FIG. 1a and FIG. 1c, and a top gate type thin film transistor as shown in FIG. 1b can be prepared by the above preparation method, but the embodiment of the present invention is It is not limited thereto as long as the metal oxide semiconductor active layer 402 in the thin film transistor is formed by an electrochemical reaction.
  • the relative positions of the metal oxide semiconductor active layer 402 and the source 501 and the drain 502 are not limited, and may be disposed in the same layer or in different layers.
  • the process of the electrochemical reaction and the material of the active region before the electrochemical reaction are not limited as long as the metal oxide semiconductor active layer 402 is formed in the active region by an electrochemical reaction.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, the method comprising: forming a gate 20, a gate insulating layer 30, a metal oxide semiconductor active layer 402, a source 501, and a drain 502 on a substrate 10;
  • the metal oxide semiconductor active layer 402 is formed by an electrochemical reaction.
  • Forming a metal oxide semiconductor active layer located in the active region by coating a metal oxide semiconductor thin film on the substrate and etching the metal oxide semiconductor thin film other than the active region by a patterning process
  • the method of the present invention proposes a new preparation metal oxidation A method of semiconductor active layer 402.
  • the material of the metal oxide semiconductor active layer is a Cu 2 O semiconductor material.
  • the metal oxide semiconductor active layer 402 is Cu 2 O
  • the electrode material for example, the material of the source and the drain
  • the diffusion of Cu and Cu 2 O can form an equilibrium, so that the stability of the semiconductor performance can be ensured, that is, the metal oxide semiconductor active layer 402 is not sensitive to the diffusion effect of the Cu metal.
  • a Cu metal material is formed into the metal oxide semiconductor active layer 402 of a Cu 2 O semiconductor material by an electrochemical reaction.
  • a first pattern of Cu metal material may be formed in the active region, and then the Cu metal material is changed into a Cu 2 O semiconductor material by an electrochemical reaction, thereby forming the first pattern into the metal oxide.
  • the embodiment of the present invention is described by taking, as an example, a metal oxide semiconductor active layer 402 in which a Cu 2 O semiconductor material is formed by electrochemical reaction using a Cu metal material, but is not limited thereto.
  • forming the metal oxide semiconductor active layer may further include: forming a thin film of a metal material on the substrate; changing a thin film of the metal material into a thin film of a metal oxide semiconductor material by an electrochemical reaction; The patterning process removes a thin film of a metal oxide semiconductor material other than the active region, and forms the metal oxide semiconductor active layer in the active region.
  • a thin film of Cu metal material on a substrate, and then the Cu film by an electrochemical reaction of a metal material becomes a thin film semiconductor materials Cu 2 O, and then, Cu is removed by a patterning process in addition to the active region 2 A thin film of a semiconductor material, thereby forming the metal oxide semiconductor active layer 402 in an active region.
  • the step of forming the Cu metal material into the metal oxide semiconductor active layer 402 of the Cu 2 O semiconductor material by an electrochemical reaction can be realized, for example, by: forming Cu by Cu
  • the substrate of the first pattern formed of the metal material is placed in water and energized to cause electrolytic reaction of the Cu metal material with water to form a Cu 2 O semiconductor material, thereby forming the first pattern into the metal oxide semiconductor active layer 402 .
  • the preparation method further includes forming a first pattern of the Cu metal material in the active region by a patterning process.
  • Cu in the first pattern of the active region can form a Cu 2 O semiconductor material, and Cu in the active region After the formation of Cu 2 O, the current is automatically cut off, and the electrolysis reaction process is terminated.
  • the first pattern and the first pattern are The metal oxide semiconductor active layer 402 differs only in the material and its structure is the same.
  • the pattern of the source 501 of the same layer, the pattern of the drain 502, and the first pattern are formed by one patterning process.
  • the pattern of the source 501, the pattern of the drain 502, and The first pattern is formed by one patterning process, that is, the source electrode 501, the drain electrode 502, and the metal oxide semiconductor active layer 402 are formed by one patterning process, and thus are formed by two patterning processes.
  • the embodiment of the present invention reduces the number of patterning processes.
  • the embodiment of the present invention is used for forming the above manner in order to additionally form an etch stop layer in order to avoid the influence on the metal oxide semiconductor active layer 402 when etching the source 501 and the drain 502.
  • the first pattern of the metal oxide semiconductor active layer 402 and the pattern of the source 501 and the pattern of the drain 502 are simultaneously formed, so that it is no longer necessary to prepare an etch barrier layer, so that the number of patterning processes can be further reduced.
  • the etch barrier layer since the source 501 and the drain 502 need to be connected to the MOS active layer 402, the etch barrier layer includes the source 501 and the metal.
  • the size of the thin film transistor is limited; since there is no such limitation in the embodiment of the present invention, the size of the thin film transistor can be reduced, thereby satisfying the high PPI (Pixels) Per Inch, the number of pixels per inch).
  • the pattern of the source 501, the pattern of the drain 502, and the first pattern formed by the one-time patterning process may be realized, for example, by forming a Cu metal on the substrate. a thin film; performing a halftone mask process on the Cu metal film, forming a pattern of the source 501, a pattern of the drain 502, and a first pattern in the active region; in this step, Other patterns formed of the Cu metal film are covered with a photoresist in addition to the first pattern before the electrochemical reaction.
  • the Cu metal film is subjected to a halftone mask process to form a pattern of the source 501, a pattern of the drain 502, and the first pattern located in the active region may pass
  • a halftone mask process to form a pattern of the source 501, a pattern of the drain 502, and the first pattern located in the active region may pass.
  • a photoresist 60 is formed on the substrate on which the Cu metal thin film 45 is formed.
  • the photoresist is completely retained. a portion 601, a photoresist semi-retaining portion 602 and a photoresist completely removing portion 603; the photoresist completely remaining portion 601 corresponding to the source 501 pattern to be formed and the region of the drain 502 pattern,
  • the photoresist half-retaining portion 602 corresponds to the active region
  • the photoresist completely removed portion 603 corresponds to a region where the Cu metal pattern is not formed and other regions than the active region.
  • the half-order mask 70 includes a completely opaque portion 701, a translucent portion 702, and a completely transparent portion 703; for example, a half-order mask 70 refers to a certain area on a transparent substrate material.
  • the working principle of the half-order mask 70 is explained as follows: by controlling the thickness of the light-shielding metal layer at different regions on the half-stage mask 70, the intensity of transmitted light in different regions is different. So that the photoresist 60 is selectively exposed and developed, and formed into a completely opaque portion 701, a translucent portion 702, and a completely transparent portion 703 of the half-order mask 70, respectively. The corresponding photoresist completely remains portion 601, the photoresist half-retained portion 602, and the photoresist completely removed portion 603.
  • the principle of the gray scale mask is similar to that of the half mask 70.
  • the photoresists 60 referred to in all embodiments of the present invention are positive gels.
  • the Cu metal film corresponding to the photoresist completely removed portion 603 is removed by an etching process to form a pattern of the source 501 and the drain 502. a pattern, and the first pattern 401 located in the active region.
  • the photoresist corresponding to the photoresist semi-retained portion 602 is removed by an ashing process.
  • the substrate obtained after S04 is placed in water and energized, and the exposed Cu metal material at the first pattern 401 is electrolytically reacted with water to form a Cu 2 O semiconductor material, thereby
  • the first pattern 401 is formed as the metal oxide semiconductor active layer 402, and after the photoresist of the photoresist completely remaining portion 601 is removed, the source 501 and the drain 502 as shown in FIG. 2e are obtained.
  • FIGS. 2a-2d only schematically illustrate the process of forming the source 501, the drain 502, and the metal oxide semiconductor active layer 402.
  • the thin film transistor as shown in FIG. 1a, it may be formed in the formation.
  • the gate electrode 20 and the gate insulating layer 30 are formed on the substrate 10 before the source electrode 501, the drain electrode 502, and the metal oxide semiconductor active layer 402.
  • the gate electrode 20 and the gate insulating layer 30 may be formed after the source electrode 501, the drain electrode 502, and the metal oxide semiconductor active layer 402 are formed, which is not limited.
  • the gate insulating layer 30 includes at least a contact with the metal oxide semiconductor active layer 402. TiO 2 and / or Al 2 O 3 layer.
  • a TiO 2 or Al 2 O 3 layer is provided on, for example, the uppermost layer of the gate insulating layer 30, so that the subsequently formed Cu metal film is bonded to the substrate.
  • the metal oxide semiconductor active layer 402 of the formed Cu 2 O material is more stable in performance.
  • the embodiment of the invention further provides a method for preparing an array substrate, comprising the method for preparing the above thin film transistor.
  • the array substrate according to the embodiment of the present invention may be an array substrate of a liquid crystal display,
  • the method of fabricating the array substrate may further include: forming a pixel electrode 801 electrically connected to the drain 502 as shown in FIG.
  • the array substrate provided by the embodiment of the invention is suitable for the production of an Advanced Super Dimensional Switching (ADS) type liquid crystal display device.
  • ADS Advanced Super Dimensional Switching
  • the core technical characteristics of the advanced super-dimensional field conversion technology are described as: forming an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate-like electrode layer to form a multi-dimensional electric field, so that the slit electrode in the liquid crystal cell All of the aligned liquid crystal molecules directly above the electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no Push Mura. advantage.
  • the method of fabricating the array substrate may further include: forming a common electrode 802 and a passivation layer as shown in FIG.
  • the array substrate of the embodiment of the present invention may also be an array substrate of an organic electroluminescent diode display (OLED).
  • the method for preparing the array substrate may further include: forming as shown in FIG. An anode 901 electrically connected to the drain 502, an organic material functional layer 902 located above the anode 901, and a cathode 903 above the organic material functional layer 902.
  • the organic material functional layer 902 may include: a hole transport layer, a light emitting layer, and an electron transport layer; for example, in order to improve the efficiency of electron and hole injection into the light emitting layer, the organic material functional layer may further include An electron injection layer between the cathode 903 and the electron transport layer, and a hole injection layer disposed between the anode 901 and the hole transport layer.
  • the material of the anode 901 and the cathode 903 it can be divided into a single-sided light-emitting array substrate and a double-sided light-emitting array substrate; that is, a material of one of the anode 901 and the cathode 903.
  • the array substrate is of a single-sided illumination type; when the materials of the anode 901 and the cathode 903 are both transparent materials and/or translucent materials, the array substrate is a double-sided illumination type.
  • the single-sided light-emitting array substrate can be further classified into an upper light-emitting type and a lower light-emitting type depending on the materials of the anode 901 and the cathode 903. For example, when the anode 901 is formed near the substrate substrate 10, the cathode 903 is formed away from the substrate substrate 10, and the material of the anode 901 is a transparent conductive material, and the material of the cathode 903 is opaque conductive.
  • the anode 901 In the case of light, since light is emitted from the anode 901 and then through the substrate substrate 10 side, it may be referred to as a lower emission type;
  • the material of the anode 901 is an opaque conductive material, and when the material of the cathode 903 is a transparent or translucent conductive material, since light is emitted from the side of the cathode 903 away from the substrate substrate 10, it may be referred to as an upper emission type.
  • the relative positions of the above two anodes 901 and 903 can also be replaced, and will be further described herein.
  • the cathode 903 is formed away from the substrate substrate 10, and the materials of the anode 901 and the cathode 903 are both
  • the materials of the anode 901 and the cathode 903 are both
  • the anode 901 is formed away from the substrate substrate 10
  • the cathode 903 is formed close to the substrate substrate 10.
  • the embodiment of the present invention further provides a thin film transistor, as shown in FIGS. 1a, 1b, and 1c, the thin film transistor includes a gate electrode 20, a gate insulating layer 30, a metal oxide semiconductor active layer 402, a source 501, and a drain. 502; the metal oxide semiconductor active layer 402 is formed by an electrochemical reaction.
  • the embodiment of the present invention does not limit the type of the thin film transistor, and may be a bottom gate type or a top gate type.
  • the relative positions of the metal oxide semiconductor active layer 402, the source 501, and the drain 502 are not limited, and may be disposed in the same layer or in different layers.
  • the process of the electrochemical reaction and the material of the active region before the electrochemical reaction are not limited as long as the metal oxide semiconductor active layer 402 is formed in the active region by an electrochemical reaction.
  • the thin film transistor may include a substrate 10 on which the gate electrode 20, the gate insulating layer 30, the metal oxide semiconductor active layer 402, the source electrode 501, and the drain electrode 502 are disposed.
  • the substrate may be a substrate substrate that does not form any other structure, or may be a substrate formed with some film layer structure.
  • Embodiments of the present invention provide a thin film transistor including a gate electrode 20, a gate insulating layer 30, a metal oxide semiconductor active layer 402, a source electrode 501, and a drain electrode 502; the metal oxide semiconductor active layer 402 is electrically A chemical reaction is formed.
  • a method of forming a metal oxide semiconductor active layer located in an active region by etching a metal oxide semiconductor thin film other than the active region by a patterning process by coating a metal oxide semiconductor thin film on a substrate The embodiment of the present invention proposes a new method for preparing the metal oxide semiconductor active layer 402.
  • the metal oxide semiconductor active layer 402 is a Cu 2 O semiconductor material.
  • the metal oxide semiconductor active layer 402 Since the material of the metal oxide semiconductor active layer 402 is Cu 2 O, the metal oxide semiconductor active layer 402 is not sensitive to the diffusion effect of the Cu metal even if the electrode material uses Cu metal.
  • the metal oxide semiconductor active layer 402 the source 501 and the drain 502 are disposed in the same layer; the source 501 and the drain 502
  • the material is Cu metal material.
  • a pattern of the source 501 using the Cu metal material and the same layer, a pattern of the drain 502, and the source can be formed by one patterning process.
  • the pattern between the pattern of the pole 501 and the pattern of the drain 502 is the first pattern 401 mentioned above, and then the Cu metal material at the first pattern 401 can be changed into a Cu 2 O semiconductor material by electrochemical reaction.
  • the first pattern 401 is thus formed as the metal oxide semiconductor active layer 402.
  • the pattern of the source 501 and the drain 502 are The pattern and the first pattern are formed by one patterning process, that is, the source electrode 501, the drain electrode 502, and the metal oxide semiconductor active layer 402 are formed by one patterning process, and thus, by two passes.
  • the patterning process forms the source 501, the drain 502, and the metal oxide semiconductor active layer 402, and the embodiment of the present invention reduces the number of patterning processes.
  • the embodiment of the present invention is used for forming the above manner in order to additionally form an etch stop layer in order to avoid the influence on the metal oxide semiconductor active layer 402 when etching the source 501 and the drain 502.
  • the first pattern 401 of the metal oxide semiconductor active layer 402 and the pattern of the source 501 and the pattern of the drain 502 are simultaneously formed, so that it is no longer necessary to prepare an etch barrier layer, thereby further reducing the number of patterning processes.
  • the etch barrier layer may include the source 501 and the a first via connected to the metal oxide semiconductor active layer 402 and a second via for connecting the drain 502 to the metal oxide semiconductor active layer 402, and the first via and the second via distance It is not too close, so that the size of the thin film transistor is limited; since there is no such limitation in the embodiment of the present invention, the size of the thin film transistor can be reduced, so that the demand of high PPI can be satisfied.
  • the gate insulating layer 30 includes at least a TiO 2 and/or Al 2 O 3 layer in contact with the metal oxide semiconductor active layer 402, the source electrode 501, and the drain electrode 502.
  • a TiO 2 or Al 2 O 3 layer is provided on, for example, the uppermost layer of the gate insulating layer 30, so that the subsequently formed Cu metal film is bonded to the substrate.
  • the metal oxide semiconductor active layer 402 of the formed Cu 2 O material, the source 501 and the drain 502 of the Cu metal material are more stable.
  • Embodiments of the present invention also provide an array substrate including the above-described thin film transistor.
  • the array substrate according to the embodiment of the present invention may be an array substrate of a liquid crystal display.
  • the array substrate may further include a pixel electrode 801 electrically connected to the drain 502.
  • the array substrate may further include a common electrode 802 and a passivation layer.
  • the array substrate of the embodiment of the present invention may also be an array substrate of an organic electroluminescent diode display.
  • the array substrate further includes an electrical connection with the drain 502.
  • one of the sub-pixels generally includes two thin film transistors, that is, a switching thin film transistor and a driving thin film transistor; the gate 20 of the switching thin film transistor is electrically connected to the gate line, and the source of the switching thin film transistor
  • the pole 501 is electrically connected to the data line.
  • the drain 502 of the switching thin film transistor is electrically connected to the gate 20 of the driving thin film transistor.
  • the source 501 of the driving thin film transistor is electrically connected to the power line, and the drain 502 and the anode 901 of the driving thin film transistor are electrically connected. connection.
  • the method of forming the same applies to the above-described method of fabricating the thin film transistor.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • the display device when the array substrate can be an array substrate of a liquid crystal display device, the display device further includes an opposite substrate (eg, a color filter substrate), and a liquid crystal layer between the array substrate and the opposite substrate.
  • an opposite substrate eg, a color filter substrate
  • the display device When the array substrate is an array substrate of an organic electroluminescent diode display, the display device further includes a package substrate.
  • the display device provided by the embodiment of the invention may be: LCD panel, electronic paper, OLED panel, liquid crystal television, liquid crystal display, digital photo frame, mobile phone, tablet computer, etc. Product or component.

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Abstract

一种薄膜晶体管及制备方法、阵列基板及制备方法、显示装置，该薄膜晶体管的制备方法包括：在基板(10)上形成栅极(20)、栅绝缘层(30)、金属氧化物半导体有源层(402)、源极(501)和漏极(502)；所述形成金属氧化物半导体有源层(402)包括：通过电化学反应形成所述金属氧化物半导体有源层(402)。该薄膜晶体管的制备方法用于薄膜晶体管、包含该薄膜晶体管的阵列基板及显示装置的制造，以提出一种新的制备金属氧化物半导体有源层的方法。

Description

薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 技术领域
本发明实施例涉及一种薄膜晶体管及制备方法、阵列基板及制备方法、显示装置。
背景技术
近年来，显示技术的发展日新月异，早期的阴极射线管(Cathode Ray Tube，简称CRT)显示器也已经被有源矩阵型显示器例如有源矩阵液晶显示器(Active Matrix Liquid Crystal Display，简称AMLCD)、有源矩阵有机发光二极管显示器(Active Matrix Organic Light Emitting Diode，简称AMOLED)所取代。在这些有源矩阵型显示器中，薄膜晶体管(Thin Film Transistor，TFT)作为有源矩阵显示技术的核心器件受到了极大的关注并被广泛应用。
根据TFT中有源层材料的不同，TFT可以分为非晶硅TFT、多晶硅TFT、金属氧化物TFT等。金属氧化物TFT和多晶硅TFT比非晶硅TFT具有更高的迁移率；而相对于多晶硅TFT，金属氧化物TFT的制作工艺由于没有离子注入及激光晶化等设备的限制而更为简单，因而，金属氧化物TFT被广泛的应用于LCD、OLED、以及高分子发光二极管显示器(Polymer Light Emitting Diode，简称PLED)。
发明内容
本发明的实施例提供一种薄膜晶体管及制备方法、阵列基板及制备方法、显示装置，以提出一种新的制备金属氧化物半导体有源层的方法。
一方面，本发明的至少一个实施例提供一种薄膜晶体管的制备方法，该方法包括在基板上形成栅极、栅绝缘层、金属氧化物半导体有源层、源极和漏极；在该方法中，所述形成金属氧化物半导体有源层包括：通过电化学反应形成所述金属氧化物半导体有源层。
另一方面，本发明的至少一个实施例提供一种薄膜晶体管，其包括栅极、 栅绝缘层、金属氧化物半导体有源层、源极和漏极；在该薄膜晶体管中，所述金属氧化物半导体有源层通过电化学反应形成。
再一方面，本发明的至少一个实施例提供一种阵列基板，其包括上述的薄膜晶体管。
又一方面，本发明的至少一个实施例提供一种阵列基板的制备方法，其包括在基板上形成薄膜晶体管，所述薄膜晶体管的制备方法为上述的薄膜晶体管的制备方法。
又一方面，本发明的至少一个实施例提供一种显示装置，其包括上述的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为本发明实施例提供的一种薄膜晶体管的结构示意图一；
图1b为本发明实施例提供的一种薄膜晶体管的结构示意图二；
图1c为本发明实施例提供的一种薄膜晶体管的结构示意图三；
图2a-2e为本发明实施例提供的一种制备金属氧化物半导体有源层、源极和漏极的过程示意图；
图3为发明实施例提供的一种阵列基板的结构示意图一；
图4为发明实施例提供的一种阵列基板的结构示意图二；
图5为发明实施例提供的一种阵列基板的结构示意图三。
附图说明：
10-基板；20-栅极；30-栅绝缘层；401-第一图案；402-金属氧化物半导体有源层；501-源极；502-漏极；45-Cu金属薄膜；60-光刻胶；601-光刻胶完全保留部分；602-光刻胶半保留部分；603-光刻胶完全去除部分；70-半阶掩膜板；701-完全不透明部分；702-半透明部分；703-完全透明部分；801-像素电极；802-公共电极；901-阳极；902-有机材料功能层；903-阴极。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
在研究中，本申请的发明人注意到，目前，制备金属氧化物TFT中的金属氧化物半导体有源层是在基板上涂布金属氧化物半导体薄膜，通过构图工艺将除有源区外的所述金属氧化物半导体薄膜刻蚀掉，从而形成位于有源区的金属氧化物半导体有源层。这使得制备方法比较单一。
本发明实施例提供了一种薄膜晶体管的制备方法，该方法包括：在基板上形成栅极、栅绝缘层、金属氧化物半导体有源层、源极和漏极；并且，所述形成金属氧化物半导体有源层包括：通过电化学反应形成所述金属氧化物半导体有源层。本发明实施例的薄膜晶体管的制备方法中，所述基板是作为衬底存在的，不属于薄膜晶体管的结构，可以是未形成任何其他结构的衬底基板，也可以是形成有一些膜层结构的基板，当然也可以是任何材质或形状的基板，这些本发明实施例不做任何限定。
需要说明的是，第一，通过上述制备方法可以制备得到例如如图1a和如图1c所示的底栅型薄膜晶体管、如图1b所示的顶栅型薄膜晶体管，但本发明实施例并不限于此，只要薄膜晶体管中的金属氧化物半导体有源层402是通过电化学反应形成即可。
本发明实施例中，并不对金属氧化物半导体有源层402和源极501、漏极502的相对位置进行限定，可以同层设置也可以不同层设置。
第二，不对电化学反应的过程以及电化学反应前有源区的材料进行限定，只要通过电化学反应在有源区形成所述金属氧化物半导体有源层402即可。
本发明实施例提供了一种薄膜晶体管的制备方法，该方法包括：在基板10上形成栅极20、栅绝缘层30、金属氧化物半导体有源层402、源极501和漏极502；在该方法中，通过电化学反应形成所述金属氧化物半导体有源层402。相对于通过在基板上涂布金属氧化物半导体薄膜，并通过构图工艺将除有源区外的所述金属氧化物半导体薄膜刻蚀掉，从而形成位于有源区的金属氧化物半导体有源层的方式，本发明实施例提出一种新的制备金属氧化 物半导体有源层402的方法。
例如，所述金属氧化物半导体有源层的材料为Cu2O半导体材料。
通常，Cu金属扩散进入非晶硅或多晶硅等半导体层时，可能导致半导体材料导体化，或者即便半导体材料没有达到导体的迁移率，也会影响半导体的性能。在本发明实施例中，由于所述金属氧化物半导体有源层402的材料是Cu2O，因此，即使电极材料(例如源极和漏极的材料)使用Cu金属，Cu2O和Cu金属接触时，Cu的扩散和Cu2O可以形成平衡，从而可以保证半导体性能的稳定，也就是说，所述金属氧化物半导体有源层402不会对Cu金属的扩散效果敏感。
进一步的，考虑到Cu金属在自然界中储备比较多且相对较便宜，因此，例如，通过电化学反应将Cu金属材料形成为Cu2O半导体材料的所述金属氧化物半导体有源层402。
在此基础上，可以先在有源区形成Cu金属材料的第一图案，然后通过电化学反应将Cu金属材料变为Cu2O半导体材料，从而使所述第一图案形成为所述金属氧化物半导体有源层402。也就是说，在至少一个实施例中，形成所述金属氧化物半导体有源层可以包括：在所述基板上形成金属薄膜；对所述金属薄膜进行一次构图工艺，形成位于所述有源区的第一图案；以及进行所述电化学反应，使所述第一图案形成所述金属氧化物半导体有源层。本发明的实施例仅以利用Cu金属材料通过电化学反应形成Cu2O半导体材料的金属氧化物半导体有源层402为例进行说明，但不限于此。
当然，形成所述金属氧化物半导体有源层也可以包括：在所述基板上形成金属材料的薄膜；通过电化学反应将所述金属材料的薄膜变为金属氧化物半导体材料的薄膜；以及通过构图工艺去掉除有源区之外的金属氧化物半导体材料的薄膜，并在有源区形成所述金属氧化物半导体有源层。例如，可以先在基板上形成Cu金属材料的薄膜，然后通过电化学反应将Cu金属材料的薄膜变为Cu2O半导体材料的薄膜，然后，通过构图工艺去掉除有源区之外的Cu2O半导体材料的薄膜，从而在有源区形成所述金属氧化物半导体有源层402。
基于上述两种实现方式，相比第二种先将整个Cu金属材料的薄膜变为Cu2O半导体材料的薄膜，然后再去除掉非有源区的Cu2O半导体材料的薄膜， 第一种方式更为简单，因而，所述通过电化学反应将Cu金属材料形成为Cu2O半导体材料的所述金属氧化物半导体有源层402的步骤，例如可以通过如下方式实现：将形成有由Cu金属材料形成的第一图案的基板放入水中并通电，使Cu金属材料与水发生电解反应形成Cu2O半导体材料，从而使所述第一图案形成为所述金属氧化物半导体有源层402。
例如，在将形成有所述第一图案的基板放入水中之前，所述制备方法还包括：通过构图工艺在所述有源区形成所述Cu金属材料的第一图案。
这里，由于O元素在Cu中有优秀的扩散性能和自发的反应特性，因此，位于有源区的第一图案中的Cu都可以形成Cu2O半导体材料，且在有源区中的Cu都形成Cu2O后，会自动截断电流，结束电解反应过程。
需要说明的是，由于从第一图案到所述金属氧化物半导体有源层402仅仅是将第一图案中的Cu金属材料变为Cu2O半导体材料，因而，所述第一图案与所述金属氧化物半导体有源层402的区别仅仅在于材料的不同，其结构是相同的。
例如，通过一次构图工艺形成同层的所述源极501的图案、所述漏极502的图案和所述第一图案。
这里，当第一图案形成后，由于从第一图案到所述金属氧化物半导体有源层402只需经过电化学反应，因而，所述源极501的图案、所述漏极502的图案和所述第一图案通过一次构图工艺形成也即是所述源极501、所述漏极502和所述金属氧化物半导体有源层402通过一次构图工艺形成，因此，相对通过两次构图工艺形成所述源极501、所述漏极502和所述金属氧化物半导体有源层402的方式，本发明实施例减小了构图工艺次数。
在此基础上，相对于为了避免刻蚀源极501和漏极502时对金属氧化物半导体有源层402的影响而额外形成刻蚀阻挡层的方式，本发明实施例由于用于形成所述金属氧化物半导体有源层402的第一图案和源极501的图案、漏极502的图案同时形成，因而无需再制备刻蚀阻挡层，从而可以进一步的减少了构图工艺次数。另外，在形成刻蚀阻挡层的方式中，由于源极501和漏极502需要与金属氧化物半导体有源层402连接，因而，上述刻蚀阻挡层包括用于使源极501与所述金属氧化物半导体有源层402连接的第一过孔和用于使漏极502与所述金属氧化物半导体有源层402连接的第二过孔，而第 一过孔和第二过孔距离不能太近，从而使得薄膜晶体管的尺寸受到限制；本发明实施例由于没有这方面的限制，因此，可以减小薄膜晶体管的尺寸，从而可以满足高PPI(Pixels Per Inch，每英寸所拥有的像素数目)的需求。
进一步的，所述通过一次构图工艺形成同层的所述源极501的图案、所述漏极502的图案和所述第一图案，例如可以通过如下过程实现：在所述基板上形成Cu金属薄膜；对所述Cu金属薄膜进行一次半色调掩膜工艺，形成所述源极501的图案、所述漏极502的图案，以及位于所述有源区的第一图案；在该步骤中，在进行电化学反应前，除所述第一图案外，由所述Cu金属薄膜形成的其他图案被光刻胶覆盖。
例如，所述对所述Cu金属薄膜进行一次半色调掩膜工艺，形成所述源极501的图案、所述漏极502的图案，以及位于所述有源区的所述第一图案可以通过如下步骤S01～S04实现，下面详细介绍这些步骤。
S01、如图2a所示，在形成有所述Cu金属薄膜45的基板上形成光刻胶60。
S02、在完成S01的基板上，如图2b所示，采用半阶掩膜板70或灰阶掩膜板对形成有所述光刻胶的基板进行曝光、显影后，形成光刻胶完全保留部分601、光刻胶半保留部分602和光刻胶完全去除部分603；所述光刻胶完全保留部分601对应待形成的所述源极501图案和所述漏极502图案的区域，所述光刻胶半保留部分602对应所述有源区，所述光刻胶完全去除部分603对应不形成Cu金属图案的区域和有源区以外的其他区域。
参考图2b所示，所述半阶掩膜板70包括完全不透明部分701、半透明部分702、完全透明部分703；例如：半阶掩膜板70是指在透明衬底材料上在某些区域形成不透光的遮光金属层，在另外一些区域形成半透光的遮光金属层，其他区域不形成任何遮光金属层；所述半透光的遮光金属层的厚度小于所述完全不透光的遮光金属层的厚度；此外，可以通过调节所述半透光的遮光金属层的厚度来改变所述半透光的遮光金属层对例如紫外光的透过率。
基于此，所述半阶掩膜板70工作原理说明如下：通过控制所述半阶掩膜板70上不同区域处遮光金属层的厚度，使曝光在不同区域的透过光的强度有所不同，从而使光刻胶60进行有选择性的曝光、显影后，形成与所述半阶掩膜板70的完全不透明部分701、半透明部分702以及完全透明部分703分别 对应的光刻胶完全保留部分601、光刻胶半保留部分602、光刻胶完全去除部分603。
所述灰阶掩膜板的原理与所述半阶掩膜板70的原理类似。
本发明所有实施例中所指的所述光刻胶60均为正性胶。
S03、在完成S02的基板上，如图2c所示，采用刻蚀工艺去除所述光刻胶完全去除部分603对应的Cu金属薄膜，形成所述源极501的图案和所述漏极502的图案，以及位于所述有源区的所述第一图案401。
S04、在完成S03的基板上，如图2d所示，采用灰化工艺去除所述光刻胶半保留部分602对应的光刻胶。
在上述S01-S04的基础上，通过将S04后得到的基板放入水中并通电，使露出的所述第一图案401处的Cu金属材料与水发生电解反应形成Cu2O半导体材料，从而使所述第一图案401形成为所述金属氧化物半导体有源层402，并在去除掉光刻胶完全保留部分601的光刻胶后，得到如图2e所示的源极501、漏极502和金属氧化物半导体有源层402同层的结构。
需要说明的是，图2a-2d仅示意性的绘示出形成源极501、漏极502和金属氧化物半导体有源层402的过程，对于薄膜晶体管，参考图1a所示，可以在形成所述源极501、漏极502和金属氧化物半导体有源层402之前先在基板10上形成栅极20和栅绝缘层30。当然，如图1b所述，也可在形成所述源极501、漏极502和金属氧化物半导体有源层402之后再形成所述栅极20和栅绝缘层30，具体不做限定。
基于上述，当所述金属氧化物半导体有源层402的Cu2O是由Cu经过电化学反应形成时，例如，所述栅绝缘层30至少包括与所述金属氧化物半导体有源层402接触的TiO2和/或Al2O3层。
由于TiO2或Al2O3与Cu金属的结合性很好，因此，在所述栅绝缘层30的例如最上层设置TiO2或Al2O3层，使后续形成的Cu金属薄膜与基板结合的较好，从而使形成的Cu2O材料的所述金属氧化物半导体有源层402性能更为稳定。
本发明实施例还提供了一种阵列基板的制备方法，包括上述薄膜晶体管的制备方法。
例如，本发明实施例所述的阵列基板可以是液晶显示器的阵列基板，在 此情况下，该阵列基板的制备方法还可以包括：形成如图3所示的与所述漏极502电连接的像素电极801。
进一步的，本发明实施例提供的阵列基板适用于高级超维场转换技术(Advanced Super Dimensional Switching，简称ADS)型液晶显示装置的生产。高级超维场转换技术的核心技术特性描述为：通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。高级超维场转换技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(Push Mura)等优点。
因此，例如，所述阵列基板的制备方法还可以包括：形成如图4所示的公共电极802和钝化层。
当然，本发明实施例所述的阵列基板还可以是有机电致发光二极管显示器(OLED)的阵列基板，在此情况下，例如，该阵列基板的制备方法还可以包括：形成如图5所示的与所述漏极502电连接的阳极901、位于阳极901上方的有机材料功能层902、位于所述有机材料功能层902上方的阴极903。
例如，所述有机材料功能层902可以包括：空穴传输层、发光层和电子传输层；例如，为了能够提高电子和空穴注入发光层的效率，所述有机材料功能层还可以包括设置在所述阴极903与所述电子传输层之间的电子注入层，以及设置在所述阳极901与所述空穴传输层之间的空穴注入层。
根据所述阳极901和所述阴极903的材料的不同，可以分为单面发光型阵列基板和双面发光型阵列基板；即：当所述阳极901和所述阴极903中其中一个电极的材料为不透明或半透明材料时，所述阵列基板为单面发光型；当所述阳极901和所述阴极903的材料均为透明材料和/或半透明材料时，所阵列基板为双面发光型。
对于单面发光型阵列基板，根据所述阳极901和所述阴极903的材料的不同，又可以分为上发光型和下发光型。例如，当所述阳极901靠近所述衬底基底10形成，所述阴极903远离所述衬底基底10形成，且所述阳极901的材料为透明导电材料，所述阴极903的材料为不透明导电材料时，由于光从阳极901、再经衬底基底10一侧出射，因此，可以称为下发光型；当所述 阳极901的材料为不透明导电材料，所述阴极903的材料为透明或半透明导电材料时，由于光从阴极903远离衬底基底10一侧出射，因此，可以称为上发光型。当然，也可以将上述两种阳极901和阴极903的相对位置进行替换，在此再赘述。
对于双面发光型阵列基板，例如，当所述阳极901靠近所述衬底基底10形成，所述阴极903远离所述衬底基底10形成，且所述阳极901和所述阴极903的材料均为透明导电和/或半透明材料时，由于光一方面从阳极901、再经衬底基底10一侧出射，另一方面从阴极903远离衬底基底10一侧出射，因此可以称为双面发光型。这里，也可以是所述阳极901远离所述衬底基底10形成，所述阴极903靠近所述衬底基底10形成。
本发明实施例还提供了一种薄膜晶体管，如图1a、1b、1c所示，该薄膜晶体管包括栅极20、栅绝缘层30、金属氧化物半导体有源层402、源极501和漏极502；所述金属氧化物半导体有源层402通过电化学反应形成。
需要说明的是，第一，本发明实施例不对所述薄膜晶体管的类型进行限定，其可以是底栅型也可以是顶栅型。
第二，不对所述金属氧化物半导体有源层402和源极501、漏极502的相对位置进行限定，可以同层设置也可以不同层设置。
第三，不对电化学反应的过程以及电化学反应前有源区的材料进行限定，只要通过电化学反应在有源区形成所述金属氧化物半导体有源层402即可。
第四，在一些实施例中，薄膜晶体管可以包括基板10，栅极20、栅绝缘层30、金属氧化物半导体有源层402、源极501和漏极502设置在该基板10上。所述基板可以是未形成任何其他结构的衬底基板，也可以是形成有一些膜层结构的基板。
本发明实施例提供了一种薄膜晶体管，包括栅极20、栅绝缘层30、金属氧化物半导体有源层402、源极501和漏极502；所述金属氧化物半导体有源层402通过电化学反应形成。相对通过在基板上涂布金属氧化物半导体薄膜，通过构图工艺将除有源区外的所述金属氧化物半导体薄膜刻蚀掉，从而形成位于有源区的金属氧化物半导体有源层的方式，本发明实施例提出一种新的制备金属氧化物半导体有源层402的方法。
例如，所述金属氧化物半导体有源层402为Cu2O半导体材料。
由于所述金属氧化物半导体有源层402的材料是Cu2O，因此，即使电极材料使用Cu金属，所述金属氧化物半导体有源层402也不会对Cu金属的扩散效果敏感。
进一步的，例如，如图1a、1b所示，所述金属氧化物半导体有源层402、所述源极501和所述漏极502同层设置；所述源极501和所述漏极502的材料为Cu金属材料。
由于Cu金属通过电化学反应可以生成Cu2O半导体，因此，可以通过一次构图工艺形成采用Cu金属材料且同层的所述源极501的图案、所述漏极502的图案以及位于所述源极501的图案、所述漏极502的图案之间的图案即上面提到的第一图案401，然后可将第一图案401处的Cu金属材料通过电化学反应变为Cu2O半导体材料，从而将第一图案401形成为所述金属氧化物半导体有源层402。
这里，当第一图案401形成后，由于从第一图案401到所述金属氧化物半导体有源层402只需经过电化学反应，因而，所述源极501的图案、所述漏极502的图案和所述第一图案通过一次构图工艺形成也即是所述源极501、所述漏极502和所述金属氧化物半导体有源层402通过一次构图工艺形成，因此，相对于通过两次构图工艺形成所述源极501、所述漏极502和所述金属氧化物半导体有源层402的方式，本发明实施例减小了构图工艺次数。
在此基础上，相对于为了避免刻蚀源极501和漏极502时对金属氧化物半导体有源层402的影响而额外形成刻蚀阻挡层的方式，本发明实施例由于用于形成所述金属氧化物半导体有源层402的第一图案401和源极501的图案、漏极502的图案同时形成，因而无需再制备刻蚀阻挡层，从而进一步的减少了构图工艺次数。另外，在形成刻蚀阻挡层的方式中，由于源极501和漏极502需要与金属氧化物半导体有源层402连接，因而，上述刻蚀阻挡层可以包括用于使源极501与所述金属氧化物半导体有源层402连接的第一过孔和用于使漏极502与所述金属氧化物半导体有源层402连接的第二过孔，而第一过孔和第二过孔距离不能太近，从而使得薄膜晶体管的尺寸受到限制；本发明实施例由于没有这方面的限制，因此，可以减小薄膜晶体管的尺寸，从而可以满足高PPI的需求。
进一步的，例如，所述栅绝缘层30至少包括与所述金属氧化物半导体有 源层402、所述源极501和所述漏极502接触的TiO2和/或Al2O3层。
由于TiO2或Al2O3与Cu金属的结合性很好，因此，在所述栅绝缘层30的例如最上层设置TiO2或Al2O3层，使后续形成的Cu金属薄膜与基板结合的较好，从而使形成的Cu2O材料的所述金属氧化物半导体有源层402、Cu金属材料的源极501和漏极502更为性能稳定。
本发明实施例还提供了一种阵列基板，包括上述的薄膜晶体管。
例如，本发明实施例所述的阵列基板可以是液晶显示器的阵列基板，在此情况下，如图3所示，该阵列基板还可以包括与所述漏极502电连接的像素电极801。
进一步的，如图4所示，所述阵列基板还可以包括公共电极802和钝化层。
当然，本发明实施例所述的阵列基板还可以是有机电致发光二极管显示器的阵列基板，在此情况下，例如，如图5所示，该阵列基板还包括与所述漏极502电连接的阳极901、位于阳极901上方的有机材料功能层902、位于所述有机材料功能层902上方的阴极903。
对于有机电致发光二极管显示器的阵列基板，其中的一个子像素一般包括两个薄膜晶体管，即开关薄膜晶体管和驱动薄膜晶体管；开关薄膜晶体管的栅极20与栅线电连接，开关薄膜晶体管的源极501与数据线电连接，开关薄膜晶体管的漏极502与驱动薄膜晶体管的栅极20电连接，驱动薄膜晶体管的源极501与电源线电连接，驱动薄膜晶体管的漏极502与阳极901电连接。
这里需要说明的是，不管薄膜晶体管是开关薄膜晶体管还是驱动薄膜晶体管，其形成方法均适用上述薄膜晶体管的制备方法。
本发明实施例还提供了一种显示装置，其包括上述的阵列基板。
例如，当该阵列基板可以为液晶显示装置的阵列基板时，该显示装置还包括对置基板(例如彩膜基板)，以及位于阵列基板和对置基板之间的液晶层。
当该阵列基板为有机电致发光二极管显示器的阵列基板时，该显示装置还包括封装基板。
本发明实施例所提供的显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功 能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年1月28日递交的中国专利申请第201510044070.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种薄膜晶体管的制备方法，包括：在基板上形成栅极、栅绝缘层、金属氧化物半导体有源层、源极和漏极；其中，所述形成金属氧化物半导体有源层，包括：
    通过电化学反应形成所述金属氧化物半导体有源层。
  2. 根据权利要求1所述的制备方法，其中，所述金属氧化物半导体有源层的材料为Cu2O半导体材料。
  3. 根据权利要求2所述的制备方法，其中，通过电化学反应将Cu金属材料形成为Cu2O半导体材料的所述金属氧化物半导体有源层。
  4. 根据权利要求3所述的制备方法，其中，所述通过电化学反应将Cu金属材料形成为Cu2O半导体材料的所述金属氧化物半导体有源层，包括：
    将形成有由Cu金属材料形成的第一图案的基板放入水中并通电，使Cu金属材料与水发生电解反应形成Cu2O半导体材料，使所述第一图案形成为所述金属氧化物半导体有源层。
  5. 根据权利要求4所述的制备方法，其中，在将形成有所述第一图案的基板放入水中之前，所述制备方法还包括：
    通过构图工艺在有源区形成所述Cu金属材料的第一图案。
  6. 根据权利要求5所述的制备方法，其中，通过一次构图工艺形成同层的所述源极的图案、所述漏极的图案和所述第一图案。
  7. 根据权利要求6所述的制备方法，其中，所述通过一次构图工艺形成同层的所述源极的图案、所述漏极的图案和所述第一图案，包括：
    在所述基板上形成Cu金属薄膜；
    对所述Cu金属薄膜进行一次半色调掩膜工艺，形成所述源极的图案、所述漏极的图案以及位于所述有源区的第一图案；
    其中，在进行电化学反应前，除所述第一图案外，由所述Cu金属薄膜形成的其他图案被光刻胶覆盖。
  8. 根据权利要求7所述的制备方法，其中，所述对所述Cu金属薄膜进行一次半色调掩膜工艺，形成所述源极的图案、所述漏极的图案以及位于所述有源区的第一图案，包括：
    在形成有所述Cu金属薄膜的基板上形成光刻胶；
    采用半阶掩膜板或灰阶掩膜板对形成有所述光刻胶的基板进行曝光、显影后，形成光刻胶完全保留部分、光刻胶半保留部分和光刻胶完全去除部分；其中，所述光刻胶完全保留部分对应待形成的所述源极图案和所述漏极图案的区域，所述光刻胶半保留部分对应所述有源区，所述光刻胶完全去除部分对应不形成Cu金属图案的区域和有源区以外的其他区域；
    采用刻蚀工艺去除所述光刻胶完全去除部分对应的Cu金属薄膜，形成所述源极的图案和所述漏极的图案，以及位于所述有源区的所述第一图案；以及
    采用灰化工艺去除所述光刻胶半保留部分的光刻胶。
  9. 根据权利要求1～3任一项所述的制备方法，其中，形成所述金属氧化物半导体有源层包括：
    在所述基板上形成金属薄膜；
    对所述金属薄膜进行一次构图工艺，形成位于所述有源区的第一图案；以及
    进行所述电化学反应，使所述第一图案形成所述金属氧化物半导体有源层。
  10. 根据权利要求1～3任一项所述的制备方法，其中，形成所述金属氧化物半导体有源层包括：
    在所述基板上形成金属材料的薄膜；
    通过电化学反应将所述金属材料的薄膜变为金属氧化物半导体材料的薄膜；以及
    通过构图工艺去掉除有源区之外的金属氧化物半导体材料的薄膜，并在有源区形成所述金属氧化物半导体有源层。
  11. 根据权利要求1～10任一项所述的制备方法，其中，所述栅绝缘层至少包括与所述金属氧化物半导体有源层接触的TiO2和/或Al2O3层。
  12. 一种薄膜晶体管，包括栅极、栅绝缘层、金属氧化物半导体有源层、源极和漏极；其中，
    所述金属氧化物半导体有源层通过电化学反应形成。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述金属氧化物半导体 有源层为Cu2O半导体材料。
  14. 根据权利要求13所述的薄膜晶体管，其中，所述金属氧化物半导体有源层、所述源极和所述漏极同层设置；
    其中，所述源极和所述漏极的材料为Cu金属材料。
  15. 根据权利要求11～14任一项所述的薄膜晶体管，其中，所述栅绝缘层至少包括与所述金属氧化物半导体有源层、所述源极和所述漏极接触的TiO2和/或Al2O3层。
  16. 一种阵列基板，包括权利要求12至15任一项所述的薄膜晶体管。
  17. 一种阵列基板的制备方法，包括在基板上形成薄膜晶体管，其中，所述薄膜晶体管的制备方法为权利要求1至11任一项所述的薄膜晶体管的制备方法。
  18. 一种显示装置，包括权利要求16所述的阵列基板。
PCT/CN2015/081992 2015-01-28 2015-06-19 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 WO2016119380A1 (zh)

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