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WO2016110174A1 - 电源电路、阵列基板及显示装置 - Google Patents

电源电路、阵列基板及显示装置 Download PDF

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Publication number
WO2016110174A1
WO2016110174A1 PCT/CN2015/097595 CN2015097595W WO2016110174A1 WO 2016110174 A1 WO2016110174 A1 WO 2016110174A1 CN 2015097595 W CN2015097595 W CN 2015097595W WO 2016110174 A1 WO2016110174 A1 WO 2016110174A1
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WIPO (PCT)
Prior art keywords
power
power line
transistor
power supply
line
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Application number
PCT/CN2015/097595
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English (en)
French (fr)
Inventor
尹静文
王俪蓉
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP15876674.1A priority Critical patent/EP3244389A4/en
Priority to US15/533,754 priority patent/US10186202B2/en
Publication of WO2016110174A1 publication Critical patent/WO2016110174A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3216—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of organic light emitting display, and more particularly to a power supply circuit, an array substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • OLED display has become a very popular emerging flat panel display at home and abroad.
  • OLED display has self-illumination, wide viewing angle, short response time, high luminous efficiency, wide color gamut, low working voltage, thin panel, large size and flexible panel, and simple manufacturing process, and it also has low The potential for cost.
  • a driving current is generally supplied to a plurality of pixel units of one row through the same power supply line.
  • 1 is an exemplary schematic diagram of a power supply circuit in the prior art. As shown in FIG. 1, the power supply VDD drives a plurality of active matrix organic light emitting diodes (AMOLEDs) D1, D2, D3, and D4 through one power supply line.
  • AMOLEDs active matrix organic light emitting diodes
  • the resistor symbol in Figure 1 represents the equivalent resistance of each segment of the power line.
  • the light-emitting diodes D1, D2, D3, and D4 emit light at the same time, since the light-emitting diode D1 is located close to the power source VDD, the voltage across the light-emitting diode D1 is larger, and the brightness is higher.
  • the light-emitting diodes D1, D4 emit light
  • the light-emitting diodes D2 and D3 do not emit light or the current flowing to D2 and D3 is extremely small (very weakly emitted)
  • the current flowing to the light-emitting diode D4 increases, and the light-emitting luminance of the light-emitting diode D1 and the light-emitting luminance of the light-emitting diode D4 are also different.
  • Fig. 2 is a schematic view for explaining a phenomenon in which the brightness of the display is uneven.
  • each of the regions may include a plurality of rows of pixel cells, and the region 2 is located close to the power source VDD, and the region 4 is located away from the power source VDD.
  • a region 2 is included with a light emitting diode D1
  • a region 3 includes light emitting diodes D2, D3,
  • a region 4 includes a light emitting diode D4, and assuming that all of the pixel cells in the region 1 emit light, the region 1 is a light emitting region.
  • the light-emitting diode D1 in the area 2 emits light
  • the area 2 is the light-emitting area
  • the light-emitting diodes D2, D3 in the area 3 do not emit light
  • the area 3 is a dark area
  • the light-emitting diode D4 in the area 4 emits light
  • the area 4 is a light-emitting area.
  • the pixel units in the area 1 all emit light, the light-emitting luminance of the area 1 gradually decreases from a position close to the power source VDD to a position away from the power source VDD due to the resistance of the power source line. Further, since the region 3 is a dark region, the region 2 is brighter than the region 1, and the region 4 has a higher luminance than that of the region 1 because the incoming current is large. As such, there will be a phenomenon in which the luminance of the display is uneven.
  • the power supply circuit, the array substrate and the display device provided by the embodiments of the present invention can improve display brightness unevenness due to different voltage drops between different rows of pixel units.
  • a power supply circuit comprising a plurality of power supply lines, each of the plurality of power supply lines supplying a voltage to a row of pixel units.
  • the plurality of power lines includes at least a first power line and a second power line, and at least one logic AND circuit is disposed between the first power line and the second power line.
  • the logic and circuit electrically connect the first power line and the second power line when the first power line and the second power line simultaneously output a high level voltage.
  • the AND circuit includes a first transistor and a second transistor.
  • the control electrode of the first transistor is connected to the second power line, the first pole of the first transistor is connected to the first power line, and the second pole of the first transistor is connected to the first pole of the second transistor.
  • the control electrode of the second transistor is connected to the first power line, and the second pole of the second transistor is connected to the second power line.
  • the first transistor and the second transistor are N-type transistors.
  • the voltage output by the power line is switched between a high level and a low level.
  • the first power line and the second power line are adjacent power lines.
  • At least one logic AND circuit is provided between every two adjacent power lines.
  • connection points of the logic and circuit with the first power line and the second power line are respectively located at positions away from the power source on the first power line and the second power line.
  • a plurality of logic and circuits are disposed between the first power line and the second power line, and the plurality of logic and circuits are spaced apart from the plurality of connection points of the first power line and the second power line On the first power line and the second power line.
  • an array substrate including any of the above power supply circuits.
  • a display device including the above array substrate is provided.
  • a power supply circuit electrically connects two power supply lines to each other while simultaneously outputting a high level voltage by providing a logic AND circuit between the two power supply lines, and therefore, a connection point between the two power supply lines
  • the voltage is close to reduce the voltage difference between the pixel units of different rows, thereby improving the brightness unevenness of the display due to the difference in voltage drop of different rows of pixel units, and the structure is simple and the cost is low.
  • FIG. 1 is an exemplary schematic diagram of a power supply circuit in the prior art
  • FIG. 2 is a schematic view for explaining a phenomenon of uneven brightness of a display
  • FIG. 3 is a schematic diagram of a power supply circuit in accordance with an embodiment of the present invention.
  • Fig. 4 is a timing chart showing the voltage output from the power supply line in the embodiment shown in Fig. 3.
  • the power supply circuit of this embodiment includes a plurality of power supply lines, each of which supplies voltage to a row of pixel units.
  • the plurality of power lines include at least a first power line n and a second power line n+1, and at least one logic AND circuit is disposed between the first power line n and the second power line n+1.
  • the logic and circuit electrically connect the first power line when the first power line n and the second power line n+1 simultaneously output a high level voltage n and the second power line n+1.
  • the first power line n and the second power line n+1 are electrically connected to each other.
  • the voltages of the first power line n and the second power line n+1 are close at the two connection points of the logic and the circuit (due to the presence of a resistor in the device constituting the logic and the circuit, it is difficult to be completely the same), thereby making the first power line
  • the driving voltages of the n-connected pixel unit and the pixel unit connected to the second power source line n+1 approach when the voltages output by the first power line n and the second power line n+1 are both high, the first power line n and the second power line n+1 are electrically connected to each other.
  • the voltages of the first power line n and the second power line n+1 are close at the two connection points of the logic and the circuit (due to the presence of a resistor in the device constituting the logic and the circuit, it is difficult to be completely the same), thereby making the first power line
  • the AND circuit includes a first transistor T1 and a second transistor T2.
  • the first transistor T1 and the second transistor T2 can be selected from thin film transistor TFTs having low noise and low power consumption, and can be fabricated in the same process together with other thin film transistors on the array substrate.
  • the first transistor T1 and the second transistor T2 may be N-type thin film transistor TFTs, wherein the gate is a gate, the first pole is a drain, and the second pole is a source.
  • the first transistor T1 and the second transistor T2 may also employ a P-type thin film transistor. In this case, an inverter can be added at the gates of the first transistor T1 and the second transistor T2.
  • the gate of the first transistor T1 is connected to the second power line n+1, the drain of the first transistor T1 is connected to the first power line n, and the source of the first transistor T1 is connected to the drain of the second transistor T2.
  • the gate of the second transistor T2 is connected to the first power line n, and the source of the second transistor T2 is connected to the second power line n+1.
  • the gate of the first transistor T1 is connected to the source of the second transistor T2 at point b on the second power line n+1, and the drain of the first transistor T1 and the gate of the second transistor T2 are on the first power line n.
  • the point a is connected, and the source of the first transistor T1 and the drain of the second transistor T2 are connected at point c.
  • connection point of the logic and circuit with the first power line n and the second power line n+1 is located at a position away from the power source Vdd on the first power line n and the second power line n+1, respectively. It can be understood that if the power supply Vdd is located at one end of the power line, the points a and b of the connection point between the logic and the circuit and the first power line n and the second power line n+1 are located at the first power line n and the second, respectively. The power line n+1 is away from the other end of the power supply Vdd position. Therefore, when the logic and the circuit are turned on, Keep the voltages on the two power lines away from the power supply Vdd.
  • Fig. 4 is a timing chart showing the voltage output from the power supply line in the embodiment shown in Fig. 3. 4 shows operational waveforms of voltages outputted by the first power supply line n and the second power supply line n+1. As shown in FIG. 4, timings of voltages output by the first power supply line n and the second power supply line n+1 include Three phases: P1 phase, P2 phase and P3 phase.
  • the timing of the voltage output from the power supply line in the power supply circuit of the present embodiment will be described by taking the first transistor T1 and the second transistor T2 as N-type transistors as an example.
  • the voltage Vdd(n) output from the first power supply line n is at a low level, and the voltage Vdd(n+1) output from the second power supply line n+1 is at a high level. Therefore, the gate of the first transistor T1 is at a high level, and the drain of the first transistor T1 is at a low level. In this case, the first transistor T1 is in an on state, and the voltage Vc at point c is close to the point a voltage Va, and is at a low level. Further, the gate of the second transistor T2 is at a low level, and the source of the second transistor T2 is at a high level. In this case, the second transistor T2 is in an off state, so that there is no electrical connection between the first power line n and the second power line n+1.
  • the first power line n can be used to complete the compensation action.
  • the voltage Vdd(n) output from the first power supply line n is at a high level, and the voltage Vdd(n+1) output from the second power supply line n+1 is at a low level. Therefore, the gate of the first transistor T1 is at a low level, and the drain of the first transistor T1 is at a high level. In this case, the first transistor T1 is in an off state. Further, the gate of the second transistor T2 is at a high level, and the source of the second transistor T2 is at a low level.
  • the second transistor T2 is in an on state, and the voltage Vc at point c is close to the voltage Vb at point b, both of which are low level, and there is no electricity between the first power line n and the second power line n+1. connection.
  • the second power line n+1 can be used to complete the compensation action.
  • the voltages output by the first power line n and the second power line n+1 are both high.
  • the first transistor T1 and the second transistor T2 are both in an on state, and the c point is electrically
  • the voltage Vc will be close to the highest voltage between the two points a and b.
  • the first power line n is electrically connected to the second power line n+1.
  • the voltages of the first power supply line n and the second power supply line n+1 at the logical and circuit connection points are close to each other, thereby improving display brightness unevenness due to different voltage drops between pixel units of different rows.
  • the voltages of the first power line n and the second power line n+1 at a plurality of positions in the light-emitting phase are close to each other, so that the driving voltages of the light-emitting diodes between the pixel units of different rows are closer, and thus the display is more Evenly.
  • the voltage output by each power line can be switched between a high level and a low level.
  • switching to a low level is generally performed to achieve compensation and the like. Need.
  • the voltage outputted by the first power line n or the second power line n+1 is at a low level, since the transistors constituting the logic and the circuit are turned off, there is no electrical connection between the first power line n and the second power line n+1. . Since the first power line n and the second power line n+1 are not electrically connected, the first power line n or the second power line n+1 can be used to perform the compensation operation normally, and does not affect the compensation when the low level is performed.
  • the first power line n and the second power line n+1 may be two adjacent power lines.
  • the first power line n and the second power line n+1 form an electrical connection when the output voltage is at a high level, preventing crosstalk between adjacent two power lines.
  • the pixel unit is a plurality of rows, so the power supply circuit in this embodiment includes a plurality of power lines.
  • the first power line n and the second power line n+1 described above are examples thereof, and represent any two power lines.
  • a logic and circuit can be arranged between every two adjacent power lines of all power lines, so that the power lines form a mesh structure, and the brightness unevenness of the display caused by different voltage drops of different rows of pixel units is avoided, and the problem is solved. Crosstalk between adjacent power lines.
  • Another embodiment of the present invention further provides an array substrate including the above implementation
  • the structure and principle of the power supply circuit have been fully described above and will not be described in detail herein.
  • the array substrate of the embodiment reduces the problem of uneven brightness of light emitted between pixel units of different rows, thereby improving display uniformity of the light emitting device.
  • Still another embodiment of the present invention further provides a display device including the array substrate in the above embodiment.
  • the display device can be any product or component having display function such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, and the like.
  • the display device of the present embodiment alleviates the problem of uneven brightness of light emission between pixel units of different rows, thereby improving display uniformity of the light emitting device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种电源电路、阵列基板及显示装置，电源电路包括多条电源线，多条电源线的每一条向一行像素单元提供电压。多条电源线至少包括第一电源线（n）和第二电源线（n+1），在第一电源线（n）和第二电源线（n+1）之间设置有至少一个逻辑与电路。逻辑与电路在第一电源线（n）和第二电源线（n+1）同时输出高电平电压时电连接第一电源线（n）和第二电源线（n+1）。通过在电源线之间设置逻辑与电路，使两条电源线在同时输出高电平时互相电连接。因此，两行电源线之间连接点处的电压接近，降低不同行像素单元之间的电压差异，从而改善由于不同行像素单元的电压降不同产生的显示器亮度不均现象，结构简单，成本低。

Description

电源电路、阵列基板及显示装置
本申请要求2015年1月8日递交的中国专利申请第201510010133.1号的优先权，在此全文引用上述中国专利申请所公开的内容以作为本申请的一部分。
技术领域
本发明涉及有机发光显示领域，尤其涉及电源电路、阵列基板及显示装置。
背景技术
目前，有机发光二极管(Organic Light Emitting Diode，简称OLED)显示器成为国内外非常热门的新兴平面显示器。OLED显示器具有自发光、广视角、短反应时间、高发光效率、广色域、低工作电压、面板薄、可制作大尺寸与可挠曲的面板及制作过程简单等特性，而且它还具有低成本的潜力。
在OLED显示器中，通常通过同一条电源线向一行的多个像素单元提供驱动电流。图1是现有技术中的电源电路的示例性示意图。如图1所示，电源VDD通过一条电源线驱动多个有源矩阵有机发光二极管(AMOLED)D1、D2、D3和D4。图1中的电阻符号表示各段电源线的等效电阻。
在一行像素单元的全部发光时，例如，有机发光二极管D1、D2、D3和D4全部发光时，由于电源线的电阻，使得在显示器的背板中电源线上位于靠近电源VDD的位置的电压比位于远离电源VDD的位置的电压高，这种现象被称为压降(IR Drop)。由于压降的影响，靠近电源VDD的位置的像素亮度高于相比较离电源VDD的位置较远的像素。即，如果发光二极管D1、D2、D3、D4同时发光，则由于发光二极管D1处在靠近电源VDD的位置，则发光二极管D1两端的电压更大，从而亮度更高。
在一行像素单元的一部分发光时，例如，发光二极管D1、D4发光， 而发光二极管D2和D3不发光或流向D2和D3的电流极小(极微弱地发光)时，流向发光二极管D4的电流增加，导致发光二极管D1的发光亮度与发光二极管D4的发光亮度也不同。
因此，在显示应用中，在上述两种情况下，不同的发光二极管之间都会产生亮度差异，产生显示器亮度不均、出现各种痕迹的现象(即，mura现象)。
图2是用于说明显示器亮度不均现象的示意图。在图2中，每个区域可以包括多行像素单元，并且区域2位于靠近电源VDD的位置，区域4位于远离电源VDD的位置。结合图1，假定区域2包括发光二极管D1，区域3包括发光二极管D2、D3，区域4包括发光二极管D4，并且假定在区域1中的像素单元全部发光，区域1是发光区域。这样，区域2中的发光二极管D1发光，区域2是发光区域；区域3中的发光二极管D2、D3不发光，区域3是暗区；区域4中的发光二极管D4发光，区域4是发光区域。
根据上述分析，在图2中，虽然区域1中的像素单元全部发光，但由于电源线存在电阻，区域1的发光亮度从靠近电源VDD的位置向远离电源VDD的位置渐渐降低。此外，由于区域3是暗区，所以区域2比区域1亮，而区域4由于进入的电流较大，发光亮度比区域1的高。如此，将会出现显示器的发光亮度不均匀的现象。
发明内容
本发明的实施例提供的电源电路、阵列基板及显示装置，可以改善由于不同行像素单元之间的压降不同导致的显示器亮度不均现象。
根据本发明的一个方面，提供一种电源电路，包括多条电源线，多条电源线的每一条向一行像素单元提供电压。其中，多条电源线至少包括第一电源线和第二电源线，在第一电源线和第二电源线之间设置有至少一个逻辑与电路。其中，逻辑与电路在第一电源线和第二电源线同时输出高电平电压时电连接第一电源线和第二电源线。
在本发明的实施例中，逻辑与电路包括第一晶体管和第二晶体管。第一晶体管的控制极连接第二电源线，第一晶体管的第一极连接第一电源线，第一晶体管的第二极连接第二晶体管的第一极。第二晶体管的控制极连接第一电源线，第二晶体管的第二极连接第二电源线。
在本发明的实施例中，第一晶体管和第二晶体管为N型晶体管。
在本发明的实施例中，电源线输出的电压在高电平和低电平之间切换。
在本发明的实施例中，第一电源线和第二电源线是相邻的电源线。
在本发明的实施例中，每两条相邻的电源线之间设置至少一个逻辑与电路。
在本发明的实施例中，逻辑与电路与第一电源线和第二电源线的连接点分别位于第一电源线和第二电源线上远离电源的位置。
在本发明的实施例中，在第一电源线和第二电源线之间设置多个逻辑与电路，多个逻辑与电路与第一电源线和第二电源线的多个连接点间隔地设置在第一电源线和第二电源线上。
根据本发明的另一个方面，提供了一种阵列基板，包括上述任一电源电路。
根据本发明的再一个方面，提供了一种显示装置，包括上述的阵列基板。
根据本发明的实施例的电源电路通过在两条电源线之间设置逻辑与电路，使两条电源线在同时输出高电平电压时互相电连接，因此，两条电源线之间连接点处的电压接近，降低不同行的像素单元之间的电压差异，从而改善由于不同行像素单元的电压降不同产生的显示器亮度不均现象，结构简单，成本低。
附图说明
为了更清楚地说明本发明的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本发明的一些实施例，而非对本发明的限制，其中：
图1是现有技术中的电源电路的示例性示意图；
图2是用于说明显示器亮度不均现象的示意图；
图3是根据本发明的实施例的电源电路的示意图；
图4是图3所示的实施例中电源线输出的电压的时序图。
具体实施方式
为了使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本发明保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内普通技术人员所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。“连接”不限于具体的连接形式，可以是直接连接，也可以是通过其他部件间接连接，可以是不可拆卸的连接，也可以是可拆卸的连接，可以是电气或信号连接，也可以是机械或物理连接。
图3是根据本发明的实施例的电源电路的示意图。如图3所示，本实施例的电源电路包括多条电源线，多条电源线的每一条向一行像素单元提供电压。多条电源线至少包括第一电源线n和第二电源线n+1，在第一电源线n和第二电源线n+1之间设置有至少一个逻辑与电路。逻辑与电路在第一电源线n和第二电源线n+1同时输出高电平电压时电连接第一电源线 n和第二电源线n+1。
在本实施例中，当第一电源线n和第二电源线n+1输出的电压均为高电平时，第一电源线n和第二电源线n+1互相电连接。第一电源线n和第二电源线n+1在逻辑与电路的两个连接点处的电压接近(由于构成逻辑与电路的器件中存在电阻，难以完全相同)，进而使得与第一电源线n连接的像素单元和与第二电源线n+1连接的像素单元的驱动电压趋近。因此，缓解了由于其中一行中某些像素单元电流小而使得不同行的像素单元之间的电压降差异较大的问题，从而改善不同行像素单元之间由于电压降差异产生的显示器亮度不均现象。
如图3所示，逻辑与电路包括第一晶体管T1和第二晶体管T2。一般而言，第一晶体管T1和第二晶体管T2可选用噪声小、功耗小的薄膜晶体管TFT，可与阵列基板上的其他薄膜晶体管一起在相同的工序中制作。例如，第一晶体管T1和第二晶体管T2可以是N型的薄膜晶体管TFT，其中，控制极是栅极，第一极是漏极，第二极是源极。本领域的技术人员应当知道，第一晶体管T1和第二晶体管T2也可以采用P型薄膜晶体管。在这种情况下，可在第一晶体管T1和第二晶体管T2的栅极处增加反相器。
第一晶体管T1的栅极连接第二电源线n+1，第一晶体管T1的漏极连接第一电源线n，第一晶体管T1的源极连接第二晶体管T2的漏极。第二晶体管T2的栅极连接第一电源线n，第二晶体管T2的源极连接第二电源线n+1。
第一晶体管T1的栅极与第二晶体管T2的源极在第二电源线n+1上的b点连接，第一晶体管T1漏极与第二晶体管T2的栅极在第一电源线n上的a点连接，第一晶体管T1的源极与第二晶体管T2的漏极在c点连接。
在本实施例中，逻辑与电路与第一电源线n和第二电源线n+1的连接点分别位于第一电源线n和第二电源线n+1上远离电源Vdd的位置。可以理解为，若电源Vdd位置位于电源线的一端，则逻辑与电路与第一电源线n和第二电源线n+1的连接点a点和b点分别位于第一电源线n和第二电源线n+1远离电源Vdd位置的另一端。因此，在逻辑与电路导通时，可以 使两条电源线上远离电源Vdd位置处的电压相同。如在背景技术中所分析的，越远离电源Vdd，则显示器亮度不均现象越严重，因此使两条电源线上远离电源Vdd位置处的电压接近，则能更好的改善不同行的像素单元之间的电压降不同产生的显示器亮度不均现象。
应当说明的是，本实施例中的说明没有限制a点和b点的具体位置，a点和b点的具体位置可根据实际需要设定。
图4是图3所示的实施例中电源线输出的电压的时序图。图4示出了第一电源线n和第二电源线n+1输出的电压的工作波形，如图4所示，第一电源线n和第二电源线n+1输出的电压的时序包括三个阶段：P1阶段、P2阶段和P3阶段。
以下，仍然以第一晶体管T1和第二晶体管T2是N型晶体管为例对于本实施例的电源电路中电源线输出的电压的时序进行说明。
在P1阶段，第一电源线n输出的电压Vdd(n)为低电平，第二电源线n+1输出的电压Vdd(n+1)为高电平。因此，第一晶体管T1的栅极为高电平，第一晶体管T1的漏极为低电平。在这种情况下，第一晶体管T1处于导通状态，c点的电压Vc接近于a点电压Va，均为低电平。并且，第二晶体管T2的栅极为低电平，第二晶体管T2的源极为高电平。在这种情况下，第二晶体管T2处于截止状态，使第一电源线n与第二电源线n+1之间没有电连接。第一电源线n可以用于完成补偿动作。
在P2阶段，第一电源线n输出的电压Vdd(n)为高电平，第二电源线n+1输出的电压Vdd(n+1)为低电平。因此，第一晶体管T1的栅极为低电平，第一晶体管T1的漏极为高电平。在这种情况下，第一晶体管T1处于截止状态。并且，第二晶体管T2的栅极为高电平，第二晶体管T2的源极为低电平。在这种情况下，第二晶体管T2处于导通状态，c点的电压Vc接近于b点电压Vb，均为低电平，第一电源线n与第二电源线n+1之间没有电连接。第二电源线n+1可以用于完成补偿动作。
在P3阶段，第一电源线n和第二电源线n+1输出的电压均为高电平。在这种情况下，第一晶体管T1和第二晶体管T2都处于导通状态，c点电 压Vc会接近于a，b两点之中的最高电压。第一电源线n与第二电源线n+1之间电连接。第一电源线n和第二电源线n+1在逻辑与电路连接点处的电压彼此接近，从而改善不同行的像素单元之间由于电压降不同产生的显示器亮度不均现象。
应当注意的是，虽然在本例中，对于包含一个逻辑与电路的情况进行了说明，但是，本领域技术人员应当理解的是，本实施例并没有对逻辑与电路的个数进行限制，逻辑与电路的个数可以是多个。在第一电源线n和第二电源线n+1之间设置多个逻辑与电路时，多个逻辑与电路与第一电源线n和第二电源线n+1的连接点间隔地设置在第一电源线n和第二电源线n+1上。因此，第一电源线n和第二电源线n+1在发光阶段在多处的电压两两彼此接近，从而使不同行的像素单元之间的发光二极管的驱动电压更为接近，因而显示更均匀。
在本实施例中，在发光阶段，每条电源线输出的电压可以在高电平和低电平之间切换，如本领域技术人员应该知道的，切换到低电平一般是为了实现补偿等功能的需要。在第一电源线n或第二电源线n+1输出的电压为低电平时，由于构成逻辑与电路的晶体管截止，使第一电源线n与第二电源线n+1之间没有电连接。由于第一电源线n和第二电源线n+1不进行电连接，第一电源线n或第二电源线n+1可以用于正常完成补偿动作，不会影响低电平时进行的补偿等功能。
第一电源线n和第二电源线n+1可以是相邻的两条电源线。第一电源线n和第二电源线n+1在输出的电压均为高电平时形成电连接，防止相邻的两条电源线之间的串扰现象。
一般情况下，像素单元为多行，因此本实施例中的电源电路包括多条电源线。上述的第一电源线n和第二电源线n+1是其中的示例，代表任意两条电源线。可以在所有电源线中的每两条相邻电源线之间设置逻辑与电路，从而使电源线形成网状结构，避免不同行像素单元的电压降不同导致的显示器亮度不均现象，并解决了相邻电源线之间的串扰问题。
本发明的另一个实施例还提供一种阵列基板，阵列基板包括上述实施 例中任一电源电路，电源电路的结构和原理在上面已经充分进行了说明，此处不再详述。
本实施例的阵列基板减轻了不同行的像素单元之间发光亮度不均匀的问题，进而提高了发光器件的显示均匀性。
本发明的再一个实施例还提供一种显示装置，显示装置包括上述实施例中的阵列基板。显示装置可以为电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。本发明虽然是以OLED显示器件为例进行说明，但本领域技术人员应该理解，对于存在由于压降(IR Drop)导致的不同行的像素单元之间的电压降不同而产生的显示器亮度不均现象的显示器件，本发明都能得到有效应用。
本实施例的显示装置减轻了不同行的像素单元之间的发光亮度不均匀的问题，进而提高了发光器件的显示均匀性。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

  1. 一种电源电路，包括多条电源线，所述多条电源线的每一条向一行像素单元提供电压；
    其中，所述多条电源线至少包括第一电源线和第二电源线，在所述第一电源线和第二电源线之间设置有至少一个逻辑与电路；
    其中，所述逻辑与电路在所述第一电源线和所述第二电源线同时输出高电平电压时电连接所述第一电源线和所述第二电源线。
  2. 如权利要求1所述的电源电路，其中，所述逻辑与电路包括第一晶体管和第二晶体管；
    所述第一晶体管的控制极连接第二电源线，所述第一晶体管的第一极连接所述第一电源线，所述第一晶体管的第二极连接所述第二晶体管的第一极；
    所述第二晶体管的控制极连接所述第一电源线，所述第二晶体管的第二极连接所述第二电源线。
  3. 如权利要求2所述的电源电路，其中，所述第一晶体管和所述第二晶体管为N型晶体管。
  4. 如权利要求1所述的电源电路，其中，所述电源线输出的电压在高电平电压和低电平电压之间切换。
  5. 如权利要求1所述的电源电路，其中，所述第一电源线和所述第二电源线是相邻的电源线。
  6. 如权利要求5所述的电源电路，其中，在每两条相邻的所述电源线之间设置至少一个所述逻辑与电路。
  7. 如权利要求1-6中任一项所述的电源电路，其中，所述逻辑与电路与所述第一电源线和所述第二电源线的连接点分别位于所述第一电源线和所述第二电源线上远离电源的位置。
  8. 如权利要求1-6中任一项所述的电源电路，其中，在所述第一电源线和所述第二电源线之间设置多个所述逻辑与电路，多个所述逻辑与电路与所述第一电源线和所述第二电源线的多个连接点间隔地设置在所述第一 电源线和所述第二电源线上。
  9. 一种阵列基板，包括如权利要求1-8任一项所述的电源电路。
  10. 一种显示装置，包括如权利要求9所述的阵列基板。
PCT/CN2015/097595 2015-01-08 2015-12-16 电源电路、阵列基板及显示装置 WO2016110174A1 (zh)

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US20170330514A1 (en) 2017-11-16
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