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WO2016101828A1 - 读取数据的方法以及装置 - Google Patents

读取数据的方法以及装置 Download PDF

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Publication number
WO2016101828A1
WO2016101828A1 PCT/CN2015/097586 CN2015097586W WO2016101828A1 WO 2016101828 A1 WO2016101828 A1 WO 2016101828A1 CN 2015097586 W CN2015097586 W CN 2015097586W WO 2016101828 A1 WO2016101828 A1 WO 2016101828A1
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WO
WIPO (PCT)
Prior art keywords
address
page
data
write
cache
Prior art date
Application number
PCT/CN2015/097586
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English (en)
French (fr)
Inventor
周建华
黎燕
张颇
王斐
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18213247.2A priority Critical patent/EP3584706B1/en
Priority to JP2017534266A priority patent/JP6399720B2/ja
Priority to AU2015371849A priority patent/AU2015371849B2/en
Priority to SG11201705180VA priority patent/SG11201705180VA/en
Priority to EP15871896.5A priority patent/EP3229126B1/en
Priority to CA2971913A priority patent/CA2971913C/en
Publication of WO2016101828A1 publication Critical patent/WO2016101828A1/zh
Priority to US15/630,105 priority patent/US10261906B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/602—Details relating to cache prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Definitions

  • the present application relates to the field of storage, and in particular, to a method and apparatus for reading data.
  • each floating gate transistor used for storage on a solid state drive (English: Solid State Drive, SSD for short) can store 2 or 3 bits (English: bit), and the bit stored on each floating gate transistor. They are distributed in different pages (English: page), so that the pages in each block are divided into different 2 or 3 types according to the storage location of the floating gate transistors.
  • LSB page LSB with floating gate transistor
  • MSB page MSB page with floating gate transistor
  • the data based on the corresponding bits of the LSB page and the MSB page are stored in the same floating gate transistor, so the LSB page and the MSB page belong to a set of shared pages (English: shared pages).
  • the shared page of a block of a certain manufacturer MLC is as follows:
  • the interference data obtained when writing data according to the experiment is as follows:
  • Table 2 above shows the interference to the vertical page when writing a horizontal page.
  • ECC Error Correcting Code
  • UNC Uncorrectable ECC Error
  • a set of shared pages includes a LAB page, an intermediate significant bit (English: middle significant bit, CSB) page, and an MSB page.
  • CSB middle significant bit
  • the existing common method is to improve the ECC error correction capability of the SSD, so that the controller of the storage device reads the page with the write interference.
  • the error in reading the data is corrected by ECC.
  • improving the error correction capability of the ECC requires the support of the controller, and in the case where the storage device provides a certain area of the spare area for the ECC, it is difficult to further improve the ECC error correction capability, so the write interference still occurs when the data is read. The resulting read error.
  • the present application provides a method and apparatus for reading data, which can reduce read data errors caused by write disturb.
  • the first aspect of the present application provides a method for reading data, including: when receiving a read command including a read target address, determining whether data pointed to by the read target address is cached in a preset cache area; And searching for the cache address corresponding to the read target address according to the first mapping relationship, and reading data pointed by the cache address in the preset cache area, where the first mapping relationship is used for recording Corresponding relationship between the target address and the cache address; if not, reading data pointed by the read target address from the non-volatile storage space.
  • the method further includes: determining, when receiving the write instruction, whether the write target address in the write instruction belongs to a highest one of the non-volatile storage spaces a valid bit page MSB page, wherein the write command includes data to be written and the write target address; if not, the write data to be stored is stored in the preset buffer and the write a non-volatile storage space corresponding to the target address, and establishing the first mapping relationship between the cache address and the target address; if yes, storing the write-once data to the write The non-volatile storage space corresponding to the target address.
  • the method further includes: acquiring between the MSB page and the LSB page in all shared page groups of the non-volatile storage space
  • the maximum difference page number is m, the m is a natural number; the cache area is allocated with at least n*p+m page sizes for the preset buffer area, wherein the p represents the non-volatile storage space.
  • the method further includes: if the write target address belongs to the MSB page in the non-volatile storage space, determining whether the MSB page where the write target address is located is the last MSB page in the block block If not, obtain the address of the shared page of the nth MSB page starting from the MSB page where the write target address is located, and as the release data address; if yes, obtain the last n+ of the block The address of the shared page of the MSB page is used as the release data address; the data pointed to by the cache address having the first mapping relationship with the release data address in the preset buffer area is released, and the first The release data address in the mapping relationship.
  • the method further includes: when the power is off, the preset buffer area Data is further stored in the non-volatile storage space, and establishes a second mapping relationship between the cache address and another save address of the non-volatile storage space; when powering up, according to the And mapping the data pointed to by the other save address of the non-volatile storage space to the cache address of the preset buffer area.
  • the preset buffer area is located in a double rate synchronous dynamic random access memory (DDR) or static Random access memory SRAM.
  • DDR synchronous dynamic random access memory
  • SRAM static Random access memory
  • the non-volatile storage space is a storage space of the solid state drive SSD.
  • a second aspect of the present application provides an apparatus for reading data, including a first determining module, a first reading module, and a second reading module; the first determining module is configured to receive a read including a read target address When the command is executed, determining whether the data pointed by the read target address is buffered in the preset buffer area, and transmitting the first determination result to the first and second reading modules; the first reading module is used to pre- When the data pointed to by the read target address is cached in the buffer area, the cache address corresponding to the read target address is found according to the first mapping relationship, and the cache is read in the preset cache area.
  • the second reading module is configured to not cache the Reading the read target from the non-volatile storage space when reading data pointed to by the target address The data pointed to by the address.
  • the method further includes: a second determining module, a first writing module, and a second writing module, where the second determining module is configured to receive the write command Determining whether the write target address in the write command belongs to the most significant bit page MSB page in the non-volatile storage space, and transmitting the second determination result to the first and second write modules, wherein
  • the write instruction includes a write data and the write target address;
  • the first write module is configured to: when the write target address does not belong to the MSB page of the non-volatile storage space, Writing data to the preset buffer area and the non-volatile storage space corresponding to the write target address, and establishing the first mapping relationship between the cache address and the target address;
  • the second write module is configured to store the write-once data to the non-volatile storage corresponding to the write target address when determining that the write target address belongs to the MSB page of the non-volatile storage space In space.
  • the method further includes: a third acquiring module and an allocating module;
  • the maximum difference page number between the MSB page and the LSB page in all shared page groups of the storage space is m, and the m is sent to the allocation module, the m is a natural number;
  • the allocation module is used to The preset buffer area allocates at least n*p+m page size buffer spaces, wherein the p represents a shared page number of the MSB page of the non-volatile storage space, and the n is a natural number, at least 1.
  • the third determining module, the first obtaining module, the second obtaining module, and the releasing module are further included;
  • the module is configured to determine, when the write target address belongs to the MSB page in the non-volatile storage space, whether the MSB page where the write target address is located is the last MSB page in the block block, and The third determination result is sent to the first and second acquisition modules;
  • the first acquisition module is configured to acquire the write target when the MSB page where the write target address is located is not the last MSB page in the block
  • the MSB page where the address is located is the address of the shared page of the nth MSB page from the start point, and is sent as the release data address to the release module;
  • the second acquisition module is used to Write to the destination address When the MSB page is the last MSB page in the block, the address of the shared page of the last n+1 MSB pages in the block is obtained, and the release data address is sent to the release module as the release data
  • the method further includes: a saving module and a cache module; And storing the data in the preset buffer area in the non-volatile storage space, and establishing a second mapping relationship between the cache address and another saved address of the non-volatile storage space. Sending the second mapping relationship to the cache module, where the cache module is configured to point data of another storage address of the non-volatile storage space according to the second mapping relationship upon power-on. Cache to the cache address of the preset buffer.
  • the preset buffer area is located in a double rate synchronous dynamic random access memory (DDR) or static random Access memory SRAM.
  • DDR synchronous dynamic random access memory
  • SRAM static random Access memory
  • the non-volatile storage space is a storage space of the solid state drive SSD.
  • the cache data is preferentially read.
  • the data pointed to by the target address is cached in the preset buffer area
  • the data is preferentially read from the preset buffer area, because the data in the buffer area does not exist.
  • the write interference of the lossy storage space reduces the read error caused by the write interference and improves the reliability of the storage device.
  • FIG. 1 is a flow chart of an embodiment of a method for reading data according to the present application
  • FIG. 2 is a partial flow chart of another embodiment of a method for reading data according to the present application.
  • FIG. 3 is a flow chart of still another embodiment of a method for reading data according to the present application.
  • FIG. 4 is a partial flow chart of still another embodiment of a method for reading data according to the present application.
  • FIG. 5 is a schematic structural diagram of an apparatus for reading data according to the present application.
  • FIG. 6 is a schematic structural diagram of another embodiment of an apparatus for reading data according to the present application.
  • FIG. 7 is a schematic structural diagram of an embodiment of a controller of the present application.
  • FIG. 1 is a flowchart of an embodiment of a method for reading data according to the present application.
  • the method of the present embodiment is performed by a controller of a storage device, and the storage device of the present application may be a floating gate transistor capable of storing any nonvolatile storage device of 2 bits or more, such as an MLC type (each floating gate transistor stores 2 bits), TLC (full name: Trinary-Level Cell) type (each floating gate transistor stores 3 bits) SSD.
  • the storage device includes a non-volatile storage space, that is, a space stored by the floating gate transistor, such as a storage matrix of an SSD.
  • the non-volatile storage space of the storage device includes a plurality of sets of shared page groups.
  • the non-volatile storage space of the MLC type storage device includes a plurality of sets of shared page groups, and each set of shared page groups includes an MSB page and an LSB page;
  • TLC A non-volatile storage space for a type of storage device includes a plurality of sets of shared page groups, each set of shared page groups including an MSB page, a CSB page, and an LSB page.
  • the method of this embodiment includes:
  • the controller of the storage device determines, when the read command including the read target address is received, whether the data pointed by the read target address is cached in the preset cache area.
  • the controller of the storage device stores the data of the storage device that is subjected to the above write interference in the preset buffer area and the non-volatile storage space, and is built.
  • the controller of the storage device receives a read command sent by the host from the SATA/SAS/PCIe interface, the read command includes a read target address to instruct the controller to read the read target from the non-volatile storage space.
  • the data pointed to by the address The controller searches for a first mapping relationship of the read target address.
  • the controller of the storage device does not necessarily determine whether the read data has a cache through the first mapping relationship.
  • the controller may additionally establish an identifier for recording whether the data at the address is cached. When the data is read, it is determined whether the data on the target read address is cached by reading the identifier of the address. Therefore, there is no specific limitation on how to judge whether the read data is cached.
  • the controller of the storage device may first determine whether the data pointed to by the read target address belongs to data that is subject to write interference, for example, determining whether the read target address belongs to the MSB page, if If the data does not belong, the data pointed to by the read target address belongs to data that is subject to write interference, that is, whether data pointed to by the read target address is cached in the preset cache area.
  • the controller of the storage device searches for the cache address corresponding to the read target address according to the first mapping relationship, and reads data pointed by the cache address in the preset cache area, where the first The mapping relationship is used to record a correspondence between the target address and the cache address.
  • the controller of the storage device searches for the cache address corresponding to the read target address according to the saved first mapping relationship. And reading the data on the cache address in the preset buffer area to implement the read data. Since the data in the buffer area does not have the write interference of the storage matrix, the data is read from the buffer area to ensure the correctness of the read data. .
  • the controller of the storage device reads data pointed by the read target address from the non-volatile storage space.
  • the controller of the storage device reads the read from the non-volatile storage space according to the normal read mode. Take the data on the target address to read the data.
  • the cache data is preferentially read.
  • the data pointed to by the target address is cached in the preset buffer area
  • the data is preferentially read from the preset buffer area, and the data in the buffer area does not exist in the non-volatile memory.
  • the write interference of the storage space reduces the read error caused by write interference and improves the reliability of the storage device.
  • FIG. 2 is a partial flow chart of another embodiment of a method for reading data according to the present application.
  • the controller of the storage device before performing the method steps of the previous embodiment, the controller of the storage device further performs:
  • the controller of the storage device determines, when receiving the write command, whether the write target address in the write command belongs to an MSB page in the non-volatile storage space, where the write command includes data to be written and The write target address.
  • Each floating gate transistor of the storage device of the present application can store more than 2 bits, so the page of the non-volatile storage space of the storage device is at least divided into two categories: LSB page and MSB page.
  • the floating gate transistor can store 3 bits
  • the page of the storage device's non-volatile storage space also includes the CSB page.
  • the controller of the storage device receives a write command sent by the host from an interface such as a SATA/SAS/PCIe interface, the write command includes a data to be written and a write destination address, to instruct the controller to store the data to be written to the write target.
  • the address points to the non-volatile storage space.
  • the controller After receiving the write command, the controller first determines whether the write target address belongs to the MSB page of the non-volatile storage space, and if not, executes 202, and if so, executes 203.
  • the controller of the storage device stores the required write data into a preset cache area and a non-volatile storage space corresponding to the write target address, and establish the cache address and the write target address.
  • the controller determines that the write destination address does not belong to the MSB page, it indicates that the write data needs to be interfered with by the write data in the subsequent MSB page, so the write data needs to be stored to the write target.
  • the address points to the non-volatile storage space and is cached to the default buffer as a backup.
  • the preset buffer area may be a double rate synchronous dynamic random access memory in the storage device. (English: Double Data Rate, referred to as: DDR).
  • the internal itself is provided with a DDR, and the data passes through the DDR regardless of whether data is written or read.
  • the preset buffer area may be set on the DDR, that is, a certain buffer space is opened in the DDR as a preset buffer area.
  • the preset buffer area may also be other memory than the non-volatile storage space, such as Static Random Access Memory (SRAM).
  • the controller acquires the cache address of the cached data to be cached in the preset buffer area, and establishes a first mapping relationship between the cached address and the write target address, so as to facilitate the preset buffer area.
  • the data in it corresponds to the data in the non-volatile storage space.
  • the first mapping relationship may be saved in a table manner in a non-volatile storage space of the storage device or in a preset buffer area.
  • the controller of the storage device stores the required write data into a non-volatile storage space corresponding to the write target address.
  • the controller determines that the data to be written belongs to the MSB page of the non-volatile storage space, it is not necessary to write the data cache to be backed up, directly according to The write destination address stores the data in non-volatile storage.
  • the controller of the storage device executes 101-103 shown in FIG. 1 after executing the above 201-203.
  • data that may be interfered by the MSB page write error is used as a cache backup, and is preferentially read from the cache when reading the partial data, so that the data is currently interfered by the write when the data is read.
  • the read error caused by write disturb is reduced, and the reliability of the storage device is improved.
  • FIG. 3 is a flowchart of still another embodiment of a method for reading data according to the present application. Specifically, the method includes:
  • the controller of the storage device acquires a maximum difference page number between the MSB page and the LSB page in all shared page groups of the non-volatile storage space, where the m is a natural number.
  • the shared pages of the storage devices of different vendors are different.
  • the first group of shared pages in each block is page0-page2, that is, the The difference between the MSB page and the LSB page is 2page
  • the second group of shared pages is page1_page4, that is, the difference between the MSB page and the LSB page is 3page
  • all the shared page groups of one block of the storage device are found to find the MSB page and the corresponding LSB page.
  • the number of pages with different phase differences is 2 or 3, so the maximum number of pages difference between the MSB page and the LSB page in all shared page groups of the storage device is 3.
  • the controller of the storage device allocates at least n*p+m page size buffer spaces to the preset buffer area, where the p represents a shared page number of the MSB page of the non-volatile storage space, The n is a natural number and is at least 1.
  • the present embodiment dynamically releases the cache of data that is no longer subject to write disturb.
  • the size of the cache space required for the preset buffer area is related to the maximum number of pages m between the MSB page and the LSB page in all shared page groups of the storage device, and the dynamic release rule.
  • the maximum difference between the MSB page and the LSB page in the shared page group of the non-volatile storage space of the storage device is m pages, which means that the shared page of the MSB page (such as its corresponding one is to be guaranteed before the MSB page is written).
  • LSB page, CSB page can be cached in the default buffer to avoid read errors caused by MSB page writes.
  • the default buffer requires at least m pages of cache space.
  • the dynamic release rule of the present application is to ensure that at least one shared page of the MAB pages before the MSB page (such as its corresponding LSB page, CSB page) can be cached in the preset buffer when writing to a certain MSB page.
  • n is at least 1 to basically ensure that the data with the current write interference is saved in the cache.
  • the data of the storage device is preset in the cache to ensure that the data with the current write interference is stored in the cache. Allocate at least m+n*p pages of cache space, for example, allocate m+n*p pages of cache space.
  • the p represents the number of shared pages of the MSB page of the non-volatile storage space of the storage device. For example, for a storage device of the MLC type, a set of shared pages includes an MSB page and an LSB page, so the storage device is not easy. The number of shared pages of the MSB page of the lossy storage space is 1, which is the LSB page.
  • a set of shared pages includes an MSB page, a CSB page, and an LSB page, so the MSB page of the non-volatile storage space of the storage device has a shared page number of 2, including a CSB page and an LSB page.
  • the controller of the storage device determines, when receiving the write command, whether the write target address in the write command belongs to an MSB page in the non-volatile storage space, where the write command includes data to be written and The write target address.
  • the controller After receiving the write command, the controller first determines whether the write destination address belongs to the MSB page of the non-volatile storage space of the storage device, and if not, executes 304, and if so, executes 305.
  • the controller of the storage device stores the required write data into the preset cache area and the non-volatile storage space corresponding to the write target address, and establish the cache address and the target address.
  • the controller of the storage device stores the required write data into a non-volatile storage space corresponding to the write target address, and determines whether the MSB page where the write target address is located is the last in the block. An MSB page.
  • the controller of the storage device only stores the write-once data to the non-volatile storage pointed by the write target address In the space, and determine whether the MSB page where the write target address is located is the last MSB page in the block, as the last MSB page of the block shown in Table 1 is page255, if it is determined that the write destination address does not belong to page255, then Execution 306, if it is determined that the write destination address belongs to page255, then 307 is performed.
  • the controller of the storage device acquires the address of the shared page of the nth MSB page starting from the MSB page where the write target address is located, and serves as a release data address.
  • a dynamic release cache is adopted.
  • the specific rule is that when the MSB page is written, at least the shared pages of the n MSB pages (such as their corresponding LSB pages and CSB pages) can be cached in the preset buffer.
  • the write interference received by the LSB page from the writing of its corresponding MSB page to the start of writing to the next MSB page is known. More serious, the minimum value of n is 1, in order to ensure that the current data with severe write interference is stored in the cache. However, in order to further reduce the read interference, it is preferable that n is at least 2, that is, when at least two MSB pages following a certain MSB page finish writing data, the corresponding MSB page is deleted. LSB page.
  • the storage device described in Table 1 in the background art is taken as an example. If the current write destination address belongs to page 6, which is MSB page, and does not belong to the last MSB page, the controller starts with page 6 and forwards. One MSB page is page4, and the second MSB page is page2. If n is 1, the page1 shared page, that is, page1, is regarded as no write interference after the data is written on page6. Therefore, the address of page1 is obtained as the release data address, so that page1 is released in the cache of the preset buffer.
  • the data in the buffer area is not released; when page 4 is written, page 0 in the buffer area is released; when page 6 is written, page 1 in the buffer area is released; when page 8 is written , release the page3 in the buffer area, and so on, that is, before the write interference cancellation of the black body part data display of the above Table 2, the correct data can be read from the cache.
  • the floating gate transistor stores more than 2 bits of the storage device, that is, obtains the shared page of the nth MSB page starting from the MSB page where the target address is written (for example, if the floating gate transistor stores 3 bits, the corresponding LSB page is included). And the address of the CBS page) as the release data address.
  • the controller of the storage device acquires an address of a shared page of the last n+1 MSB pages in the block as the release data address.
  • the MSB page where the write target address is located is the last MSB page of the block, that is, the write interference cancellation of all the pages of the block is released, so that all data buffers of the block can be released, according to the release cache rule of the above 306, when writing When the last MSB page is reached, the data of the shared page of the last n+1 MSB pages remaining in the block is buffered in the preset buffer area, wherein the n is a natural number and is at least 1.
  • the controller acquires the shared page of the last n+1 MSB pages in the block (if the floating gate transistor stores 2 bits, that is, the LSB page; if the floating gate transistor stores 3 bits, that is, the address including the LSB page and the CSB page), as the Release the data address.
  • the controller of the storage device releases data pointed to by the cache address in the preset buffer area that has the first mapping relationship with the release data address, and deletes the release data address in the first mapping relationship.
  • the controller of the storage device acquires the release data address according to the first mapping relationship
  • the cache address with the first mapping relationship is released, and the release of the data on the cache address is released, so that the dynamic release buffer is performed under the premise that the data retention cache that is currently seriously interfered by the write is guaranteed. Since the cache has been released, the release data address in the first mapping relationship and the cache address are deleted.
  • the controller of the storage device determines, when the read command including the read target address is received, whether the data pointed by the read target address is cached in the preset cache area. If there is a cache, execute 310, and if there is no cache, execute 311.
  • the controller of the storage device searches for a cache address corresponding to the read target address according to the first mapping relationship, and reads data pointed by the cache address in the preset cache area.
  • the controller of the storage device reads data pointed by the read target address from the non-volatile storage space.
  • the data in this embodiment may be caused by the MSB page write interference
  • the data of the read error is cached, and the data is read from the cache when the data is read. Therefore, when the data is read, the data is currently written.
  • the interference causes a read error, which greatly reduces the probability of read errors due to write interference.
  • the present embodiment is directed to a memory device that only writes interference to its shared page and the shared page of the MSB page adjacent to it before writing to the MSB page, so the dynamic release buffer is adopted to reduce the required cache space.
  • the present application allocates a cache space according to the maximum difference page number m of the shared page group of the storage device to be compatible with storage devices of different vendors.
  • FIG. 4 is a partial flow chart of still another embodiment of the method for reading data according to the present application.
  • the method of this embodiment further includes:
  • the controller of the storage device When power is off, the controller of the storage device saves the data in the preset buffer area in the non-volatile storage space, and establishes the cache address and the non-volatile storage space. The second mapping relationship between the addresses is saved.
  • the data in the preset buffer area is lost after the storage device is powered off.
  • the controller saves the data in the preset buffer area in the non-volatile storage space when the power is turned off, and Establishing a second mapping relationship between the cache address in the preset buffer area and the other saved address in the non-volatile storage space, so that the previously cached data of the preset buffer area can be
  • the data stored in the lossy storage device is also associated.
  • the controller of the storage device caches data pointed to by another save address of the non-volatile storage space to the cache address of the preset cache area according to the second mapping relationship.
  • the controller of the storage device After re-powering on, acquires another saved address of the non-volatile storage space in the second mapping relationship, and caches the data on the other saved address to have a second mapping with the other saved address.
  • the cached address of the relationship is re-cached according to the original cache address to cache the data before the power-down of the preset buffer, so that when the data of the cached non-volatile storage space needs to be read, the first The mapping relationship reads the corresponding cache data to achieve correct read data.
  • FIG. 5 is a schematic structural diagram of an apparatus for reading data according to the present application.
  • the device 500 for reading data may specifically be a controller of a storage device, and the storage device may be a floating gate transistor capable of storing any non-volatile storage device of 2 bits or more, such as an MLC type or a TLC type SSD.
  • the device 500 for reading data includes a first determining module 510, a first reading module 520, a second reading module 530, the device 500 for reading data, and a preset buffer area 570 and a non-volatile storage space 580. connection.
  • the first determining module 510 is configured to determine, when the read command including the read target address is received, whether the data pointed by the read target address is cached in the preset buffer area 570, and send the first determination result to the first The module 520 and the second reading module 530 are read.
  • the present application uses a cache backup for data that may be affected by the above write interference, and prioritizes the read in the preset buffer 570 when reading the data. the way.
  • the first determining module 510 receives, from the SATA/SAS interface, a read command sent by the host, where the read command includes a read target address to indicate that the read target address is read from the non-volatile storage space 580.
  • the data The first determining module 510 searches for a first mapping relationship of the read target address. If yes, it determines that the data pointed to by the read target address is cached in the preset buffer area 570; if it does not exist, it determines that it is a preset cache. The area pointed to by the read target address is not cached in area 570.
  • the first determining module 510 does not necessarily determine to read by using the first mapping relationship. Whether the data fetched has a cache. In other embodiments, the first determining module 510 may additionally establish an identifier for recording whether the data at the address is cached. When reading the data, determining whether the data on the read target address is cached by reading the identifier of the address. Therefore, there is no specific limitation on how to judge whether the read data is cached or not.
  • the first determining module 510 may further determine whether the data pointed by the read target address belongs to data that is subject to write interference, for example, determining whether the read target address belongs to the MSB page, if If not, it is determined whether the data pointed by the read target address is cached in the preset buffer area 570.
  • the first reading module 520 is configured to: when the data pointed by the read target address is cached in the preset buffer area, find a cache address corresponding to the read target address according to the first mapping relationship, and The data pointed to by the cache address is read in the preset buffer area 570, wherein the first mapping relationship is used to record a correspondence between the target address and the cache address.
  • the first reading module 520 acquires and reads the target according to the saved first mapping relationship.
  • the cache address corresponding to the address, and the data on the cache address is read in the preset buffer area 570 to implement the read data. Since the data in the buffer area is not interfered with by the write data, the slave cache Reading data in the area ensures the correctness of the read data.
  • the second reading module 530 is configured to read data pointed by the read target address from the non-volatile storage space 580 when the data pointed by the read target address is not cached in the preset buffer area 570. .
  • the second reading module 530 reads the read from the non-volatile storage space 580 according to the normal reading manner. The data on the target address to achieve read data.
  • the device 500 for reading data of the embodiment may further include a second determining module 540, a first writing module 550, and a second writing module 560.
  • the second determining module 540 is configured to: when receiving the write command, determine whether the write target address in the write command belongs to the MSB page in the non-volatile storage space, and send the second determination result to the first write Module 550, second write module 560, wherein The write command includes data to be written and the write target address.
  • the second determining module 540 receives a write command sent by the host from an interface, such as a SATA/SAS/PCIe interface, the write command includes a write data and a write target address to indicate that the write data needs to be stored to the write destination address.
  • the non-volatile storage space 580 (such as the storage matrix of the storage device). After receiving the write command, the second determining module 540 first determines whether the write target address belongs to the MSB page of the non-volatile storage space of the storage device.
  • the first writing module 550 is configured to store the write-once data into the preset buffer area 570 and store the write to the write when the write target address does not belong to the MSB page in the non-volatile storage space. And entering a non-volatile storage space 580 corresponding to the target address, and establishing a first mapping relationship between the cache address and the write target address.
  • the first write module 550 indicates that the data to be written may be subjected to write interference when writing data in the subsequent MSB page, so the need
  • the write data is stored in the non-volatile storage space 580 pointed to by the write destination address and cached to the preset cache area as a backup.
  • the preset buffer area 570 can be a DDR or SRAM in the storage device.
  • the first writing module 550 acquires the cache address of the write data buffer in the preset buffer area 570, and establishes a first mapping relationship between the cache address and the write target address, so as to facilitate
  • the data in the preset buffer 570 is associated with the data in the non-volatile storage space 580.
  • the first mapping relationship may be saved in a non-volatile storage space 580 of the storage device or in the preset buffer area 570 in a tabular manner.
  • the second writing module 560 is configured to store the write-once data to the non-volatile corresponding to the write target address when determining that the write target address belongs to the MSB page in the non-volatile storage space Storage space 580.
  • the second judging module 540 determines that the data to be written belongs to the MSB page of the non-volatile storage space, it is not necessary to save the data cache to be backed up.
  • the data is stored into the non-volatile storage space 580 directly according to the write target address.
  • the data in this embodiment may be caused by the MSB page write interference
  • the data of the read error is cached, and the data is read from the cache when the data is read. Therefore, when the data is read, the data is currently written. Interference caused by reading errors, greatly The probability of read errors due to write disturb is reduced, and the reliability of the storage device is improved.
  • FIG. 6 is a schematic structural diagram of an apparatus for reading data according to the present application. Specifically, except for the module included in the previous embodiment (wherein the module in FIG. 5 is not shown in FIG. 6 if it is not mentioned in the following description of the present embodiment, this does not mean the reading of the present embodiment.
  • the device for reading data does not include the module.
  • the device 600 for reading data further includes a third obtaining module 610, an allocating module 620, a third determining module 630, a first obtaining module 640, a second obtaining module 650, and a releasing module 660.
  • the save module 670 and the cache module 680 is a schematic structural diagram of an apparatus for reading data according to the present application. Specifically, except for the module included in the previous embodiment (wherein the module in FIG. 5 is not shown in FIG. 6 if it is not mentioned in the following description of the present embodiment, this does not mean the reading of the present embodiment.
  • the device for reading data does not include the module.
  • the third obtaining module 610 is configured to obtain the maximum difference page number between the MSB page and the LSB page in all the shared page groups of the non-volatile storage space, and send the m to the allocating module 620.
  • the m is a natural number.
  • the shared pages of the storage devices of different vendors are different.
  • the first group of shared pages in each block is page0-page2, that is, the difference between the MSB page and the LSB page. 2page
  • the second group of shared pages is page1_page4 that is, the difference between the MSB page and the LSB page is 3page
  • all the shared page groups traversing a block of the storage device find that the number of pages between the MSB page and the corresponding LSB page is 2 Or 3, so the maximum difference between the MSB page and the LSB page in all shared page groups of the storage device is 3.
  • the allocation module 620 is configured to allocate at least n*p+m page size buffer spaces for the preset buffer area 570, where the p represents the shared page number of the MSB page of the non-volatile storage space.
  • n be a natural number, at least 1.
  • the present embodiment dynamically releases the cache of data that is no longer subject to write disturb.
  • the size of the cache space required by the preset buffer area 570 is related to the maximum number of pages m between the MSB page and the LSB page in all shared page groups of the storage device, and the dynamic release rule.
  • the allocating module 620 allocates at least the preset buffer area.
  • m+n*p page cache space for example, allocates cache space of m+n*p pages.
  • the p represents the number of shared pages of the MSB page of the non-volatile storage space of the storage device, for example, for the MLC class A type of shared device includes a MSB page and an LSB page. Therefore, the MSB page of the non-volatile storage space of the storage device has a shared page number of 1, which is an LSB page.
  • a set of shared pages includes an MSB page, a CSB page, and an LSB page, so the MSB page of the non-volatile storage space of the storage device has a shared page number of 2, including a CSB page and an LSB page.
  • the third determining module 630 is configured to determine, when the write target address belongs to the MSB page in the non-volatile storage space, whether the MSB page where the write target address is located is the last MSB page in the block block. And sending the third determination result to the first obtaining module 640 and the second obtaining module 650.
  • the third determining module 630 determines whether the MSB page where the write target address is located is the last in the block. An MSB page.
  • the first obtaining module 640 is configured to: when the MSB page where the write target address is located is not the last MSB page in the block, obtain the nth MSB page starting from the MSB page where the write target address is located The address of the shared page is sent to the release module 660 as the release data address.
  • a dynamic release cache is adopted.
  • the specific rule is that when the MSB page is written, at least the shared pages of the n MSB pages (such as their corresponding LSB pages and CSB pages) can be cached in the preset buffer.
  • the write interference received by the LSB page from the writing of its corresponding MSB page to the start of writing to the next MSB page is known. More serious, the minimum value of n is 1, in order to ensure that the current data with severe write interference is stored in the cache. However, in order to further reduce the read interference, it is preferable that n is at least 2, that is, when at least two MSB pages following a certain MSB page finish writing data, the LSB page corresponding to the MSB page is deleted.
  • the storage device described in Table 1 in the background is taken as an example. If the current write destination address belongs to page 6, which is an MSB page, and does not belong to the last MSB page, the first obtaining module 640 starts with page 6. The first MSB page forward is page4, and the second MSB page is page2. If n is 1, the page1 shared page, that is, page1, will not write write interference after writing data on page6, so page1 will be generated. The address is used as the release data address to release page1 corresponding to the cache in the preset buffer 570.
  • the floating gate transistor stores more than 2 bits of the storage device, that is, obtains the shared page of the nth MSB page starting from the MSB page where the target address is written (for example, if the floating gate transistor stores 3 bits, the corresponding LSB page is included). And the address of the CBS page) as the release data address.
  • the second obtaining module 650 is configured to obtain an address of a shared page of the last n+1 MSB pages in the block when the MSB page where the write target address is the last MSB page in the block, as the release The data address is sent to the release module 660.
  • the MSB page in which the target address is located is the last MSB page of the block, that is, the write interference of all the pages of the block is eliminated, so that all the data caches of the block can be released, according to the release in the first obtaining module 640.
  • the cache rule when writing to the last MSB page, the data of the shared page of the last n+1 MSB pages remaining in the block is buffered in the preset buffer area, wherein the n is a natural number, at least 1.
  • the second obtaining module 650 acquires the shared page of the last n+1 MSB pages in the block (if the floating gate transistor stores 2 bits, that is, the LSB page; if the floating gate transistor stores 3 bits, that is, the address including the LSB page and the CSB page), As the release data address.
  • the release module 660 is configured to release data pointed to by the cache address in the preset buffer area that has the first mapping relationship with the release data address, and delete the release data address in the first mapping relationship.
  • the release module 660 obtains a cache address having a first mapping relationship with the release data address according to the first mapping relationship, and releases the release of the data on the cache address, so as to ensure that the data retention cache that is currently seriously affected by write write is saved. Perform a dynamic release cache. Since the cache has been released, the release data address in the first mapping relationship and the cache address are deleted.
  • the saving module 670 is configured to save the data in the preset buffer area 570 in the non-volatile storage space when the power is turned off, and establish the cache address and the non-volatile storage space. And storing a second mapping relationship between the addresses, where the second mapping relationship is Sended to the cache module 680.
  • the save module 670 saves the data in the preset buffer area in the non-volatile storage space when the power is turned off. And establishing a second mapping relationship between the cache address in the preset buffer area and the other saved address in the non-volatile storage space, so that the previously cached data of the preset buffer area and the non-volatile storage device can be The other saved data is corresponding.
  • the cache module 680 is configured to buffer, when the power is on, the data pointed to by the other save address of the non-volatile storage space to the cache address of the preset buffer area 570 according to the second mapping relationship.
  • the cache module 680 After re-powering, the cache module 680 acquires another saved address of the non-volatile storage space in the second mapping relationship, and caches the data on the other saved address in a second mapping relationship with the other saved address.
  • the cached address is re-cached according to the original cache address to cache the data before the power-down of the preset buffer, so that when the data of the cached non-volatile storage space needs to be read, the first mapping relationship established according to the previous mapping relationship can be established. Read the corresponding cache data to achieve correct read data.
  • the apparatus for reading data of the present application is limited to all modules including the present embodiment.
  • the apparatus for reading data may include only the third obtaining module in addition to the module shown in FIG. 5. , the distribution module, or only the third determination module, the first acquisition module, the second acquisition module, the release module, or only the save module and the cache module, or a module of the two parts of the above three parts .
  • FIG. 7 is a schematic structural diagram of an embodiment of a controller of the present application.
  • the controller 700 of the present embodiment includes a receiver 701, a processor 702, a memory 703, and a bus 704.
  • the controller 700 is connected to a preset buffer area 710 and a non-volatile storage space 720.
  • the receiver 701 is configured to receive a write command and a read command.
  • the processor 702 is used to calculate the processor 702 .
  • the A mapping relationship finds a cache address corresponding to the read target address, and reads data pointed by the cache address in the preset cache area 710, wherein the first mapping relationship is used to record the a correspondence between the target address and the cache address;
  • the data pointed to by the read target address is not cached in the preset buffer, the data pointed by the read target address is read from the non-volatile storage space 720.
  • processor 702 is further configured to:
  • the write-once data is stored in the non-volatile storage space 720 corresponding to the write target address.
  • processor 702 is further configured to:
  • the MSB page where the write target address is located is not the last MSB page in the block, acquire the address of the shared page of the nth MSB page starting from the MSB page where the write target address is located, and As a release data address, the n is a natural number, at least 1;
  • the second obtaining module is configured to acquire an address of a shared page of the last n+1 MSB pages in the block when the MSB page where the write target address is the last MSB page in the block, as the Release the data address, the n is a natural number, at least 1;
  • processor 702 is further configured to:
  • Obtaining a maximum difference page number between the MSB page and the LSB page in all the shared page groups of the non-volatile storage space 720 is m, where the m is a natural number;
  • processor 702 is further configured to:
  • the data pointed to by the other save address of the non-volatile storage space 720 is cached to the cache address of the preset buffer area 710 according to the second mapping relationship.
  • Memory 703 can include read only memory and random access memory and provides instructions and data to processor 702. A portion of the memory 703 may also include non-volatile random access memory (NVRAM). In various other implementations, the memory 703 can also be located in the same storage medium as the non-volatile storage space 610.
  • NVRAM non-volatile random access memory
  • the memory 703 stores the following elements, executable modules or data structures, or a subset thereof, or an extended set thereof:
  • Operation instructions include various operation instructions for implementing various operations.
  • Operating system Includes a variety of system programs for implementing various basic services and handling hardware-based tasks.
  • the processor 702 performs the above operation by calling an operation instruction stored in the memory 703, which can be stored in the operating system.
  • the processor 702 may also be referred to as a CPU (Central Processing Unit).
  • CPU Central Processing Unit
  • the various components of the controller are coupled together by a bus 704.
  • the bus 704 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. However, for clarity of description, various buses are labeled as bus 704 in the figure.
  • Processor 702 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 702 or an instruction in a form of software.
  • the processor 702 described above may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or discrete hardware. Component.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA off-the-shelf programmable gate array
  • the methods, steps, and logical block diagrams disclosed in the embodiments of the present invention may be implemented or carried out.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 703, and the processor 702 reads the information in the memory 703 and completes the steps of the above method in combination with its hardware.
  • the data of the page which is prone to read data error due to write interference in the storage space is buffered into the preset buffer area, and in the data of the read page, the data is read from the buffer area, so as to Avoid reading data that may be in error in the middle of storage, reducing the error of read data caused by write interference, and thus improving the reliability of the storable device.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device implementations described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the unit described as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, Located in one place, or distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • a computer readable storage medium A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

一种读取数据的方法以及装置，其中，所述方法包括：在接收到包括读取目标地址的读指令时，判断预设缓存区中是否缓存有所述读取目标地址指向的数据（101）；如果有，则根据第一映射关系查找到所述读取目标地址对应的缓存地址，并在所述预设缓存区中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系（102）；如果没有，则从非易失性存储空间中读取所述读取目标地址指向的数据（103）。通过上述方式，能够降低由于写干扰而导致的读数据出错。

Description

读取数据的方法以及装置 技术领域
本申请涉及存储领域，特别是涉及一种读取数据的方法以及装置。
背景技术
目前，固态硬盘(英文：Solid State Drive，简称：SSD)上用于存储的每个浮栅晶体管均可以存储2个或3个比特(英文：bit)，而每个浮栅晶体管上存储的bit是分别分布在不同的页(英文：page)中的，使得每个block中的page按照在浮栅晶体管的存储位置分为不同的2或3类。
以多阶单元储存(英文：Multi Level Cell，简称：MLC)为例，其浮栅晶体管的2个bit分别称为最低有效位(英文：Least Significant Bit，简称：LSB)和最高有效位(英文：Most Significant Bit，简称：MSB)，故将每个block中分别分布在浮栅晶体管不同bit的page分为两类：LSB page(存在浮栅晶体管的LSB上，LSB page也可称为lower page，本申请均统一为LSB page)和MSB page(存在浮栅晶体管的MSB上，MSB page也可称为upper page，本申请均统一为MSB page)。基于LSB page和MSB page对应bit的数据存储在同一个浮栅晶体管，故LSB page和MSB page属于一组共享页(英文：shared pages)，具体某厂家MLC的一个block的共享页如下表1：
Figure PCTCN2015097586-appb-000001
Figure PCTCN2015097586-appb-000002
表1
由于在写入数据的时候是要求必须先写LSB再写MSB的，故需写完整个LSB page才能写入对应的MSB page。而在写入MSB page的过程中，会对先写入的LSB page的数据造成干扰。以上面提供的某厂家MLC为例，根据实验得到在写入数据时的干扰数据如下表2：
Page Page0 Page1 Page2 Page3 Page4 Page5 Page6 Page7 Page8
Page0 0 0 125 105 5 3 4 6 3
Page1   2 1 1 50 35 8 9 6
Page2     0 0 0 0 0 0 0
Page3       0 0 0 296 193 25
Page4         17 15 14 15 16
Page5           0 0 0 270
Page6             0 0 0
Page7               1 0
Page8                 0
表2
上表2表示写入横向的page时，对竖向的page的干扰情况。由上表2可知，在写入MSB page时，其共享页LSB page以及邻近的MSB page的共享页LSB page会出现较严重的错误检查和纠正(英文：“Error Correcting Code，简称：ECC)或不可纠正的ECC错误(英文：Uncorrectable ECC Error，简称：UNC)，如表2中下划线部分为较严重的出错数。
同理，对于浮栅晶体管存储更多bit的存储设备，如3bit的存储设备，即一组共享页包括LAB page、中间有效位页(英文：middle significant bit，简称：CSB)page和MSB page，在写高位的page时，对低位的page也会存在写干扰。
故，如果在低位的page存在写干扰时读取该低位page的数据，则会出现读数据出错。针对该问题，现有常用方式即为提高SSD的ECC纠错能力，以使存储设备的控制器在读取到存在写干扰的page 的数据时，通过ECC纠正读数据的错误。然而提高ECC的纠错能力需要控制器的支持，且在存储设备提供用于做ECC的spare area空间一定的情况下，很难再进一步提升ECC纠错能力，故在读数据时仍出现由于写干扰而导致的读出错。
发明内容
本申请提供一种读取数据的方法以及装置，能够降低由于写干扰而导致的读数据出错。
本申请第一方面提供一种读取数据的方法，包括：在接收到包括读取目标地址的读指令时，判断预设缓存区中是否缓存有所述读取目标地址指向的数据；如果有，则根据第一映射关系查找到所述读取目标地址对应的缓存地址，并在所述预设缓存区中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系；如果没有，则从非易失性存储空间中读取所述读取目标地址指向的数据。
结合第一方面，在第一方面的第一种可能实施方式中，还包括：在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间中的最高有效位页MSB page，其中，所述写指令包括需写入数据和所述写入目标地址；如果不属于，则将所述需写入数据存储到所述预设缓存区和所述写入目标地址对应的非易失性存储空间中，并建立所述缓存地址与所述目标地址之间的所述第一映射关系；如果属于，则将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间中。
结合第一方面的第一种可能实施方式，在第一方面的第二种可能实施方式中，还包括：获取所述非易失性存储空间的所有共享页组中MSB page与LSB page之间的最大相差页数为m，所述m为自然数；为所述预设缓存区分配至少n*p+m个page大小的缓存空间，其中，所述p表示所述非易失性存储空间的MSB page的共享页数，所述n为自然数，至少为1。
结合第一方面的第二种可能实施方式，在第一方面的第三种可能 实施方式中，还包括：如果所述写入目标地址属于所述非易失性存储空间中的MSB page，则判断所述写入目标地址所在的MSB page是否为块block中的最后一个MSB page；如果不是，则获取以所述写入目标地址所在的MSB page为始点向前第n个MSB page的共享页的地址，并作为释放数据地址；如果是，则获取所述block中最后n+1个MSB page的共享页的地址，作为所述释放数据地址；将所述预设缓存区中与所述释放数据地址具有第一映射关系的缓存地址指向的数据释放，并删除所述第一映射关系中的所述释放数据地址。
结合第一方面或者第一方面的第一种至第三种可能实施方式，在第一方面的第四种可能实施方式中，还包括：在掉电时，将所述预设缓存区中的数据另保存在所述非易失性存储空间中，并建立所述缓存地址与所述非易失性存储空间的另保存地址之间的第二映射关系；在上电时，根据所述第二映射关系，将所述非易失性存储空间的另保存地址指向的数据缓存至所述预设缓存区的所述缓存地址上。
结合第一方面或者第一方面的第一种至第三种可能实施方式，在第一方面的第五种可能实施方式中，所述预设缓存区位于双倍速率同步动态随机存储器DDR或者静态随机存取存储器SRAM中。
结合第一方面或者第一方面的第一种至第三种可能实施方式，在第一方面的第六种可能实施方式中，所述非易失性存储空间为固态硬盘SSD的存储空间。
本申请第二方面提供一种读取数据的装置，包括第一判断模块、第一读取模块和第二读取模块；所述第一判断模块用于在接收到包括读取目标地址的读指令时，判断预设缓存区中是否缓存有所述读取目标地址指向的数据，并将第一判断结果发送到第一、第二读取模块；所述第一读取模块用于在预设缓存区中缓存有所述读取目标地址指向的数据时，根据第一映射关系查找到与所述读取目标地址对应的缓存地址，并在所述预设缓存区中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系；所述第二读取模块用于在预设缓存区中没有缓存所述读取目标地址指向的数据时，从所述非易失性存储空间中读取所述读取目标 地址指向的数据。
结合第二方面，在第二方面的第一种可能实施方式中，还包括第二判断模块、第一写入模块、第二写入模块，所述第二判断模块用于在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间中的最高有效位页MSB page，并将第二判断结果发送给第一、第二写入模块，其中，所述写指令包括需写入数据和所述写入目标地址；所述第一写入模块用于在判断所述写入目标地址不属于非易失性存储空间的MSB page时，将所述需写入数据存储到所述预设缓存区和所述写入目标地址对应的非易失性存储空间中，并建立所述缓存地址与所述目标地址之间的所述第一映射关系；所述第二写入模块用于在判断所述写入目标地址属于非易失性存储空间的MSB page时，将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间中。
结合第二方面的第一种可能实施方式，在第二方面的第二种可能实施方式中，还包括第三获取模块和分配模块；所述第三获取模块用于获取所述非易失性存储空间的所有共享页组中MSB page与LSB page之间的最大相差页数为m，并将所述m发送给所述分配模块，所述m为自然数；所述分配模块用于为所述预设缓存区分配至少n*p+m个page大小的缓存空间，其中，所述p表示所述非易失性存储空间的MSB page的共享页数，所述n为自然数，至少为1。
结合第二方面的第二种可能实施方式，在第二方面的第三种可能实施方式中，还包括第三判断模块、第一获取模块、第二获取模块和释放模块；所述第三判断模块用于在所述写入目标地址属于所述非易失性存储空间中的MSB page时，判断所述写入目标地址所在的MSB page是否为块block中的最后一个MSB page，并将第三判断结果发送给第一、第二获取模块；所述第一获取模块用于在所述写入目标地址所在的MSB page不为block中的最后一个MSB page时，获取以所述写入目标地址所在的MSB page为始点向前第n个MSB page的共享页的地址，并作为释放数据地址，将所述释放数据地址发送给所述释放模块；所述第二获取模块用于在所述写入目标地址所在的 MSB page为block中的最后一个MSB page时，获取所述block中最后n+1个MSB page的共享页的地址，作为所述释放数据地址，将所述释放数据地址发送给所述释放模块；所述释放模块用于将所述预设缓存区中与所述释放数据地址具有第一映射关系的缓存地址指向的数据释放，并删除所述第一映射关系中的所述释放数据地址。
结合第二方面或者第二方面的第一至第三种可能实施方式，在第二方面的第四种可能实施方式中，还包括保存模块和缓存模块；所述保存模块用于在掉电时，将所述预设缓存区中的数据另保存在所述非易失性存储空间中，并建立所述缓存地址与所述非易失性存储空间的另保存地址之间的第二映射关系，将所述第二映射关系发送给所述缓存模块；所述缓存模块用于在上电时，根据所述第二映射关系，将所述非易失性存储空间的另保存地址指向的数据缓存至所述预设缓存区的所述缓存地址上。
结合第二方面或者第二方面的第一至第三种可能实施方式，在第二方面的第五种可能实施方式中，所述预设缓存区位于双倍速率同步动态随机存储器DDR或者静态随机存取存储器SRAM中。
结合第二方面或者第二方面的第一至第三种可能实施方式，在第二方面的第六种可能实施方式中，所述非易失性存储空间为固态硬盘SSD的存储空间。
上述方案中，采用缓存数据优先读取的方式，在预设缓存区缓存有读取目标地址指向的数据时，优先从预设缓存区中读取数据，由于缓存区中的数据不存在非易失性存储空间的写干扰，故降低了由于写干扰导致的读出错，提高了存储设备的可靠性。
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图1是本申请读取数据的方法一实施方式的流程图；
图2是本申请读取数据的方法另一实施方式的部分流程图；
图3是本申请读取数据的方法再一实施方式的流程图；
图4是本申请读取数据的方法又再一实施方式的部分流程图；
图5是本申请读取数据的装置一实施方式的结构示意图；
图6是本申请读取数据的装置另一实施方式的结构示意图
图7是本申请控制器一实施方式的结构示意图。
具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
请参阅图1，图1是本申请读取数据的方法一实施方式的流程图。本实施方式的方法由存储设备的控制器执行，本申请的存储设备可以为浮栅晶体管可存储2bit以上的任意非易失性存储设备，如MLC类型(每个浮栅晶体管存储2bit)、TLC(全称：Trinary-Level Cell)类型(每个浮栅晶体管存储3bit)的SSD。存储设备包括非易失性存储空间，所述非易失性存储空间即为浮栅晶体管存储的空间，具体如SSD的存储矩阵。存储设备的非易失性存储空间包括多组共享页组，例如，MLC类型的存储设备的非易失性存储空间包括多组共享页组，每组共享页组包括MSB page和LSB page；TLC类型的存储设备的非易失性存储空间包括多组共享页组，每组共享页组包括MSB page、CSB page和LSB page。
具体地，本实施方式的所述方法包括：
101：存储设备的控制器在接收到包括读取目标地址的读指令时，判断预设缓存区中是否缓存有所述读取目标地址指向的数据。
如背景技术中所述，当将数据写入存储设备的非易失性存储空间的MSB page中时，会对其共享页即如对应的LSB page、CSB page产生写干扰，从而可能导致读数据出错。为避免由于写入MSB page时所带来写干扰，本申请采用对会受到上述写干扰影响的数据进行缓存备份，并在读取该类数据时，优先考虑预设缓存区中读取的方式。
具体如，将写入数据时，存储设备的控制器将存储设备的会受到上述写干扰的数据同时存储在预设缓存区和非易失性存储空间，且建 立缓存地址与非易失性存储空间的地址之间的第一映射关系。当存储设备的控制器从SATA/SAS/PCIe接口接收到主机发送的读指令时，该读指令包括读取目标地址，以指示控制器从非易失性存储空间中读取所述读取目标地址指向的数据。控制器查找是否存在读取目标地址的第一映射关系，如果存在，则判断为预设缓存区中缓存有读取目标地址指向的数据，并执行102；如果不存在，则判断为预设缓存区中没有缓存读取目标地址指向的数据，并执行103。
可以理解的是，存储设备的控制器未必通过第一映射关系判断读取的数据是否有缓存。在其他实施方式中，控制器还可以另外建立记录该地址上的数据是否缓存的标识，在读数据时，通过读取该地址的标识判断该目标读地址上的数据是否缓存。故在此对如何判断读取的数据是否缓存的方式不作具体限定。
另外，存储设备的控制器在接收到读指令时，还可先判断所述读取目标地址指向的数据是否属于会受到写干扰的数据，例如判断所述读取目标地址是否属于MSB page，如果不属于，则所述读取目标地址指向的数据属于会受到写干扰的数据，即判断所述预设缓存区中是否缓存有所述读取目标地址指向的数据。
102：存储设备的控制器根据第一映射关系查找到所述读取目标地址对应的缓存地址，并在所述预设缓存区中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系。
根据优选读取缓存的原则，如果判断预设缓存区缓存有读取目标地址指向的数据，则存储设备的控制器根据保存的第一映射关系，查找到与读取目标地址对应的缓存地址，并在预设缓存区中读取该缓存地址上的数据，以实现读数据，由于缓存区中的数据不存在存储矩阵的写干扰情况，故从缓存区中读取数据保证读数据的正确性。
103：存储设备的控制器从所述非易失性存储空间中读取所述读取目标地址指向的数据。
如果判断预设缓存区没有缓存读取目标地址指向的数据，则存储设备的控制器按照正常读取方式，从非易失性存储空间中读取所述读 取目标地址上的数据，以实现读数据。
本实施方式采用缓存数据优先读取的方式，在预设缓存区缓存有读取目标地址指向的数据时，优先从预设缓存区中读取数据，由于缓存区中的数据不存在非易失性存储空间的写干扰，故降低了由于写干扰导致的读出错，提高了存储设备的可靠性。
请参阅图2，图2是本申请读取数据的方法另一实施方式的部分流程图。本实施方式中，存储设备的控制器在执行上一实施方式的方法步骤之前，还执行：
201：存储设备的控制器在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间中的MSB page，其中，所述写指令包括需写入数据和所述写入目标地址。
本申请的存储设备的每个浮栅晶体管可存储2bit以上，故将存储设备的非易失性存储空间的page至少分为LSB page和MSB page两大类，当浮栅晶体管可存储3bit时，存储设备的非易失性存储空间的page还包括CSB page。
存储设备的控制器从接口如SATA/SAS/PCIe接口接收到主机发送的写指令，该写指令包括需写入数据和写入目标地址，以指示控制器将需写入数据存储到写入目标地址指向的非易失性存储空间中。控制器接收到写指令后，先判断写入目标地址是否属于该非易失性存储空间的MSB page，如果不属于，则执行202，如果属于，则执行203。
202：存储设备的控制器将所述需写入数据存储到预设缓存区和所述写入目标地址对应的非易失性存储空间中，并建立所述缓存地址与所述写入目标地址之间的第一映射关系。
如背景技术中所述，当将数据写入存储设备的非易失性存储空间的MSB page中时，会对其共享页即如对应的LSB page、CSB page产生写干扰，从而可能导致读数据出错。故，控制器在判断写入目标地址不属于MSB page时，即表示该需写入数据在后续的MSB page写入数据时可能会受到写干扰，故将该需写入数据存储到写入目标地址指向的非易失性存储空间中，并且缓存到预设缓存区作为备份。其中，该预设缓存区可以为存储设备中的双倍速率同步动态随机存储器 (英文：Double Data Rate，简称：DDR)。例如，对于常规的SSD，其内部本身设置有DDR，无论写数据还是读数据，数据均会经过DDR。基于此种存储方式，可优选将预设缓存区设置在DDR上，即在DDR中开放一定缓存空间作为预设缓存区。当然，该预设缓存区还可以为除该非易失性存储空间之外的其他存储器，如静态随机存取存储器(英文：Static Random-Access Memory，简称：SRAM)。
在上述写入完成后，控制器获取该需写入数据缓存在预设缓存区中的缓存地址，并建立缓存地址和写入目标地址之间的第一映射关系，以便于将预设缓存区中的数据与非易失性存储空间中的数据对应起来。该第一映射关系可以以表格方式保存在存储设备的非易失性存储空间中或者预设缓存区中。
203：存储设备的控制器将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间中。
由于非易失性存储空间的MSB page不存在写干扰，故当控制器判断需写入数据属于非易失性存储空间的MSB page时，则无需将所述需写入数据缓存备份，直接根据写入目标地址将数据存储到非易失性存储空间中。
存储设备的控制器在执行上述201-203后，再执行图1所示的101-103。
本实施方式将可能受到MSB page写干扰而导致读出错的数据均作缓存备份，并在读取此部分数据时优先从缓存中读取，故避免了读取数据时由于该数据当前受到写干扰而导致读出错的情况，降低了由于写干扰导致的读出错，提高了存储设备的可靠性。
请参阅图3，图3是本申请读取数据的方法再一实施方式的流程图。具体，该方法包括：
301：存储设备的控制器获取所述非易失性存储空间的所有共享页组中MSB page与LSB page之间的最大相差页数为m，所述m为自然数。
不同厂商的存储设备的共享页是不同的，如背景技术的表1所示的存储设备，其每个block中的第一组共享页为page0—page2，即该 MSB page与LSB page之间相差2page，第二组共享页为page1—page4，即该MSB page与LSB page之间相差3page，遍历存储设备一个block的所有共享页组发现MSB page与对应LSB page之间相差的页数均为2或者3，故存储设备所有共享页组中的MSB page与LSB page之间的最大相差页数为3。
302：存储设备的控制器为所述预设缓存区分配至少n*p+m个page大小的缓存空间，其中，所述p表示所述非易失性存储空间的MSB page的共享页数，所述n为自然数，至少为1。
为了尽量降低对缓存空间的占用量，本实施方式动态释放不再受到写干扰的数据的缓存。预设缓存区所需的缓存空间大小即与存储设备的所有共享页组中的MSB page与LSB page之间的最大相差页数m、以及动态释放规则相关。存储设备的非易失性存储空间的共享页组中的MSB page与LSB page之间的最大相差m页，即表示要想保证在写完MSB page前，该MSB page的共享页(如其对应的LSB page、CSB page)能缓存在预设缓存区中以避免受到MSB page写干扰导致读出错，预设缓存区起码需要m个page的缓存空间。同时，本申请的动态释放规则为写入某一MSB page时，至少保证所述MSB page之前的n个MAB page的共享页(如其对应的LSB page、CSB page)能缓存预设缓存区中。根据实验数据，n至少为1即可基本保证当前写干扰较严重的数据均保存在缓存中。
根据上述缓存空间大小规定原则和存储设备的非易失性存储空间的共享页组的设置规则，为保证当前写干扰较严重的数据均保存在缓存中，存储设备的控制器为预设缓存区分配至少m+n*p个page的缓存空间，例如分配m+n*p个page的缓存空间。所述p表示所述存储设备的非易失性存储空间的MSB page的共享页数，例如对于MLC类型的存储设备，其一组共享页包括MSB page、LSB page，故该存储设备的非易失性存储空间的MSB page的共享页数为1，即为LSB page。对于TLC类型的存储设备，其一组共享页包括MSB page、CSB page以及LSB page，故该存储设备的非易失性存储空间的MSB page的共享页数为2，包括CSB page以及LSB page。
303：存储设备的控制器在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间中的MSB page，其中，所述写指令包括需写入数据和所述写入目标地址。
控制器接收到写指令后，先判断写入目标地址是否属于该存储设备的非易失性存储空间的MSB page，如果不属于，则执行304，如果属于，则执行305。
304：存储设备的控制器将所述需写入数据存储到所述预设缓存区和所述写入目标地址对应的非易失性存储空间中，并建立所述缓存地址与所述目标地址之间的所述第一映射关系。
305:存储设备的控制器将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间中，并判断所述写入目标地址所在的MSB page是否为block中的最后一个MSB page。
如果所述写入目标地址属于所述非易失性存储空间中的MSB page，则存储设备的控制器只将所述需写入数据存储到所述写入目标地址指向的非易失性存储空间中，并且判断写入目标地址所在的MSB page是否为block中的最后一个MSB page，如表1所示的block的最后一个MSB page即为page255，如果判断写入目标地址不属于page255，则执行306，如果判断写入目标地址属于page255，则执行307。
306：存储设备的控制器获取以所述写入目标地址所在的MSB page为始点向前第n个MSB page的共享页的地址，并作为释放数据地址。
本实施方式采用动态释放缓存的方式，具体规则为写入MSB page时，至少保证n个MSB page的共享页(如其对应的LSB page、CSB page)能缓存预设缓存区中。在根据背景技术中表2所示的MLC类型存储设备为例，由表2可知，LSB page从其对应的MSB page写入到下一个MSB page开始写入之间的过程中所受到的写干扰比较严重，n的最小值为1，才能保证当前写干扰较严重的数据均保存在缓存中。但为进一步降低读干扰，优选n至少为2，即当某一MSB page后面的至少2个MSB page写完数据后，才删除该MSB page对应的 LSB page。
具体，继续以背景技术中的表1所述的存储设备为例，假如当前写入目标地址属于page6，为MSB page，且不属于最后一个MSB page，故控制器以page6为始点，向前第1个MSB page为page4，向前第2个MSB page为page2。如果n为1，即将page4的共享页即page1视为在page6写入数据后则不再产生写干扰，故获取page1的地址作为释放数据地址，以将page1对应在预设缓存区的缓存释放。根据上述动态释放缓存的方式，当写入page2时，不释放缓存区中的数据；当写入page4，释放缓存区中的page0；当写入page6，释放缓存区中的page1；当写入page8，释放缓存区中的page3……依次类推，即实现在上表2的黑体部分数据显示的写干扰消除前，均能够从缓存中读取到正确数据。
浮栅晶体管存储多于2bit的存储设备同理，即获取以写入目标地址所在的MSB page为始点向前第n个MSB page的共享页(如浮栅晶体管存储3bit，则包括对应的LSB page和CBS page)的地址，作为释放数据地址。
307：存储设备的控制器获取所述block中最后n+1个MSB page的共享页的地址，作为所述释放数据地址。
如果写入目标地址所在的MSB page为block的最后一个MSB page，即表示该block的所有page的写干扰消除，故可将该block的所有数据缓存释放，根据上述306的释放缓存规则，当写到最后一个MSB page的时候，block中还剩余最后n+1个MSB page的共享页的数据缓存在预设缓存区中，其中，所述n为自然数，至少为1。故控制器获取block中最后n+1个MSB page的共享页(如果浮栅晶体管存储2bit，即为LSB page；如果浮栅晶体管存储3bit，即包括LSB page和CSB page)的地址，作为所述释放数据地址。
308：存储设备的控制器将预设缓存区中与所述释放数据地址具有第一映射关系的缓存地址指向的数据释放，并删除所述第一映射关系中的所述释放数据地址。
存储设备的控制器根据第一映射关系，获取与所述释放数据地址 具有第一映射关系的缓存地址，并释放该缓存地址上的数据释放，实现在保证当前严重受到写干扰的数据保持缓存的前提下进行动态释放缓存。由于该缓存已经释放，故删除第一映射关系中的该释放数据地址与该缓存地址。
309：存储设备的控制器在接收到包括读取目标地址的读指令时，判断预设缓存区中是否缓存有所述读取目标地址指向的数据。如果有缓存，则执行310，如果没有缓存，则执行311。
310：存储设备的控制器根据第一映射关系查找到所述读取目标地址对应的缓存地址，并在所述预设缓存区中读取所述缓存地址指向的数据。
311：存储设备的控制器从所述非易失性存储空间中读取所述读取目标地址指向的数据。
由于本实施方式将可能受到MSB page写干扰而导致读出错的数据均作缓存备份，并在读取此部分数据时优先从缓存中读取，故避免了读取数据时由于该数据当前受到写干扰而导致读出错的情况，大大降低了由于写干扰导致读出错的概率。而且，本实施方式针对存储设备在写入MSB page时只会对其共享页以及其前面相邻的MSB page的共享页产生写干扰，故采用动态释放缓存的方式，以减小所需缓存空间。同时，本申请根据存储设备的共享页组的最大相差页数m分配缓存空间，以兼容不同厂商的存储设备。
请参阅图4，图4是本申请读取数据的方法又再一实施方式的部分流程图。本实施方式的方法除包括上面实施方式的步骤外，还包括：
401：在掉电时，存储设备的控制器将预设缓存区中的数据另保存在所述非易失性存储空间中，并建立所述缓存地址与所述非易失性存储空间的另保存地址之间的第二映射关系。
由于在存储设备掉电后，预设缓存区中的数据会丢失。为保证下次上电后仍能对非易失性存储空间中的数据的正确读取，在掉电时，控制器将预设缓存区中的数据另保存在非易失性存储空间，并且建立预设缓存区中的缓存地址和在非易失性存储空间中的另保存地址之间的第二映射关系，使得能够将预设缓存区的之前缓存的数据与非易 失性存储设备另保存的数据对应起来。
402：在上电时，存储设备的控制器根据所述第二映射关系，将所述非易失性存储空间的另保存地址指向的数据缓存至所述预设缓存区的所述缓存地址上。
在重新上电后，存储设备的控制器获取第二映射关系中的非易失性存储空间的另保存地址，并将该另保存地址上的数据对应缓存在与该另保存地址具有第二映射关系的缓存地址上，以将预设缓存区掉电前缓存的数据按照原来缓存地址重新缓存，使得在需要读取有缓存的非易失性存储空间的数据时，能够按照之前建立的第一映射关系读取对应的缓存数据，实现正确的读数据。
请参阅图5，图5是本申请读取数据的装置一实施方式的结构示意图。本实施方式中，读取数据的装置500具体可以为存储设备的控制器，所述存储设备可以为浮栅晶体管可存储2bit以上的任意非易失性存储设备，如MLC类型、TLC类型的SSD。所述读取数据的装置500包括第一判断模块510、第一读取模块520、第二读取模块530，该读取数据的装置500与预设缓存区570和非易失性存储空间580连接。
第一判断模块510用于在接收到包括读取目标地址的读指令时，判断预设缓存区570中是否缓存有所述读取目标地址指向的数据，并将第一判断结果发送到第一读取模块520、第二读取模块530。
为避免由于写入MSB page时所带来写干扰，本申请采用对可能受到上述写干扰影响的数据进行缓存备份，并在读取该类数据时，优先考虑预设缓存区570中读取的方式。
具体如，第一判断模块510从SATA/SAS接口接收到主机发送的读指令，该读指令包括读取目标地址，以指示从非易失性存储空间580中读取所述读取目标地址指向的数据。第一判断模块510查找是否存在读取目标地址的第一映射关系，如果存在，则判断为预设缓存区570中缓存有读取目标地址指向的数据；如果不存在，则判断为预设缓存区570中没有缓存读取目标地址指向的数据。
可以理解的是，第一判断模块510未必通过第一映射关系判断读 取的数据是否有缓存。在其他实施方式中，第一判断模块510还可以另外建立记录该地址上的数据是否缓存的标识，在读数据时，通过读取该地址的标识判断该读取目标地址上的数据是否缓存。故在此对如何判断读取的数据是否与缓存的方式不作具体限定。
另外，第一判断模块510在接收到读指令时，还可先判断所述读取目标地址指向的数据是否属于会受到写干扰的数据，例如判断所述读取目标地址是否属于MSB page，如果不属于，再判断所述预设缓存区570中是否缓存有所述读取目标地址指向的数据。
第一读取模块520用于在预设缓存区中缓存有所述读取目标地址指向的数据时，根据第一映射关系查找到与所述读取目标地址对应的缓存地址，并在所述预设缓存区570中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系。
根据优选读取缓存的原则，在第一判断模块510判断预设缓存区570缓存有读取目标地址指向的数据时，第一读取模块520根据保存的第一映射关系，获取与读取目标地址对应的缓存地址，并在预设缓存区570中读取该缓存地址上的数据，以实现读数据，由于缓存区中的数据不会如存储矩阵中的数据那样受到写干扰，故从缓存区中读取数据保证读数据的正确性。
第二读取模块530用于在预设缓存区570中没有缓存所述读取目标地址指向的数据时，从所述非易失性存储空间580中读取所述读取目标地址指向的数据。
在第一判断模块510判断预设缓存区570没有缓存读取目标地址指向的数据时，第二读取模块530按照正常读取方式，从非易失性存储空间580中读取所述读取目标地址上的数据，以实现读数据。
可选地，本实施方式的读取数据的装置500还可包括第二判断模块540、第一写入模块550和第二写入模块560。
第二判断模块540用于在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间中的MSB page，并将第二判断结果发送给第一写入模块550、第二写入模块560，其中，所述 写指令包括需写入数据和所述写入目标地址。
第二判断模块540从接口如SATA/SAS/PCIe接口接收到主机发送的写指令，该写指令包括需写入数据和写入目标地址，以指示将需写入数据存储到写入目标地址指向的非易失性存储空间580(如存储设备的存储矩阵)中。第二判断模块540接收到写指令后，先判断写入目标地址是否属于该存储设备的非易失性存储空间的MSB page。
第一写入模块550用于在判断所述写入目标地址不属于非易失性存储空间中的MSB page时，将所述需写入数据存储到预设缓存区570和存储到所述写入目标地址对应的非易失性存储空间580中，并建立所述缓存地址与所述写入目标地址之间的第一映射关系。
第一写入模块550在第二判断模块540判断写入目标地址不属于MSB page时，即表示该需写入数据在在后续的MSB page写入数据时可能会受到写干扰，故将该需写入数据存储到写入目标地址指向的非易失性存储空间580中，并且缓存到预设缓存区作为备份。其中，该预设缓存区570可以为存储设备中的DDR或者SRAM。
在上述写入完成后，第一写入模块550获取该需写入数据缓存在预设缓存区570中的缓存地址，并建立缓存地址和写入目标地址之间的第一映射关系，以便于将预设缓存区570中的数据与非易失性存储空间580中的数据对应起来。该第一映射关系可以以表格方式保存在存储设备的非易失性存储空间580中或者预设缓存区570中。
第二写入模块560用于在判断所述写入目标地址属于非易失性存储空间中的MSB page时，将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间580中。
由于非易失性存储空间的MSB page不存在写干扰，故当第二判断模块540判断需写入数据属于非易失性存储空间的MSB page时，无需将所述需写入数据缓存备份，直接根据写入目标地址将数据存储到非易失性存储空间580中。
由于本实施方式将可能受到MSB page写干扰而导致读出错的数据均作缓存备份，并在读取此部分数据时优先从缓存中读取，故避免了读取数据时由于该数据当前受到写干扰而导致读出错的情况，大大 降低了由于写干扰导致读出错的概率，提高了存储设备的可靠性。
请参阅图6，图6是本申请读取数据的装置一实施方式的结构示意图。具体，除了上一实施方式所包括的模块之外(其中，图5中的模块若在本实施方式下面描述中没有提及则不在图6中示出，但这并不表示本实施方式的读取数据的装置不包括该模块)，该读取数据的装置600还包括第三获取模块610、分配模块620、第三判断模块630、第一获取模块640、第二获取模块650、释放模块660、保存模块670和缓存模块680。
第三获取模块610用于获取所述非易失性存储空间的所有共享页组中MSB page与LSB page之间的最大相差页数为m，并将所述m发送给所述分配模块620，所述m为自然数。
不同厂商的存储设备的共享页是不同的，如背景技术的表1所示的存储设备，其每个block中的第一组共享页为page0—page2，即该MSB page与LSB page之间相差2page，第二组共享页为page1—page4，即该MSB page与LSB page之间相差3page，遍历存储设备一个block的所有共享页组发现MSB page与对应LSB page之间相差的页数均为2或者3，故存储设备所有共享页组中的MSB page与LSB page之间的最大相差页数为3。
分配模块620用于为所述预设缓存区570分配至少n*p+m个page大小的缓存空间，其中，所述p表示所述非易失性存储空间的MSB page的共享页数，所述n为自然数，至少为1。
为了尽量降低对缓存空间的占用量，本实施方式动态释放不再受到写干扰的数据的缓存。预设缓存区570所需的缓存空间大小即与存储设备的所有共享页组中的MSB page与LSB page之间的最大相差页数m、以及动态释放规则相关。
根据上述缓存空间大小规定原则和存储设备的非易失性存储空间的共享页组的设置规则，为保证当前写干扰较严重的数据均保存在缓存中，分配模块620为预设缓存区分配至少m+n*p个page的缓存空间，例如分配m+n*p个page的缓存空间。所述p表示所述存储设备的非易失性存储空间的MSB page的共享页数，例如对于MLC类 型的存储设备，其一组共享页包括MSB page、LSB page，故该存储设备的非易失性存储空间的MSB page的共享页数为1，即为LSB page。对于TLC类型的存储设备，其一组共享页包括MSB page、CSB page以及LSB page，故该存储设备的非易失性存储空间的MSB page的共享页数为2，包括CSB page以及LSB page。
第三判断模块630用于在所述写入目标地址属于所述非易失性存储空间中的MSB page时，判断所述写入目标地址所在的MSB page是否为块block中的最后一个MSB page，并将第三判断结果发送给第一获取模块640、第二获取模块650。
例如，在第二判断模块540判断所述写入目标地址属于所述非易失性存储空间中的MSB page时，第三判断模块630判断写入目标地址所在的MSB page是否为block中的最后一个MSB page。
第一获取模块640用于在所述写入目标地址所在的MSB page不为block中的最后一个MSB page时，获取以所述写入目标地址所在的MSB page为始点向前第n个MSB page的共享页的地址，作为所述释放数据地址，将所述释放数据地址发送给所述释放模块660。
本实施方式采用动态释放缓存的方式，具体规则为写入MSB page时，至少保证n个MSB page的共享页(如其对应的LSB page、CSB page)能缓存预设缓存区中。在根据背景技术中表2所示的MLC类型存储设备为例，由表2可知，LSB page从其对应的MSB page写入到下一个MSB page开始写入之间的过程中所受到的写干扰比较严重，n的最小值为1，才能保证当前写干扰较严重的数据均保存在缓存中。但为进一步降低读干扰，优选n至少为2，即当某一MSB page后面的至少2个MSB page写完数据后，才删除该MSB page对应的LSB page。
具体，继续以背景技术中的表1所述的存储设备为例，假如当前写入目标地址属于page6，为MSB page，且不属于最后一个MSB page，故第一获取模块640以page6为始点，向前第1个MSB page即为page4，向前第2个MSB page为page2。如果n为1，即将page4的共享页即page1在page6写入数据后则不再产生写干扰，故将page1 的地址作为释放数据地址，以将page1对应在预设缓存区570的缓存释放。
浮栅晶体管存储多于2bit的存储设备同理，即获取以写入目标地址所在的MSB page为始点向前第n个MSB page的共享页(如浮栅晶体管存储3bit，则包括对应的LSB page和CBS page)的地址，作为释放数据地址。
第二获取模块650用于在所述写入目标地址所在的MSB page为block中的最后一个MSB page时，获取所述block中最后n+1个MSB page的共享页的地址，作为所述释放数据地址，将所述释放数据地址发送给所述释放模块660。
如果写入目标地址所在的MSB page为block的最后一个MSB page，即表示该block的所有page的写干扰消除，故可将该block的所有数据缓存释放，根据上述第一获取模块640中的释放缓存规则，当写到最后一个MSB page的时候，block中还剩余最后n+1个MSB page的共享页的数据缓存在预设缓存区中，其中，所述n为自然数，至少为1。故第二获取模块650获取block中最后n+1个MSB page的共享页(如果浮栅晶体管存储2bit，即为LSB page；如果浮栅晶体管存储3bit，即包括LSB page和CSB page)的地址，作为所述释放数据地址。
释放模块660用于将所述预设缓存区中与所述释放数据地址具有第一映射关系的缓存地址指向的数据释放，并删除所述第一映射关系中的所述释放数据地址。
释放模块660根据第一映射关系，获取与所述释放数据地址具有第一映射关系的缓存地址，并释放该缓存地址上的数据释放，实现在保证当前严重受到写干扰的数据保持缓存的前提下进行动态释放缓存。由于该缓存已经释放，故删除第一映射关系中的该释放数据地址与该缓存地址。
保存模块670用于在掉电时，将所述预设缓存区570中的数据另保存在所述非易失性存储空间中，并建立所述缓存地址与所述非易失性存储空间的另保存地址之间的第二映射关系，将所述第二映射关系 发送给所述缓存模块680。
由于在存储设备掉电后，预设缓存区570中的数据会丢失。为保证下次上电后仍能对非易失性存储空间中的数据的正确读取，在掉电时，保存模块670将预设缓存区中的数据另保存在非易失性存储空间，并且建立预设缓存区中的缓存地址和在非易失性存储空间中的另保存地址之间的第二映射关系，使得能够将预设缓存区的之前缓存的数据与非易失性存储设备另保存的数据对应起来。
缓存模块680用于在上电时，根据所述第二映射关系，将所述非易失性存储空间的另保存地址指向的数据缓存至所述预设缓存区570的所述缓存地址上。
在重新上电后，缓存模块680获取第二映射关系中的非易失性存储空间的另保存地址，并将该另保存地址上的数据对应缓存在与该另保存地址具有第二映射关系的缓存地址上，以将预设缓存区掉电前缓存的数据按照原来缓存地址重新缓存，使得在需要读取有缓存的非易失性存储空间的数据时，能够按照之前建立的第一映射关系读取对应的缓存数据，实现正确的读数据。
可以理解的是，本申请读取数据的装置限于包括本实施方式的所有模块，在不同实施方式中，读取数据的装置除包括图5所示的模块外，还可只包括第三获取模块、分配模块，或者还只包括第三判断模块、第一获取模块、第二获取模块、释放模块，或者还只包括保存模块和缓存模块，或者还包括上述三部分的模块的其中两部分的模块。
参阅图7，图7是本申请控制器一实施方式的结构示意图。本实施方式的控制器700包括接收器701、处理器702、存储器703以及总线704，控制器700与预设缓存区710和非易失性存储空间720连接。
接收器701用于接收写指令和读指令。
处理器702用于
在接收到包括读取目标地址的读指令时，判断预设缓存区710中是否缓存有所述读取目标地址指向的数据；
在预设缓存区中缓存有所述读取目标地址指向的数据时，根据第 一映射关系查找到与所述读取目标地址对应的缓存地址，并在所述预设缓存区710中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系；
在预设缓存区中没有缓存所述读取目标地址指向的数据时，从所述非易失性存储空间720中读取所述读取目标地址指向的数据。
可选地，处理器702还可用于:
在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间720中的最高有效位页MSB page，其中，所述写指令包括需写入数据和所述写入目标地址；
在判断所述写入目标地址不属于非易失性存储空间的MSB page时，将所述需写入数据存储到所述预设缓存区710和所述写入目标地址对应的非易失性存储空间720中，并建立所述缓存地址与所述目标地址之间的所述第一映射关系；
在判断所述写入目标地址属于非易失性存储空间的MSB page时，将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间720中。
可选地，处理器702还用于：
在所述写入目标地址属于所述非易失性存储空间720中的MSB page时，判断所述写入目标地址所在的MSB page是否为块block中的最后一个MSB page；
在所述写入目标地址所在的MSB page不为block中的最后一个MSB page时，获取以所述写入目标地址所在的MSB page为始点向前第n个MSB page的共享页的地址，并作为释放数据地址，所述n为自然数，至少为1；
所述第二获取模块用于在所述写入目标地址所在的MSB page为block中的最后一个MSB page时，获取所述block中最后n+1个MSB page的共享页的地址，作为所述释放数据地址，所述n为自然数，至少为1；
将所述预设缓存区710中与所述释放数据地址具有第一映射关系的缓存地址指向的数据释放，并删除所述第一映射关系中的所述释 放数据地址。
可选地，处理器702还用于：
获取所述非易失性存储空间720的所有共享页组中MSB page与LSB page之间的最大相差页数为m，所述m为自然数；
为所述预设缓存区710分配至少n*p+m个page大小的缓存空间，其中，所述p表示所述非易失性存储空间720的MSB page的共享页数，所述n为自然数，至少为1。
可选地，处理器702还用于：
在掉电时，将所述预设缓存区710中的数据另保存在所述非易失性存储空间720中，并建立所述缓存地址与所述非易失性存储空间720的另保存地址之间的第二映射关系；
在上电时，根据所述第二映射关系，将所述非易失性存储空间720的另保存地址指向的数据缓存至所述预设缓存区710的所述缓存地址上。
存储器703可以包括只读存储器和随机存取存储器，并向处理器702提供指令和数据。存储器703的一部分还可以包括非易失性随机存取存储器(NVRAM)。在不同其他实施方式中，存储器703还可以与非易失性存储空间610位于同一存储介质中。
存储器703存储了如下的元素，可执行模块或者数据结构，或者它们的子集，或者它们的扩展集:
操作指令：包括各种操作指令，用于实现各种操作。
操作系统：包括各种系统程序，用于实现各种基础业务以及处理基于硬件的任务。
在本发明实施例中，处理器702通过调用存储器703存储的操作指令(该操作指令可存储在操作系统中)，来执行上述操作。
处理器702还可以称为CPU(Central Processing Unit，中央处理单元)。具体的应用中，控制器的各个组件通过总线704耦合在一起，其中总线704除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线704。
上述本发明实施例揭示的方法可以应用于处理器702中，或者由处理器702实现。处理器702可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器702中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器702可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器703，处理器702读取存储器703中的信息，结合其硬件完成上述方法的步骤。
上述方案中，通过将存储空间中由于写干扰而容易出现读数据出错的page的数据缓存到预设缓存区中，并在读取该page的数据中，选择从缓存区中读取数据，以避免读取到存储中间可能会出错的数据，降低了由于写干扰导致的读数据出错，进而提高可存储设备的可靠性。
在本申请所提供的几个实施方式中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施方式仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以 位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施方式中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施方式所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (14)

  1. 一种读取数据的方法，其特征在于，包括：
    在接收到包括读取目标地址的读指令时，判断预设缓存区中是否缓存有所述读取目标地址指向的数据；
    如果有，则根据第一映射关系查找到所述读取目标地址对应的缓存地址，并在所述预设缓存区中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系；
    如果没有，则从非易失性存储空间中读取所述读取目标地址指向的数据。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间中的最高有效位页MSB page，其中，所述写指令包括需写入数据和所述写入目标地址；
    如果不属于，则将所述需写入数据存储到所述预设缓存区和所述写入目标地址对应的非易失性存储空间中，并建立所述缓存地址与所述目标地址之间的所述第一映射关系；
    如果属于，则将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间中。
  3. 根据权利要求2所述的方法，其特征在于，还包括：
    获取所述非易失性存储空间的所有共享页组中MSB page与LSB page之间的最大相差页数为m，所述m为自然数；
    为所述预设缓存区分配至少n*p+m个page大小的缓存空间，其中，所述p表示所述非易失性存储空间的MSB page的共享页数，所述n为自然数，至少为1。
  4. 根据权利要求3所述的方法，其特征在于，还包括：
    如果所述写入目标地址属于所述非易失性存储空间中的MSB page，则判断所述写入目标地址所在的MSB page是否为块block中 的最后一个MSB page；
    如果不是，则获取以所述写入目标地址所在的MSB page为始点向前第n个MSB page的共享页的地址，并作为释放数据地址；
    如果是，则获取所述block中最后n+1个MSB page的共享页的地址，作为所述释放数据地址；
    将所述预设缓存区中与所述释放数据地址具有第一映射关系的缓存地址指向的数据释放，并删除所述第一映射关系中的所述释放数据地址。
  5. 根据权利要求1至4任一项所述的方法，其特征在于，还包括：
    在掉电时，将所述预设缓存区中的数据另保存在所述非易失性存储空间中，并建立所述缓存地址与所述非易失性存储空间的另保存地址之间的第二映射关系；
    在上电时，根据所述第二映射关系，将所述非易失性存储空间的另保存地址指向的数据缓存至所述预设缓存区的所述缓存地址上。
  6. 根据权利要求1至4任一项所述的方法，其特征在于，所述预设缓存区位于双倍速率同步动态随机存储器DDR或者静态随机存取存储器SRAM中。
  7. 根据权利要求1至4任一项所述的方法，其特征在于，所述非易失性存储空间为固态硬盘SSD的存储空间。
  8. 一种读取数据的装置，其特征在于，包括第一判断模块、第一读取模块和第二读取模块；
    所述第一判断模块用于在接收到包括读取目标地址的读指令时，判断预设缓存区中是否缓存有所述读取目标地址指向的数据，并将第一判断结果发送到第一、第二读取模块；
    所述第一读取模块用于在预设缓存区中缓存有所述读取目标地址指向的数据时，根据第一映射关系查找到与所述读取目标地址对应的缓存地址，并在所述预设缓存区中读取所述缓存地址指向的数据，其中，所述第一映射关系用于记录所述目标地址与所述缓存地址之间的对应关系；
    所述第二读取模块用于在预设缓存区中没有缓存所述读取目标地址指向的数据时，从所述非易失性存储空间中读取所述读取目标地址指向的数据。
  9. 根据权利要求8所述的装置，其特征在于，还包括第二判断模块、第一写入模块、第二写入模块，
    所述第二判断模块用于在接收到写指令时，判断所述写指令中的写入目标地址是否属于非易失性存储空间中的最高有效位页MSB page，并将第二判断结果发送给第一、第二写入模块，其中，所述写指令包括需写入数据和所述写入目标地址；
    所述第一写入模块用于在判断所述写入目标地址不属于非易失性存储空间的MSB page时，将所述需写入数据存储到所述预设缓存区和所述写入目标地址对应的非易失性存储空间中，并建立所述缓存地址与所述目标地址之间的所述第一映射关系；
    所述第二写入模块用于在判断所述写入目标地址属于非易失性存储空间的MSB page时，将所述需写入数据存储到所述写入目标地址对应的非易失性存储空间中。
  10. 根据权利要求9所述的装置，其特征在于，还包括第三获取模块和分配模块；
    所述第三获取模块用于获取所述非易失性存储空间的所有共享页组中MSB page与LSB page之间的最大相差页数为m，并将所述m发送给所述分配模块，所述m为自然数；
    所述分配模块用于为所述预设缓存区分配至少n*p+m个page大小的缓存空间，其中，所述p表示所述非易失性存储空间的MSB page的共享页数，所述n为自然数，至少为1。
  11. 根据权利要求10所述的装置，其特征在于，还包括第三判断模块、第一获取模块、第二获取模块和释放模块；
    所述第三判断模块用于在所述写入目标地址属于所述非易失性存储空间中的MSB page时，判断所述写入目标地址所在的MSB page是否为块block中的最后一个MSB page，并将第三判断结果发送给 第一、第二获取模块；
    所述第一获取模块用于在所述写入目标地址所在的MSB page不为block中的最后一个MSB page时，获取以所述写入目标地址所在的MSB page为始点向前第n个MSB page的共享页的地址，并作为释放数据地址，将所述释放数据地址发送给所述释放模块；
    所述第二获取模块用于在所述写入目标地址所在的MSB page为block中的最后一个MSB page时，获取所述block中最后n+1个MSB page的共享页的地址，作为所述释放数据地址，将所述释放数据地址发送给所述释放模块；
    所述释放模块用于将所述预设缓存区中与所述释放数据地址具有第一映射关系的缓存地址指向的数据释放，并删除所述第一映射关系中的所述释放数据地址。
  12. 根据权利要求8至11任一项所述的装置，其特征在于，还包括保存模块和缓存模块；
    所述保存模块用于在掉电时，将所述预设缓存区中的数据另保存在所述非易失性存储空间中，并建立所述缓存地址与所述非易失性存储空间的另保存地址之间的第二映射关系，将所述第二映射关系发送给所述缓存模块；
    所述缓存模块用于在上电时，根据所述第二映射关系，将所述非易失性存储空间的另保存地址指向的数据缓存至所述预设缓存区的所述缓存地址上。
  13. 根据权利要求8所述的装置，其特征在于，所述预设缓存区位于双倍速率同步动态随机存储器DDR或者静态随机存取存储器SRAM中。
  14. 根据权利要求8所述的装置，其特征在于，所述非易失性存储空间为固态硬盘SSD的存储空间。
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