WO2016192321A1

WO2016192321A1 - Phase ambiguity correction method and device, and computer storage medium

Info

Publication number: WO2016192321A1
Application number: PCT/CN2015/094926
Authority: WO
Inventors: 秦文平; 何开江
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2015-06-03
Filing date: 2015-11-18
Publication date: 2016-12-08
Also published as: CN106301666A

Abstract

Disclosed are a phase ambiguity correction method and device, and computer storage medium. The method comprises: receiving a training sequence transmitted by a transmitting side, the training sequence comprising a plurality of sub-frames, and lengths and segmentations of each sub-frame in the training sequence being configured as set values; determining positions of frame headers of each sub-frame in the training sequence; acquiring a phase ambiguity correction factor by calculating a frame header symbol phase of the sub-frame and comparing the same with a known sub-frame header phase; and performing QPSK phase ambiguity correction on received data by utilizing the phase ambiguity correction factor.

Description

Phase blur correction method and device, computer storage medium

Technical field

The invention relates to a phase blur correction technology, in particular to a phase blur correction method and device, and a computer storage medium.

Background technique

Optical fiber transmission has a core position in long-distance transmission networks due to its large throughput, low unit capacity and high reliability. However, the cost of fiber construction is high. How to use limited fiber resources to increase data throughput is a goal that network operators are pursuing.

To improve the throughput rate of optical fibers, there are two efforts: 1. Reduce the frequency spacing between adjacent optical channels, thereby increasing the number of channels in the 1550 nm window. Currently, the DWDM (Dense Wavelength Division Multiplexing) adjacent channel has a frequency interval of 50 GHz and 25 GHz, and can accommodate 64 to 160 DWDM frequency channels on a single fiber. 2. Increase the data rate on a single optical channel. In 100G systems, digital signal processing (DSP, Digital Signal Processing) technology is used to combat dispersion and intersymbol interference, and higher-order modulation methods such as Quadrature Phase Shift Keying (QPSK) are used. In order to achieve this.

After the QPSK modulation method is adopted, when the receiving end performs frequency phase offset correction, phase blurring occurs due to a specific algorithm. How to monitor and correct the phase ambiguity effect of this QPSK adjustment mode, and implement it on the ASIC, so that low power consumption and configurability need to be solved.

Summary of the invention

To solve the above technical problem, an embodiment of the present invention provides a phase blur correction method and apparatus, and a computer storage medium.

The phase blur correction method provided by the embodiment of the present invention includes:

Receiving a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values;

Determining a frame header position of each subframe in the training sequence;

Obtaining a phase blur correction factor by comparing a phase of the frame header symbol of the subframe with a phase of a known subframe header;

The received data is subjected to QPSK phase blur correction using the phase blur correction factor.

In the embodiment of the present invention, the phase correction correction factor is used to perform QPSK phase blur correction on the received data, including:

The data received in parallel is buffered by the signal;

When the frame header indication signal of the subframe is valid, calculating a phase blur correction factor according to the received data;

The QPSK phase blur correction is performed on the delayed buffer data by using the calculated phase blur correction factor.

In the embodiment of the present invention, the phase blur correction factor is obtained by comparing the phase of the frame header symbol of the subframe with the phase of the known subframe header, including:

Calculating the phase of each symbol in the header of the sub-frame in parallel;

The phase blur correction factor is calculated by the difference between the calculated phase and the phase of the known sub-frame header.

In the embodiment of the present invention, the method further includes:

The position where the QPSK phase blur correction is performed is determined by the control of the effective depth of the buffer unit, and the position of the QPSK phase blur correction is between any symbols from the previous subframe to the current subframe.

In the embodiment of the present invention, the method further includes:

When the sub-frame header is not reached, the input signal is signal gated by an enable signal to remove the invalid transition.

The phase blur correction apparatus provided by the embodiment of the invention includes:

The receiving unit is configured to receive a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values;

a determining unit configured to determine a frame header position of each subframe in the training sequence;

a phase blur correction factor unit configured to obtain a phase blur correction factor by comparing a phase of the frame header symbol of the subframe with a phase of a known subframe frame header;

And a correction unit configured to perform QPSK phase blur correction on the received data by using the phase blur correction factor.

In the embodiment of the present invention, the correcting unit includes:

a cache subunit configured to buffer data received in parallel;

a calculating subunit configured to calculate a phase blur correction factor according to the received data when the frame header indication signal of the subframe is valid;

The correction subunit is configured to perform QPSK phase blur correction on the delayed buffered data using the calculated phase blur correction factor.

In the embodiment of the present invention, the phase blur correction factor unit is further configured to calculate a phase of each symbol in the frame header of the sub-frame in parallel; and calculate a difference between the calculated phase and the phase of the known sub-frame header. A phase blur correction factor is obtained.

In the embodiment of the present invention, the device further includes:

a first control unit configured to determine, by a control of an effective depth of the buffer unit, a position where the QPSK phase blur correction is performed, where the position of the QPSK phase blur correction is between any symbol between the previous subframe and the current subframe .

In the embodiment of the present invention, the device includes:

a second control unit configured to enable an input signal by an enable signal when the subframe header is not reached The signal is gated to remove invalid transitions.

The computer storage medium provided by the embodiment of the present invention stores a computer program for executing the phase blur correction method described above.

In the technical solution of the embodiment of the present invention, the QPSK phase blur is corrected by inserting a training sequence on the transmitting side and detecting the training sequence on the receiving side. Specifically, the training sequence sent by the sending side is received, where the training sequence includes multiple subframes, and the length and segmentation of each subframe in the training sequence are configured as set values; and the frame header of each subframe in the training sequence is determined. a phase blur correction factor obtained by comparing a phase of the frame header symbol of the subframe with a phase of a known subframe header; using the phase blur correction factor to perform quadrature phase shift keying on the received data QPSK phase blur correction. In the technical solution of the embodiment of the present invention, the length of the training sequence is fixed, the interval may be fixed, or may be fixed in segments, the content of the training sequence is configurable, and is also known to the receiving end. After the phase blur correction factor is calculated, the position for phase correction is configurable, and compensation can be performed from any position before the previous subframe and before the current subframe. The phase blur correction factor is calculated by using a parallel circuit to minimize the calculation delay, thereby reducing the data buffer depth and reducing the circuit area. Moreover, the power consumption of the device is further reduced by methods such as signal gating.

DRAWINGS

1 is a schematic flow chart of a phase blur correction method according to an embodiment of the present invention;

2 is a schematic structural diagram of a training sequence according to an embodiment of the present invention;

3 is a block diagram of a circuit for calculating a phase blur correction factor according to an embodiment of the present invention;

4 is a schematic diagram of a variable depth buffer for performing stepwise selection on an input side according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a variable depth buffer for performing stepwise selection on an output side according to an embodiment of the present invention; FIG.

Figure 6 is a general block diagram of a correction circuit in accordance with an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a phase blur correction apparatus according to an embodiment of the present invention.

detailed description

The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

1 is a schematic flowchart of a phase blur correction method according to an embodiment of the present invention. As shown in FIG. 1, the phase blur correction method includes the following steps:

Step 101: Receive a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values.

In the embodiment of the present invention, an optical transport network (OTN) network using a QSPK modulation mode is required to insert a special training sequence on the transmitting side in order to correct the phase ambiguity introduced by the QPSK frequency offset and the phase offset adjustment algorithm at the receiving end. That is, a so-called sub-frame is constructed. In the present invention, the design of the training sequence has the following characteristics:

The high throughput of the OTN 100G DSP chip is under the current technical conditions, the main frequency of a single set of circuits can not be processed, and multiple sets of parallel circuits are needed for processing. The length of the training sequence and the length of the internal subframe are designed as integer multiples of the number of parallel circuits, which can effectively reduce the processing difficulty. The overhead caused by the training sequence must be less than 1%. In the same training sequence, the length and segmentation of each subframe can be flexibly matched, and the ratio of the length of the training sequence can be selected before and after the subframe is inserted into the training sequence to facilitate the selection of the PLL. Further, in the same training sequence, there are a plurality of subframes. The ratio of the frame length before and after the insertion of the sub-frame is small enough to facilitate the selection of the Phase Locked Loop (PLL) and reduce its cost.

Under the constraints of the above design, through the script, the training sequence length, the number of parallel circuit sets, the overhead, etc. are used as variables, the program is written, the automatic traversal is performed, and then the filtering is performed according to the frame length ratio, and the structure of the required training sequence can be obtained. Figure 2 is one of the frame structures produced in accordance with the above constraints.

Step 102: Determine a frame header position of each subframe in the training sequence.

In the embodiment of the present invention, the structure of the training sequence is transparent to the receiving side. Therefore, pick up After receiving the frame header of the training sequence, the receiving side can locate the frame header position of each subframe, and can obtain the phase blur correction factor by calculating the phase of the frame header symbol of the subframe and comparing with the phase of the known subframe frame header. And then perform QPSK phase blur correction on the received data.

Step 103: Obtain a phase blur correction factor by comparing the phase of the frame header symbol of the subframe with the phase of the known subframe header.

In the embodiment of the present invention, the position of the QPSK phase blur correction is determined by the control of the effective depth of the buffer unit, and the position of the QPSK phase blur correction is between any symbols from the previous subframe to the current subframe.

In the embodiment of the present invention, when the subframe frame header is not reached, the input signal is gated by the enable signal to remove the invalid jump.

In the embodiment of the present invention, the phase is calculated in parallel for each symbol in the frame header of the sub-frame; and the phase blur correction factor is calculated by calculating the difference between the phase and the phase of the known sub-frame header.

For the calculation step of the correction factor, referring to FIG. 3, in order to minimize the power consumption, when the subframe header is not reached, the input signal is gated by the enable signal EN to remove the invalid jump.

Using 8 sets of circuits, the phase of the sub-frame header is calculated in parallel, the difference between the phase and the known phase is calculated, the radians are adjusted to the range of 2π, and the unit vector is obtained, and then the unit vector is accumulated to obtain a vector. Then, the phase is obtained, and finally the correction factor is determined. The use of parallel circuits sacrifices a small amount of resources in the factor calculation unit, in exchange for the significant resource savings of the signal buffer unit.

Considering the randomness of the QPSK phase ambiguity on the training sequence, when the aliasing is detected on the training sequence, the actual aliasing may have occurred before the arrival of the subframe. Therefore, the embodiment of the present invention supports the data before the subframe. Correction is made, and the correction can start from any symbol between the previous subframe and the current subframe. The flexibility of this calibration starting point is achieved by the control of the effective depth of the buffer unit.

The embodiment of the present invention adopts the structure shown in FIG. 4 or FIG. 5 when controlling the effective depth of the data buffer unit. 4 is a variable depth buffer selected step by step on the input side, and FIG. 5 is a variable depth buffer selected step by step on the output side, with respect to a common variable depth buffer uniformly selected on the output side, FIG. 4 and FIG. 5 are more advantageous for the ASIC (Application Specific Integrated Circuit) routing, which reduces the possibility of wiring congestion.

Step 104: Perform quadrature phase shift keying QPSK phase blur correction on the received data by using the phase blur correction factor.

In the embodiment of the present invention, the data received in parallel is buffered; when the header indication signal of the subframe is valid, the phase fuzzy correction factor is calculated according to the received data; and the calculated phase fuzzy correction factor is used. The QPSK phase blur correction is performed on the delayed buffer data.

Referring to Fig. 6, Fig. 6 is an overall block diagram of the correction circuit. The following only describes the correction process of the X polarization state, and the Y polarization state is similar: the data entering in parallel enters the X polarization state signal buffer. Meanwhile, if the frame header indication signal is valid, the first 8 symbols of the input data are taken and sent to the X polarization state factor calculation module. The delayed data from the X-polarization signal buffer module is entered into the X-polarization phase correction module together with the correction factor calculated by the X-polarization factor calculation unit to perform QPSK phase blur correction.

In the technical solution of the embodiment of the present invention, the structure of the training sequence may be reselected according to the multiplication ratio of the PLL, and the length of the training sequence and the length of the subframe are equal to the number of parallel circuits of the circuit for implementation, and the starting point of the correction is flexible and configurable. And it is beneficial to ASIC implementation, and effectively controls the power consumption when the circuit is idling.

FIG. 7 is a phase blur correction apparatus according to an embodiment of the present invention. As shown in FIG. 7, the apparatus includes:

The receiving unit 71 is configured to receive a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values;

a determining unit 72, configured to determine a frame header position of each subframe in the training sequence;

The phase blur correction factor unit 73 is configured to obtain a phase blur correction factor by comparing the phase of the frame header symbol of the subframe with the phase of the known subframe frame header;

The correcting unit 74 is configured to perform quadrature phase shift keying QPSK phase blur correction on the received data by using the phase blur correction factor.

In the embodiment of the present invention, the correcting unit 74 includes:

The buffer subunit 741 is configured to buffer the data received in parallel;

The calculating subunit 742 is configured to calculate a phase blur correction factor according to the received data when the frame header indication signal of the subframe is valid;

The correction sub-unit 743 is configured to perform QPSK phase blur correction on the delayed buffer data using the calculated phase blur correction factor.

In the embodiment of the present invention, the phase blur correction factor unit 73 is further configured to calculate the phase of each symbol in the frame header of the sub-frame in parallel; and the difference between the calculated phase and the phase of the known sub-frame header, The phase blur correction factor is calculated.

In the embodiment of the present invention, the device further includes:

The first control unit 75 is configured to determine, by the control of the effective depth of the buffer unit, the position where the QPSK phase blur correction is performed, where the position of the QPSK phase blur correction is any symbol from the previous subframe to the current subframe. between.

In the embodiment of the present invention, the device includes:

The second control unit 76 is configured to perform signal gating on the input signal by the enable signal when the subframe frame header is not reached to remove the invalid jump.

It will be understood by those skilled in the art that the implementation functions of the units and their subunits in the phase blur correction apparatus shown in FIG. 7 can be understood by referring to the related description of the phase blur correction method described above. The functions of each unit and its subunits in the phase blur correction apparatus shown in FIG. 7 can be realized by a program running on a processor, or can be realized by a specific logic circuit.

In practical applications, each unit module in the phase blur correction device may be implemented by a central processing unit. (CPU, Central Processing Unit), or digital signal processor (DSP, Digital Signal Processor), or Field-Programmable Gate Array (FPGA) implementation.

The apparatus for tracking the service signaling according to the embodiment of the present invention may also be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a separate product. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

Correspondingly, an embodiment of the present invention further provides a computer storage medium, wherein a computer program for executing the phase blur correction method of the embodiment of the present invention is stored.

The technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

In the several embodiments provided by the present invention, it should be understood that the disclosed method and smart device may be implemented in other manners. The device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place. The party may also be distributed to multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one second processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; The above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention.

Claims

A phase blur correction method, the method comprising:

Receiving a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values;

Determining a frame header position of each subframe in the training sequence;

Obtaining a phase blur correction factor by comparing a phase of the frame header symbol of the subframe with a phase of a known subframe header;

The phase-shift keying QPSK phase blur correction is performed on the received data by using the phase blur correction factor.
The phase blur correction method according to claim 1, wherein the performing QPSK phase blur correction on the received data by using the phase blur correction factor comprises:

The data received in parallel is buffered by the signal;

When the frame header indication signal of the subframe is valid, calculating a phase blur correction factor according to the received data;

The QPSK phase blur correction is performed on the delayed buffer data by using the calculated phase blur correction factor.
The phase blur correction method according to claim 1, wherein the phase blur correction factor is obtained by comparing the phase of the frame header symbol of the subframe with the phase of the known subframe header, including:

Calculating the phase of each symbol in the header of the sub-frame in parallel;

The phase blur correction factor is calculated by the difference between the calculated phase and the phase of the known sub-frame header.
The phase blur correction method according to claim 1, wherein the method further comprises:

The position of the QPSK phase blur correction is determined by the control of the effective depth of the buffer unit, and the position of the QPSK phase blur correction is between the previous subframe and the current subframe. Between the symbols.
The phase blur correction method according to any one of claims 1 to 4, wherein the method further comprises:

When the sub-frame header is not reached, the input signal is signal gated by an enable signal to remove the invalid transition.
A phase blur correction device, the device comprising:

The receiving unit is configured to receive a training sequence sent by the sending side, where the training sequence includes multiple subframes, and the length and segment configuration of each subframe in the training sequence are set values;

a determining unit configured to determine a frame header position of each subframe in the training sequence;

a phase blur correction factor unit configured to obtain a phase blur correction factor by comparing a phase of the frame header symbol of the subframe with a phase of a known subframe frame header;

And a correction unit configured to perform quadrature phase shift keying QPSK phase blur correction on the received data by using the phase blur correction factor.
The phase blur correction device according to claim 6, wherein the correction unit comprises:

a cache subunit configured to buffer data received in parallel;

a calculating subunit configured to calculate a phase blur correction factor according to the received data when the frame header indication signal of the subframe is valid;

The correction subunit is configured to perform QPSK phase blur correction on the delayed buffered data using the calculated phase blur correction factor.
The phase blur correction device according to claim 6, wherein the phase blur correction factor unit is further configured to calculate a phase thereof in parallel for each symbol in the header of the sub-frame; by calculating the phase and the known sub- The phase blur correction factor is calculated by the difference between the phase of the frame header.
The phase blur correction device of claim 6, wherein the device further comprises:

a first control unit configured to determine that the effective depth is controlled by the cache unit The position of the QPSK phase blur correction, the position of the QPSK phase blur correction is between any symbols from the previous subframe to the current subframe.
The phase blur correction device according to any one of claims 6 to 9, wherein the device comprises:

The second control unit is configured to perform signal gating on the input signal by the enable signal when the subframe frame header is not reached to remove the invalid jump.
A computer storage medium having stored therein computer executable instructions configured to perform the phase blur correction method of any of claims 1-5.