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WO2016161770A1 - 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 - Google Patents

移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 Download PDF

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Publication number
WO2016161770A1
WO2016161770A1 PCT/CN2015/089724 CN2015089724W WO2016161770A1 WO 2016161770 A1 WO2016161770 A1 WO 2016161770A1 CN 2015089724 W CN2015089724 W CN 2015089724W WO 2016161770 A1 WO2016161770 A1 WO 2016161770A1
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WO
WIPO (PCT)
Prior art keywords
node
voltage
shift register
register unit
noise
Prior art date
Application number
PCT/CN2015/089724
Other languages
English (en)
French (fr)
Inventor
杨东
陈希
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/907,993 priority Critical patent/US9991004B2/en
Priority to EP15888322.3A priority patent/EP3282440B1/en
Publication of WO2016161770A1 publication Critical patent/WO2016161770A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to a shift register unit and a driving method thereof, a scan driving circuit, and a display device.
  • GOA Gate Drive on Array
  • GOA also has some problems in practical applications. For example, in order to achieve stable output of each row of scanning signals and prevent false interference caused by noise interference, it is often necessary to additionally set a plurality of circuit components in each row of GOA units, so that the number of circuit components in each GOA unit may reach ten. Several, severely restrict the control of product cost and the reduction of power consumption. Therefore, how to use the least possible circuit components to achieve stable output of the GOA unit to eliminate noise interference has become an urgent problem to be solved in the field.
  • the present disclosure provides a shift register unit and a driving method thereof, a scan driving circuit, and a display device, which can realize a stable output of a GOA unit that eliminates noise interference by relatively few circuit components.
  • the present disclosure provides a shift register unit including an input end, an output end, a reset end, and a first noise emitting end; the shift register unit further includes:
  • An input module connected to the input end and the first node, configured to pull down a voltage at the first node by a control of a signal connected at the input end;
  • An output module connected to the output end and the first node, configured to use a first clock signal to pull up a voltage at the output end under control of a voltage at the first node;
  • a reset module connected to the reset end and the first node, for receiving a signal at the reset end Control pulls down the voltage at the first node;
  • An output pull-down module coupled to the output for lowering a voltage at the output terminal at a control of the second clock signal
  • a first noise canceling module connected to the first noise emitting end and the first node, for releasing the noise voltage at the first node to the first noise emitting end under the control of the third clock signal;
  • the first noise canceling module is further configured to disconnect an electrical connection between the first noise emitting end and the first node while a voltage at the first node is pulled high.
  • the first noise emitting module includes a first transistor, a gate of the first transistor is connected to the third clock signal, and one of a source and a drain is connected to the first noise emitting end, and Connecting the first node;
  • the voltage of the signal at the first noise-cancelling end that is at least a portion of the voltage at the first node being pulled up is greater than or equal to the voltage of the third clock signal.
  • the shift register unit further includes a second noise emitting end and a second noise emitting module connected to the first node;
  • the second noise emitting module is further connected to the second noise emitting end, and is configured to release the noise voltage at the first node to the second noise emitting end under the control of the fourth clock signal;
  • the second noise canceling module is further configured to disconnect an electrical connection between the second noise emitting end and the first node during a period when a voltage at the first node is pulled high.
  • the second noise emitting module includes a second transistor, a gate of the second transistor is connected to the fourth clock signal, and one of a source and a drain is connected to the second noise emitting end, and Connecting the first node;
  • the voltage of the signal at the second noise-cancelling end is at least a portion of the voltage at which the voltage at the first node is pulled higher than the voltage of the fourth clock signal.
  • the phases of the third clock signal, the first clock signal, the fourth clock signal, and the second clock signal are sequentially delayed in the same clock cycle of the shift register unit.
  • the output module includes:
  • a gate of the third transistor is connected to the first node, one of the source and the drain is connected to the first clock signal, and the other is connected to the output end.
  • the output pull-down module includes a fourth transistor, and the gate of the fourth transistor Connected to the second clock signal, one of the source and the drain is connected to the output, and the other is connected to the low-voltage line.
  • the input module includes a fifth transistor, a gate of the fifth transistor is connected to the input end, one of a source and a drain is connected to a high-level voltage line, and the other is connected to the first node. .
  • the reset module includes a sixth transistor, a gate of the sixth transistor is connected to the reset end, one of a source and a drain is connected to the first node, and the other is connected to a low-voltage line. .
  • the present disclosure further provides a driving method of a shift register unit, where the shift register unit includes an input end, an output end, a reset end, and a first noise emitting end, and includes the shift register unit.
  • the first node of the internal, the driving method includes:
  • the control of the signal connected at the input pulls down the voltage at the first node
  • Controlling the signal connected to the reset terminal pulls down the voltage at the first node and pulls down the voltage at the output terminal under control of the second clock signal;
  • the noise voltage at the first node is released to the first noise canceling end under the control of the third clock signal.
  • the present disclosure further provides a scan driving circuit comprising a plurality of stages of any one of the above shift register units, wherein: an input end of the Nth stage shift register unit and an N-2th stage shift register unit The output terminal is connected; the first noise canceling end of the Nth shift register unit is connected to the output end of the N-1th shift register unit; the reset end of the Nth shift register unit and the N+2 shift The output of the register unit is connected; the N is greater than or equal to 3.
  • the shift register unit further includes a second noise canceling end, wherein the second noise emitting end of the Nth stage shift register unit is connected to an output end of the N+1th shift register unit.
  • the present disclosure also provides a display device comprising any of the above scan drive circuits.
  • the present disclosure is based on the setting of the noise canceling end and the noise canceling module in the shift register unit, and can periodically perform noise cancellation on the first node by using a clock signal to eliminate shift register.
  • the noise is disturbed by the unit; at the same time, the noise-cancelling module can avoid the time period when the potential of the first node of the shift register unit is pulled high by a certain setting, thereby ensuring stable output of the output signal.
  • the function of the noise canceling module can be realized by at least one transistor, so the present disclosure can realize the stable output of the GOA unit to eliminate noise interference through relatively few circuit components, which is beneficial to reducing the cost and power consumption of the product.
  • 1 is a block diagram showing the structure of a shift register unit in one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the circuit structure of a shift register unit in one embodiment of the present disclosure
  • FIG. 3 is a circuit timing diagram of the circuit structure shown in FIG. 2 in one clock cycle
  • FIG. 4 is a flow chart showing the steps of a driving method of a shift register unit in one embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a scan driving circuit in one embodiment of the present disclosure.
  • the shift register unit includes an input terminal INPUT, an output terminal OUTPUT, a reset terminal RESET, and a first noise emitting terminal LEAK1, and further includes an output pull-down module 14 and an input module 11 and an output module 12 connected to the first node PU. And a reset module 13 and a first noise canceling module 15, wherein:
  • the input module 11 is further connected to the input terminal INPUT, and is configured to pull down the voltage at the first node PU at the control of the signal connected to the input terminal INPUT;
  • the output module 12 is further connected to the output terminal OUTPUT for pulling up the voltage at the output terminal OUTPUT by using the first clock signal CLK2 under the control of the voltage at the first node PU;
  • the reset module 13 is further connected to the reset terminal RESET for the reset end.
  • the control of the signal connected by RESET pulls down the voltage at the first node PU;
  • the output pull-down module 14 is connected to the output terminal OUTPUT for lowering the voltage at the output terminal OUTPUT under the control of the second clock signal CLK4;
  • the first noise canceling module 15 is further connected to the first noise emitting end LEAK1 for releasing the noise voltage at the first node PU to the first noise emitting end LEAK1 under the control of the third clock signal CLK1;
  • the first noise canceling module 15 is further configured to disconnect the electrical connection between the first noise emitting end LEAK1 and the first node PU during a period in which the voltage at the first node PU is pulled high.
  • the input module 11 pulls up the voltage at the first node PU, so that the voltage control output module 12 at the first node PU pulls up the voltage at the output terminal OUTPUT to complete the shift.
  • the register unit outputs a shift of the pulse signal.
  • the reset terminal RESET receives the pulse signal
  • the reset module 13 pulls down the voltage at the first node PU, so that the output module 11 stops working; meanwhile, the second clock signal CLK4 can control the output pull-down module 14 to pull down the output terminal OUTPUT. Potential, complete reset of the shift register unit.
  • the first noise canceling module 15 disconnects the electrical connection between the first noise emitting end LEAK1 and the first node PU, so that the first noise canceling module 15 does not affect the shift.
  • the register outputs a shift of the pulse signal; and in other time periods, the third clock signal CLK1 may periodically control the first noise canceling module 15 to release the noise voltage at the first node PU to the first noise emitting end LEAK1, To eliminate noise interference from the shift register unit.
  • the embodiment of the present disclosure can periodically denoise the first node by using a clock signal based on the setting of the noise canceling end and the noise canceling module in the shift register unit to eliminate the noise received by the shift register unit.
  • the noise-cancelling module can avoid the time period during which the potential of the first node of the shift register unit is pulled up by a certain setting, thereby ensuring stable output of the output signal.
  • the function of the noise canceling module can be realized by a minimum of one transistor, so the embodiment of the present disclosure can realize the stable output of the GOA unit to eliminate noise interference through relatively few circuit components, thereby reducing the cost and power consumption of the product. .
  • the input terminal INPUT, the output terminal OUTPUT, the reset terminal RESET, and the first noise-dissipation terminal LEAK1 included in the above-mentioned shift register unit may be actual circuit connection components, or may be virtual circuit nodes in a circuit structure.
  • a person skilled in the art can make a selection according to an application scenario, and the disclosure does not limit this.
  • the above-mentioned term “under the control of (some signal) ... (execution of some action)” refers to whether or not to perform a certain time according to the state of a certain signal at a certain time.
  • An action such as “the input module 11 is used to pull down the voltage at the first node PU at the control of the signal connected to the input terminal INPUT” can be understood as “the input module 11 is used to select the signal according to the input terminal INPUT at a certain moment.
  • the input module 11 may include an electrical signal controlled switching element, such that the control end of the switching element is connected to the input terminal INPUT, One end is connected to the high-level voltage line, and the second end is connected to the first node PU, wherein the switching element is used to form or disconnect the electricity between the first end and the second end under the control of the signal connected to the control end. connection.
  • the switching element can be, for example, a relay, a transistor, or the like.
  • the first to third clock signals refer to clock signals having the same frequency and having different phases in the same clock cycle.
  • the above clock cycle is hereby agreed to start from the moment when the third clock signal is turned from a low level to a high level, to the next time from the low level to the high level of the third clock signal. The time between the end of the flat time.
  • the introduction of the above three clock signals indicates that the shift register unit can operate under a three-phase clock signal.
  • the shift register unit can also operate at circuit timing of a four phase clock signal, an eight phase clock signal, or other multiphase clock signal.
  • FIG. 2 is a circuit diagram showing the structure of a shift register unit in one embodiment of the present disclosure.
  • the shift register unit includes a second noise canceling end (represented by a signal Gn+1 connected by the second noise emitting end in FIG. 2) and a second noise emitting module 16 connected to the first node PU.
  • the second noise canceling module 16 is further connected to the second noise emitting end, and is configured to release the noise voltage at the first node PU to the second noise emitting end under the control of the fourth clock signal CLK3; the second noise emitting end
  • the module 16 is further configured to disconnect the electrical connection between the second noise canceling end and the first node PU while the voltage at the first node PU is pulled high.
  • the shift register unit can also set a second noise canceling module (or more noise canceling module) having similar structure and function as the first noise emitting module, and respectively under the control of different clock signals.
  • the first node PU is denoised to further reduce the noise voltage present at the first node PU.
  • the first noise canceling module 15 includes a first transistor M1, and a gate of the first transistor M1 is connected to the third clock signal CLK1.
  • One of the source and the drain is connected to the first noise-dissipating end LEAK1 (indicated by the signal Gn-1 connected by the first noise-cancelling end in FIG. 2), and the other is connected to the first node PU; wherein, the first The voltage of the signal Gn-1 connected to the noise reduction terminal at least part of the time when the voltage at the first node PU is pulled up is greater than or equal to the voltage of the third clock signal CLK1.
  • the gate voltage of the first transistor M1 is less than or equal to the source voltage and the drain voltage, and operates in the cut-off region, the source and the The current does not pass between the drains, so the first noise canceling module 15 does not affect the shift output of the signal connected to the input terminal by the shift register unit.
  • the first transistor M1 can periodically turn on the signal Gn-1 connected to the first noise-cancelling end by the first node PU under the action of the third clock signal CLK1, thereby The noise voltage at the first node PU is released to the first noise emitting end LEAK1. It can be seen that the function of the first noise-cancelling module 15 described above can be realized by one transistor, and the noise interference received by the shift register unit can be eliminated and the stable output of the output terminal signal can be guaranteed.
  • the second noise canceling module 16 includes a second transistor M2 in FIG. 2, a gate of the second transistor M2 is connected to the fourth clock signal CLK3, and one of the source and the drain is connected to the second noise emitting end. (in FIG. 2, the signal Gn+1 connected by the second noise-cancelling end is connected), and the other is connected to the first node PU; the voltage of the signal Gn+1 connected to the second noise-cancelling terminal at the first node PU is The voltage at least part of the time that is pulled high is greater than or equal to the voltage of the fourth clock signal CLK3.
  • the second noise canceling module 16 may also not affect the shift output of the signal connected to the input terminal by the shift register unit, and may also release the noise voltage at the first node PU to the second noise emitting end.
  • the function of the second noise canceling module can also be implemented by one transistor, which can further eliminate the noise interference received by the shift register unit and ensure the stable output of the output signal.
  • the output module 12 includes a first capacitor C1 and a third transistor M3 in FIG. 2, wherein: a first end of the first capacitor is connected to the first node PU; and a gate of the third transistor M3 is first
  • the node PU is connected, one of the source and the drain is connected to the first clock signal CLK2, and the other is connected to the output terminal OUTPUT (indicated by the output signal Gn in FIG. 2).
  • the first capacitor C1 stores the voltage loaded at both ends (the first clock signal CLK2 is at a low level); the first clock signal CLK2 turns high.
  • the function of the output module 12 described above can be realized by a circuit structure composed of a capacitor and a transistor.
  • the output pull-down module 14 includes a fourth transistor M4 in FIG. 2, a gate of the fourth transistor M4 is coupled to the second clock signal CLK4, and one of the source and the drain is connected to the output terminal OUTPUT (in FIG. 2 The middle side is represented by the output terminal signal Gn), and the other is connected to the low level voltage line VGL.
  • the second clock signal CLK4 can periodically turn on the fourth transistor M4 such that the output terminal OUTPUT is periodically turned on with the low-level voltage line VGL, thereby achieving a pull-down of the voltage at the output terminal OUTPUT. It can be seen that the function of the above output pull-down module 14 can be realized by a circuit structure composed of one transistor.
  • the input module 11 includes a fifth transistor M5 in FIG. 2, and the gate of the fifth transistor M5 is connected to the input terminal INPUT (indicated by the signal Gn-2 connected to the input terminal in FIG. 2), the source One of the drains is connected to the high-voltage voltage line VDD, and the other is connected to the first node PU.
  • the fifth transistor M5 can be turned on under the control of the signal Gn-2 connected to the input terminal, so that the high-level voltage line VDD is pulled up by the source and the drain of the fifth transistor M5 by the voltage at the first node PU. It can be seen that the function of the above input module 11 can be realized by a circuit structure composed of one transistor.
  • the reset module 13 includes a sixth crystal M6 in FIG. 2, and the gate of the sixth transistor M6 is connected to the reset terminal RESET (indicated by the signal Gn+2 connected to the reset terminal in FIG. 2), the source One of the drains is connected to the first node PU and the other is connected to the low-level voltage line VSS.
  • the fifth transistor M5 can be turned on under the control of the signal Gn+2 connected to the reset terminal, such that the low-level voltage line VSS pulls down the voltage at the first node PU through the source and drain of the sixth transistor M6. It can be seen that the function of the above reset module 13 can be realized by a circuit structure composed of one transistor.
  • FIG. 3 is a circuit timing diagram of the circuit structure shown in FIG. 2 in one clock cycle.
  • the phases of the third clock signal CLK1, the first clock signal CLK2, the fourth clock signal CLK3, and the second clock signal CLK4 are sequentially delayed in the same clock cycle of the shift register unit.
  • the shift register unit can realize stable output of the GOA unit to eliminate noise interference by relatively few circuit components, wherein:
  • phase I and II Gn-2 is high, so that M5 is turned on, and the voltage at the PU is pulled by VDD. High; in phases II and III, CLK1 and Gn-1 are at a high level, so that the gate voltage of M1 is less than or equal to the source voltage and the drain voltage, and is in a closed state, and the voltage at the first node PU does not pass through the M1 direction.
  • Gn-1 leakage in phase III, IV, Gn-2 turns to low level, M5 turns off, C1 stores the voltage difference between the voltage of PU and the voltage of CLK2 in phase I and II, so that after CLK2 goes high Further pull up the voltage at the PU, while M3 turns on, the high level on CLK2 pulls the voltage of Gn through M3, and the shift register unit outputs a high level at the output end, relative to the signal Gn-2 connected to the input terminal.
  • the structure of the input module 11 and the reset module 13 are symmetrical, and thus can be exchanged with each other; the structures of the first noise-cancelling module 15 and the second noise-cancelling module 16 are also symmetrical, and can also be exchanged with each other. Therefore, the phase of the third clock signal CLK1, the first clock signal CLK2, the fourth clock signal CLK3, and the second clock signal CLK4 in the same clock cycle is changed to be sequentially advanced, and Gn-2 and Gn+ are added. 2 mutual exchange, VSS and VDD exchange, Gn-1 and Gn+1 exchange, the shift output of the shift register unit can be realized by the same workflow. Based on this, the shift register unit circuit shown in FIG. 2 can cooperate with the circuit timing shown in FIG. 3 to realize the function of bidirectional shift output under the four-phase clock signal.
  • bidirectional shift register unit operating under other multi-phase clock signals can also be obtained based on similar settings, which is not limited in this disclosure.
  • the present disclosure provides a driving method of a shift register unit.
  • the shift register unit includes an input terminal, an output terminal, a reset terminal, and a first noise emitting terminal, and includes a first node located inside the shift register unit.
  • 4 is a flow chart showing the steps of a method of driving a shift register unit in one embodiment of the present disclosure. Referring to Figure 4, the method includes:
  • Step 401 the control of the signal connected to the input terminal pulls down the voltage at the first node
  • Step 402 using the first clock signal to pull up the voltage at the output end under the control of the voltage at the first node, and disconnecting the first noise emitting end and the first node during the period when the voltage at the first node is pulled high. Electrical connection
  • Step 403 the control of the signal connected at the reset terminal pulls down the voltage at the first node, and controls the voltage at the low output terminal under the control of the second clock signal;
  • Step 404 releasing the noise voltage at the first node to the first noise emitting end under the control of the third clock signal.
  • the circuit timing of the circuit structure based on the shift register unit shown in FIG. 2 and FIG. 3 is also an example of the above steps 401 to 404, and details are not described herein again. It should be noted that the execution order of the above steps 401 to 404 is associated with the timing relationship of the first to third clock signals, and thus there is no absolute sequence.
  • the above method may further include the following steps not shown in FIG. 4 (the execution order may be not limited):
  • Step 402a disconnecting the electrical connection between the second noise emitting end and the first node during a period in which the voltage at the first node is pulled high;
  • Step 405 releasing the noise voltage at the first node to the second noise emitting end under the control of the fourth clock signal.
  • the function of the shift register under the multi-phase clock signal can be realized, and the stable output of the GOA unit to eliminate noise interference can be realized by relatively few circuit components.
  • FIG. 5 is a schematic structural diagram of a scan driving circuit in one embodiment of the present disclosure.
  • the input terminal INPUT of the Nth stage shift register unit GOA_N is connected to the output terminal OUTPUT of the N-2th shift register unit GOA_N-2; the Nth stage shift register unit
  • the first noise canceling terminal LEAK1 of the GOA_N is connected to the output terminal OUTPUT of the N-1th shift register unit GOA_N-1; the reset terminal RESET of the Nth shift register unit GOA_N and the N+2 shift register unit GOA_N
  • the output of OUT2 is connected to OUTPUT (not shown).
  • the shift register unit further includes a second noise emitting end.
  • the second noise canceling end of the Nth stage shift register unit GOA_N is connected to the output terminal OUTPUT of the N+1th stage shift register unit GOA_N+1.
  • the even-numbered shift register unit constitutes a set of shift registers operating under a pair of clock signals
  • odd-order shift The bit register unit constitutes a set of shift registers operating under another pair of clock signals, the signals transmitted by the two sets of shift registers differing in phase by a half clock pulse width. It can be seen that the scan driving circuit can realize bidirectional scanning under a four-phase clock signal.
  • the Nth stage shift register unit GOA_N can periodically release the noise voltage at the first node in the shift register unit to the Nth under the control of the third clock signal.
  • the output terminal OUTPUT of the 1-stage shift register unit GOA_N-1 is pulled low by the output pull-down module 14 of the N-1th stage shift register unit GOA_N-1 under the action of the second clock signal in the same clock cycle. Thereby, the release of the noise voltage at the first node in the Nth stage shift register unit GOA_N is completed.
  • other stage shift register units can also complete the release of the noise voltage at the first node based on the same principle.
  • the process is similar, and the first stage of the Nth stage shift register unit GOA_N can be completed by the output terminal OUTPUT of the N+1th stage shift register unit GOA_N+1 and its output pull-down module 14. The release of the noise voltage at the node.
  • the output terminal of the (N+1)th shift register unit GOA_N+1 The signal connected may have the same waveform as Gn+1 and CLK3 in FIG. 3, and the signal connected to the output of the N-1th shift register unit GOA_N-1 may have the same signals as Gn-1 and CLK1 in FIG.
  • the first noise canceling module 15 and the second noise canceling module 16 in the Nth stage shift register unit GOA_N do not affect the first node PU during the period when the voltage at the first node PU is pulled high.
  • the voltage at the location does not affect the normal output of the signal at the output OUTPUT of the N-stage shift register unit GOA_N.
  • the embodiment of the present disclosure can periodically perform noise cancellation on the first node by using a clock signal based on the setting of the noise canceling end and the noise canceling module in the shift register unit to eliminate noise interference received by the shift register unit.
  • the noise-cancelling module can avoid the time period when the potential at the first node of the shift register unit of the current stage is pulled up by a certain setting, thereby ensuring stable output of the signal at the output end.
  • the function of the noise canceling module can be realized by at least one transistor, so the present disclosure
  • the embodiment can realize the stable output of the GOA unit to eliminate noise interference by relatively few circuit components, which is beneficial to reduce the cost and power consumption of the product.
  • embodiments of the present disclosure provide a display device including any one of the above-described scan driving circuits.
  • the display device in this embodiment may be any product or component having a display function such as a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like. Since the display device includes any of the above-described scan driving circuits, the same technical problem can be solved and the same technical effects can be achieved.
  • the orientation or positional relationship of the terms “upper”, “lower” and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present disclosure and simplified description. It is not intended or implied that the device or the component of the invention may have a particular orientation, and is constructed and operated in a particular orientation, and thus is not to be construed as limiting the disclosure.
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • the meaning of the above terms in the present disclosure can be understood as appropriate.

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Abstract

一种移位寄存器单元及其驱动方法、扫描驱动电路、显示装置，其中的移位寄存器单元包括输入端（INPUT）、输出端（OUTPUT）、复位端（RESET）和第一放噪端（LEAK1），还包括输出下拉模块（14）以及相连于第一节点（PU）的输入模块（11）、输出模块（12）、复位模块（13）和第一放噪模块（15）；输入模块（11）用于在输入端（INPUT）所接信号的控制下拉高第一节点（PU）处的电压；第一放噪模块（15）用于在第三时钟信号（CLK1）的控制下将第一节点（PU）处的噪声电压释放至第一放噪端（LEAK1），还用于在第一节点（PU）处的电压被拉高的期间断开第一放噪端（LEAK1）与第一节点（PU）之间的电连接。由此可以通过相对较少的电路元器件实现GOA单元排除噪声干扰的稳定输出。

Description

移位寄存器单元及其驱动方法、扫描驱动电路、显示装置 技术领域
本公开涉及一种移位寄存器单元及其驱动方法、扫描驱动电路、显示装置。
背景技术
GOA(Gate Drive on Array，阵列基板行驱动技术)相较于传统工艺，不仅节约了成本，还可以实现显示面板两边对称的美观设计，也省去了芯片的绑定区域以及例如扇出区的布线区域，有利于窄边框设计的实现。同时，由于可以省去行方向上的芯片绑定工艺，对整体的产能、良率提升也较有利。
但是，GOA在实际应用中也存在一些问题。比如为了实现每一行扫描信号的稳定输出、并防止噪声干扰造成误输出，常需要在每一行的GOA单元中额外设置若干个电路元器件，使得每一GOA单元中的电路元器件数量可能达到十几个，严重制约了产品成本的控制和功耗的降低。因此，如何使用尽可能少的电路元器件来实现GOA单元的排除噪声干扰的稳定输出，成为了本领域亟待解决的问题。
发明内容
本公开提供一种移位寄存器单元及其驱动方法、扫描驱动电路、显示装置，可以通过相对较少的电路元器件实现GOA单元的排除噪声干扰的稳定输出。
第一方面，本公开提供了一种移位寄存器单元，包括输入端、输出端、复位端和第一放噪端；所述移位寄存器单元还包括：
输入模块，与所述输入端和第一节点相连，用于在输入端所接信号的控制下拉高所述第一节点处的电压；
输出模块，与所述输出端和第一节点相连，用于在所述第一节点处电压的控制下利用第一时钟信号拉高所述输出端处的电压；
复位模块，与所述复位端和第一节点相连，用于在所述复位端所接信号 的控制下拉低所述第一节点处的电压；
输出下拉模块，与所述输出端相连，用于在第二时钟信号的控制下拉低所述输出端处的电压；
第一放噪模块，与所述第一放噪端和第一节点相连，用于在第三时钟信号的控制下将所述第一节点处的噪声电压释放至所述第一放噪端；
其中，所述第一放噪模块还用于在第一节点处的电压被拉高的期间断开所述第一放噪端与所述第一节点之间的电连接。
可选地，所述第一放噪模块包括第一晶体管，所述第一晶体管的栅极连接所述第三时钟信号，源极与漏极中的一个连接所述第一放噪端，另一个连接所述第一节点；
所述第一放噪端所接信号在所述第一节点处的电压被拉高的至少部分时间内的电压大于等于所述第三时钟信号的电压。
可选地，所述移位寄存器单元还包括第二放噪端以及连接所述第一节点的第二放噪模块；
所述第二放噪模块还与所述第二放噪端相连，用于在第四时钟信号的控制下将所述第一节点处的噪声电压释放至所述第二放噪端；
其中，所述第二放噪模块还用于在第一节点处的电压被拉高的期间断开所述第二放噪端与所述第一节点之间的电连接。
可选地，所述第二放噪模块包括第二晶体管，所述第二晶体管的栅极连接所述第四时钟信号，源极与漏极中的一个连接所述第二放噪端，另一个连接所述第一节点；
所述第二放噪端所接信号在所述第一节点处的电压被拉高的至少部分时间内的电压大于等于所述第四时钟信号的电压。
可选地，在所述移位寄存器单元的同一时钟周期内，所述第三时钟信号、所述第一时钟信号、所述第四时钟信号及所述第二时钟信号的相位依次滞后。
可选地，所述输出模块包括：
第一电容，其第一端与所述第一节点相连；以及
第三晶体管，所述第三晶体管的栅极与所述第一节点相连，源极和漏极中的一个连接所述第一时钟信号，另一个连接所述输出端。
可选地，所述输出下拉模块包括第四晶体管，所述第四晶体管的栅极连 接所述第二时钟信号，源极和漏极中的一个连接所述输出端，另一个连接低电平电压线。
可选地，所述输入模块包括第五晶体管，所述第五晶体管的栅极连接所述输入端，源极和漏极中的一个连接高电平电压线，另一个连接所述第一节点。
可选地，所述复位模块包括第六晶体管，所述第六晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述第一节点，另一个连接低电平电压线。
第二方面，本公开还提供了一种移位寄存器单元的驱动方法，所述移位寄存器单元包括输入端、输出端、复位端和第一放噪端，并包括位于所述移位寄存器单元内部的第一节点，所述驱动方法包括：
在输入端所接信号的控制下拉高所述第一节点处的电压；
在所述第一节点处电压的控制下利用第一时钟信号拉高所述输出端处的电压，并在第一节点处的电压被拉高的期间断开所述第一放噪端与所述第一节点之间的电连接；
在所述复位端所接信号的控制下拉低所述第一节点处的电压，并在第二时钟信号的控制下拉低所述输出端处的电压；以及
在第三时钟信号的控制下将所述第一节点处的噪声电压释放至所述第一放噪端。
第三方面，本公开还提供了一种扫描驱动电路，包括多级上述任意一种移位寄存器单元，其中：第N级移位寄存器单元的输入端与第N-2级移位寄存器单元的输出端相连；第N级移位寄存器单元的第一放噪端与第N-1级移位寄存器单元的输出端相连；第N级移位寄存器单元的复位端与第N+2级移位寄存器单元的输出端相连；所述N大于等于3。
可选地，所述移位寄存器单元还包括第二放噪端，其中，所述第N级移位寄存器单元的第二放噪端与第N+1级移位寄存器单元的输出端相连。
第四方面，本公开还提供了一种显示装置，包括上述任意一种扫描驱动电路。
由上述技术方案可知，本公开基于移位寄存器单元中放噪端和放噪模块的设置，可以利用时钟信号周期性地对第一节点进行放噪，以排除移位寄存 器单元受到的噪声干扰；同时，放噪模块可以通过一定设置避开本级移位寄存器单元的第一节点处电位被拉高的时间段，因而可以保障输出端信号的稳定输出。并且，放噪模块的功能最少只需一个晶体管就可以实现，所以本公开可以通过相对较少的电路元器件实现GOA单元的排除噪声干扰的稳定输出，有利于降低产品的成本和功耗。
附图说明
图1是本公开的一个实施例中的移位寄存器单元的结构框图；
图2是本公开的一个实施例中的移位寄存器单元的电路结构示意图；
图3是一个时钟周期内的图2所示电路结构的电路时序图；
图4是本公开的一个实施例中的移位寄存器单元的驱动方法的步骤流程示意图；
图5是本公开的一个实施例中的扫描驱动电路的结构示意图。
具体实施方式
为使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1是本公开的一个实施例中的移位寄存器单元的结构框图。参见图1，该移位寄存器单元包括输入端INPUT、输出端OUTPUT、复位端RESET和第一放噪端LEAK1，还包括输出下拉模块14以及相连于第一节点PU的输入模块11、输出模块12、复位模块13和第一放噪模块15，其中：
上述输入模块11还与上述输入端INPUT相连，用于在输入端INPUT所接信号的控制下拉高上述第一节点PU处的电压；
上述输出模块12还与上述输出端OUTPUT相连，用于在上述第一节点PU处电压的控制下利用第一时钟信号CLK2拉高上述输出端OUTPUT处的电压；
上述复位模块13还与上述复位端RESET相连，用于在上述复位端 RESET所接信号的控制下拉低上述第一节点PU处的电压；
上述输出下拉模块14与上述输出端OUTPUT相连，用于在第二时钟信号CLK4的控制下拉低上述输出端OUTPUT处的电压；
上述第一放噪模块15还与上述第一放噪端LEAK1相连，用于在第三时钟信号CLK1的控制下将上述第一节点PU处的噪声电压释放至上述第一放噪端LEAK1；
上述第一放噪模块15还用于在第一节点PU处的电压被拉高的期间断开上述第一放噪端LEAK1与上述第一节点PU之间的电连接。
基于上述结构，输入端INPUT接收到脉冲信号时，输入模块11拉高第一节点PU处的电压，从而第一节点PU处的电压控制输出模块12拉高输出端OUTPUT处的电压，完成移位寄存器单元对该脉冲信号的移位输出。在复位端RESET接收到脉冲信号时，复位模块13拉低第一节点PU处的电压，从而输出模块11停止工作；同时，第二时钟信号CLK4可以控制输出下拉模块14拉低输出端OUTPUT处的电位，完成该移位寄存器单元的复位。
第一节点PU处的电压被拉高的期间，第一放噪模块15断开第一放噪端LEAK1与第一节点PU之间的电连接，从而第一放噪模块15不会影响移位寄存器对上述脉冲信号的移位输出；而在其他时段内，第三时钟信号CLK1可以周期性地控制第一放噪模块15将第一节点PU处的噪声电压释放至第一放噪端LEAK1，以排除移位寄存器单元受到的噪声干扰。
可以看出，本公开的实施例基于移位寄存器单元中的放噪端和放噪模块的设置，可以利用时钟信号周期性地对第一节点进行放噪，以排除移位寄存器单元受到的噪声干扰；同时，放噪模块可以通过一定设置避开本级移位寄存器单元的第一节点处电位被拉高的时间段，因而可以保障输出端信号的稳定输出。并且，放噪模块的功能最少只需一个晶体管就可以实现，所以本公开的实施例可以通过相对较少的电路元器件实现GOA单元排除噪声干扰的稳定输出，有利于降低产品的成本和功耗。
需要说明的是，上述移位寄存单元包括的输入端INPUT、输出端OUTPUT、复位端RESET和第一放噪端LEAK1可以是实际的电路连接部件，也可以是电路结构中的虚拟电路节点，本领域技术人员可以根据应用场景进行选择，本公开对此不做限制。
还需要说明的是，上述“在……(某种信号)的控制下……(执行某种动作)”的用语指的是根据某种信号在某一时刻的状态来选择该时刻是否执行某种动作，例如“输入模块11用于在输入端INPUT所接信号的控制下拉高上述第一节点PU处的电压”可以理解为“输入模块11用于根据输入端INPUT所接信号在某一时刻的状态来选择该时刻是否去拉高上述第一节点PU处的电压”；作为一种示例，输入模块11可以包括电信号控制的开关元件，使开关元件的控制端与输入端INPUT相连，第一端与高电平电压线相连，第二端与第一节点PU相连，其中的开关元件用于在控制端所接信号的控制下形成或断开第一端与第二端之间的电连接。开关元件可以例如是继电器、晶体管等。
另外需要说明的是，在本公开的一个实施例中，上述第一至第三时钟信号指的是具有相同频率、并在同一时钟周期内的具有不同相位的时钟信号。为描述方便，这里将上述时钟周期约定为从第三时钟信号的某一次的由低电平转为高电平的时刻开始、到第三时钟信号的下一次的由低电平转为高电平的时刻结束之间的时间。上述三个时钟信号的引入表明了该移位寄存器单元可以工作在三相时钟信号下。当然，基于类似的设置，该移位寄存器单元还可以工作在四相时钟信号、八相时钟信号或者其他多相时钟信号的电路时序下。
图2是本公开的一个实施例中的移位寄存器单元的电路结构示意图。
第一方面，该移位寄存器单元包括第二放噪端(图2中以第二放噪端所接的信号Gn+1表示)以及连接上述第一节点PU的第二放噪模块16。该第二放噪模块16还与上述第二放噪端相连，用于在第四时钟信号CLK3的控制下将第一节点PU处的噪声电压释放至第二放噪端；该第二放噪模块16还用于在第一节点PU处的电压被拉高的期间断开第二放噪端与第一节点PU之间的电连接。基于此，该移位寄存器单元还可以设置与第一放噪模块具有类似结构和功能的第二放噪模块(或者还可以设置更多的放噪模块)，并分别在不同时钟信号的控制下对第一节点PU进行放噪，以进一步减小第一节点PU处存在的噪声电压。
第二方面，在该移位寄存器单元的电路结构中，上述第一放噪模块15包括第一晶体管M1，该第一晶体管M1的栅极连接上述第三时钟信号CLK1， 源极与漏极中的一个连接上述第一放噪端LEAK1(图2中以第一放噪端所接的信号Gn-1表示)，另一个连接上述第一节点PU；其中，上述第一放噪端所接的信号Gn-1在第一节点PU处的电压被拉高的至少部分时间内的电压大于等于上述第三时钟信号CLK1的电压。在此基础之上，在上述第一节点PU处的电压被拉高的至少部分时间内，第一晶体管M1的栅极电压小于等于源极电压和漏极电压，工作在截止区，源极与漏极之间不会通过电流，所以第一放噪模块15不会影响移位寄存器单元对输入端所接信号的移位输出。除此之外的任意时间内，第一晶体管M1可以在第三时钟信号CLK1的作用下，周期性地将第一节点PU与第一放噪端所接的信号Gn-1导通，从而可以将第一节点PU处的噪声电压释放到第一放噪端LEAK1处。可以看出，上述第一放噪模块15的功能可由一个晶体管实现，并可以排除移位寄存器单元受到的噪声干扰并保障输出端信号的稳定输出。
类似地，上述第二放噪模块16在图2中包括第二晶体管M2，第二晶体管M2的栅极连接上述第四时钟信号CLK3，源极与漏极中的一个连接上述第二放噪端(图2中以第二放噪端所接的信号Gn+1表示)，另一个连接上述第一节点PU；上述第二放噪端所接信号Gn+1在上述第一节点PU处的电压被拉高的至少部分时间内的电压大于等于上述第四时钟信号CLK3的电压。基于此，第二放噪模块16也可以不影响移位寄存器单元对输入端所接信号的移位输出，并且还可以将第一节点PU处的噪声电压释放到第二放噪端处。类似地，第二放噪模块的功能也可由一个晶体管实现，可以进一步排除移位寄存器单元受到的噪声干扰并保障输出端信号的稳定输出。
第三方面，上述输出模块12在图2中包括第一电容C1和第三晶体管M3，其中：第一电容的第一端与上述第一节点PU相连；第三晶体管M3的栅极与第一节点PU相连，源极和漏极中的一个连接上述第一时钟信号CLK2，另一个连接上述输出端OUTPUT(在图2中以输出端信号Gn表示)。基于此，第一节点PU处电压被输入模块11拉高后，第一电容C1存储加载在两端的电压(此时第一时钟信号CLK2为低电平)；在第一时钟信号CLK2转为高电平后，第一节点PU处电压与第一时钟信号CLK2之间的电压差仍被第一电容C1保持，从而第一节点PU处电压进一步升高，同时输出端OUTPUT被此时的第一时钟信号经由第三晶体管M3拉高，移位寄存器单元 输出高电平。可以看出，上述输出模块12的功能可以由一个电容和一个晶体管组成的电路结构来实现。
第四方面，上述输出下拉模块14在图2中包括第四晶体管M4，第四晶体管M4的栅极连接上述第二时钟信号CLK4，源极和漏极中的一个连接输出端OUTPUT(在图2中以输出端信号Gn表示)，另一个连接低电平电压线VGL。基于此，第二时钟信号CLK4可以周期性地打开第四晶体管M4，使得输出端OUTPUT周期性地与低电平电压线VGL导通，实现输出端OUTPUT处电压的拉低。可以看出，上述输出下拉模块14的功能可以由一个晶体管组成的电路结构来实现。
第五方面，上述输入模块11在图2中包括第五晶体管M5，上述第五晶体管M5的栅极连接上述输入端INPUT(在图2中以输入端所接信号Gn-2表示)，源极和漏极中的一个连接高电平电压线VDD，另一个连接上述第一节点PU。基于此，第五晶体管M5可以在输入端所接信号Gn-2的控制下开启，使得高电平电压线VDD经过第五晶体管M5的源极和漏极拉高第一节点PU处的电压。可以看出，上述输入模块11的功能可以由一个晶体管组成的电路结构来实现。
第六方面，上述复位模块13在图2中包括第六晶体M6，上述第六晶体管M6的栅极连接上述复位端RESET(在图2中以复位端所接信号Gn+2表示)，源极和漏极中的一个连接上述第一节点PU，另一个连接低电平电压线VSS。基于此，第五晶体管M5可以在复位端所接信号Gn+2的控制下开启，使得低电平电压线VSS经过第六晶体管M6的源极和漏极拉低第一节点PU处的电压。可以看出，上述复位模块13的功能可以由一个晶体管组成的电路结构来实现。
对应于图2所示的全部电路结构，图3是一个时钟周期内的图2所示电路结构的电路时序图。参见图3，在上述移位寄存器单元的同一时钟周期内，上述第三时钟信号CLK1、上述第一时钟信号CLK2、上述第四时钟信号CLK3及上述第二时钟信号CLK4的相位依次滞后。基于此，该移位寄存器单元可以通过相对较少的电路元器件实现GOA单元排除噪声干扰的稳定输出，其中：
阶段I、II内，Gn-2为高电平，使得M5开启，PU处的电压被VDD拉 高；阶段II、III内，CLK1与Gn-1为高电平，使得M1的栅极电压小于等于源极电压和漏极电压，处于关闭状态，第一节点PU处的电压不会通过M1向Gn-1漏电；阶段III、IV内，Gn-2转为低电平，M5关闭，C1存储了阶段I、II内PU处电压与CLK2电压的电压差，从而在CLK2转为高电平后进一步拉高PU处的电压，同时M3打开，CLK2上的高电平通过M3拉高Gn的电压，移位寄存器单元在输出端输出高电平，相对于输入端所接信号Gn-2而言，相当于向后移位了一个时钟脉冲的宽度，即实现了输入端所接信号的移位输出；阶段IV、V内，CLK3与Gn+1为高电平，使得M2的栅极电压小于等于源极电压和漏极电压，处于关闭状态，第一节点PU处的电压不会通过M2向Gn+1漏电；阶段V、VI内，CLK4和Gn+2为高电平，M4和M6打开，PU处的电压被VSS经过M6拉低，输出端所接信号Gn被VGL经过M4拉低，从而移位寄存器单元复位到不工作的状态；而除上述各阶段之外的时间内，CLK1和CLK3会周期性地将M1和M2打开，使得被拉低后的PU处还可能存在的噪声电压可以分别通过M1和M2释放至Gn-1和Gn+1上，保持PU处电位的稳定，防止该移位寄存器单元在不工作时间段内的误输出。
可以看出，上述输入模块11与复位模块13的结构是对称的，因而可以相互交换；上述第一放噪模块15与第二放噪模块16的结构也是对称的，同样可以相互交换。从而，将上述第三时钟信号CLK1、上述第一时钟信号CLK2、上述第四时钟信号CLK3及上述第二时钟信号CLK4在同一时钟周期内的相位变更为依次超前，并将Gn-2与Gn+2相互交换、VSS与VDD交换、Gn-1与Gn+1相互交换，可以通过同样的工作流程实现该移位寄存器单元的移位输出。基于此，图2所示的移位寄存器单元电路可以与如图3所示的电路时序相互配合，实现四相时钟信号下双向移位输出的功能。
当然，基于类似的设置还可以得到工作在其他多相时钟信号下的双向移位寄存器单元，本公开对此不做限制。
基于同样的构思，本公开提供了一种移位寄存器单元的驱动方法。该移位寄存器单元包括输入端、输出端、复位端和第一放噪端，并包括位于该移位寄存器单元内部的第一节点。图4是本公开的一个实施例中的移位寄存器单元的驱动方法的步骤流程示意图。参见图4，该方法包括：
步骤401，在输入端所接信号的控制下拉高第一节点处的电压；
步骤402，在第一节点处电压的控制下利用第一时钟信号拉高输出端处的电压，并在第一节点处的电压被拉高的期间断开第一放噪端与第一节点之间的电连接；
步骤403，在复位端所接信号的控制下拉低第一节点处的电压，并在第二时钟信号的控制下拉低输出端处的电压；以及
步骤404，在第三时钟信号的控制下将第一节点处的噪声电压释放至第一放噪端。
可以看出，上述图2、图3所示出的基于移位寄存器单元电路结构的电路时序也同样是上述步骤401至步骤404的一种示例，在此不再赘述。而需要说明的是，上述步骤401至步骤404的执行顺序是与第一至第三时钟信号的时序关系相关联的，因而并不存在绝对的先后顺序。另外，在上述移位寄存器单元还包括第二放噪端时，上述方法可以还包括下述未在图4中示出的步骤(执行顺序可以不做限制)：
步骤402a，在第一节点处的电压被拉高的期间断开第二放噪端与第一节点之间的电连接；以及
步骤405，在第四时钟信号的控制下将第一节点处的噪声电压释放至第二放噪端。
基于此，可以实现多相时钟信号下的移位寄存器的功能，并可以通过相对较少的电路元器件实现GOA单元的排除噪声干扰的稳定输出。
进一步地，基于同样的构思，本公开的实施例提供了一种扫描驱动电路，该扫描驱动电路包括上述任意一种移位寄存器单元。图5是本公开的一个实施例中的扫描驱动电路的结构示意图。
参见图5，对于任意的N大于等于3，第N级移位寄存器单元GOA_N的输入端INPUT与第N-2级移位寄存器单元GOA_N-2的输出端OUTPUT相连；第N级移位寄存器单元GOA_N的第一放噪端LEAK1与第N-1级移位寄存器单元GOA_N-1的输出端OUTPUT相连；第N级移位寄存器单元GOA_N的复位端RESET与第N+2级移位寄存器单元GOA_N+2的输出端OUTPUT相连(未示出)。
进一步地，未在图5中示出的是，在移位寄存器单元还包括第二放噪端 时，第N级移位寄存器单元GOA_N的第二放噪端与第N+1级移位寄存器单元GOA_N+1的输出端OUTPUT相连。
基于上述结构，结合图2所示的移位寄存器单元电路以及图3所示的电路时序，其中，偶数级移位寄存器单元构成工作在一对时钟信号下的一组移位寄存器，奇数级移位寄存器单元构成工作在另一对时钟信号下的一组移位寄存器，两组移位寄存器所传递的信号在相位上相差半个时钟脉冲的宽度。可以看出，该扫描驱动电路可以实现四相时钟信号下的双向扫描。
以第一放噪端LEAK1为例，第N级移位寄存器单元GOA_N可以在第三时钟信号的控制下，周期性地将该移位寄存器单元内第一节点处的噪声电压释放至第N-1级移位寄存器单元GOA_N-1的输出端OUTPUT，并且在同一时钟周期内的第二时钟信号的作用下，被第N-1级移位寄存器单元GOA_N-1的输出下拉模块14拉低，从而完成第N级移位寄存器单元GOA_N中第一节点处噪声电压的释放。类似地，其他级移位寄存器单元也可以基于同样的原理完成第一节点处噪声电压的释放。对于第二放噪端，这一过程也是类似的，可以通过第N+1级移位寄存器单元GOA_N+1的输出端OUTPUT及其输出下拉模块14完成第N级移位寄存器单元GOA_N中第一节点处噪声电压的释放。而且在图3所示的第三时钟信号CLK1、第一时钟信号CLK2、第四时钟信号CLK3及第二时钟信号CLK4的电路时序下，第N+1级移位寄存器单元GOA_N+1的输出端所接信号可以与图3中的Gn+1及CLK3具有相同的波形，同时第N-1级移位寄存器单元GOA_N-1的输出端所接信号可以与图3中的Gn-1及CLK1具有相同的波形。因而基于与前文相同的理由，第N级移位寄存器单元GOA_N中的第一放噪模块15和第二放噪模块16不会在第一节点PU处电压被拉高的期间影响第一节点PU处的电压，所以不会影响第N级移位寄存器单元GOA_N的输出端OUTPUT处信号的正常输出。
由此可见，本公开的实施例基于移位寄存器单元中放噪端和放噪模块的设置，可以利用时钟信号周期性地对第一节点进行放噪，以排除移位寄存器单元受到的噪声干扰；同时，放噪模块可以通过一定设置避开本级移位寄存器单元的第一节点处电位被拉高的时间段，因而可以保障输出端信号的稳定输出。并且，放噪模块的功能最少只需一个晶体管就可以实现，所以本公开 的实施例可以通过相对较少的电路元器件实现GOA单元的排除噪声干扰的稳定输出，有利于降低产品的成本和功耗。
基于同样的构思，本公开的实施例提供一种显示装置，该显示装置包括上述任意一种扫描驱动电路。需要说明的是，本实施例中的显示装置可以为显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置包括上述任意一种扫描驱动电路，因而可以解决相同的技术问题，达到同样的技术效果。
在本公开的描述中需要说明的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开的各实施例的技术方案的精神和范围。
本申请要求于2015年4月10日递交的中国专利申请第201510169597.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种移位寄存器单元，包括输入端、输出端、复位端和第一放噪端；所述移位寄存器单元还包括：
    输入模块，与所述输入端和第一节点相连，用于在输入端所接信号的控制下拉高所述第一节点处的电压；
    输出模块，与所述输出端和所述第一节点相连，用于在所述第一节点处电压的控制下利用第一时钟信号拉高所述输出端处的电压；
    复位模块，与所述复位端和所述第一节点相连，用于在所述复位端所接信号的控制下拉低所述第一节点处的电压；
    输出下拉模块，与所述输出端相连，用于在第二时钟信号的控制下拉低所述输出端处的电压；
    第一放噪模块，与所述第一放噪端和所述第一节点相连，用于在第三时钟信号的控制下将所述第一节点处的噪声电压释放至所述第一放噪端；
    其中，所述第一放噪模块还用于在第一节点处的电压被拉高的期间断开所述第一放噪端与所述第一节点之间的电连接。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一放噪模块包括第一晶体管，所述第一晶体管的栅极连接所述第三时钟信号，源极与漏极中的一个连接所述第一放噪端，另一个连接所述第一节点；
    所述第一放噪端所接信号在所述第一节点处的电压被拉高的至少部分时间内的电压大于等于所述第三时钟信号的电压。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：
    第二放噪端；以及
    第二放噪模块，与所述第二放噪端和所述第一节点相连，用于在第四时钟信号的控制下将所述第一节点处的噪声电压释放至所述第二放噪端；
    其中，所述第二放噪模块还用于在第一节点处的电压被拉高的期间断开所述第二放噪端与所述第一节点之间的电连接。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第二放噪模块包括第二晶体管，所述第二晶体管的栅极连接所述第四时钟信号，源极与漏极 中的一个连接所述第二放噪端，另一个连接所述第一节点；
    所述第二放噪端所接信号在所述第一节点处的电压被拉高的至少部分时间内的电压大于等于所述第四时钟信号的电压。
  5. 根据权利要求4所述的移位寄存器单元，其中，在所述移位寄存器单元的同一时钟周期内，所述第三时钟信号、所述第一时钟信号、所述第四时钟信号及所述第二时钟信号的相位依次滞后。
  6. 根据权利要求1至5中任意一项所述的移位寄存器单元，其中，所述输出模块包括：
    第一电容，所述第一电容的第一端与所述第一节点相连；以及
    第三晶体管，所述第三晶体管的栅极与所述第一节点相连，源极和漏极中的一个连接所述第一时钟信号，另一个连接所述输出端。
  7. 根据权利要求1至5中任意一项所述的移位寄存器单元，其中，所述输出下拉模块包括第四晶体管，所述第四晶体管的栅极连接所述第二时钟信号，源极和漏极中的一个连接所述输出端，另一个连接低电平电压线。
  8. 根据权利要求1至5中任意一项所述的移位寄存器单元，其中，所述输入模块包括第五晶体管，所述第五晶体管的栅极连接所述输入端，源极和漏极中的一个连接高电平电压线，另一个连接所述第一节点。
  9. 根据权利要求1至5中任意一项所述的移位寄存器单元，其中，所述复位模块包括第六晶体管，所述第六晶体管的栅极连接所述复位端，源极和漏极中的一个连接所述第一节点，另一个连接低电平电压线。
  10. 一种移位寄存器单元的驱动方法，其中，所述移位寄存器单元包括输入端、输出端、复位端和第一放噪端，并包括位于所述移位寄存器单元内部的第一节点，所述驱动方法包括：
    在输入端所接信号的控制下拉高所述第一节点处的电压；
    在所述第一节点处电压的控制下利用第一时钟信号拉高所述输出端处的电压，并在第一节点处的电压被拉高的期间断开所述第一放噪端与所述第一节点之间的电连接；
    在所述复位端所接信号的控制下拉低所述第一节点处的电压，并在第二时钟信号的控制下拉低所述输出端处的电压；以及
    在第三时钟信号的控制下将所述第一节点处的噪声电压释放至所述第一 放噪端。
  11. 一种扫描驱动电路，包括多级如权利要求1至9中任意一项所述的移位寄存器单元，其中：第N级移位寄存器单元的输入端与第N-2级移位寄存器单元的输出端相连；第N级移位寄存器单元的第一放噪端与第N-1级移位寄存器单元的输出端相连；第N级移位寄存器单元的复位端与第N+2级移位寄存器单元的输出端相连；所述N大于等于3。
  12. 根据权利要求11所述的扫描驱动电路，其中，所述移位寄存器单元还包括第二放噪端，其中，所述第N级移位寄存器单元的第二放噪端与第N+1级移位寄存器单元的输出端相连。
  13. 一种显示装置，包括如权利要求11或12所述的扫描驱动电路。
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