WO2016059692A1

WO2016059692A1 - Computer and i/o processing control method

Info

Publication number: WO2016059692A1
Application number: PCT/JP2014/077507
Authority: WO
Inventors: 悠介古山; 晃浦上
Original assignee: 株式会社日立製作所
Priority date: 2014-10-16
Filing date: 2014-10-16
Publication date: 2016-04-21

Abstract

A computer having an I/O device driver, managing vector information, and allocating a plurality of I/O cues to each of a plurality of interrupt sources. The I/O device driver manages mapping information indicating the corresponding relationship between vectors and interrupt source numbers. An I/O device has a control unit, holds a bit map-type register that manages the interrupt source numbers, and manages such that the interrupt source numbers and bit positions in the bit map correspond. The I/O device driver sends execution instructions for I/O processing including vectors and interrupt source numbers to the control unit. The control unit executes I/O processing, manipulates bits corresponding to interrupt source numbers, and generates interruptions including the vectors. The I/O device driver references the mapping information and specifies a plurality of interrupt source numbers to be associated with the vectors, reads values for bits corresponding to each of the plurality of interrupt source numbers, and specifies interrupt sources.

Description

Computer and control method of I / O processing

The present invention relates to a method for controlling I / O processing in a computer that supports multi-queue technology.

Conventionally, in an I / O process for a network device or a storage system, a plurality of I / O commands are managed using a queue structure. The I / O device driver enqueues an I / O command in the I / O activation queue when the I / O processing is activated, and dequeues a response command from the I / O response queue when an IO response is made.

In a system that supports multi-queues, an interrupt factor can be associated with each I / O queue pair. An interrupt factor can be defined from a combination of a CPU (CPU core), an I / O device core, a guest OS, and the like. Further, in a system that supports multi-queues, interrupt vectors and queues are associated one-to-one. This improves the performance of I / O processing.

When an interrupt occurs, the I / O device driver specifies an interrupt factor corresponding to the generated interrupt by accessing a register group such as an interrupt factor register and an interrupt factor aggregation register.

Generally, a process in which a CPU core of a computer accesses a register using PCI MMIO has a higher processing cost than a memory access of a computer, and causes a deterioration in performance of I / O processing.

On the other hand, by associating an interrupt vector (vector number) with an interrupt factor (a combination of an identification number of the I / O device core and an identification number of the guest OS, etc.), the I / O device driver assigns the interrupt vector. Based on this, it is possible to quickly identify the interrupt factor. This method eliminates the need for register access and improves IO performance.

As the number of CPU cores, guest OSs, and I / O device cores increases, the number of necessary I / O queues also increases. On the other hand, the number of interrupt vectors that can be secured by a computer that supports MSI-X is limited. Therefore, there is a possibility that the interrupt vector and the I / O queue cannot be associated one-on-one.

Therefore, it is necessary to set one interrupt vector so that multiple interrupt factors (I / O queues) are shared. At this time, the I / O device driver needs to access a register for specifying the identification number of the I / O device core, a register for specifying the identification number of the guest OS, and the like in addition to the registers described above. Therefore, there are two major problems when sharing interrupt vectors in a system that supports multi-queues.

One problem is that the hardware cost increases because the I / O device needs to hold multiple registers. Another problem is that the performance of I / O processing is degraded because the register needs to be accessed multiple times.

The invention described in Patent Document 1 is known as a method for solving the above-described problems. Patent Document 1 states that “a plurality of registers each storing a flag value indicating whether or not an interrupt request has occurred for each of a plurality of interrupt factors is provided, and a plurality of interrupt factors associated with the same interrupt vector are included. From the information processing device that identifies the interrupt factor that generated the interrupt request based on the flag value and executes interrupt processing according to the interrupt request, the information processing device corresponds to the interrupt factor that generated the interrupt request An interrupt vector detecting means for detecting the interrupt vector to be attached; a selecting means for selecting the flag value of the interrupt factor associated with the detected interrupt vector from the flag values stored in the register; Storage means for storing the selected flag value; and reading the flag value stored in the storage means; And control means for identifying the interrupt factor that caused the interrupt request based on the serial read-out flag value, that the having "are described.

JP 2012-103879 A

In the invention described in Patent Document 1, when the number of interrupt factors is large, the size of the list register corresponding to the storage means increases, the number of control registers increases, and the configuration of the selector becomes complicated. Further, since the interrupt vector and the control register are associated with each other, there is no degree of freedom for setting the interrupt factor for the interrupt vector.

In the invention described in Patent Document 1 and the conventional I / O processing, since a register exists for each interrupt vector, a plurality of I / O queues (interrupt factors) associated with the same interrupt vector are included in the register. Share Therefore, if I / O processing occurs continuously in multiple I / O queues associated with the same interrupt vector, the I / O device continues until one interrupt is completed and the register is reset. Cannot be interrupted. Therefore, since the I / O processing is executed sequentially, it causes a decrease in the performance of the I / O processing.

In the present invention, the hardware cost for specifying the interrupt factor is suppressed, and the control of the I / O processing capable of specifying the interrupt factor at high speed is realized. Also, the present invention realizes a system that executes I / O processing in parallel even when I / O processing of a plurality of I / O queues that share the same interrupt vector occurs continuously.

A typical example of the invention disclosed in the present application is as follows. That is, a computer on which at least one operating system runs, the computer including at least one processor including a plurality of processor cores, a storage device connected to the at least one processor, and a plurality of I / O device cores An interrupt that includes at least one I / O device connected to the at least one processor, has an I / O device driver that controls the at least one I / O device, and executes an interrupt vector and interrupt processing Managing interrupt vector information indicating a correspondence relationship with a handler, the interrupt factor is defined based on a combination of a plurality of interrupt elements, and a plurality of I / O queues are assigned to each of the plurality of interrupt factors, The I / O device uses the plurality of I / O queues. A plurality of I / O processes are executed in parallel, and the I / O device driver includes a plurality of interrupt handlers, manages interrupt factor numbers, and indicates a correspondence relationship between the interrupt vectors and the interrupt factor numbers The interrupt factor number is defined based on a bit string composed of one or more bits corresponding to each of the plurality of interrupt elements, and the I / O device is the I / O device driver Having a control unit that executes I / O processing in response to a request from the host, holding a bitmap-format register for managing the interrupt factor number, and the interrupt factor number and a bit in the bitmap corresponding to the register The I / O device driver manages the first interrupt factor number in the first interrupt vector. And the second interrupt factor number are associated with each other, an I / O processing execution request corresponding to the first interrupt factor number is received from the operating system, and the second interrupt factor number corresponds to the first interrupt factor number. A first I / O command is inserted into the I / O queue, and an instruction to execute a first I / O process including the first interrupt vector and the first interrupt factor number is transmitted to the control unit; When receiving an instruction to execute the first I / O process, the control unit executes an I / O process corresponding to the first I / O command, refers to the register, and executes the first I / O process. The first interrupt command including the first interrupt vector is inserted into the I / O queue corresponding to the first interrupt factor number. Raised When the occurrence of the first interrupt is detected, the I / O device driver activates an interrupt handler corresponding to the first interrupt vector based on the interrupt vector information, and refers to the mapping information. Then, the first interrupt factor number and the second interrupt factor number associated with the first interrupt vector are specified, and the first interrupt factor number and the second interrupt factor are specified from the register. By reading the value of the bit corresponding to each of the numbers, it is specified that an interrupt factor corresponding to the first interrupt factor number has occurred, and the I / O queue corresponding to the first interrupt factor number The first response command is acquired from the first response command, and a response process corresponding to the first response command is executed. That.

According to the present invention, when one interrupt vector is shared by a plurality of interrupt factors, the I / O device driver can specify the interrupt factor by referring only to the bitmap format register. . In addition, since the I / O device only needs to hold a bitmap format register, the hardware cost can be reduced.

Issues, configurations, and effects other than those described above will be clarified by the description of the following examples.

It is a block diagram explaining the structure of the computer system of Example 1. FIG. FIG. 3 is a block diagram illustrating an outline of a process flow in the computer according to the first embodiment. It is explanatory drawing which shows an example of the structure of the interrupt factor number of Example 1. FIG. FIG. 6 is an explanatory diagram illustrating an example of an interrupt factor number notification register according to the first embodiment. FIG. 6 is an explanatory diagram illustrating an example of I / O queue information according to the first embodiment. It is explanatory drawing which shows an example of the mapping table of Example 1. FIG. It is explanatory drawing which shows an example of the mapping table of Example 1. FIG. 6 is an explanatory diagram illustrating an example of an I / O queue address table according to the first embodiment. FIG. 6 is a flowchart illustrating an initial setting process executed by the HBA device driver according to the first embodiment. 6 is an explanatory diagram illustrating an internal operation of a computer in communication processing according to Embodiment 1. FIG. FIG. 6 is an explanatory diagram illustrating an internal operation of the computer in the I / O processing according to the first embodiment. FIG. 6 is a sequence diagram illustrating the flow of I / O processing according to the first embodiment. FIG. 6 is a sequence diagram illustrating the flow of I / O processing according to the first embodiment. FIG. 6 is a sequence diagram illustrating the flow of I / O processing according to the first embodiment. FIG. 6 is a sequence diagram illustrating the flow of I / O processing according to the first embodiment. FIG. 6 is a sequence diagram illustrating the flow of I / O processing according to the first embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration of a computer system according to the first embodiment.

The computer system includes a computer 100, a storage device 130, and a client device 140. The computer 100 and the storage device 130 are connected to each other via a network 150 such as a SAN (Storage Area Network). The computer 100 and the client device 140 are connected via a network 160 such as a LAN (Local Area Network) or a WAN (Wide Area Network).

The computer 100 executes a predetermined job. The computer 100 according to the first embodiment is a computer that supports virtual technology, and a plurality of virtual computers (VMs) 114 operate on the computer 100. On the VM 114, a guest OS is further executed.

The storage device 130 provides a storage area used by the guest OS. The storage device 130 includes a controller (not shown), an interface, and a plurality of storage devices. As the storage device, for example, an HDD (Hard Disk Drive) and an SSD (Solid State Drive) can be considered. The storage device 130 creates a plurality of logical disks 131 from the storage areas of each of the plurality of storage devices, and allocates the logical disks 131 to the guest OS on the VM 114.

The client device 140 is a computer operated by a user who uses a service provided by the computer 100. The client device 140 includes a CPU, memory, storage device, NIC, and the like (not shown).

Here, the details of the computer 100 will be described. The computer 100 includes one or more CPUs 101, a memory 102, a storage device 103, an HBA 104, and a NIC 105 as computer resources. Each component included in the computer 100 is connected to each other via an internal bus or the like. Note that the computer 100 may include an I / O device other than the HBA 104.

CPU 101 executes a program stored in memory 102. Various functions of the computer 100 can be realized by the CPU 101 executing the program. In the following description, when a program is mainly described, it indicates that the program is being executed by the CPU 101.

The CPU 101 has a plurality of CPU cores that execute various arithmetic processes. The CPU core has a cache memory (not shown), and the CPU 101 has a cache memory accessible to all CPU cores.

The memory 102 stores a plurality of programs executed by the CPU 101 and information used for executing the plurality of programs. Note that the memory 102 may be either a volatile memory or a nonvolatile memory.

The storage device 103 stores programs and information. The storage device 103 may be an HDD, an SSD, or the like. Note that the program and information stored in the memory 102 may be stored in the storage device 103. In this case, the CPU 101 reads out the program and information from the storage device 103 and loads it onto the memory 102.

The HBA 104 is an interface for connecting to the storage apparatus 130 via the network 150. The HBA 104 includes a plurality of HBA cores 120 and a register group 125. The HBA 104 includes a memory (not shown).

The HBA core 120 executes a program that realizes firmware (FW) 121 that executes predetermined processing. The register group 125 is a set of registers for controlling interrupts of I / O processing.

The computer of Example 1 supports the multi-queue function. In a computer that supports the multi-queue function, an interrupt factor can be defined for each combination of the CPU 101, the HBA core 120, and the guest OS. In the first embodiment, it is assumed that an interrupt factor and a pair of an I / O activation queue and an I / O response queue are associated one-to-one.

In the following description, elements such as the CPU 101, the HBA core 120, and the guest OS that define interrupt factors are also described as interrupt elements. When the I / O activation queue and the I / O response queue are not distinguished from each other, the I / O activation queue and the I / O response queue pair are also simply referred to as an I / O queue. .

When the interrupt elements are the CPU 101, the HBA core 120, and the guest OS, in this embodiment, I / O queue pairs are generated by the number of multiplication values that the CPU 101, the HBA core 120, and the guest OS can take. Is done. At this time, when the I / O queue pair and the interrupt vector are associated one-to-one, the performance of the I / O processing is the highest.

However, the hypervisor 110 and the OS such as the guest OS have a limit on the number of interrupt vectors that can be secured. For this reason, when the number of interrupt vectors with the maximum I / O performance is larger than the number of interrupt vectors that can be secured by the OS, it is necessary to set so that a plurality of interrupt factors share one interrupt vector.

Interrupt vector sharing can be realized by assigning one interrupt vector to possible values of one interrupt element. For example, in the case of a computer system in which two guest OSs are operating, the CPU 101 and the HBA core are the same, and one interrupt vector is assigned to two interrupt factors that are different only in the guest OS type, so that the computer 100 is set. The number of interrupt vectors to be used is half of the maximum number of interrupt vectors.

When a plurality of interrupt factors are set so as to share one interrupt vector, the conventional register group 125 includes an interrupt factor register for each HBA core 120 and an interrupt factor reset register for each HBA core 120. . In addition, the conventional register group 125 includes registers for determining interrupt elements such as the guest OS and the CPU 101 in order to specify an interrupt factor.

On the other hand, the register group 125 of the first embodiment is characterized in that it includes only an interrupt factor number notification register 251 (FIG. 2) and an interrupt factor number reset register as will be described later.

The NIC 105 is an interface for connecting to the client device 140 via the network 160.

Here, the program and memory space stored in the memory 102 will be described. The memory 102 stores a program for realizing the hypervisor 110 and the HBA device driver 111. A part of the storage area of the memory 102 is secured as a PCI memory space 112 and a data transfer area 113. In addition, data that is the substance of the VM 114 is stored in a part of the storage area of the memory 102.

The hypervisor 110 provides a virtual environment using the computer resources described above. Specifically, the hypervisor 110 generates a plurality of VMs 114 by logically dividing computer resources, and operates a guest OS on each VM 114. In the example illustrated in FIG. 1, three VMs 114 are managed by the hypervisor 110.

The HBA device driver 111 is a driver that controls the HBA 104. Specifically, the HBA device driver 111 controls the HBA 104 in order to access the storage apparatus 130.

The PCI memory space 112 is a storage area (MMIO space) for the CPU 101 to access an I / O device such as the HBA 104. The data transfer area 113 is a storage area (DMA area) for transferring data read or written by the HBA device driver 111 and the FW 121.

The PCI memory space 112 is a memory space in which the register group 125 or the like in the HBA 104 is mapped to the address space of the memory 102. In general, the memory space accessed by the CPU 101 includes an address area for accessing a main storage device such as the memory 102 and an address area for accessing an I / O device such as the HBA 104. The PCI memory space 112 according to the first embodiment is an address area for accessing an I / O device. When the CPU 101 accesses the PCI memory space 112, the I / O device recognizes that there is an access to the memory address to which the I / O device is mapped, and sends a response to the access to the register held by the I / O device to the CPU 101. return.

The above is the description of the program and memory space stored in the memory 102. Next, the flow of I / O processing and communication processing between the FW 121 and the HBA device driver 111 in the computer 100 will be described with reference to FIG. In the following description, communication processing between the FW 121 and the HBA device driver 111 is also simply referred to as communication processing.

FIG. 2 is a block diagram for explaining an overview of the processing flow in the computer 100 according to the first embodiment.

First, the configuration of the HBA device driver 111 will be described. The HBA device driver 111 includes an interrupt handler 200 and a transmission unit 220, and holds a mapping table 210 and I / O queue information 230.

The interrupt handler 200 is a functional unit that realizes processing or control corresponding to an interrupt from the HBA 104. The transmission unit 220 is a functional unit that transmits various instructions and information in response to a request received from the guest OS.

The mapping table 210 is information for managing the correspondence between interrupt factor numbers and interrupt vectors (vector numbers). Details of the interrupt factor number will be described later with reference to FIG. Details of the mapping table 210 will be described later with reference to FIG.

The I / O queue information 230 is information for managing the correspondence between interrupt factor numbers, interrupt factors, and I / O queues. In the I / O queue, there are two queues: an I / O activation queue and an I / O response queue. Details of the I / O queue information 230 will be described later with reference to FIG.

Next, details of the PCI memory space 112 and the data transfer area 113 will be described.

The data transfer area 113 includes an I / O activation queue group 260, an I / O response queue group 270, and an FW-driver interface area 280.

The I / O activation queue group 260 includes a plurality of I / O activation queues. The I / O response queue group 270 includes a plurality of I / O response queues.

The FW-driver interface area 280 is a storage area operated during communication between the FW 121 and the HBA device driver 111. The FW-driver interface area 280 includes a shared information area 281 and a communication area 282.

The shared information area 281 is a storage area for storing information shared by the FW 121 and the HBA device driver 111. The shared information area 281 of the first embodiment stores an I / O queue address table 700 (see FIG. 7). The communication area 282 is a storage area that is accessed when communication processing is executed. The shared information area 281 stores interrupt factor number definition information, which will be described later.

The PCI memory space 112 includes an interrupt vector table 240 and a register group 250.

The interrupt vector table 240 is information for managing the correspondence between the interrupt vector and the interrupt handler 200. The interrupt vector table 240 is a well-known one, and a detailed description thereof will be omitted.

The register group 250 is a memory address for the HBA device driver 111 to access the register group 125 itself of the HBA 104.

Next, the flow of conventional communication processing and I / O processing will be described. In the following description, it is assumed that one interrupt vector is shared by a plurality of interrupt factors. First, the flow of conventional communication processing will be described.

When the HBA device driver 111 receives a communication processing execution request from the guest OS on the VM 114, the HBA device driver 111 instructs the FW 121 to execute the processing by accessing the FW-driver interface area 280.

The FW 121 executes the instructed process, and then generates an interrupt including a predetermined interrupt vector. In this case, the CPU 101 refers to the interrupt vector table 240 and calls the interrupt handler 200 corresponding to the notified interrupt vector.

The interrupt handler 200 of the HBA device driver 111 refers to a register included in the register group 250 and identifies an interrupt factor. Furthermore, the interrupt handler 200 identifies a response destination guest OS based on the identified interrupt factor, and notifies the identified guest OS of the completion of the requested communication process.

Note that when one interrupt factor occupies one interrupt vector, the HBA device driver 111 can uniquely identify the interrupt factor from the interrupt vector, and therefore does not need to access the register group 250. The above is the description of the flow of conventional communication processing.

Next, the flow of conventional I / O processing will be described.

When the HBA device driver 111 receives an I / O processing execution request from the guest OS on the VM 114, the HBA device driver 111 instructs the FW 121 to execute the processing by accessing the FW-driver interface area 280.

The FW 121 executes processing instructed to the storage apparatus 130, and then generates an interrupt including a predetermined interrupt vector. In this case, the CPU 101 refers to the interrupt vector table 240 and calls the interrupt handler 200 corresponding to the notified interrupt vector.

The interrupt handler 200 of the HBA device driver 111 refers to a register included in the register group 250 and identifies an interrupt factor. Furthermore, the interrupt handler 200 identifies the response destination guest OS based on the identified interrupt factor, and notifies the identified guest OS of the completion of the requested I / O processing.

Note that when one interrupt factor occupies one interrupt vector, the HBA device driver 111 can uniquely identify the interrupt factor from the interrupt vector, and therefore does not need to access the register group 250. The above is the description of the flow of conventional I / O processing.

When a single interrupt vector is shared by a plurality of interrupt factors, in conventional communication processing and I / O processing, the HBA device driver 111 accesses a plurality of types of registers multiple times in order to identify the interrupt factor. There is a need. However, the access processing via the PCI memory space 112 increases the processing cost and causes the performance of the I / O processing to deteriorate.

Therefore, in order to improve the performance of I / O processing, it is necessary to reduce the number of accesses to the register group 250 as much as possible. In the first embodiment, the above-described problem is solved by using a new identification number called an interrupt factor number.

The method of defining interrupt factor numbers and the meaning of interrupt factor numbers will be described with reference to FIGS.

FIG. 3 is an explanatory diagram showing an example of the structure of the interrupt factor number according to the first embodiment. FIG. 4 is an explanatory diagram illustrating an example of the interrupt factor number notification register 251 according to the first embodiment.

In the first embodiment, the HBA device driver 111 generates an interrupt factor number as shown in FIG. 3 based on the interrupt factor. The interrupt factor number is defined based on the bit string. FIG. 3 shows an interrupt factor number composed of an 11-bit bit string. Therefore, the HBA device driver 111 can generate 512 interrupt factor numbers. When the length of the bit string is 12 bits, the number of interrupt factor numbers that can be generated is 1024.

The HBA device driver 111 associates one or more bits with one interrupt element in advance. For example, definition information for generating an interrupt factor number is registered in the HBA device driver 111 in advance as interrupt factor number definition information. The definition information includes a bit length defining an interrupt factor number, a type of interrupt element, a bit position corresponding to the interrupt element in a bit string defining the interrupt factor number, a bit length of the interrupt element, and the like.

In this embodiment, it is assumed that the relationship between interrupt elements and bits is defined as follows. The interrupt elements according to the first embodiment include the CPU 101, the HBA core 120, the interrupt type, the interrupt priority, and the guest OS.

The upper 2 bits of the bit string are bits corresponding to the CPU 101 identification number. The next 2 bits are bits corresponding to the identification number of the HBA core 120. The next 2 bits are bits corresponding to the interrupt type. Here, the interrupt type is information for identifying an interrupt of an I / O process or an interrupt of a communication process.

The next 1 bit of the interrupt type is a bit corresponding to the interrupt priority indicating the priority order of interrupts. The next 4 bits are bits corresponding to the guest OS that notifies the interrupt response.

Note that the bit length of each interrupt element and the position of the bit associated with each interrupt element can be appropriately changed according to the hardware configuration and software configuration of the computer 100.

In the first embodiment, the HBA 104 holds a bitmap having a predetermined size as the interrupt factor number notification register 251 in advance. Each bit of the bitmap is associated with an interrupt factor number defined using a bit string as shown in FIG. That is, one bit of the bitmap corresponds to one interrupt factor number.

At this time, the interrupt factor number notification register 251 in the bitmap format can be interpreted as shown in FIG. Here, it is assumed that the number of guest OSs is “16” and the priority is either “0” or “1”.

When the interrupt factor number notification register 251 is expressed as a bit map of 16 bits in one row, the bit map columns are arranged in the order of interrupt elements corresponding to the least significant bits of the bit string, that is, the guest OS identification numbers. Each row of the bitmap is arranged based on a combination of interrupt elements (priority, interrupt type, HBA core 120, and CPU 101) corresponding to the upper bits of the bit string. More specifically, the bitmap row is configured so that it can be identified from the least significant bit of the bit string defining the interrupt factor number.

Therefore, the meaning of the row and column of the bitmap can be changed by changing the configuration of the bit string of the interrupt factor number. The number of bits included in the bitmap (bitmap size) may be larger than the number of interrupt factor numbers. When the FW 121 associates the interrupt factor number with the bit of the bitmap, the FW 121 does not handle a bit for which no interrupt factor number exists as a management target.

The HBA device driver 111 stores the interrupt factor number definition information and operation information indicating how to use the interrupt factor number notification register 251 in the shared information area 281. The FW 121 of the HBA 104 manages the bit position of the bitmap and the interrupt factor number so as to correspond to each other as shown in FIG. 4 based on the definition information of the interrupt factor number. Also, the FW 121 of the HBA 104 operates the bit of the interrupt factor number notification register 251 based on the operation information.

The HBA device driver 111 can specify the interrupt factor from the bit of the bitmap as will be described later. Specifically, the following processing is executed in the I / O processing or communication processing.

The FW 121 of the HBA 104 refers to the interrupt factor number notification register 251 when executing the I / O process or the communication process, and manipulates the bit that matches the interrupt factor corresponding to the I / O process.

The HBA device driver 111 refers to the interrupt factor number notification register 251, that is, the bit map as shown in FIG. 4, and identifies which bit is being operated. As described above, since the bit position and the interrupt factor number have a one-to-one correspondence, the HBA device driver 111 can specify the interrupt factor number based on the bit value of the interrupt factor number notification register 251.

FIG. 5 is an explanatory diagram illustrating an example of the I / O queue information 230 according to the first embodiment.

The I / O queue information 230 stores a plurality of entries for managing interrupt factor numbers, interrupt factors, and I / O queue correspondences. The entry includes an interrupt factor number 501, an HBA core number 502, a CPU number 503, a guest OS number 504, an I / O activation queue address 505, and an I / O response queue address 506.

Interrupt factor number 501 is a column that stores interrupt factor numbers. In this embodiment, it is assumed that the interrupt factor number 501 of each entry is stored in ascending order.

The HBA core number 502, the CPU number 503, and the guest OS number 504 are interrupt element identification information. The HBA core number 502 is a column that stores the identification number of the HBA core 120 that executes the I / O processing. The CPU number 503 is a column that stores the identification number of the CPU 101 that executes the response process. The guest OS number 504 is a column that stores the identification number of the guest OS that notifies the response to the I / O processing.

The I / O activation queue address 505 is a column that stores an address indicating the position of the I / O activation queue in which an I / O command for realizing I / O processing is inserted. The I / O response queue address 506 is a column that stores an address indicating the position of the I / O response queue in which a response command for realizing response processing is inserted.

6A and 6B are explanatory diagrams illustrating an example of the mapping table 210 according to the first embodiment.

The mapping table 210 stores a plurality of entries for managing the correspondence relationship between the interrupt vector, the interrupt factor number, and the interrupt handler 200. The entry includes an interrupt vector 601, an interrupt factor number 602, and an interrupt handler 603.

The interrupt vector 601 is a column for storing an interrupt vector. The interrupt factor number 602 is a column for storing an interrupt factor number associated with an interrupt vector. The interrupt handler 603 is a column that stores identification information of the interrupt handler 200 that is activated when an interrupt vector is received.

FIG. 6A shows the mapping table 210 when the interrupt vector and the interrupt factor number are associated one-to-one. FIG. 6B shows the mapping table 210 when a plurality of interrupt factor numbers are associated with one interrupt vector.

As shown in FIG. 6B, when a plurality of interrupt factor numbers are shared by one interrupt vector, the HBA device driver 111 associates the interrupt factor numbers with the interrupt vectors so that the interrupt factor numbers are continuous.

As shown in FIG. 4, consecutive interrupt factor numbers in one row are numbers corresponding to interrupt factors having different values of interrupt elements such as the CPU 101 and the HBA core 120, and different only in the guest OS. For this reason, the HBA device driver 111 reads the values of consecutive bits in the bit table at a time when an interrupt vector is notified when a plurality of interrupt factor numbers are shared by one interrupt vector. The interrupt factor number corresponding to can be specified.

The general HBA device driver 111 can read out the value of 32 bits by one reading because the size of data that can be read from the register group 125 at a time is 4 bytes. Therefore, it is possible to reduce the number of readings of the register group 125 necessary for specifying the interrupt factor number.

FIG. 7 is an explanatory diagram illustrating an example of the I / O queue address table 700 according to the first embodiment.

The I / O queue address table 700 stores a plurality of entries for managing the correspondence between interrupt factor numbers and I / O queues. Each entry includes an interrupt factor number 701, an I / O activation queue address 702, and an I / O response queue address 703.

The interrupt factor number 701, the I / O activation queue address 702, and the I / O response queue address 703 are the same as the interrupt factor number 501, the I / O activation queue address 505, and the I / O response queue address 506, respectively. It is.

FIG. 8 is a flowchart illustrating an initial setting process executed by the HBA device driver 111 according to the first embodiment.

The HBA device driver 111 starts the initial setting process at a predetermined timing. For example, the initial setting process is started when the computer 100 is turned on or when an execution instruction is given by the administrator of the computer 100.

The HBA device driver 111 determines the number of I / O queue pairs based on the system configuration of the computer 100, and generates an I / O queue (step S801).

In this embodiment, the number of I / O queue pairs coincides with the number of I / O interrupt factors. For example, the HBA device driver 111 uses the following equation (1) to calculate I / O queue pairs: Determine the number of. Note that the number of guest OSs may be either the maximum number of guest OSs that can be set in the computer 100 or the number of guest OSs currently running on the computer 100.

The HBA device driver 111 generates an interrupt factor number corresponding to each I / O interrupt factor, and assigns the generated interrupt factor number to each I / O queue (step S802). In step S802, for example, the following processing is executed.

The HBA device driver 111 prepares a bit string of a predetermined length based on the definition information of the interrupt factor number, and associates the bit of each bit string with the interrupt element. Furthermore, the HBA device driver 111 generates an interrupt factor number corresponding to the I / O interrupt factor by setting the value of the interrupt element in each bit.

The HBA device driver 111 generates an interrupt factor number so that an interrupt factor is different for only an interrupt factor corresponding to the least significant bit in the bit string. As a result, the bitmap can be interpreted as shown in FIG.

At this time, the HBA device driver 111 prepares empty I / O queue information 230 and sets the generated interrupt factor number in the interrupt factor number 501 of the I / O queue information 230. Further, the HBA device driver 111 sets values for the HBA core number 502, the CPU number 503, and the guest OS number 504 based on the interrupt factor corresponding to the interrupt factor number.

Furthermore, the HBA device driver 111 assigns one interrupt factor number to each I / O queue pair. That is, the same interrupt factor number is assigned to the I / O transmission queue and the I / O response queue constituting the pair.

At this time, the HBA device driver 111 sets the address of the I / O transmission queue in the I / O activation queue address 505 of the I / O queue information 230, and also sets the I / O response queue in the I / O response queue address 506. Set the address.

The above is the description of the process in step S802.

Next, the HBA device driver 111 generates an interrupt factor number corresponding to an interrupt factor other than the I / O interrupt factor, and assigns the generated interrupt factor number to each interrupt factor (step S803). The method for generating the interrupt factor number is the same as that in step S802.

The HBA device driver 111 stores information (not shown) for managing the correspondence between the interrupt factor number and the interrupt factor on the memory 102. The information stores a plurality of entries including an interrupt factor number, an identification number of the HBA core 120, an identification number of the CPU 101, and an identification number of the guest OS.

The HBA device driver 111 calculates the total number of interrupt factors by adding the number of I / O interrupt factors and the number of interrupt factors other than I / O (step S804).

The HBA device driver 111 makes an inquiry to the hypervisor 110 to check the number of interrupt vectors that can be secured by the hypervisor 110 (step S805). Further, the HBA device driver 111 determines whether or not the number of interrupt vectors that can be secured by the hypervisor 110 is equal to or greater than the total number of interrupt factors (step S806).

When it is determined that the number of interrupt vectors that can be secured by the hypervisor 110 is smaller than the total number of interrupt factors, the HBA device driver 111 sets a sharing method for a plurality of interrupt factors to share one interrupt vector (step S807). It is assumed that the sharing method is set in the HBA device driver 111 in advance.

The HBA device driver 111 sets the vector sharing mode based on the set sharing method (step S808). Thereafter, the HBA device driver 111 proceeds to step S810. Specifically, the HBA device driver 111 is set so that the interrupt factor number notification register 251 can be accessed.

If it is determined in step S806 that the number of interrupt vectors that can be secured by the hypervisor 110 is equal to or greater than the total number of interrupt factors, the HBA device driver 111 sets the vector occupation mode (step S809). Thereafter, the HBA device driver 111 proceeds to step S810.

In step S810, the HBA device driver 111 generates the mapping table 210 by associating the interrupt vector and the interrupt factor in accordance with each operation mode (vector occupation mode or vector sharing mode) (step S810). Here, the specific process of step S810 in each operation mode will be described.

(1) When the operation mode is the vector occupation mode

The HBA device driver 111 associates the interrupt vector with the interrupt factor number on a one-to-one basis. Assume that the association method is preset.

The HBA device driver 111 generates an empty mapping table 210 and sets interrupt vectors in the ascending order in the interrupt vector 601. Further, the HBA device driver 111 sets an interrupt factor number associated with each interrupt vector in the interrupt factor number 602.

Furthermore, the HBA device driver 111 sets access information to the interrupt handler corresponding to the interrupt factor in the interrupt handler 603.

(2) When the operation mode is the vector sharing mode

The HBA device driver 111 associates a plurality of consecutive interrupt factor numbers with one interrupt vector. Specifically, a plurality of interrupt factors having the same interrupt element corresponding to the upper bit and different interrupt elements corresponding to the lowest bit share one interrupt vector. From another viewpoint, a plurality of interrupt factor numbers for calling the same interrupt handler 200 share one interrupt vector.

Note that, depending on the sharing method, consecutive interrupt factor numbers may not be obtained. In this case, the HBA device driver 111 associates the interrupt vector and the interrupt factor number so that the interrupt factor number is a serial number as much as possible.

The HBA device driver 111 generates an empty mapping table 210 and sets interrupt vectors in the ascending order in the interrupt vector 601. Further, the HBA device driver 111 sets a plurality of interrupt factor numbers associated with each interrupt vector in the interrupt factor number 602.

The above is the description of the processing in step S810.

Next, the HBA device driver 111 generates the I / O queue address table 700 in the shared information area 281 (step S811). Thereafter, the HBA device driver 111 ends the initial setting process.

Specifically, the HBA device driver 111 registers the same number of entries as the number of entries registered in the I / O queue information 230 in the empty I / O queue address table 700. The HBA device driver 111 adds an interrupt factor number 501, an I / O activation queue address 505, and an I / O response to the interrupt factor number 701, I / O activation queue address 702, and I / O response queue address 703 of each entry. The same value as the queue address 506 is set.

Also, the HBA device driver 111 notifies the FW 121 of the definition information and operation information of the interrupt factor number. The operation information defines that the FW 121 operates the interrupt factor number notification register 251 when operating in the vector sharing mode and receiving an instruction to execute an I / O command including an interrupt factor number. Thereby, the FW 121 can operate the interrupt factor number notification register 251 in cooperation with the HBA device driver 111.

Next, a specific processing flow of communication processing and I / O processing according to the first embodiment will be described.

First, the flow of communication processing will be described. FIG. 9 is an explanatory diagram illustrating an internal operation of the computer 100 in the communication processing according to the first embodiment.

First, the VM 114 requests the HBA device driver 111 to execute communication processing via the hypervisor 110.

The transmission unit 220 of the HBA device driver 111 instructs the FW 121 of the HBA 104 to execute communication processing via the communication area 282. The instruction includes an interrupt vector and an interrupt notification number.

The FW 121 of the HBA 104 executes communication processing. Further, the FW 121 of the HBA 104 refers to the interrupt factor number notification register 251 and manipulates a bit that matches the interrupt factor number corresponding to the communication process. Thereafter, the FW 121 of the HBA 104 generates an interrupt including an interrupt vector.

The CPU 101 refers to the interrupt vector table 240 based on the interrupt vector included in the generated interrupt and calls the interrupt handler 200 corresponding to the interrupt vector. The interrupt handler 200 determines whether or not the interrupt vector is shared.

When the interrupt vector is not shared, the interrupt handler 200 can uniquely identify the interrupt factor, and thus responds to the VM 114 that is the response destination of the interrupt as it is.

When the interrupt vector is shared, the interrupt handler 200 executes the following process.

(1) The interrupt handler 200 refers to the mapping table 210 based on the interrupt vector, and specifies a plurality of interrupt factor numbers associated with the interrupt vector.

In this embodiment, as shown in FIG. 6B, a plurality of consecutive interrupt factor numbers are associated with one interrupt vector. Therefore, the interrupt handler 200 can identify the interrupt factor by reading the values of the four bits from the interrupt factor number as the starting point. Here, the interrupt factor number as the starting point is the smallest interrupt factor number among the interrupt factor numbers registered in the interrupt factor number 602.

(2) The interrupt handler 200 reads the value of four bits from the bit as the starting point from the interrupt factor number notification register 251. Furthermore, the interrupt handler 200 specifies an interrupt factor number corresponding to the generated interrupt based on the read bit value.

(3) The interrupt handler 200 identifies the interrupt response destination VM 114 by analyzing the identified interrupt factor number. Furthermore, the interrupt handler 200 responds to the VM 114 that is the response destination of the interrupt.

Next, a specific flow of I / O processing will be described. FIG. 10 is an explanatory diagram illustrating an internal operation of the computer 100 in the I / O processing according to the first embodiment. 11, FIG. 12A, FIG. 12B, FIG. 13A, and FIG. 13B are sequence diagrams illustrating the flow of I / O processing according to the first embodiment. 11 shows the flow of I / O processing in the vector occupation mode, and FIGS. 12A, 12B, 13A, and 13B show the flow of I / O processing in the vector sharing mode.

The I / O processing in the vector occupation mode will be described with reference to FIGS.

When the HBA device driver 111 receives an I / O request from the VM 114 via the hypervisor 110, the HBA device driver 111 starts I / O processing.

First, the transmission unit 220 of the HBA device driver 111 refers to the I / O queue information 230 and inserts an I / O command into the I / O activation queue corresponding to the interrupt factor (step S1101). Here, it is assumed that the interrupt factor number is “32”. The mapping table 210 is in the state shown in FIG. 6A. Therefore, the interrupt vector assigned to the interrupt factor number “32” is “2”.

The transmission unit 220 of the HBA device driver 111 instructs the HBA 104 to execute the I / O command inserted in the I / O processing queue (step S1102). Specifically, the HBA device driver 111 refers to the mapping table 210 and specifies an interrupt vector associated with the interrupt factor number. Further, the HBA device driver 111 outputs an I / O command execution instruction including an interrupt vector and an interrupt factor number to the FW 121 of the HBA 104. Here, the instruction includes an interrupt vector “2” and an interrupt factor number “32”.

When the FW 121 of the HBA 104 receives an I / O command execution instruction from the HBA device driver 111, the FW 121 acquires the addresses of the I / O activation queue and the I / O response queue associated with the interrupt factor number (step S1103).

Specifically, the FW 121 refers to the I / O queue address table 700 based on the interrupt factor number, and searches for an entry in which the interrupt factor number 701 matches the interrupt factor number included in the execution instruction. The FW 121 uses the I / O activation queue address 702 and the I / O response queue address 703 of the retrieved entry to determine the I / O transmission queue in which the I / O command is inserted and the I / O response queue used at the time of response. Get the address.

The FW 121 of the HBA 104 reads the I / O command from the I / O activation queue based on the acquired address, and executes the I / O command (step S1104). As a result, the I / O processing for the storage apparatus 130 is executed. The FW 121 of the HBA 104 accesses the storage device 130 according to the processing content of the I / O processing.

When the FW 121 of the HBA 104 receives an I / O completion notification from the storage device 130 (step S1105), it inserts a response command into the I / O response queue, and further responds to the interrupt vector notified from the HBA device driver 111. An interrupt is generated (step S1106). Here, the FW 121 of the HBA 104 generates an interrupt for the interrupt vector “2”.

The CPU 101 refers to the interrupt vector table 240 based on the interrupt vector included in the generated interrupt and calls the interrupt handler 200 corresponding to the interrupt vector. The interrupt handler 200 refers to the mapping table 210 and determines whether or not the interrupt vector is shared. In the mapping table 210 shown in FIG. 6A, since one interrupt factor number is assigned to one interrupt vector, the interrupt handler 200 determines that the interrupt vector is not shared.

If the interrupt vector is not shared, the interrupt handler 200 can uniquely identify the interrupt factor. Therefore, the interrupt handler 200 refers to the mapping table 210 and acquires the interrupt factor number corresponding to the interrupt vector (step S1107). Further, the interrupt handler 200 refers to the I / O queue information 230 and searches for an entry in which the interrupt factor number 501 matches the acquired interrupt factor number. The interrupt handler 200 acquires the address of the I / O response queue from the I / O response queue address 506 of the retrieved entry.

The interrupt handler 200 reads a response command from the I / O response queue corresponding to the interrupt factor number, and executes response processing based on the response command (step S1108). As a result, a response can be notified to the VM 114 that has transmitted the I / O request.

Next, I / O processing in the vector sharing mode will be described with reference to FIGS. 10, 12A, and 12B.

When the HBA device driver 111 receives an I / O request from the VM 114 via the hypervisor 110, the HBA device driver 111 starts I / O processing. Here, it is assumed that the interrupt factor number is “32”. The mapping table 210 is in the state shown in FIG. 6B. Therefore, the interrupt vector assigned to the interrupt factor number “32” is “1”. The interrupt vector “1” is shared with other interrupt factor numbers “33”, “34”, and “35”.

Since the processing from step S1201 to step S1205 has the same contents as the processing from step S1101 to step S1105, description thereof will be omitted.

When receiving the I / O completion notification from the storage device 130, the FW 121 of the HBA 104 operates the bit corresponding to the notified interrupt factor number among the bits included in the interrupt factor number notification register 251 (step S1206). . Here, the FW 121 of the HBA 104 operates the bit corresponding to the interrupt factor number “32”.

The FW 121 of the HBA 104 inserts a response command into the I / O response queue, and further generates an interrupt for the interrupt vector from the HBA device driver 111 (step S1207). Here, the FW 121 of the HBA 104 generates an interrupt for the interrupt vector “1”.

The CPU 101 refers to the interrupt vector table 240 based on the interrupt vector included in the generated interrupt and calls the interrupt handler 200 corresponding to the interrupt vector. The interrupt handler 200 refers to the mapping table 210 and determines whether or not the interrupt vector is shared. In the mapping table 210 shown in FIG. 6B, the interrupt handler 200 determines that the interrupt vector is shared because four interrupt factor numbers share one interrupt vector.

The interrupt handler 200 acquires all interrupt factor numbers sharing the interrupt vector notified from the HBA device driver 111 from the mapping table 210 (step S1208). Here, since the interrupt vector is “1”, the interrupt handler 200 acquires four interrupt factor numbers “32”, “33”, “34”, and “35”.

The interrupt handler 200 refers to the interrupt factor number notification register 251 and identifies an interrupt notification number corresponding to the generated interrupt (step S1209). Specifically, the following processing is executed.

The interrupt handler 200 selects a reference interrupt factor number from among a plurality of interrupt factor numbers acquired from the mapping table 210. Here, the interrupt handler 200 selects the interrupt factor number having the smallest value as the reference interrupt factor number. That is, “32” is selected as the reference interrupt factor number.

The interrupt handler 200 refers to the interrupt factor number notification register 251 and reads the value of a predetermined number of bits including the bit corresponding to the reference interrupt factor number. For example, it is assumed that the interrupt handler 200 reads a value of a 4-bit bit that is larger than the reference interrupt factor number and that is continuous from the reference interrupt factor number. In this case, the interrupt handler 200 reads values of four bits from “32” to “35”.

The interrupt handler 200 can specify the interrupt factor number corresponding to the bit by specifying the bit being operated based on the read bit value.

The interrupt handler 200 reads a predetermined range of bit values at a time. Therefore, when a plurality of discontinuous interrupt factor numbers are assigned to one interrupt vector, the interrupt handler 200 needs to frequently access the interrupt factor number notification register 251.

In this embodiment, in order to reduce the number of accesses to the interrupt factor number notification register 251 as described above, the HBA device driver 111 assigns a plurality of consecutive interrupt factor numbers to one interrupt vector. Thus, the interrupt handler 200 can grasp the operation states of a plurality of interrupt factor numbers sharing one interrupt vector with a small number of read processes.

The interrupt handler 200 can specify that the interrupt factor number corresponding to the interrupt is “32” by executing the processing described above. The above is the description of the processing in step S1209.

The interrupt handler 200 resets the value of the bit read in step S1208 among the bits of the interrupt factor number notification register 251 (step S1210).

Specifically, the interrupt handler 200 resets the values of a plurality of bits whose values have been read. For example, when the interrupt handler 200 reads the 4-bit value from the interrupt factor number “32” once, the interrupt handler 200 resets the values of the four bits from the interrupt factor numbers “32” to “35”. Further, when the interrupt handler 200 reads the 4-bit value from the interrupt factor number “32” twice, the interrupt handler 200 resets the values of the eight bits from the interrupt factor numbers “32” to “39”.

The interrupt handler 200 reads a response command from the I / O response queue corresponding to the specified interrupt factor number, and executes a response process based on the response command (step S1211).

Next, I / O processing in the vector sharing mode will be described with reference to FIGS. 10, 13A, and 13B. 13A and 13B show the flow of I / O processing when a plurality of I / O processing occurs continuously.

Conventionally, the HBA 104 holds a register for each HBA core 120 in order to specify an interrupt factor. For this reason, when a plurality of I / O processes using the same HBA core 120 are executed, the plurality of I / O processes cannot be processed in parallel, and must be sequentially processed (serialized).

This is because, when an interrupt occurs, the HBA device driver 111 refers to a register held by the HBA core 120 in order to identify the cause of the interrupt and cannot operate the register until the reset is performed.

On the other hand, the HBA 104 of the first embodiment only needs to hold the interrupt factor number notification register 251 and does not need to hold a register for each HBA core. Therefore, the problem as described above does not occur. Therefore, the computer 100 according to the first embodiment can execute a plurality of I / O processes in parallel regardless of the interrupt factor corresponding to the I / O process.

Hereinafter, a specific processing flow will be described. Here, it is assumed that two I / O processes corresponding to interrupt factor numbers “32” and “33” are executed as I / O processes using the same HBA core 120. In general, interrupt factor numbers do not have to be consecutive.

The transmission unit 220 of the HBA device driver 111 refers to the I / O queue information 230 and inserts an I / O command into the I / O activation queue corresponding to the interrupt factor (steps S1301 and S1302). Specifically, the transmission unit 220 inserts an I / O command into each of the I / O activation queue corresponding to the interrupt factor number “32” and the I / O activation queue corresponding to the interrupt factor number “33”. .

The transmission unit 220 of the HBA device driver 111 instructs the FW 121 of the HBA 104 to execute the I / O command inserted in the I / O processing queue (steps S1303 and S1304). Specifically, the HBA device driver 111 transmits an I / O command execution instruction including the interrupt vector “1” and the interrupt factor number “32” to the FW 121 of the HBA 104, and the interrupt vector “1” and the interrupt factor An instruction to execute an I / O command including the number “33” is transmitted to the FW 121 of the HBA 104.

When the FW 121 of the HBA 104 receives an instruction to execute an I / O command including the interrupt vector “1” and the interrupt factor number “32” from the HBA device driver 111, the FW 121 and the I / O activation queue associated with the interrupt factor number The address of the I / O response queue is acquired (step S1305). Further, the FW 121 of the HBA 104 reads the I / O command from the I / O activation queue based on the acquired address, and executes the I / O command (step S1306).

When the FW 121 of the HBA 104 receives an instruction to execute an I / O command including the interrupt vector “1” and the interrupt factor number “33” from the HBA device driver 111, the I / O activation associated with the interrupt factor number is performed. The addresses of the queue and the I / O response queue are acquired (step S1307). Further, the FW 121 of the HBA 104 reads the I / O command from the I / O activation queue based on the acquired address, and executes the I / O command (step S1308).

When the FW 121 of the HBA 104 receives a notification of completion of I / O corresponding to the interrupt factor number “32” from the storage device 130 (step S1309), the interrupt factor number among the bits included in the interrupt factor number notification register 251 The bit corresponding to “32” is manipulated (step S1311). Further, the FW 121 of the HBA 104 inserts a response command into the I / O response queue, and further generates an interrupt for the interrupt vector “1” (step S1313).

In addition, when the FW 121 of the HBA 104 receives a notification of completion of I / O corresponding to the interrupt factor number “33” from the storage device 130 (step S1310), among the bits included in the interrupt factor number notification register 251, the interrupt The bit corresponding to the factor number “33” is manipulated (step S1312). Further, the FW 121 of the HBA 104 inserts a response command into the I / O response queue, and further generates an interrupt for the interrupt vector “1” (step S1314).

The interrupt handler 200 acquires all interrupt factor numbers sharing the interrupt vector from the mapping table 210 (step S1315). Here, since the interrupt vector is “1”, the interrupt handler 200 acquires four interrupt factor numbers “32”, “33”, “34”, and “35”.

The interrupt handler 200 refers to the interrupt factor number notification register 251 and specifies that the interrupt notification numbers corresponding to the generated interrupt are “32” and “33” (step S1316).

The interrupt handler 200 resets the value of the bit read in step S1315 among the bits of the interrupt factor number notification register 251 (step S1317).

The interrupt handler 200 reads a response command from the I / O response queue corresponding to each of the interrupt factor numbers “32” and “33”, and executes response processing based on the response command (step S1318).

In the prior art, after the interrupt in step S1313 occurs, the interrupt in step S1314 cannot be generated until the reset process as in step S1317 is executed. On the other hand, in this embodiment, the HBA 104 does not need to hold a register for each HBA core 121, and only holds the interrupt factor number notification register 251. Therefore, the problems as described above can be solved.

As described above, according to the first embodiment, the computer 100 may hold only the interrupt factor number notification register 251 as a register for specifying an interrupt factor. Therefore, the hardware cost can be reduced.

Also, the interrupt handler 200 of the first embodiment can identify the interrupt factor at high speed by accessing the interrupt factor number notification register 251. In particular, since the HBA device driver 111 sets so that consecutive interrupt factor numbers share one interrupt vector, the interrupt factor can be identified at high speed by reading the value of consecutive bits in the interrupt factor number notification register 251. That is, the HBA device driver 111 can specify the interrupt factor by accessing the interrupt factor number notification register 251 once or a small number of times.

In addition, since the computer according to the first embodiment does not need to hold a register for each HBA core 120, even when a plurality of I / O processes occur continuously, the computer can execute the processes in parallel. it can. In addition, the determination of the interrupt factor number, management, and interrupt processing using the interrupt factor number are performed by the HBA device driver 111 and the FW 121. Therefore, it is possible to respond flexibly without being limited to the configuration of the computer 100.

In addition, this invention is not limited to the above-mentioned Example, Various modifications are included. Further, for example, the above-described embodiments are described in detail for easy understanding of the present invention, and are not necessarily limited to those provided with all the described configurations. Further, a part of the configuration of each embodiment can be added to, deleted from, or replaced with another configuration.

In addition, each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. The present invention can also be realized by software program codes that implement the functions of the embodiments. In this case, a storage medium in which the program code is recorded is provided to the computer, and a CPU included in the computer reads the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code itself and the storage medium storing it constitute the present invention. Examples of storage media for supplying such program codes include flexible disks, CD-ROMs, DVD-ROMs, hard disks, SSDs (Solid State Drives), optical disks, magneto-optical disks, CD-Rs, magnetic tapes, A non-volatile memory card, ROM, or the like is used.

Further, the program code for realizing the functions described in this embodiment can be implemented by a wide range of programs or script languages such as assembler, C / C ++, Perl, Shell, PHP, Java, and the like.

Furthermore, by distributing the program code of the software that realizes the functions of the embodiments via a network, the program code is stored in a storage means such as a hard disk or memory of a computer or a storage medium such as a CD-RW or CD-R. The CPU included in the computer may read and execute the program code stored in the storage unit or the storage medium.

In the above-described embodiments, the control lines and information lines indicate those that are considered necessary for the explanation, and do not necessarily indicate all the control lines and information lines on the product. All the components may be connected to each other.

Claims

A computer running at least one operating system,
The calculator is
At least one processor including a plurality of processor cores, a storage device connected to the at least one processor, and a plurality of I / O device cores, and at least one I / O device connected to the at least one processor Prepared,
An I / O device driver for controlling the at least one I / O device;
Manages interrupt vector information indicating the correspondence between interrupt vectors and interrupt handlers that execute interrupt processing.
The interrupt factor is defined based on a combination of a plurality of interrupt elements,
A plurality of I / O queues are assigned to each of a plurality of interrupt factors,
The I / O device executes a plurality of I / O processes in parallel using the plurality of I / O queues,
The I / O device driver is
Contains multiple interrupt handlers,
Manage interrupt source numbers
Managing mapping information indicating the correspondence between the interrupt vector and the interrupt factor number;
The interrupt factor number is defined based on a bit string composed of one or more bits corresponding to each of the plurality of interrupt elements,
The I / O device is
A control unit that executes I / O processing in response to a request from the I / O device driver;
Holds a bitmap format register that manages the interrupt factor number,
The interrupt factor number and the bit position in the bit map corresponding to the register are managed to correspond to each other,
The I / O device driver is
When the first interrupt factor number and the second interrupt factor number are associated with the first interrupt vector, the operating system issues an I / O processing execution request corresponding to the first interrupt factor number. Accept,
Inserting a first I / O command into the I / O queue corresponding to the first interrupt factor number;
An instruction to execute a first I / O process including the first interrupt vector and the first interrupt factor number is transmitted to the control unit;
The controller is
When the execution instruction of the first I / O process is received, the I / O process corresponding to the first I / O command is executed,
Referring to the register, manipulating a bit corresponding to the first interrupt factor number;
Insert a first response command into the I / O queue corresponding to the first interrupt factor number,
Generating a first interrupt including the first interrupt vector;
The I / O device driver is
If the occurrence of the first interrupt is detected, an interrupt handler corresponding to the first interrupt vector is activated based on the interrupt vector information,
Referring to the mapping information, identifying the first interrupt factor number and the second interrupt factor number associated with the first interrupt vector;
The interrupt of the interrupt factor corresponding to the first interrupt factor number has occurred by reading the value of the bit corresponding to each of the first interrupt factor number and the second interrupt factor number from the register Identify
A computer that acquires the first response command from an I / O queue corresponding to the first interrupt factor number and executes response processing corresponding to the first response command.
The computer according to claim 1,
The plurality of interrupt elements are the processor, the I / O device core, the operating system, an interrupt type, and an interrupt priority.
The I / O device driver is
Generating the plurality of I / O queues by the number of the plurality of interrupt factors, and associating the plurality of interrupt factors with the plurality of I / O queues;
Generating the interrupt factor number by setting the value of each of the plurality of interrupt elements to one or more bits corresponding to each of the plurality of interrupt elements;
Determining the correspondence between the interrupt vector and the interrupt factor number;
Registering the correspondence between the interrupt vector and the interrupt factor number in the mapping information,
Sending the interrupt factor number definition information and the register operation method to the control unit,
The controller is
Based on the definition information of the interrupt factor number, the interrupt factor number and the bit position in the bit map corresponding to the register are managed to correspond to each other,
A computer that operates a bitmap corresponding to the register based on an operation method of the register.
The computer according to claim 2,
The I / O device driver is
For the plurality of interrupt factors identifiable by the interrupt element corresponding to the least significant bit of the bit string, generate the interrupt factor number so that the interrupt factor number is a serial number,
When the plurality of interrupt factor numbers are associated with one interrupt vector and registered in the mapping information, the plurality of interrupt factor numbers are serially assigned to the plurality of interrupt factor numbers. A computer characterized by associating interrupt factor numbers.
The computer according to claim 3, wherein
The I / O device driver is
After receiving an I / O process execution request corresponding to the first interrupt factor number from the operating system, receiving an I / O process execution request corresponding to the second interrupt factor number from the operating system;
After inserting the first I / O command into the I / O queue corresponding to the first interrupt factor number, the second I / O command into the I / O queue corresponding to the second interrupt factor number Insert
After transmitting an instruction to execute the first I / O process to the control unit, an instruction to execute a second I / O process including the first interrupt vector and the second interrupt factor number is sent to the control unit. To
The controller is
When an instruction to execute the first I / O process and an instruction to execute the second I / O process are received, the I / O process corresponding to the first I / O command is executed, and then the first I / O process is executed. I / O processing corresponding to the I / O command of 2 is executed,
After manipulating the bit corresponding to the first interrupt factor number, manipulating the bit corresponding to the second interrupt factor number;
After inserting the first response command into the I / O queue corresponding to the first interrupt factor number, the second response command into the I / O queue corresponding to the second interrupt factor number Insert
After generating the first interrupt, generating a second interrupt including the first interrupt vector;
The I / O device driver is
When the occurrence of the first interrupt and the second interrupt is detected, the interrupt vector corresponding to the first interrupt vector is activated with reference to the interrupt vector.
Referring to the mapping information, identifying the first interrupt factor number and the second interrupt factor number associated with the first interrupt vector;
By reading the value of the bit corresponding to each of the first interrupt factor number and the second interrupt factor number from the register, each of the first interrupt factor number and the second interrupt factor number is read. Identify that an interrupt with the corresponding interrupt factor has occurred,
Obtaining the first response command from the I / O queue corresponding to the first interrupt factor number, executing response processing corresponding to the first response command;
A computer that acquires the second response command from an I / O queue corresponding to the second interrupt factor number, and executes a response process corresponding to the second response command.
The computer according to claim 3, wherein
The I / O device driver is
When a third interrupt factor number is associated with the second interrupt vector, an I / O processing execution request corresponding to the third interrupt factor number is received from the operating system;
A third I / O command is inserted into the I / O queue corresponding to the third interrupt factor number;
An instruction to execute a third I / O process including the second interrupt vector and the third interrupt factor number is transmitted to the control unit;
The controller is
When the execution instruction of the third I / O process is received, the I / O process corresponding to the third I / O command is executed,
Insert a third response command into the I / O queue corresponding to the third interrupt factor number,
Generating a third interrupt including the second interrupt vector;
The I / O device driver is
When the occurrence of the third interrupt is detected, an interrupt handler corresponding to the second interrupt vector is activated based on the interrupt vector information,
With reference to the mapping information, the third interrupt factor number associated with the second interrupt vector is specified,
A computer that acquires the third response command from an I / O queue corresponding to the third interrupt factor number and executes response processing corresponding to the third response command.
A method for controlling I / O processing in a computer running at least one operating system, comprising:
The calculator is
At least one processor including a plurality of processor cores, a storage device connected to the at least one processor, and a plurality of I / O device cores, and at least one I / O device connected to the at least one processor Prepared,
An I / O device driver for controlling the at least one I / O device;
Manages interrupt vector information indicating the correspondence between interrupt vectors and interrupt handlers that execute interrupt processing.
The interrupt factor is defined based on a combination of a plurality of interrupt elements,
A plurality of I / O queues are assigned to each of a plurality of interrupt factors,
The I / O device executes a plurality of I / O processes in parallel using the plurality of I / O queues,
The I / O device driver is
Contains multiple interrupt handlers,
Manage interrupt source numbers
Managing mapping information indicating the correspondence between the interrupt vector and the interrupt factor number;
The interrupt factor number is defined based on a bit string composed of one or more bits corresponding to each of the plurality of interrupt elements,
The I / O device is
A control unit that executes I / O processing in response to a request from the I / O device driver;
Holds a bitmap format register that manages the interrupt factor number,
The interrupt factor number and the bit position in the bit map corresponding to the register are managed to correspond to each other,
The control method of the I / O process is as follows:
When the I / O device driver associates the first interrupt factor number and the second interrupt factor number with the first interrupt vector, the I / O device driver responds to the first interrupt factor number from the operating system. A first step of accepting an I / O processing execution request;
A second step in which the I / O device driver inserts a first I / O command into an I / O queue corresponding to the first interrupt factor number;
A third step in which the I / O device driver transmits an instruction to execute a first I / O process including the first interrupt vector and the first interrupt factor number to the control unit;
A fourth step of executing an I / O process corresponding to the first I / O command when the control unit receives an instruction to execute the first I / O process;
A fifth step in which the control unit manipulates a bit corresponding to the first interrupt factor number with reference to the register;
A sixth step in which the control unit inserts a first response command into the I / O queue corresponding to the first interrupt factor number;
A seventh step for causing the control unit to generate a first interrupt including the first interrupt vector;
An eighth step of activating an interrupt handler corresponding to the first interrupt vector based on the interrupt vector information when the I / O device driver detects the occurrence of the first interrupt;
A ninth step in which the I / O device driver refers to the mapping information and identifies the first interrupt factor number and the second interrupt factor number associated with the first interrupt vector;
The I / O device driver reads the value of the bit corresponding to each of the first interrupt factor number and the second interrupt factor number from the register, thereby corresponding to the first interrupt factor number. A tenth step of specifying that an interrupt factor has occurred;
The I / O device driver acquires the first response command from the I / O queue corresponding to the first interrupt factor number, and executes a response process corresponding to the first response command An I / O processing control method comprising: an eleventh step.
The I / O processing control method according to claim 6,
The plurality of interrupt elements are the processor, the I / O device core, the operating system, an interrupt type, and an interrupt priority.
The control method of the I / O process is as follows:
A twelfth step in which the I / O device driver generates the plurality of I / O queues by the number of the plurality of interrupt factors and associates the plurality of interrupt factors with the plurality of I / O queues; ,
A thirteenth step in which the I / O device driver generates the interrupt factor number by setting a value of each of the plurality of interrupt elements in one or more bits corresponding to each of the plurality of interrupt elements. When,
A fourteenth step in which the I / O device driver determines a correspondence relationship between the interrupt vector and the interrupt factor number;
A fifteenth step in which the I / O device driver registers a correspondence relationship between the interrupt vector and the interrupt factor number in the mapping information;
The I / O device driver includes a sixteenth step of transmitting definition information of the interrupt factor number and a method of operating the register to the control unit,
The controller is
Based on the definition information of the interrupt factor number, the interrupt factor number and the bit position in the bit map corresponding to the register are managed to correspond to each other,
A control method of I / O processing, wherein a bitmap corresponding to the register is operated based on an operation method of the register.
The I / O processing control method according to claim 7,
The thirteenth step generates the interrupt factor numbers so that the interrupt factor numbers are serial numbers for the plurality of interrupt factors identifiable by the interrupt element corresponding to the least significant bit of the bit string. Including steps,
In the fourteenth step, when the plurality of interrupt factor numbers are associated with one interrupt vector and registered in the mapping information, the one interrupt factor number is a serial number. A method for controlling an I / O process, comprising a step of associating the plurality of interrupt factor numbers with an interrupt vector.
The I / O processing control method according to claim 8, comprising:
The first step receives an I / O processing execution request corresponding to the first interrupt factor number from the operating system, and then receives an I / O corresponding to the second interrupt factor number from the operating system. Including a step of accepting a process execution request,
In the second step, after the first I / O command is inserted into the I / O queue corresponding to the first interrupt factor number, the I / O queue corresponding to the second interrupt factor number is inserted. Inserting a second I / O command;
The third step includes a second I / O process including the first interrupt vector and the second interrupt factor number after the execution instruction of the first I / O process is transmitted to the control unit. Transmitting the execution instruction to the control unit,
In the fourth step, when an instruction to execute the first I / O process and an instruction to execute the second I / O process are received, the I / O process corresponding to the first I / O command is received. And executing an I / O process corresponding to the second I / O command after executing
The fifth step includes the step of manipulating the bit corresponding to the second interrupt factor number after manipulating the bit corresponding to the first interrupt factor number,
In the sixth step, after the first response command is inserted into the I / O queue corresponding to the first interrupt factor number, the I / O queue corresponding to the second interrupt factor number is inserted. Inserting a second response command;
The seventh step includes generating a second interrupt including the first interrupt vector after generating the first interrupt,
The eighth step includes a step of activating an interrupt handler corresponding to the first interrupt vector with reference to the interrupt vector when the occurrence of the first interrupt and the second interrupt is detected. ,
The ninth step includes the step of referring to the mapping information and identifying the first interrupt factor number and the second interrupt factor number associated with the first interrupt vector,
The tenth step reads the value of the bit corresponding to each of the first interrupt factor number and the second interrupt factor number from the register, whereby the first interrupt factor number and the second interrupt factor number are read out. Including the step of identifying the occurrence of an interrupt factor corresponding to each of the interrupt factor numbers of
The eleventh step includes
Obtaining the first response command from the I / O queue corresponding to the first interrupt factor number, and executing response processing corresponding to the first response command;
Obtaining the second response command from the I / O queue corresponding to the second interrupt factor number, and executing a response process corresponding to the second response command. I / O processing control method.
The I / O processing control method according to claim 8, comprising:
When the third interrupt factor number is associated with the second interrupt vector, the I / O device driver requests the I / O processing execution corresponding to the third interrupt factor number from the operating system. A step of accepting,
The I / O device driver inserting a third I / O command into an I / O queue corresponding to the third interrupt factor number;
The I / O device driver transmitting an instruction to execute a third I / O process including the second interrupt vector and the third interrupt factor number to the control unit;
A step of executing an I / O process corresponding to the third I / O command when the control unit receives an instruction to execute the third I / O process;
The control unit inserting a third response command into an I / O queue corresponding to the third interrupt factor number;
The control unit generating a third interrupt including the second interrupt vector;
When the I / O device driver detects the occurrence of the third interrupt, starting an interrupt handler corresponding to the second interrupt vector based on the interrupt vector information;
The I / O device driver refers to the mapping information and identifies the third interrupt factor number associated with the second interrupt vector;
The I / O device driver acquires the third response command from the I / O queue corresponding to the third interrupt factor number, and executes a response process corresponding to the third response command And a step of controlling the I / O processing.