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WO2015104084A1 - Trench mosfet transistor device and corresponding production method - Google Patents

Trench mosfet transistor device and corresponding production method Download PDF

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Publication number
WO2015104084A1
WO2015104084A1 PCT/EP2014/075092 EP2014075092W WO2015104084A1 WO 2015104084 A1 WO2015104084 A1 WO 2015104084A1 EP 2014075092 W EP2014075092 W EP 2014075092W WO 2015104084 A1 WO2015104084 A1 WO 2015104084A1
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WO
WIPO (PCT)
Prior art keywords
trench
region
substrate
transistor device
mosfet transistor
Prior art date
Application number
PCT/EP2014/075092
Other languages
German (de)
French (fr)
Inventor
Christian Tobias Banzhaf
Original Assignee
Robert Bosch Gmbh
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Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2015104084A1 publication Critical patent/WO2015104084A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Definitions

  • the present invention relates to a trench MOSFET transistor device, a substrate for a trench MOSFET transistor device and a corresponding manufacturing method.
  • Substrates comprising a silicon carbide layer are finding increasing use for standard components.
  • power semiconductors which block voltages of more than 1.2 kV are realized as a trench metal-oxide-semiconductor field-effect transistor (trench MOSFET) using such substrates.
  • trench MOSFET trench metal-oxide-semiconductor field-effect transistor
  • Such power semiconductors find, for example, in electromobile applications, ie
  • Automotive vehicles with batteries such as lithium-ion cell based batteries or in photovoltaic systems use.
  • microelectromechanical systems can be realized with such substrates.
  • a substrate (n-doped 4H-) for example, a substrate (n-doped 4H-
  • SiC substrate whose silicon carbide layer has a hexagonal crystal structure.
  • a trench is patterned perpendicular to the substrate surface in a dry chemical plasma etching process.
  • the ditch is going through
  • FIG. 7 is a schematic cross-sectional view of a trench type MOSFET transistor device known from JP2010-258385 A.
  • reference numeral 1 denotes a silicon carbide substrate, which is a
  • Front V and a back R has.
  • the reverse side R has the substrate 1 which has a basic doping of the n + type, a drain terminal portion 1 a n + -type.
  • the back R is on the drain connection area 1 a a
  • Drain metallization 10 is provided.
  • an epitaxial drift region 1 b includes the n "type in.
  • On the front side V is provided in connection to the drift region 1 b is a p-doped region 1c, which is formed for example by epitaxy or implantation.
  • From the A trench G extends into the interior of the substrate 1 as far as into the drift region 1b in the interior of the trench G.
  • a gate dielectric layer 3 is deposited in the interior of the trench G and a gate metallization 30 is provided on the side of the trench G in the p-doped region 1c is an n + -type source region 5 with a source metallization 20. Will become a
  • FIG. 8 shows a schematic cross-sectional representation of a trench MOSFET transistor device described in DE 10 2013 209 256.3.
  • an additional p + -doped separation region 1d is provided between adjacent trenches G to reduce the stress of the gate dielectric 3 specifically in the lower corners of the trench G, and thus a sufficient blocking capability of the transistor device to ensure.
  • this requires ion implantation with high ion energy in order to achieve a sufficiently deep extension of the p + separation region 1 d into the interior of the substrate 1, preferably to at least the depth extent of the trench G or even more deeper.
  • Such an implantation is very time-consuming, because multiple ionized ions must be used, whereby only a very small implantation current comes about.
  • such an implantation requires very high acceleration voltages, which only a few implantation devices or production environments can provide.
  • such a large collision energy leads to
  • the present invention provides a trench MOSFET transistor device according to claim 1, a substrate for a trench MOSFET transistor device according to claim 6 and a corresponding manufacturing method according to claim 10.
  • Dry etch processes which structure narrow trenches with a high aspect ratio at a lower etching rate than wide trenches with a low
  • the deep implantation for the separation regions which takes place in the narrow trenches according to the invention, can separate adjacent trenches with gate structures in such a way that a field can no longer act on the gate dielectric, since it is about the
  • the body diode can be designed as a pure pn diode.
  • the inventive trench MOSFET transistor device the corresponding substrate for a trench MOSFET transistor device and the corresponding
  • Manufacturing processes make it possible to minimize the cost of further process steps and at the same time greatly increase the quality of the component.
  • a source metallization is provided on the front side of the substrate and the second trench with a
  • the buried doped separation region can advantageously be electrically connected.
  • a buried third doping region of the second conductivity type is provided below the first trench. This allows the short circuit risk to be further reduced.
  • a plurality of spaced-apart second trenches having the second depth extension are arranged from the front side in the first doping region laterally from the source connection region, below which a contiguous buried second doping region of the second conductivity type is arranged with the third depth extension.
  • the substrate is a
  • Silicon carbide substrate Such a substrate is of good short-circuit strength.
  • 1 is a schematic cross-sectional view of a trench MOSFET
  • Fig. 2a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the first embodiment of the present invention in successive stages of manufacture; 3 is a schematic cross-sectional view of a trench MOSFET
  • Fig. 4a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the second embodiment of the present invention in successive stages of manufacture; a schematic cross-sectional view of a trench MOSFET transistor device according to a third embodiment of the present invention;
  • FIG. 6a), b) show schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the third embodiment of the present invention in successive stages of manufacture;
  • FIG. 7 is a schematic cross-sectional view of a trench MOSFET transistor device known from JP2010-258385 A;
  • FIG. 8 shows a schematic cross-sectional representation of a trench MOSFET transistor device described in DE 10 2013 209 256.3.
  • FIG. 1 is a schematic cross-sectional view of a trench MOSFET transistor device according to a first embodiment of the present invention.
  • the first embodiment in contrast to the known trench MOSFET
  • Transistor device shown in FIG. 7 or FIG. 8 a buried, preferably annular, separation region I provided in the substrate 1, which are of the p + -type and has been generated by an ion implantation in the narrow trenches G '.
  • the buried separation region I adjoins that of the front side V of the
  • Substrate 1 outgoing narrow trench G ' which has a smaller depth extension T' than a depth extension T of the trench G for the gate structure is.
  • the separation region I adjoining the underside of the trench G ' in turn, has a depth extent T "which is at least as great as the depth extent T of the trench G (see FIG. 2a), b)).
  • the narrow trench G ' is filled with a metallization region 20a which corresponds to the source metallization 20, whereby the separation region I is set to the same potential as the source region 5.
  • the metallization region 20a for the trench G 'could also be realized with a different metallization which is then in electrical contact with the source metallization 20. Due to the fact that for the production of the separation region I, which is carried out by implantation of the unfilled narrow trench G ', a lower implantation depth and thus a lower implantation energy is necessary, the damage to the crystal structure in the region of the separation region I is much lower than in the prior art and can thus be healed much easier, for example in a corresponding Anneal polish.
  • FIG. 2a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the first embodiment of the present invention in successive stages of manufacture.
  • the silicon carbide substrate 1 is patterned to make the trenches G and G 'in a single anisotropic plasma etching step AE using a mask M, taking advantage of the ARDE effect.
  • the depth extent T of the trench G for the gate structure is low
  • the ratio of the depth extents T '/ T can be adjusted accordingly.
  • the mask M for the plasma etching step is replaced by a mask M 'for the implantation of the separation region I, which in particular protects the gate G for the gate structure.
  • the implantation step IS which is carried out to produce the separation region I, only the region below the trench G 'is implanted and thus the p + -type separation region I is produced, which has the depth extent T "which is at least as great as that Depth extension T of the trench G.
  • the remaining process steps for producing the trench MOSFET transistor device according to FIG. 1 are carried out in a known manner, as known, for example, from JP 2010/258385 A.
  • FIG. 3 shows a schematic cross-sectional view of a trench MOSFET transistor device according to a second embodiment of the present invention.
  • an additional p + -type separation region 11 below the trench G for the second embodiment is provided.
  • Gate structure provided. This additionally reduces field effects at the lower corners of the trench G.
  • the representation according to FIG. 4a) corresponds to the representation according to FIG. 2a). Still referring to Fig. 4b), in the second embodiment, however, the mask M for the plasma etching step after the simultaneous formation of the trenches G, G 'is left on the front side V of the substrate 1, followed by the implantation step IS, simultaneously the separation region I below the narrow trench G 'and the separation region 11 below the trench G for the
  • the further masking step is omitted, which leads to a further simplification of the method.
  • 5 shows a schematic cross-sectional representation of a trench MOSFET
  • Transistor device according to a third embodiment of the present invention.
  • the third embodiment relates to the case in which the p + -doped separation region ⁇ should have a greater width extension.
  • a plurality of adjacent narrow trenches GT, G2 ', G3' are provided, through which the implantation step IE can take place. Due to the lateral extent of the implantation region, a laterally widened contiguous separation region ⁇ thus forms in the periphery of the trench G for the gate structure.
  • the trenches G1 ', G2', G3 ' are filled with corresponding metallization regions 20a', 20a ", 20a '", which correspond to either the source metallization 20 or a separate one
  • Metallization in electrical contact with the source metalization are 20.
  • an additional separation region 11 is provided below the trench G for the gate structure.
  • the third embodiment is the same as the second embodiment.
  • 6a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the third embodiment of the present invention in successive stages of manufacture.
  • Gate structure also in the third embodiment simultaneously with the trenches GT, G2 ', G3' for the implantation of the separation region ⁇ produced.
  • the mask M1 used in this case can, as shown in FIG. 6b), also be used for the ion implantation step IS, in which the contiguous p + -type separation region ⁇ below the trenches GT, G2 ', G3' simultaneously with the additional separation region 11 below the trench G for the gate structure.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention relates to a trench MOSFET transistor device and a corresponding production method. The trench MOSFET transistor device comprises a substrate (1) of a first conduction type (n+) having a front side (V) and a rear side (R); a drain terminal region (1a) of the first conduction type (n+) at the rear side (R) of the substrate (1), a drift region (1b) of the first conduction type (n-) adjacent to the drain terminal region (1a), a first doping region (1c) of the second doping type (p) adjacent to the drift region (1b), and a source terminal region (5) of the first conduction type (n+) at the front side (V) of the substrate (1); a first trench (G) having a first depth extent (T), which is formed proceeding from the front side (V) of the substrate (1) in the source terminal region (5), the first doping region (1c) and the drift region (1b) and in which a gate structure (3, 30) is arranged such that as a result of a voltage being applied, a channel region (K) can be formed between the drift region (1b) and the source terminal region (5) in the first doping region (1c); a second trench (G'; G1', G2', G3') having a second depth extent (T'), which is less than the first depth extent (T), which second trench is arranged proceeding from the front side (V) in the first doping region (1c) laterally with respect to the source terminal region (5); and a second doping region (I; I') of the second conduction type (p+) buried below the second trench (G'; G1', G2', G3') and having a third depth extent (T''), which is at least of the same magnitude as the first depth extent (T).

Description

Beschreibung Titel  Description title
TRENCH-MOSFET-TRANSISTORVORRICHTUNG UND ENTSPRECHENDES HERSTELLUNGSVERFAHREN TRENCH MOSFET TRANSISTOR DEVICE AND CORRESPONDING MANUFACTURING METHOD
Die vorliegende Erfindung betrifft eine Trench-MOSFET-Transistorvorrichtung, ein Substrat für eine Trench-MOSFET-Transistorvorrichtung und ein entsprechendes Herstellungsverfahren. The present invention relates to a trench MOSFET transistor device, a substrate for a trench MOSFET transistor device and a corresponding manufacturing method.
Obwohl auf beliebige Trench-MOSFET-Transistorvorrichtungen anwendbar, werden die vorliegende Erfindung und die ihr zugrundeliegende Problematik anhand von Trench- MOSFET-Transistorvorrichtungen auf Basis von einem Siliziumcarbid-Substrat erläutert. Although applicable to any trench MOSFET transistor device, the present invention and its underlying problem will be explained with reference to trench MOSFET transistor devices based on a silicon carbide substrate.
Stand der Technik Substrate, die eine Siliziumcarbidschicht umfassen, finden zunehmend Verwendung für Standardbauteile. Beispielsweise werden Leistungshalbleiter, die bis Spannungen von mehr als 1 ,2 kV sperren, als Graben-Metall-Oxid-Halbleiter-Feldeffekttransistor (Trench- MOSFET) unter Verwendung von solchen Substraten realisiert. Solche Leistungshalbleiter finden beispielsweise in elektromobilen Anwendungen, alsoBackground Art Substrates comprising a silicon carbide layer are finding increasing use for standard components. By way of example, power semiconductors which block voltages of more than 1.2 kV are realized as a trench metal-oxide-semiconductor field-effect transistor (trench MOSFET) using such substrates. Such power semiconductors find, for example, in electromobile applications, ie
Kraftfahrzeugen mit Batterien, beispielsweise Lithium-Ionen-Zellen basierten Batterien oder in Photovoltaikanlagen Verwendung. Auch mikroelektromechanische Systeme können mit solchen Substraten realisiert werden. Zur Realisierung eines Trench-MOSFET wird beispielsweise ein Substrat (n-dotiertes 4H-Automotive vehicles with batteries, such as lithium-ion cell based batteries or in photovoltaic systems use. Also microelectromechanical systems can be realized with such substrates. For the realization of a trench MOSFET, for example, a substrate (n-doped 4H-
SiC-Substrat) verwendet, dessen Siliziumcarbidschicht eine hexagonale Kristallstruktur aufweist. SiC substrate) whose silicon carbide layer has a hexagonal crystal structure.
In einem derartigen Substrat wird senkrecht zur Substratoberfläche ein Graben in einem trockenchemischen Plasmaätzprozess strukturiert. Der Graben wird durch ein In such a substrate, a trench is patterned perpendicular to the substrate surface in a dry chemical plasma etching process. The ditch is going through
Gatedielektrikum und eine darüberliegende Gatemetallisierungsschicht zumindest teilweise gefüllt. Durch die vertikale Anordnung des Trench-MOSFET-Kanals kann die Packungsdichte von parallel verschalteten Transistoren z.B. im Vergleich mit lateral angeordneten VD-MOSFETs deutlich erhöht werden. Fig. 7 zeigt eine schematische Querschnittsdarstellung einer aus der JP2010-258385 A bekannten Trench-MOSFET-Transistorvorrichtung. Gate dielectric and an overlying gate metallization at least partially filled. The vertical arrangement of the trench MOSFET channel, the packing density of parallel-connected transistors, for example, can be significantly increased compared with laterally disposed VD-MOSFETs. Fig. 7 is a schematic cross-sectional view of a trench type MOSFET transistor device known from JP2010-258385 A.
In Fig. 7 bezeichnet Bezugszeichen 1 ein Siliziumcarbid-Substrat, welches eine In Fig. 7, reference numeral 1 denotes a silicon carbide substrate, which is a
Vorderseite V und eine Rückseite R aufweist. Auf der Rückseite R weist das Substrat 1 , welches eine Grunddotierung vom n+-Typ aufweist, einen Drainanschlussbereich 1 a vom n+-Typ auf. Auf der Rückseite R ist auf dem Drainanschlussbereich 1 a eine Front V and a back R has. On the reverse side R has the substrate 1 which has a basic doping of the n + type, a drain terminal portion 1 a n + -type. On the back R is on the drain connection area 1 a a
Drainmetallisierung 10 vorgesehen. An den Drainanschlussbereich 1 a schließt sich ein epitaktischer Driftbereich 1 b vom n"-Typ an. Auf der Vorderseite V ist im Anschluss an den Driftbereich 1 b ein p-dotierter Bereich 1c vorgesehen, welcher beispielsweise durch Epitaxie oder Implantation gebildet ist. Von der Vorderseite V ausgehend erstreckt sich ein Graben G in das Innere des Substrats 1 bis in den Driftbereich 1 b hinein. Im Inneren des Grabens G abgeschieden ist eine Gatedielektrikumsschicht 3 und darüber eine Gatemetallisierung 30. Seitlich des Grabens G in dem p-dotierten Bereich 1c vorgesehen ist ein Sourcebereich 5 vom n+-Typ mit einer Sourcemetallisierung 20. Wird eine Drain metallization 10 is provided. To the drain region 1 a is an epitaxial drift region 1 b includes the n "type in. On the front side V is provided in connection to the drift region 1 b is a p-doped region 1c, which is formed for example by epitaxy or implantation. From the A trench G extends into the interior of the substrate 1 as far as into the drift region 1b in the interior of the trench G. A gate dielectric layer 3 is deposited in the interior of the trench G and a gate metallization 30 is provided on the side of the trench G in the p-doped region 1c is an n + -type source region 5 with a source metallization 20. Will become a
Spannung an die Gatemetallisierung 30 angelegt, so bildet sich an der Seitenwand des Grabens G ein Kanalbereich K aus. Voltage applied to the gate metallization 30, so formed on the side wall of the trench G, a channel region K from.
Üblicherweise werden Anordnungen mit einer Vielzahl von derartigen benachbarten Trench-MOSFET-Transistorvorrichtungen gebildet, von denen die Figuren jeweils nur eine einzige zeigen. Conventionally, arrangements are formed with a plurality of such adjacent trench MOSFET transistor devices, of which the figures show only a single one at a time.
Bei der Trench-MOSFET-Transistorvorrichtung gemäß Fig. 7 kann der strukturbedingte Übergang von der Seitenwand des Grabens G zum Boden des Grabens G in der In the trench MOSFET transistor device according to FIG. 7, the structural transition from the side wall of the trench G to the bottom of the trench G in FIG
Anwendung zu sehr hohen Feldstärken in diesem Bereich führen, die höher sind als eine Durchbruchschwelle, bei der die Gatedielektrikumsschicht 3 im Sperrfall elektrisch durchbrochen und das Bauelement beschädigt wird. Application lead to very high field strengths in this area, which are higher than a breakthrough threshold, in which the gate dielectric layer 3 is electrically broken in the blocking case and the component is damaged.
Fig. 8 zeigt eine schematische Querschnittsdarstellung einer in der DE 10 2013 209 256.3 beschriebenen Trench-MOSFET-Transistorvorrichtung. Bei der in Fig. 8 gezeigten Trench-MOSFET-Transistorvorrichtung ist ein zusätzlicher p+- dotierter Separationsbereich 1d zwischen benachbarten Gräben G vorgesehen, um die Belastung des Gatedielektrikums 3 speziell in den unteren Ecken des Grabens G zu reduzieren und somit eine ausreichende Sperrfähigkeit der Transistorvorrichtung zu gewährleisten. FIG. 8 shows a schematic cross-sectional representation of a trench MOSFET transistor device described in DE 10 2013 209 256.3. In the trench MOSFET transistor device shown in Fig. 8, an additional p + -doped separation region 1d is provided between adjacent trenches G to reduce the stress of the gate dielectric 3 specifically in the lower corners of the trench G, and thus a sufficient blocking capability of the transistor device to ensure.
Im Fall eines Siliziumcarbid-Substrats 1 muss hierfür eine Ionenimplantation mit großer lonenenergie erfolgen, um eine ausreichend tiefe Erstreckung des p+-Separationsbereichs 1 d ins Innere des Substrats 1 hinein zu erreichen, und zwar vorzugsweise bis mindestens zur Tiefenerstreckung des Grabens G oder sogar noch tiefer. In the case of a silicon carbide substrate 1, this requires ion implantation with high ion energy in order to achieve a sufficiently deep extension of the p + separation region 1 d into the interior of the substrate 1, preferably to at least the depth extent of the trench G or even more deeper.
Solch eine Implantation ist sehr zeitaufwendig, denn mehrfach ionisierte Ionen müssen verwendet werden, wodurch nur ein sehr geringer Implantationsstrom zustande kommt. Zudem erfordert solch eine Implantation sehr große Beschleunigungsspannungen, welche nur wenige Implantationsvorrichtungen bzw. Produktionsumgebungen zur Verfügung stellen können. Des Weiteren führt eine derart große Kollisionsenergie der zu Such an implantation is very time-consuming, because multiple ionized ions must be used, whereby only a very small implantation current comes about. In addition, such an implantation requires very high acceleration voltages, which only a few implantation devices or production environments can provide. Furthermore, such a large collision energy leads to
implantierenden Spezies zu extremen Kristallschäden, welche nur schwer durch implanting species to extreme crystal damage, which is difficult due to
Annealprozesse auszuheilen sind. Offenbarung der Erfindung Anneal processes are to heal. Disclosure of the invention
Die vorliegende Erfindung schafft eine Trench-MOSFET-Transistorvorrichtung nach Anspruch 1 , ein Substrat für eine Trench-MOSFET-Transistorvorrichtung nach Anspruch 6 und ein entsprechendes Herstellungsverfahren nach Anspruch 10. The present invention provides a trench MOSFET transistor device according to claim 1, a substrate for a trench MOSFET transistor device according to claim 6 and a corresponding manufacturing method according to claim 10.
Bevorzugte Weiterbildungen sind Gegenstand der jeweiligen Unteransprüche. Vorteile der Erfindung Die der vorliegenden Erfindung zugrunde liegende Idee besteht darin, in einem einzelnen trockenchemischen Plasmaätzschritt breitere, tiefere Gräben für die Gatestrukturen und schmalere, flachere Gräben zur Tiefenimplantation der Separationsbereiche anzulegen. Mit anderen Worten ist für die simultane Strukturierung aller Gräben nur ein einziger Plasmaätzschritt erforderlich. Der für die Strukturierung der Gräben verwendete Plasmaätzschritt bedient sich des ARDE-Effekts (Aspect Ratio Dependent Etching) bzw. des RIE-Lags in Preferred developments are the subject of the respective subclaims. Advantages of the Invention The idea underlying the present invention is to create wider, deeper trenches for the gate structures and narrower, shallower trenches for depth implantation of the separation areas in a single dry chemical plasma etching step. In other words, only a single plasma etching step is required for the simultaneous structuring of all trenches. The plasma etching step used to structure the trenches uses the ARDE effect (Aspect Ratio Dependent Etching) or the RIE lag in
Trockenätzprozessen, wodurch schmale Gräben mit hohem Aspektverhältnis mit einer geringeren Ätzrate strukturiert werden als breite Gräben mit einem niedrigen Dry etch processes, which structure narrow trenches with a high aspect ratio at a lower etching rate than wide trenches with a low
Aspektverhältnis. Bedingt ist dies durch die geringere Dichte an Radikalen und Ionen in schmalen Gräben. Bei einer bevorzugten Weiterbildung kann die nach dem Aspect ratio. This is due to the lower density of radicals and ions in narrow trenches. In a preferred embodiment, the after the
Plasmaätzschritt verbleibende (teilweise verbrauchte) Maskierungsschicht beim Plasma etching step remaining (partially spent) masking layer in
Durchführen der anschließenden Tiefenimplantation für die Separationsgebiete als Implantationsmaske für alle angelegten Gräben gleichzeitig verwendet werden. Performing the subsequent deep implantation for the separation areas as an implantation mask for all created trenches used simultaneously.
Die in die erfindungsgemäßen schmalen Gräben erfolgte Tiefenimplantation für die Separationsgebiete kann benachbarte Gräben mit Gatestrukturen derart separieren, dass ein Feld nicht mehr an das Gatedielektrikum angreifen kann, da es um das The deep implantation for the separation regions, which takes place in the narrow trenches according to the invention, can separate adjacent trenches with gate structures in such a way that a field can no longer act on the gate dielectric, since it is about the
Gatedielektrikum herumgeleitet wird. Zudem kann die Bodydiode als reine pn-Diode ausgeführt werden. Gatedielektrikum is passed around. In addition, the body diode can be designed as a pure pn diode.
Die erfindungsgemäße Trench-MOSFET-Transistorvorrichtung, das entsprechende Substrat für eine Trench-MOSFET-Transistorvorrichtung und das entsprechende The inventive trench MOSFET transistor device, the corresponding substrate for a trench MOSFET transistor device and the corresponding
Herstellungsverfahren erlauben es, den Aufwand für weitere Prozessschritte gering zu halten und gleichzeitig die Qualität des Bauelements stark zu erhöhen. Manufacturing processes make it possible to minimize the cost of further process steps and at the same time greatly increase the quality of the component.
Gemäß einer bevorzugten Ausführungsform ist auf der Vorderseite des Substrats eine Sourcemetallisierung vorgesehen ist und der zweite Graben mit einem According to a preferred embodiment, a source metallization is provided on the front side of the substrate and the second trench with a
Metallisierungsbereich gefüllt, der in elektrischem Kontakt mit der Sourcemetallisierung steht. So läßt sich der vergrabene dotierte Separationsbereich vorteilhaft elektrisch anschließen. Metallization area filled, which is in electrical contact with the source metallization. Thus, the buried doped separation region can advantageously be electrically connected.
Gemäß einer weiteren bevorzugten Ausführungsform ist unterhalb des ersten Grabens ein vergrabener dritter Dotierungsbereich des zweiten Leitungstyps vorgesehen. So läßt sich das Kurzschlussrisiko weiter reduzieren. According to a further preferred embodiment, a buried third doping region of the second conductivity type is provided below the first trench. This allows the short circuit risk to be further reduced.
Gemäß einer weiteren bevorzugten Ausführungsform sind mehrere beabstandete zweite Gräben mit der zweiten Tiefenerstreckung ausgehend von der Vorderseite in dem ersten Dotierungsbereich seitlich vom Sourceanschlussbereich angeordnet, unter denen ein zusammenhängender vergrabener zweiter Dotierungsbereich des zweiten Leitungstyps mit der dritten Tiefenerstreckung angeordnet ist. So läßt sich ein breiter Separationsbereich bilden. According to a further preferred embodiment, a plurality of spaced-apart second trenches having the second depth extension are arranged from the front side in the first doping region laterally from the source connection region, below which a contiguous buried second doping region of the second conductivity type is arranged with the third depth extension. Thus, a wide separation range can be formed.
Gemäß einer weiteren bevorzugten Ausführungsform ist das Substrat ein According to a further preferred embodiment, the substrate is a
Siliziumcarbidsubstrat. Ein derartiges Substrat ist von guter Kurzschlussfestigkeit. Silicon carbide substrate. Such a substrate is of good short-circuit strength.
Kurze Beschreibung der Zeichnungen Brief description of the drawings
Die vorliegende Erfindung wird nachfolgend anhand der in den schematischen Figuren der Zeichnungen angegebenen Ausführungsbeispiele näher erläutert. Es zeigen The present invention will be explained in more detail with reference to the exemplary embodiments indicated in the schematic figures of the drawings. Show it
Fig. 1 eine schematische Querschnittsdarstellung einer Trench-MOSFET-1 is a schematic cross-sectional view of a trench MOSFET
Transistorvorrichtung gemäß einer ersten Ausführungsform der vorliegenden Erfindung; Transistor device according to a first embodiment of the present invention;
Fig. 2a), b) schematische Querschnittsdarstellungen eines Substrats für eine Trench- MOSFET-Transistorvorrichtung gemäß der ersten Ausführungsform der vorliegenden Erfindung in aufeinanderfolgenden Herstellungsstadien; Fig. 3 eine schematische Querschnittsdarstellung einer Trench-MOSFET-Fig. 2a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the first embodiment of the present invention in successive stages of manufacture; 3 is a schematic cross-sectional view of a trench MOSFET
Transistorvorrichtung gemäß einer zweiten Ausführungsform der vorliegenden Erfindung; Transistor device according to a second embodiment of the present invention;
Fig. 4a), b) schematische Querschnittsdarstellungen eines Substrats für eine Trench- MOSFET-Transistorvorrichtung gemäß der zweiten Ausführungsform der vorliegenden Erfindung in aufeinanderfolgenden Herstellungsstadien; eine schematische Querschnittsdarstellung einer Trench-MOSFET- Transistorvorrichtung gemäß einer dritten Ausführungsform der vorliegend Erfindung; Fig. 4a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the second embodiment of the present invention in successive stages of manufacture; a schematic cross-sectional view of a trench MOSFET transistor device according to a third embodiment of the present invention;
Fig. 6a), b) schematische Querschnittsdarstellungen eines Substrats für eine Trench- MOSFET-Transistorvorrichtung gemäß der dritten Ausführungsform der vorliegenden Erfindung in aufeinanderfolgenden Herstellungsstadien; Fig. 7 eine schematische Querschnittsdarstellung einer aus der JP2010-258385 A bekannten Trench-MOSFET-Transistorvorrichtung; und 6a), b) show schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the third embodiment of the present invention in successive stages of manufacture; Fig. 7 is a schematic cross-sectional view of a trench MOSFET transistor device known from JP2010-258385 A; and
Fig. 8 eine schematische Querschnittsdarstellung einer in der DE 10 2013 209 256.3 beschriebenen Trench-MOSFET-Transistorvorrichtung. 8 shows a schematic cross-sectional representation of a trench MOSFET transistor device described in DE 10 2013 209 256.3.
Ausführungsformen der Erfindung Embodiments of the invention
In den Figuren bezeichnen gleiche Bezugszeichen gleiche bzw. funktionsgleiche In the figures, like reference numerals designate the same or functionally identical
Elemente. Elements.
Fig. 1 zeigt eine schematische Querschnittsdarstellung einer Trench-MOSFET- Transistorvorrichtung gemäß einer ersten Ausführungsform der vorliegenden Erfindung. Bei der ersten Ausführungsform ist im Unterschied zur bekannten Trench-MOSFET-1 is a schematic cross-sectional view of a trench MOSFET transistor device according to a first embodiment of the present invention. In the first embodiment, in contrast to the known trench MOSFET
Transistorvorrichtung nach Fig. 7 bzw. Fig. 8 ein vergrabener, vorzugsweise ringförmiger, Separationsbereich I im Substrat 1 vorgesehen, welcher vom p+-Typ sind und durch eine Ionenimplantation in die schmalen Gräben G' erzeugt worden ist. Der vergrabene Separationsbereich I schließt sich an den von der Vorderseite V desTransistor device shown in FIG. 7 or FIG. 8, a buried, preferably annular, separation region I provided in the substrate 1, which are of the p + -type and has been generated by an ion implantation in the narrow trenches G '. The buried separation region I adjoins that of the front side V of the
Substrats 1 ausgehenden schmalen Graben G' an, der eine geringere Tiefenerstreckung T' aufweist als eine Tiefenerstreckung T des Grabens G für die Gatestruktur ist. Der sich an die Unterseite des Grabens G' angrenzende Separationsbereich I seinerseits weist eine Tiefenerstreckung T" auf, welche mindestens so groß ist wie die Tiefenerstreckung T des Grabens G (vgl. Fig. 2a), b)). Substrate 1 outgoing narrow trench G ', which has a smaller depth extension T' than a depth extension T of the trench G for the gate structure is. The separation region I adjoining the underside of the trench G ', in turn, has a depth extent T "which is at least as great as the depth extent T of the trench G (see FIG. 2a), b)).
Verfüllt ist der schmale Graben G' mit einem Metallisierungsbereich 20a, welche der Sourcemetallisierung 20 entspricht, wodurch der Separationsbereich I auf das gleiche Potenzial wie der Sourcebereich 5 gelegt ist. The narrow trench G 'is filled with a metallization region 20a which corresponds to the source metallization 20, whereby the separation region I is set to the same potential as the source region 5.
Alternativ dazu könnte der Metallisierungsbereich 20a für den Graben G' auch mit einer anderen Metallisierung realisiert werden, welche dann in elektrischem Kontakt mit der Sourcemetallisierung 20 steht. Aufgrund der Tatsache, dass zur Herstellung des Separationsbereichs I, welcher durch Implantation der ungefüllten schmalen Graben G' erfolgt, eine geringere Implantationstiefe und hiermit eine geringere Implantationsenergie notwendig ist, ist die Schädigung der Kristallstruktur im Bereich des Separationsbereichs I wesentlich geringer als beim Stand der Technik und kann somit wesentlich einfacher ausgeheilt werden, beispielsweise in einem entsprechenden Annealprozess. Alternatively, the metallization region 20a for the trench G 'could also be realized with a different metallization which is then in electrical contact with the source metallization 20. Due to the fact that for the production of the separation region I, which is carried out by implantation of the unfilled narrow trench G ', a lower implantation depth and thus a lower implantation energy is necessary, the damage to the crystal structure in the region of the separation region I is much lower than in the prior art and can thus be healed much easier, for example in a corresponding Annealprozess.
Fig. 2a), b) sind schematische Querschnittsdarstellungen eines Substrats für eine Trench- MOSFET-Transistorvorrichtung gemäß der ersten Ausführungsform der vorliegenden Erfindung in aufeinanderfolgenden Herstellungsstadien. Mit Bezug auf Fig. 2a) erfolgt die Strukturierung des Substrats 1 aus Siliziumcarbid zur Herstellung der Gräben G und G' in einem einzelnen anisotropen Plasmaätzschritt AE unter Verwendung einer Maske M, wobei der ARDE-Effekt ausgenutzt wird. Demzufolge ist die Tiefenerstreckung T des Grabens G für die Gatestruktur mit geringem 2a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the first embodiment of the present invention in successive stages of manufacture. With reference to Fig. 2a), the silicon carbide substrate 1 is patterned to make the trenches G and G 'in a single anisotropic plasma etching step AE using a mask M, taking advantage of the ARDE effect. As a result, the depth extent T of the trench G for the gate structure is low
Aspektverhältnis größer als die Tiefenerstreckung T' des schmalen Grabens G' für die Tiefenimplantation mit höherem Aspektverhältnis, also vorliegend geringerer Breite. Aspect ratio greater than the depth extension T 'of the narrow trench G' for the depth implantation with a higher aspect ratio, in the present case smaller width.
Durch geeignete Wahl der Prozessparameter des Plasmaätzprozesses lässt sich das Verhältnis der Tiefenerstreckungen T'/T entsprechend einstellen. Weiter mit Bezug auf Fig. 2b) wird bei der ersten Ausführungsform die Maske M für den Plasmaätzschritt durch eine Maske M' für die Implantation des Separationsbereichs I ersetzt, welche insbesondere den Graben G für die Gatestruktur schützt. By suitable choice of the process parameters of the plasma etching process, the ratio of the depth extents T '/ T can be adjusted accordingly. With further reference to FIG. 2b), in the first embodiment, the mask M for the plasma etching step is replaced by a mask M 'for the implantation of the separation region I, which in particular protects the gate G for the gate structure.
Bei dem Implantationsschritt IS, welcher zur Herstellung des Separationsbereichs I erfolgt, wird demzufolge nur der Bereich unterhalb des Grabens G' implantiert und somit der Separationsbereich I vom p+-Typ erzeugt, welcher die Tiefenerstreckung T" aufweist, die mindestens so groß ist wie die Tiefenerstreckung T des Grabens G. Accordingly, in the implantation step IS, which is carried out to produce the separation region I, only the region below the trench G 'is implanted and thus the p + -type separation region I is produced, which has the depth extent T "which is at least as great as that Depth extension T of the trench G.
Die übrigen Prozessschritte zur Herstellung der Trench-MOSFET-Transistorvorrichtung gemäß Fig. 1 erfolgen in bekannter Weise, wie beispielsweise aus der JP 2010/258385 A bekannt. The remaining process steps for producing the trench MOSFET transistor device according to FIG. 1 are carried out in a known manner, as known, for example, from JP 2010/258385 A.
Fig. 3 zeigt eine schematische Querschnittsdarstellung einer Trench-MOSFET- Transistorvorrichtung gemäß einer zweiten Ausführungsform der vorliegenden Erfindung. Bei der zweiten Ausführungsform ist im Vergleich zur ersten Ausführungsform ein zusätzlicher Separationsbereich 11 vom p+-Typ unterhalb des Grabens G für die 3 shows a schematic cross-sectional view of a trench MOSFET transistor device according to a second embodiment of the present invention. In the second embodiment, as compared with the first embodiment, an additional p + -type separation region 11 below the trench G for the
Gatestruktur vorgesehen. Dies vermindert zusätzlich Feldeffekte an den unteren Ecken des Grabens G. Gate structure provided. This additionally reduces field effects at the lower corners of the trench G.
Ansonsten ist die zweite Ausführungsform gleich der oben beschriebenen ersten Otherwise, the second embodiment is the same as the first one described above
Ausführungsform. Embodiment.
Fig. 4a), b) sind schematische Querschnittsdarstellungen eines Substrats für eine Trench- MOSFET-Transistorvorrichtung gemäß der zweiten Ausführungsform der vorliegenden Erfindung in aufeinanderfolgenden Herstellungsstadien. 4a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the second embodiment of the present invention in successive stages of manufacture.
Die Darstellung gemäß Fig. 4a) entspricht der Darstellung gemäß Fig. 2a). Weiter mit Bezug auf Fig. 4b) wird bei der zweiten Ausführungsform jedoch die Maske M für den Plasmaätzschritt nach der simultanen Herstellung der Gräben G, G' auf der Vorderseite V des Substrats 1 belassen, woran anschließend der Implantationsschritt IS durchgeführt wird, durch den simultan der Separationsbereich I unterhalb des schmalen Grabens G' sowie der Separationsbereich 11 unterhalb des Grabens G für die The representation according to FIG. 4a) corresponds to the representation according to FIG. 2a). Still referring to Fig. 4b), in the second embodiment, however, the mask M for the plasma etching step after the simultaneous formation of the trenches G, G 'is left on the front side V of the substrate 1, followed by the implantation step IS, simultaneously the separation region I below the narrow trench G 'and the separation region 11 below the trench G for the
Gatestruktur erzeugt werden. Gate structure are generated.
Somit entfällt bei der zweiten Ausführungsform der weitere Maskierungsschritt, was zu einer weiteren Vereinfachung des Verfahrens führt. Fig. 5 zeigt eine schematische Querschnittsdarstellung einer Trench-MOSFET-Thus, in the second embodiment, the further masking step is omitted, which leads to a further simplification of the method. 5 shows a schematic cross-sectional representation of a trench MOSFET
Transistorvorrichtung gemäß einer dritten Ausführungsform der vorliegenden Erfindung. Transistor device according to a third embodiment of the present invention.
Die dritte Ausführungsform betrifft den Fall, in dem der p+-dotierte Separationsbereich Γ eine größere Breitenerstreckung aufweisen soll. The third embodiment relates to the case in which the p + -doped separation region Γ should have a greater width extension.
In diesem Fall werden mehrere benachbarte schmale Gräben GT, G2', G3' vorgesehen, durch die der Implantationsschritt IE erfolgen kann. Aufgrund der lateralen Ausdehnung des Implantationsbereichs bildet sich somit ein lateral verbreiterter zusammenhängender Separationsbereich Γ in der Peripherie des Grabens G für die Gatestruktur. Die Gräben G1 ', G2', G3' sind mit entsprechenden Metallisierungsbereichen 20a', 20a", 20a'" verfüllt, welche entweder der Sourcemetallisierung 20 entsprechen oder eine separate In this case, a plurality of adjacent narrow trenches GT, G2 ', G3' are provided, through which the implantation step IE can take place. Due to the lateral extent of the implantation region, a laterally widened contiguous separation region Γ thus forms in the periphery of the trench G for the gate structure. The trenches G1 ', G2', G3 'are filled with corresponding metallization regions 20a', 20a ", 20a '", which correspond to either the source metallization 20 or a separate one
Metallisierung in elektrischem Kontakt mit der Sourcemetallisierung 20 sind. Metallization in electrical contact with the source metalization are 20.
Auch bei der dritten Ausführungsform ist unterhalb des Grabens G für die Gatestruktur ein zusätzlicher Separationsbereich 11 vorgesehen. Also in the third embodiment, an additional separation region 11 is provided below the trench G for the gate structure.
Ansonsten ist die dritte Ausführungsform gleich wie die zweite Ausführungsform aufgebaut. Fig. 6a), b) sind schematische Querschnittsdarstellungen eines Substrats für eine Trench- MOSFET-Transistorvorrichtung gemäß der dritten Ausführungsform der vorliegenden Erfindung in aufeinanderfolgenden Herstellungsstadien. Otherwise, the third embodiment is the same as the second embodiment. 6a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the third embodiment of the present invention in successive stages of manufacture.
Wie in Fig. 6a) dargestellt, wird beim Plasmaätzschritt AE der Graben G für die As shown in FIG. 6a), in the plasma etching step AE, the trench G for the
Gatestruktur auch bei der dritten Ausführungsform simultan mit den Gräben GT, G2', G3' für die Implantation des Separationsbereichs Γ hergestellt. Die dabei verwendete Maske M1 kann, wie in Fig. 6b) gezeigt, auch für den lonenimplantationsschritt IS verwendet werden, in dem der zusammenhängende breite Separationsbereich Γ vom p+-Typ unterhalb der Gräben GT, G2', G3' simultan mit dem zusätzlichen Separationsbereich 11 unterhalb des Grabens G für die Gatestruktur hergestellt wird. Gate structure also in the third embodiment simultaneously with the trenches GT, G2 ', G3' for the implantation of the separation region Γ produced. The mask M1 used in this case can, as shown in FIG. 6b), also be used for the ion implantation step IS, in which the contiguous p + -type separation region Γ below the trenches GT, G2 ', G3' simultaneously with the additional separation region 11 below the trench G for the gate structure.
Die sich an Fig. 6b) anschließenden Prozessschritte zur Fertigstellung der Trench- MOSFET-Transistorvorrichtung gemäß Fig. 5 erfolgen in an sich bekannter Weise nach Entfernen der Maske M 1 für den Plasmaätzschritt AE und dem Implantationsschritt IS. The process steps subsequent to FIG. 6b) for the completion of the trench MOSFET transistor device according to FIG. 5 are carried out in a manner known per se after removal of the mask M 1 for the plasma etching step AE and the implantation step IS.
Obwohl die vorliegende Erfindung anhand bevorzugter Ausführungsbeispiele vorstehend vollständig beschrieben wurde, ist sie darauf nicht beschränkt, sondern auf vielfältige Art und Weise modifizierbar. Inbesondere sind die verwendeten Materialien und Topologien nur beispielshaft. Although the present invention has been fully described above with reference to preferred embodiments, it is not limited thereto but is modifiable in a variety of ways. In particular, the materials and topologies used are exemplary only.

Claims

Ansprüche  claims
Patentansprüche 1. Trench-MOSFET-Transistorvorrichtung mit: einem Substrat (1) eines ersten Leitungstyps (n+) mit einer Vorderseite (V) und einer Rückseite (R); einem Drainanschlussbereich (1 a) des ersten Leitungstyps (n+) an der Rückseite (R) des Substrats (1), einem sich an den Drainanschlussbereich (1a) anschließenden Driftbereich (1 b) des ersten Leitungstyps (n"), einem sich an den Driftbereich (1 b) anschließenden ersten Dotierungsbereich (1 c) des zweiten Leitungstyps (p) und einem Claims 1. A trench MOSFET transistor device comprising: a substrate (1) of a first conductivity type (n + ) having a front side (V) and a back side (R); a drain connection region (1 a) of the first conductivity type (n + ) at the rear side (R) of the substrate (1) adjoining the drain connection region (1a) drift region (1 b) of the first conductivity type (n " ) the drift region (1 b) subsequent first doping region (1 c) of the second conductivity type (p) and a
Sourceanschlussbereich (5) des ersten Leitungstyps (n+) an der Vorderseite (V) des Substrats (1); einem ersten Graben (G) mit einer ersten Tiefenerstreckung (T), der ausgehend von der Vorderseite (V) des Substrats (1) in dem Sourceanschlussbereich (5), dem ersten Dotierungsbereich (1 c) und dem Driftbereich (1 b) gebildet ist und in dem eine Source terminal region (5) of the first conductivity type (n +) at the front side (V) of the substrate (1); a first trench (G) having a first depth extent (T) formed from the front side (V) of the substrate (1) in the source terminal region (5), the first doping region (1c) and the drift region (1b) and in the one
Gatestruktur (3, 30) so angeordnet sind, dass durch Anlegen einer Spannung ein Gate structure (3, 30) are arranged so that by applying a voltage
Kanalbereich (K) zwischen dem Driftbereich (1 b) und dem Sourceanschlussbereich (5) in dem ersten Dotierungsbereich (1c) bildbar ist; einem zweiten Graben (G'; G1\ G2', G3') mit einer zweiten Tiefenerstreckung (T), welche geringer als die erste Tiefenerstreckung (T) ist, welcher ausgehend von der Vorderseite Channel region (K) between the drift region (1 b) and the source terminal region (5) in the first doping region (1 c) can be formed; a second trench (G '; G1 \ G2', G3 ') having a second depth extent (T) which is less than the first depth extent (T) which extends from the front side
(V) in dem ersten Dotierungsbereich (1 c) seitlich vom Sourceanschlussbereich (5) angeordnet ist; und einem unterhalb des zweiten Grabens (G'; G1', G2', G3') vergrabenen zweiten (V) in the first doping region (1 c) is arranged laterally from the source connection region (5); and a second buried below the second trench (G ', G1', G2 ', G3')
Dotierungsbereich (I; Γ) des zweiten Leitungstyps (p+) mit einer dritten TiefenerstreckungDoping region (I; Γ) of the second conductivity type (p + ) with a third depth extension
(T"), welche mindestens so groß wie die erste Tiefenerstreckung (T) ist. (T "), which is at least as large as the first depth extension (T).
2. Trench-MOSFET-Transistorvorrichtung nach Anspruch 1 , wobei auf der Vorderseite (V) des Substrats (1) eine Sourcemetallisierung (20) vorgesehen ist und der zweite Graben (G'; G1 ', G2', G3') mit einem Metallisierungsbereich (20a; 20a', 20a"; 20a'") gefüllt ist, der in elektrischem Kontakt mit der Sourcemetallisierung (20) steht. 2. Trench MOSFET transistor device according to claim 1, wherein on the front side (V) of the substrate (1) a source metallization (20) is provided and the second trench (G ';G1', G2 ', G3') with a metallization region (20a; 20a ', 20a ";20a'") which is in electrical contact with the source metallization (20).
3. Trench-MOSFET-Transistorvorrichtung nach Anspruch 1 oder 2, wobei unterhalb des ersten Grabens (G) ein vergrabener dritter Dotierungsbereich (11 ) des zweiten 3. trench MOSFET transistor device according to claim 1 or 2, wherein below the first trench (G) a buried third doping region (11) of the second
Leitungstyps (p+) vorgesehen ist. Line type (p +) is provided.
4. Trench-MOSFET-Transistorvorrichtung nach Anspruch 1 oder 2, wobei mehrere beabstandete zweite Gräben (G1 '; G2'; G3') mit der zweiten Tiefenerstreckung (T) ausgehend von der Vorderseite (V) in dem ersten Dotierungsbereich (1c) seitlich vom Sourceanschlussbereich (5) angeordnet sind, unter denen ein zusammenhängender vergrabener zweiter Dotierungsbereich (I; Γ) des zweiten Leitungstyps (p+) mit der dritten Tiefenerstreckung (T')angeordnet ist. 4. Trench MOSFET transistor device according to claim 1 or 2, wherein a plurality of spaced second trenches (G1 '; G2'; G3 ') with the second depth extension (T) from the front side (V) in the first doping region (1c) laterally from the source terminal region (5) are arranged, under which a contiguous buried second doping region (I; Γ) of the second conductivity type (p +) with the third depth extension (T ') is arranged.
5. Trench-MOSFET-Transistorvorrichtung nach einem der vorhergehenden Ansprüche, wobei das Substrat (1) ein Siliziumcarbidsubstrat ist. 5. Trench MOSFET transistor device according to one of the preceding claims, wherein the substrate (1) is a silicon carbide substrate.
6. Substrat für eine Trench-MOSFET-Transistorvorrichtung mit: einer Vorderseite (V) und einer Rückseite (R); einem ersten Graben (G) mit einer ersten Tiefenerstreckung (T), der ausgehend von der Vorderseite (V) des Substrats (1) gebildet ist; einem zweiten Graben (G'; G1', G2', G3') mit einer zweiten Tiefenerstreckung (T), welche geringer als die erste Tiefenerstreckung (T) ist, welcher ausgehend von der Vorderseite (V) seitlich des ersten Grabens (G) gebildet ist; und einem unterhalb des zweiten Grabens (G'; G1 ', G2', G3') vergrabenen Dotierungsbereich (I; Γ) des zweiten Leitungstyps (p+) mit einer dritten Tiefenerstreckung (T"), welche mindestens so groß wie die erste Tiefenerstreckung (T) ist. 6. A substrate for a trench MOSFET transistor device, comprising: a front side (V) and a back side (R); a first trench (G) having a first depth extent (T) formed from the front side (V) of the substrate (1); a second trench (G '; G1', G2 ', G3') having a second depth extent (T) which is less than the first depth extent (T) which extends from the front face (V) laterally of the first trench (G) is formed; and a doping region (I; Γ) of the second conductivity type (p +) buried below the second trench (G '; G1', G2 ', G3') having a third depth extent (T ") which is at least as great as the first depth extent ( T) is.
7. Substrat für eine Trench-MOSFET-Transistorvorrichtung nach Anspruch 6, wobei unterhalb des ersten Grabens (G) ein vergrabener weiterer Dotierungsbereich (11) des zweiten Leitungstyps (p+) vorgesehen ist. 7. The substrate for a trench MOSFET transistor device according to claim 6, wherein below the first trench (G) a buried further doping region (11) of the second conductivity type (p +) is provided.
8. Substrat für eine Trench-MOSFET-Transistorvorrichtung nach Anspruch 6 oder 7, wobei mehrere beabstandete zweite Gräben (G1 '; G2'; G3') mit der zweiten Tiefenerstreckung (T) ausgehend von der Vorderseite (V) in dem ersten Dotierungsbereich (1c) seitlich vom ersten Graben (G) angeordnet sind, unter denen ein zusammenhängender vergrabener zweiter Dotierungsbereich (I; Γ) des zweiten A substrate for a trench MOSFET transistor device according to claim 6 or 7, wherein a plurality of spaced apart second trenches (G1 ';G2'; G3 ') are connected to the second Depth extension (T) are arranged starting from the front side (V) in the first doping region (1c) laterally from the first trench (G), under which a contiguous buried second doping region (I; Γ) of the second
Leitungstyps (p+) mit der dritten Tiefenerstreckung (T')angeordnet ist. Conduction type (P +) with the third depth extension (T ') is arranged.
9. Substrat für eine Trench-MOSFET-Transistorvorrichtung nach einem der Ansprüche 6 bis 8, wobei das Substrat (1) ein Siliziumcarbidsubstrat ist. The substrate for a trench MOSFET transistor device according to any one of claims 6 to 8, wherein the substrate (1) is a silicon carbide substrate.
10. Herstellungsverfahren für eine Trench-MOSFET-Transistorvorrichtung mit den Schritten: 10. A method of manufacturing a trench MOSFET transistor device comprising the steps of:
Bereitstellen von einem Substrat (1) eines ersten Leitungstyps (n+) mit einer Vorderseite (V) und einer Rückseite (R); Bilden von einem Drainanschlussbereich (1a) des ersten Leitungstyps (n+) an der Rückseite (R) des Substrats (1), einem sich an den Drainanschlussbereich (1 a) anschließenden Driftbereich (1 b) des ersten Leitungstyps (n"), einem sich an den Driftbereich (1 b) anschließenden ersten Dotierungsbereich (1 c) des zweiten Leitungstyps (p) und einem Sourceanschlussbereich (5) des ersten Leitungstyps (n+) an der Providing a substrate (1) of a first conductivity type (n + ) having a front side (V) and a back side (R); Forming a drain connection region (1a) of the first conductivity type (n +) at the rear side (R) of the substrate (1), a drift region (1b) of the first conductivity type (n " ) adjoining the drain connection region (1a) to the drift region (1 b) subsequent first doping region (1 c) of the second conductivity type (p) and a source connection region (5) of the first conductivity type (n +) at the
Vorderseite (V) des Substrats (1); Front side (V) of the substrate (1);
Ätzen von einem ersten Graben (G) mit einer ersten Tiefenerstreckung (T) in einem Ätzschritt (AE), der ausgehend von der Vorderseite (V) des Substrats (1) in dem Etching a first trench (G) with a first depth extension (T) in an etching step (AE) starting from the front side (V) of the substrate (1) in the
Sourceanschlussbereich (5), dem ersten Dotierungsbereich (1 c) und dem Driftbereich (1 b) gebildet ist; gleichzeitiges Ätzen von einem zweiten Graben (G'; G1', G2', G3') in dem mit einer zweiten Tiefenerstreckung (T), welche geringer als die erste Tiefenerstreckung (T) ist, welcher ausgehend von der Vorderseite (V) in dem ersten Dotierungsbereich (1 c) seitlich vom Sourceanschlussbereich (5) angeordnet ist; und Source terminal region (5), the first doping region (1 c) and the drift region (1 b) is formed; simultaneously etching a second trench (G ', G1', G2 ', G3') in the second trench (T) which is smaller than the first trench (T), starting from the front (V) in the second trench first doping region (1 c) is arranged laterally from the source connection region (5); and
Bilden von einem unterhalb des zweiten Grabens (G'; G1\ G2', G3') vergrabenen zweiten Dotierungsbereich (I; Γ) des zweiten Leitungstyps (p+) mit einer dritten Tiefenerstreckung (T"), welche mindestens so groß wie die erste Tiefenerstreckung (T) ist, in einem durch den zweiten Graben (G'; G1', G2', G3') hindurch ausgeführten lonenimplantationsschritt (IS); wobei in dem ersten Graben (G) eine Gatestruktur (3, 30) so angeordnet wird, dass durch Anlegen einer Spannung ein Kanalbereich (K) zwischen dem Driftbereich (1 b) und dem Sourceanschlussbereich (5) in dem ersten Dotierungsbereich (1 c) bildbar ist. Forming a second doping region (I; Γ) of the second conductivity type (p +) buried below the second trench (G '; G1 \ G2', G3 ') with a third depth extension (T ") at least as great as the first depth extension (T) is, in an ion implantation step (IS) performed through the second trench (G ';G1', G2 ', G3'); wherein in the first trench (G) a gate structure (3, 30) is arranged so that by applying a voltage a channel region (K) between the drift region (1 b) and the source connection region (5) in the first doping region (1 c) is picturable.
1 1. Herstellungsverfahren für eine Trench-MOSFET-Transistorvorrichtung nach Anspruch 10, wobei auf der Vorderseite (V) des Substrats (1) eine Sourcemetallisierung (20) vorgesehen wird und der zweite Graben (G'; G1', G2', G3') mit einem A manufacturing method for a trench MOSFET transistor device according to claim 10, wherein a source metallization (20) is provided on the front side (V) of the substrate (1) and the second trench (G '; G1', G2 ', G3' ) with a
Metallisierungsbereich (20a; 20a', 20a"; 20a'") gefüllt wird, der in elektrischem Kontakt mit der Sourcemetallisierung (20) steht. Metallization region (20a, 20a ', 20a "; 20a'") is in electrical contact with the source metallization (20).
12. Herstellungsverfahren für eine Trench-MOSFET-Transistorvorrichtung nach Anspruch 10 oder 11 , wobei unterhalb des ersten Grabens (G) ein vergrabener dritter 12. A manufacturing method of a trench MOSFET transistor device according to claim 10 or 11, wherein below the first trench (G) is a buried third
Dotierungsbereich (11) des zweiten Leitungstyps (p+) in dem parallel durch den ersten Graben (G) hindurch ausgeführten lonenimplantationsschritt (IS) vorgesehen wird. Doping region (11) of the second conductivity type (p +) is provided in the ion implantation step (IS) performed in parallel through the first trench (G).
13. Herstellungsverfahren für eine Trench-MOSFET-Transistorvorrichtung nach Anspruch 10, 11 oder 12, wobei mehrere beabstandete zweite Gräben (G1 '; G2'; G3') mit der zweiten Tiefenerstreckung (T) ausgehend von der Vorderseite (V) in dem ersten A fabrication method for a trench MOSFET transistor device according to claim 10, 11 or 12, wherein a plurality of spaced second trenches (G1 '; G2'; G3 ') have the second depth extent (T) from the front side (V) in the first one
Dotierungsbereich (1 c) seitlich vom Sourceanschlussbereich (5) in dem Ätzschritt (AE) simultan geätzt werden, unter denen ein zusammenhängender vergrabener zweiter Dotierungsbereich (I; Γ) des zweiten Leitungstyps (p+) mit der dritten Tiefenerstreckung (T") in dem durch die zweiten Graben (G'; G1', G2', G3') hindurch ausgeführten lonenimplantationsschritt (IS) gebildet wird. Doping region (1 c) are etched laterally from the source terminal region (5) in the etching step (AE), under which a contiguous buried second doping region (I; Γ) of the second conductivity type (p +) with the third depth extension (T ") in the by the second trenches (G ', G1', G2 ', G3') are formed through an ion implantation step (IS).
14. Herstellungsverfahren für eine Trench-MOSFET-Transistorvorrichtung nach einem der Ansprüche 10 bis 13, wobei das Substrat (1) ein Siliziumcarbidsubstrat ist. The manufacturing method of a trench MOSFET transistor device according to any one of claims 10 to 13, wherein the substrate (1) is a silicon carbide substrate.
PCT/EP2014/075092 2014-01-13 2014-11-20 Trench mosfet transistor device and corresponding production method WO2015104084A1 (en)

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