WO2015188542A1 - Low temperature polysilicon thin film transistor manufacturing method and array substrate manufacturing method - Google Patents
Low temperature polysilicon thin film transistor manufacturing method and array substrate manufacturing method Download PDFInfo
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- WO2015188542A1 WO2015188542A1 PCT/CN2014/088421 CN2014088421W WO2015188542A1 WO 2015188542 A1 WO2015188542 A1 WO 2015188542A1 CN 2014088421 W CN2014088421 W CN 2014088421W WO 2015188542 A1 WO2015188542 A1 WO 2015188542A1
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- temperature polysilicon
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- amorphous silicon
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 81
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 81
- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000010410 layer Substances 0.000 claims abstract description 112
- 238000000034 method Methods 0.000 claims abstract description 73
- 230000008569 process Effects 0.000 claims abstract description 52
- 238000000059 patterning Methods 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 47
- 238000005224 laser annealing Methods 0.000 claims description 27
- 230000000717 retained effect Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Definitions
- Embodiments of the present invention relate to a method of fabricating a low temperature polysilicon thin film transistor and a method of fabricating the array substrate.
- Embodiments of the present invention provide a method of fabricating a low temperature polysilicon thin film transistor and a method of fabricating the array substrate. According to an embodiment of the invention,
- a method for fabricating a low temperature polysilicon thin film transistor comprising:
- a pattern including the source and the drain is formed, and the source and the drain are connected to the active layer through the contact hole and low temperature polysilicon at the bottom of the contact hole.
- Forming the pattern including the active layer on the base substrate includes:
- Amorphous silicon is processed using an excimer laser annealing process to convert the top amorphous silicon to low temperature polysilicon;
- a pattern including the active layer is formed by a patterning process, the active layer including amorphous silicon and low temperature polysilicon on amorphous silicon.
- Forming the pattern including the active layer on the base substrate includes:
- Amorphous silicon is processed using an excimer laser annealing process to convert all amorphous silicon into low temperature polysilicon;
- a pattern including the active layer is formed by a patterning process to form the active layer, the active layer including low temperature polysilicon.
- Forming low temperature polysilicon at the bottom of the contact hole includes:
- the active layer at the bottom of the contact hole is processed using an excimer laser annealing process.
- Forming low temperature polysilicon at the bottom of the contact hole includes:
- Amorphous silicon is processed using an excimer laser annealing process to convert amorphous silicon into low temperature polysilicon;
- a buffer layer is formed on the base substrate before the pattern including the active layer is formed on the base substrate.
- the excimer laser used in the excimer laser annealing process is a XeCl laser having a wavelength of 308 nm.
- the excimer laser used in the excimer laser annealing process has an energy density of 200 to 300 mJ/cm 2 .
- the coincidence ratio between the spots at two adjacent moments in the excimer laser annealing process is 94 to 98%.
- the embodiment of the present invention further provides a method for fabricating an array substrate, and the method for fabricating the array substrate includes the method for fabricating the low temperature polysilicon thin film transistor according to any of the above.
- FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor formed corresponding to different steps of a first embodiment of the present invention
- FIG. 2 is a schematic structural view of a low temperature polysilicon thin film transistor formed correspondingly to different steps of the second embodiment of the present invention.
- the manufacturing method of the low-temperature polysilicon thin film transistor comprises: forming a layer of amorphous silicon on the base substrate; converting the upper portion of the amorphous silicon into low-temperature polysilicon by an excimer laser annealing process to form an active layer; forming gate insulation in sequence a layer, a gate and an interlayer insulating layer; etching a contact hole corresponding to the source and the drain on the interlayer insulating layer and the gate insulating layer to expose the low temperature polysilicon; finally, forming a source and a drain, and a source The pole and the drain are in contact with the low temperature polysilicon through the contact hole, thereby forming a low temperature polysilicon thin film transistor.
- the inventors have found that since the thicknesses of the gate insulating layer and the interlayer insulating layer in different regions are not uniform, in the process of etching to form the contact hole, over-etching is easily caused, so that the low-temperature polysilicon at the bottom of the contact hole is etched. Dropping causes the subsequently formed source or drain to be in poor contact with the active layer, thereby reducing the performance of the low temperature polysilicon thin film transistor.
- the embodiment of the invention provides a method for fabricating a low-temperature polysilicon thin film transistor and a method for fabricating the array substrate, which can solve the technical problem that the source or the drain is in poor contact with the active layer.
- the manufacturing method of the low temperature polysilicon thin film transistor comprises the following steps:
- Step S101 forming a pattern including an active layer on the base substrate, the active layer including low temperature polysilicon.
- the active layer can be formed in two ways:
- Method 1 as shown in FIG. 1, forming a layer of amorphous silicon 21 on the base substrate 1; using an excimer
- the laser annealing process treats the amorphous silicon 21 to convert the top amorphous silicon 21 into low temperature polysilicon 22; a pattern including the active layer 2 is formed through a patterning process to form the active layer 2.
- the active layer 2 formed includes amorphous silicon 21 and low temperature polysilicon 22 on amorphous silicon 21.
- Method 2 as shown in FIG. 2, a layer of amorphous silicon 21 is formed on the base substrate 1; then, the amorphous silicon 21 is processed by an excimer laser annealing process to convert all of the amorphous silicon 21 into low temperature polysilicon 22 A pattern including the active layer 2 is formed through a patterning process to form the active layer 2.
- the active layer 2 formed includes low temperature polysilicon 22.
- the amorphous silicon 21 formed on the base substrate 1 is thick, it is suitable for the first method, and when the amorphous silicon 21 formed on the base substrate 1 is thin, it is suitable for the second method.
- the basic principle of using an excimer laser annealing process to convert amorphous silicon 21 into low-temperature polysilicon 22 is as follows: a high-energy excimer laser is irradiated onto the surface of amorphous silicon 21 to melt, cool, and recrystallize amorphous silicon 21 to achieve The transition of amorphous silicon 21 to polysilicon 22.
- the low-temperature polysilicon 22 prepared by the excimer laser annealing process has large crystal grains, good spatial selectivity, few intragranular defects, good electrical characteristics, and little influence on the temperature of the substrate substrate 1 during the excimer laser annealing process.
- the excimer laser emits an excimer laser to form a spot on the surface of the amorphous silicon 21, and the excimer laser scans along a certain trajectory, thereby moving the spot along a certain trajectory to make the surface of the entire amorphous silicon 21 uniform.
- the ground is irradiated by an excimer laser, and there is a certain overlap between the spots at two adjacent moments during the scanning process.
- the patterning process of the embodiment of the present invention includes: coating a photoresist, masking with a mask, exposing, developing, etching, stripping the photoresist, and the like.
- the low temperature polysilicon 22 is first formed, and the pattern of the active layer 2 is formed by a patterning process so that the formed low temperature polysilicon 22 is relatively uniform.
- the embodiment of the present invention is not limited thereto, and after the amorphous silicon 21 is formed, the pattern of the active layer 2 is formed by a patterning process, and then the low temperature polysilicon 22 is formed.
- a buffer layer may be formed on the base substrate 1 before the pattern including the active layer 2 is formed on the base substrate 1.
- the function of the buffer layer is to isolate the base substrate 1 from the active layer 2, and to prevent impurities in the base substrate 1 from entering the active layer 2, affecting the performance of the active layer 2.
- thermal diffusion between the amorphous silicon 21 and the base substrate 1 can be reduced, thereby reducing the influence of temperature on the substrate 1 during the excimer laser annealing process.
- Step S102 forming a gate insulating layer on the active layer 2.
- the gate insulating layer 3 is formed on the active layer 2 by a method such as plasma chemical vapor deposition.
- Step S103 forming a pattern including a gate on the gate insulating layer 3.
- a gate metal layer is formed on the gate insulating layer 3 by sputtering or evaporation, and then a pattern including the gate electrode 4 is formed through a patterning process.
- Step S104 forming an interlayer insulating layer on the gate, and forming a contact hole corresponding to the source and the drain on the interlayer insulating layer and the gate insulating layer by a patterning process.
- an interlayer insulating layer 5 is formed on the gate electrode 4 by plasma enhanced chemical vapor deposition or the like, and then corresponding to the source electrode 7 and the drain electrode 8 is formed on the interlayer insulating layer 5 and the gate insulating layer 3 by a patterning process.
- Step S105 forming low temperature polysilicon at the bottom of the contact hole.
- the step of forming the low temperature polysilicon 22 at the bottom of the contact hole 6 differs depending on the method employed to form the pattern including the active layer 2 on the base substrate 1 in step S101.
- the excimer laser annealing process is used to the bottom of the contact hole 6.
- the source layer 2 is processed so that the amorphous silicon 21 exposed when the interlayer insulating layer 5 and the gate insulating layer 3 are etched in step S104 is converted into the low temperature polysilicon 22.
- FIG. 1 shows that the amorphous silicon 21 exposed when the interlayer insulating layer 5 and the gate insulating layer 3 are etched in step S104 is converted into the low temperature polysilicon 22.
- the interlayer insulating layer 5 and the gate insulating layer 3 are applied in step S104.
- the etching is performed, the base substrate 1 or the buffer layer under the gate insulating layer 3 is exposed. Therefore, the amorphous silicon 21 needs to be formed on the base substrate 1 first; then, the excimer laser annealing process is used to The crystalline silicon 21 is processed to convert the amorphous silicon 21 into low temperature polysilicon 22; finally, only one low temperature polysilicon at the bottom of the contact hole 6 is retained by one patterning process.
- the interlayer insulating layer 5 and the gate insulating layer 3 in the region where the contact hole 6 is located are removed only when the contact hole 6 is formed by the patterning process, the low-temperature polysilicon other than the bottom portion of the contact hole 6 is removed by a patterning process. At the time, only the low-temperature polysilicon at the bottom of the contact hole 6 is left. Therefore, when the low-temperature polysilicon other than the bottom of the contact hole 6 is removed by a patterning process, the mask used to form the contact hole 6 may be selected, as long as the contact hole 6 is selected and formed.
- the opposite photoresist can be used to reduce production costs. For example, if a positive photoresist is used for forming the contact hole 6, a negative photoresist is used here, and if a negative photoresist is used for forming the contact hole 6, a positive photoresist is used here.
- Step S106 forming a pattern including a source and a drain.
- the source and the drain are connected to the active layer through the contact hole and the low temperature polysilicon at the bottom of the contact hole.
- a source/drain metal layer is formed on the substrate 1 subjected to the excimer laser annealing process by sputtering or evaporation, and then formed by a patterning process including the source 7 And a pattern of the drain 8, wherein the source 7 and the drain 8 are connected to the active layer 2 through the contact hole 6 and the low temperature polysilicon 22 at the bottom of the contact hole 6.
- the source 7 and the drain 8 have good ohmic contact with the active layer 2, so that the low temperature polysilicon thin film transistor has better performance.
- Embodiments of the present invention provide a method of fabricating a low temperature polysilicon thin film transistor.
- the method includes forming low temperature polysilicon at a bottom of the contact hole after forming a contact hole corresponding to the source and the drain, so that the subsequently formed source and drain are connected to the active layer through the contact hole and the low temperature polysilicon at the bottom of the contact hole, It can solve the technical problem that the source or the drain is in poor contact with the active layer.
- the excimer laser used in the excimer laser annealing process used in the excimer laser annealing process is, for example, a XeCl laser having a wavelength of 308 nm.
- the excimer laser has an energy density of 200 to 300 mJ/cm 2 .
- the coincidence ratio between the spots at two adjacent moments in the excimer laser annealing process is 94 to 98%.
- other parameter values of the excimer laser may be selected depending on the thickness of the low-temperature polysilicon film layer to be formed, and the like.
- the embodiment of the invention further provides a method for fabricating an array substrate, and the method for fabricating the array substrate comprises the method for fabricating the low temperature polysilicon thin film transistor described above.
- the method for fabricating the array substrate further includes the fabrication of a structure such as a pixel electrode, which can be obtained by those skilled in the art without any creative work, which is not limited by the embodiment of the present invention.
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Abstract
A low temperature polysilicon thin film transistor manufacturing method and array substrate manufacturing method, the manufacturing method comprising: forming a pattern comprising an active layer (2) on a base substrate (2), the active layer comprising low temperature polysilicon (22); forming a gate insulation layer (3) on the active layer; forming a pattern comprising a gate (4) on the gate insulation layer; forming an interlayer insulation layer (5) on the gate, and forming contact holes corresponding to a source electrode (7) and a drain electrode (8) on the interlayer insulation layer and the gate insulation layer via a patterning process; forming low temperature polysilicon at the bottom of the contact holes; and forming a pattern comprising the source electrode and the drain electrode, the source electrode and the drain electrode being connected to the active layer via the contact holes and the low temperature polysilicon at the bottom of the contact holes.
Description
本发明的实施例涉及一种低温多晶硅薄膜晶体管的制作方法和阵列基板的制作方法。Embodiments of the present invention relate to a method of fabricating a low temperature polysilicon thin film transistor and a method of fabricating the array substrate.
由于低温多晶硅薄膜晶体管具有较高的电子迁移率、较快的响应速度、良好的稳定性等优点，因此常用的主动式阵列液晶显示器多采用低温多晶硅薄膜晶体管。Since low-temperature polysilicon thin film transistors have the advantages of high electron mobility, fast response speed, good stability, etc., commonly used active array liquid crystal displays mostly use low temperature polysilicon thin film transistors.
发明内容Summary of the invention
本发明的实施例提供了一种低温多晶硅薄膜晶体管的制作方法和阵列基板的制作方法。根据本发明的实施例，Embodiments of the present invention provide a method of fabricating a low temperature polysilicon thin film transistor and a method of fabricating the array substrate. According to an embodiment of the invention,
一种低温多晶硅薄膜晶体管的制作方法，包括：A method for fabricating a low temperature polysilicon thin film transistor, comprising:
在衬底基板上形成包括有源层的图形，所述有源层包括低温多晶硅；Forming a pattern including an active layer on the base substrate, the active layer including low temperature polysilicon;
在所述有源层上形成栅极绝缘层；Forming a gate insulating layer on the active layer;
在所述栅极绝缘层上形成包括栅极的图形；Forming a pattern including a gate on the gate insulating layer;
在所述栅极上形成层间绝缘层，通过构图工艺使所述层间绝缘层和所述栅极绝缘层上形成对应于源极和漏极的接触孔；Forming an interlayer insulating layer on the gate, and forming a contact hole corresponding to the source and the drain on the interlayer insulating layer and the gate insulating layer by a patterning process;
在所述接触孔底部形成低温多晶硅；以及Forming low temperature polysilicon at the bottom of the contact hole;
形成包括所述源极和所述漏极的图形，所述源极和所述漏极通过所述接触孔以及所述接触孔底部的低温多晶硅连接所述有源层。A pattern including the source and the drain is formed, and the source and the drain are connected to the active layer through the contact hole and low temperature polysilicon at the bottom of the contact hole.
所述在衬底基板上形成包括有源层的图形包括：Forming the pattern including the active layer on the base substrate includes:
在所述衬底基板上形成一层非晶硅；Forming a layer of amorphous silicon on the base substrate;
使用准分子激光退火工艺对非晶硅进行处理，使顶部的非晶硅转化为低温多晶硅；以及Amorphous silicon is processed using an excimer laser annealing process to convert the top amorphous silicon to low temperature polysilicon;
通过构图工艺形成包括所述有源层的图形，以形成所述有源层，所述有源层包括非晶硅和位于非晶硅上的低温多晶硅。
A pattern including the active layer is formed by a patterning process, the active layer including amorphous silicon and low temperature polysilicon on amorphous silicon.
所述在衬底基板上形成包括有源层的图形包括：Forming the pattern including the active layer on the base substrate includes:
在所述衬底基板上形成一层非晶硅；Forming a layer of amorphous silicon on the base substrate;
使用准分子激光退火工艺对非晶硅进行处理，使非晶硅全部转化为低温多晶硅；以及Amorphous silicon is processed using an excimer laser annealing process to convert all amorphous silicon into low temperature polysilicon;
通过构图工艺形成包括所述有源层的图形，以形成所述有源层，所述有源层包括低温多晶硅。A pattern including the active layer is formed by a patterning process to form the active layer, the active layer including low temperature polysilicon.
所述在所述接触孔底部形成低温多晶硅包括：Forming low temperature polysilicon at the bottom of the contact hole includes:
使用准分子激光退火工艺对所述接触孔底部的所述有源层进行处理。The active layer at the bottom of the contact hole is processed using an excimer laser annealing process.
所述在所述接触孔底部形成低温多晶硅包括：Forming low temperature polysilicon at the bottom of the contact hole includes:
在所述衬底基板上形成非晶硅；Forming amorphous silicon on the base substrate;
使用准分子激光退火工艺对非晶硅进行处理，使非晶硅转化为低温多晶硅；以及Amorphous silicon is processed using an excimer laser annealing process to convert amorphous silicon into low temperature polysilicon;
通过一次构图工艺，仅保留所述接触孔底部的低温多晶硅。Only one low temperature polysilicon at the bottom of the contact hole is retained by one patterning process.
在衬底基板上形成包括有源层的图形之前，在所述衬底基板上形成缓冲层。A buffer layer is formed on the base substrate before the pattern including the active layer is formed on the base substrate.
所述准分子激光退火工艺中使用的准分子激光为XeCl激光，其波长为308nm。The excimer laser used in the excimer laser annealing process is a XeCl laser having a wavelength of 308 nm.
所述准分子激光退火工艺中使用的准分子激光的能量密度为200～300mJ/cm2。The excimer laser used in the excimer laser annealing process has an energy density of 200 to 300 mJ/cm 2 .
所述准分子激光退火工艺中的相邻两个时刻的光斑之间的重合率为94～98％。The coincidence ratio between the spots at two adjacent moments in the excimer laser annealing process is 94 to 98%.
此外，本发明实施例还提供了一种阵列基板的制作方法，该阵列基板的制作方法包括以上任一项所述的低温多晶硅薄膜晶体管的制作方法。In addition, the embodiment of the present invention further provides a method for fabricating an array substrate, and the method for fabricating the array substrate includes the method for fabricating the low temperature polysilicon thin film transistor according to any of the above.
以下将结合附图对本发明的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本发明，其中：The embodiments of the present invention will be described in more detail below with reference to the accompanying drawings, in which FIG.
图1为本发明的第一实施例的不同步骤对应形成的低温多晶硅薄膜晶体管各结构示意图；1 is a schematic structural view of a low temperature polysilicon thin film transistor formed corresponding to different steps of a first embodiment of the present invention;
图2为本发明的第二实施例的不同步骤对应形成的低温多晶硅薄膜晶体管个结构示意图。
2 is a schematic structural view of a low temperature polysilicon thin film transistor formed correspondingly to different steps of the second embodiment of the present invention.
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例只是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，相关领域普通技术人员在不需要付出创造性劳动前提下所获得的所有其他实施例，都应属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the relevant art based on the embodiments of the present invention without the need for creative labor shall fall within the protection scope of the present invention.
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meaning as understood by those having ordinary skill in the art to which the invention pertains. The words "a", "an", "the" and "the" The word "comprising" or "comprises" or the like means that the element or item preceding the word is intended to be in the "Upper", "lower", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.
低温多晶硅薄膜晶体管的制作方法包括：在衬底基板上形成一层非晶硅；通过准分子激光退火工艺使非晶硅的上层部分转化为低温多晶硅，以形成有源层；依次形成栅极绝缘层、栅极和层间绝缘层；在层间绝缘层和栅极绝缘层上刻蚀形成对应于源极和漏极的接触孔，使低温多晶硅暴露；最后，形成源极和漏极，源极和漏极通过接触孔与低温多晶硅接触，从而形成低温多晶硅薄膜晶体管。The manufacturing method of the low-temperature polysilicon thin film transistor comprises: forming a layer of amorphous silicon on the base substrate; converting the upper portion of the amorphous silicon into low-temperature polysilicon by an excimer laser annealing process to form an active layer; forming gate insulation in sequence a layer, a gate and an interlayer insulating layer; etching a contact hole corresponding to the source and the drain on the interlayer insulating layer and the gate insulating layer to expose the low temperature polysilicon; finally, forming a source and a drain, and a source The pole and the drain are in contact with the low temperature polysilicon through the contact hole, thereby forming a low temperature polysilicon thin film transistor.
发明人发现，由于不同区域的栅极绝缘层和层间绝缘层的厚度不均匀，因此，在刻蚀形成接触孔的过程中，容易造成过蚀刻，从而使得接触孔底部的低温多晶硅被刻蚀掉，导致后续形成的源极或者漏极与有源层接触不良，从而降低了低温多晶硅薄膜晶体管的性能。The inventors have found that since the thicknesses of the gate insulating layer and the interlayer insulating layer in different regions are not uniform, in the process of etching to form the contact hole, over-etching is easily caused, so that the low-temperature polysilicon at the bottom of the contact hole is etched. Dropping causes the subsequently formed source or drain to be in poor contact with the active layer, thereby reducing the performance of the low temperature polysilicon thin film transistor.
本发明实施例提供了一种低温多晶硅薄膜晶体管的制作方法和阵列基板的制作方法，能够解决源极或者漏极与有源层接触不良的技术问题。The embodiment of the invention provides a method for fabricating a low-temperature polysilicon thin film transistor and a method for fabricating the array substrate, which can solve the technical problem that the source or the drain is in poor contact with the active layer.
该低温多晶硅薄膜晶体管的制作方法，包括以下步骤：The manufacturing method of the low temperature polysilicon thin film transistor comprises the following steps:
步骤S101：在衬底基板上形成包括有源层的图形，有源层包括低温多晶硅。Step S101: forming a pattern including an active layer on the base substrate, the active layer including low temperature polysilicon.
例如，可以采用两种方法形成有源层：For example, the active layer can be formed in two ways:
方法一，如图1所示，在衬底基板1上形成一层非晶硅21；使用准分子
激光退火工艺对非晶硅21进行处理，使顶部的非晶硅21转化为低温多晶硅22；经过构图工艺形成包括有源层2的图形，以形成有源层2。形成的有源层2包括非晶硅21和位于非晶硅21上的低温多晶硅22。 Method 1, as shown in FIG. 1, forming a layer of amorphous silicon 21 on the base substrate 1; using an excimer
The laser annealing process treats the amorphous silicon 21 to convert the top amorphous silicon 21 into low temperature polysilicon 22; a pattern including the active layer 2 is formed through a patterning process to form the active layer 2. The active layer 2 formed includes amorphous silicon 21 and low temperature polysilicon 22 on amorphous silicon 21.
方法二，如图2所示，在衬底基板1上形成一层非晶硅21；然后，使用准分子激光退火工艺对非晶硅21进行处理，使非晶硅21全部转化为低温多晶硅22；经过构图工艺形成包括有源层2的图形，以形成有源层2。形成的有源层2包括低温多晶硅22。Method 2, as shown in FIG. 2, a layer of amorphous silicon 21 is formed on the base substrate 1; then, the amorphous silicon 21 is processed by an excimer laser annealing process to convert all of the amorphous silicon 21 into low temperature polysilicon 22 A pattern including the active layer 2 is formed through a patterning process to form the active layer 2. The active layer 2 formed includes low temperature polysilicon 22.
需要说明的是，在衬底基板1上形成的非晶硅21较厚时适用于方法一，在衬底基板1上形成的非晶硅21较薄时适用于方法二。It should be noted that when the amorphous silicon 21 formed on the base substrate 1 is thick, it is suitable for the first method, and when the amorphous silicon 21 formed on the base substrate 1 is thin, it is suitable for the second method.
而使用准分子激光退火工艺使非晶硅21转变为低温多晶硅22的基本原理如下：高能量的准分子激光照射到非晶硅21表面，使非晶硅21融化、冷却、再结晶，实现从非晶硅21到多晶硅22的转变。准分子激光退火工艺制备的低温多晶硅22的晶粒大、空间选择性好、晶内缺陷少、电学特性好，且准分子激光退火工艺过程中对衬底基板1的温度影响较小。在此过程中，准分子激光器发射出准分子激光，在非晶硅21表面形成光斑，准分子激光器沿一定轨迹进行扫描，进而使得光斑沿一定轨迹移动，以使整个非晶硅21的表面均匀地受到准分子激光的照射，在扫描过程中，相邻两个时刻的光斑之间存在一定的重合。The basic principle of using an excimer laser annealing process to convert amorphous silicon 21 into low-temperature polysilicon 22 is as follows: a high-energy excimer laser is irradiated onto the surface of amorphous silicon 21 to melt, cool, and recrystallize amorphous silicon 21 to achieve The transition of amorphous silicon 21 to polysilicon 22. The low-temperature polysilicon 22 prepared by the excimer laser annealing process has large crystal grains, good spatial selectivity, few intragranular defects, good electrical characteristics, and little influence on the temperature of the substrate substrate 1 during the excimer laser annealing process. In this process, the excimer laser emits an excimer laser to form a spot on the surface of the amorphous silicon 21, and the excimer laser scans along a certain trajectory, thereby moving the spot along a certain trajectory to make the surface of the entire amorphous silicon 21 uniform. The ground is irradiated by an excimer laser, and there is a certain overlap between the spots at two adjacent moments during the scanning process.
需要说明的是，本发明实施例的构图工艺包括：涂覆光刻胶，使用掩膜板遮盖，曝光，显影，刻蚀，剥离光刻胶等步骤。It should be noted that the patterning process of the embodiment of the present invention includes: coating a photoresist, masking with a mask, exposing, developing, etching, stripping the photoresist, and the like.
在一个示例中，先形成低温多晶硅22，经过构图工艺形成有源层2的图形，以使得形成的低温多晶硅22较均匀。但是本发明的实施例并不局限于此，也可以形成非晶硅21后，先经过构图工艺形成有源层2的图形，然后再形成低温多晶硅22。In one example, the low temperature polysilicon 22 is first formed, and the pattern of the active layer 2 is formed by a patterning process so that the formed low temperature polysilicon 22 is relatively uniform. However, the embodiment of the present invention is not limited thereto, and after the amorphous silicon 21 is formed, the pattern of the active layer 2 is formed by a patterning process, and then the low temperature polysilicon 22 is formed.
此外，在衬底基板1上形成包括有源层2的图形之前还可以先在衬底基板1上形成缓冲层。缓冲层的作用在于将衬底基板1与有源层2隔绝，避免衬底基板1中的杂质进入有源层2，影响有源层2的性能。此外还可减少非晶硅21与衬底基板1之间的热扩散，从而降低准分子激光退火工艺过程中温度对衬底基板1的影响。Further, a buffer layer may be formed on the base substrate 1 before the pattern including the active layer 2 is formed on the base substrate 1. The function of the buffer layer is to isolate the base substrate 1 from the active layer 2, and to prevent impurities in the base substrate 1 from entering the active layer 2, affecting the performance of the active layer 2. In addition, thermal diffusion between the amorphous silicon 21 and the base substrate 1 can be reduced, thereby reducing the influence of temperature on the substrate 1 during the excimer laser annealing process.
步骤S102：在有源层2上形成栅极绝缘层。Step S102: forming a gate insulating layer on the active layer 2.
使用等离子体化学气相沉积等方法在有源层2上形成栅极绝缘层3。
The gate insulating layer 3 is formed on the active layer 2 by a method such as plasma chemical vapor deposition.
步骤S103：在栅极绝缘层3上形成包括栅极的图形。Step S103: forming a pattern including a gate on the gate insulating layer 3.
首先使用溅射或者蒸镀等方法在栅极绝缘层3上形成一层栅极金属层，然后经过一次构图工艺形成包括栅极4的图形。First, a gate metal layer is formed on the gate insulating layer 3 by sputtering or evaporation, and then a pattern including the gate electrode 4 is formed through a patterning process.
步骤S104：在栅极上形成层间绝缘层，并且通过构图工艺使层间绝缘层和栅极绝缘层上形成对应于源极和漏极的接触孔。Step S104: forming an interlayer insulating layer on the gate, and forming a contact hole corresponding to the source and the drain on the interlayer insulating layer and the gate insulating layer by a patterning process.
首先使用等离子体增强化学气相沉积等方法在栅极4上形成层间绝缘层5，然后通过构图工艺在层间绝缘层5和栅极绝缘层3上形成对应于源极7和漏极8的接触孔6。First, an interlayer insulating layer 5 is formed on the gate electrode 4 by plasma enhanced chemical vapor deposition or the like, and then corresponding to the source electrode 7 and the drain electrode 8 is formed on the interlayer insulating layer 5 and the gate insulating layer 3 by a patterning process. Contact hole 6.
步骤S105：在接触孔底部形成低温多晶硅。Step S105: forming low temperature polysilicon at the bottom of the contact hole.
在接触孔6底部形成低温多晶硅22的步骤根据步骤S101中在衬底基板1上形成包括有源层2的图形所采用的方法不同而不同。例如，如图1所示，当衬底基板1上形成的非晶硅21较厚，采用方法一形成包括有源层2的图形时，则使用准分子激光退火工艺对接触孔6底部的有源层2进行处理，以使得在步骤S104中对层间绝缘层5和栅极绝缘层3进行刻蚀时暴露出的非晶硅21转变为低温多晶硅22。如图2所示，当衬底基板1上形成的非晶硅21较薄，采用方法二形成包括有源层2的图形时，在步骤S104中对层间绝缘层5和栅极绝缘层3进行刻蚀时，会使得位于栅极绝缘层3下的衬底基板1或者缓冲层暴露，因此，需要先在衬底基板1上形成非晶硅21；然后，使用准分子激光退火工艺对非晶硅21进行处理，使非晶硅21转化为低温多晶硅22；最后，经过一次构图工艺，仅保留接触孔6底部的低温多晶硅。The step of forming the low temperature polysilicon 22 at the bottom of the contact hole 6 differs depending on the method employed to form the pattern including the active layer 2 on the base substrate 1 in step S101. For example, as shown in FIG. 1, when the amorphous silicon 21 formed on the base substrate 1 is thick, and the pattern including the active layer 2 is formed by the method 1, the excimer laser annealing process is used to the bottom of the contact hole 6. The source layer 2 is processed so that the amorphous silicon 21 exposed when the interlayer insulating layer 5 and the gate insulating layer 3 are etched in step S104 is converted into the low temperature polysilicon 22. As shown in FIG. 2, when the amorphous silicon 21 formed on the base substrate 1 is thin, and the pattern including the active layer 2 is formed by the second method, the interlayer insulating layer 5 and the gate insulating layer 3 are applied in step S104. When the etching is performed, the base substrate 1 or the buffer layer under the gate insulating layer 3 is exposed. Therefore, the amorphous silicon 21 needs to be formed on the base substrate 1 first; then, the excimer laser annealing process is used to The crystalline silicon 21 is processed to convert the amorphous silicon 21 into low temperature polysilicon 22; finally, only one low temperature polysilicon at the bottom of the contact hole 6 is retained by one patterning process.
需要说明的是，由于在通过构图工艺形成接触孔6时，仅去除接触孔6所在区域的层间绝缘层5和栅极绝缘层3，而在经过构图工艺去除接触孔6底部以外的低温多晶硅时，仅保留接触孔6底部的低温多晶硅，因此，在通过构图工艺去除接触孔6底部以外的低温多晶硅时，可以选用形成接触孔6时所采用的掩膜板，只要选用与形成接触孔6时相反的光刻胶即可，以降低生产成本。例如，若形成接触孔6时选用正性光刻胶，则此处选用负性光刻胶，若形成接触孔6时选用负性光刻胶，则此处选用正性光刻胶。It should be noted that, since the interlayer insulating layer 5 and the gate insulating layer 3 in the region where the contact hole 6 is located are removed only when the contact hole 6 is formed by the patterning process, the low-temperature polysilicon other than the bottom portion of the contact hole 6 is removed by a patterning process. At the time, only the low-temperature polysilicon at the bottom of the contact hole 6 is left. Therefore, when the low-temperature polysilicon other than the bottom of the contact hole 6 is removed by a patterning process, the mask used to form the contact hole 6 may be selected, as long as the contact hole 6 is selected and formed. The opposite photoresist can be used to reduce production costs. For example, if a positive photoresist is used for forming the contact hole 6, a negative photoresist is used here, and if a negative photoresist is used for forming the contact hole 6, a positive photoresist is used here.
步骤S106：形成包括源极和漏极的图形。源极和漏极通过接触孔以及接触孔底部的低温多晶硅连接有源层。Step S106: forming a pattern including a source and a drain. The source and the drain are connected to the active layer through the contact hole and the low temperature polysilicon at the bottom of the contact hole.
首先，使用溅射或者蒸镀等方法，在经过准分子激光退火工艺处理后的衬底基板1上，形成一层源漏极金属层，然后通过构图工艺形成包括源极7
和漏极8的图形，其中源极7和漏极8通过接触孔6以及接触孔6底部的低温多晶硅22连接有源层2。以此方式，源极7和漏极8与有源层2之间具有良好的欧姆接触，使低温多晶硅薄膜晶体管具有较好的性能。First, a source/drain metal layer is formed on the substrate 1 subjected to the excimer laser annealing process by sputtering or evaporation, and then formed by a patterning process including the source 7
And a pattern of the drain 8, wherein the source 7 and the drain 8 are connected to the active layer 2 through the contact hole 6 and the low temperature polysilicon 22 at the bottom of the contact hole 6. In this way, the source 7 and the drain 8 have good ohmic contact with the active layer 2, so that the low temperature polysilicon thin film transistor has better performance.
上述步骤顺序仅是为了说明本发明原理的示例性实施例，因此，这些顺序可以根据需要进行变化，而变化之后的实施例都应落入本发明的范围。The above-described sequence of steps is merely illustrative of exemplary embodiments of the present invention, and therefore, the order may be varied as needed, and the embodiments after the changes are intended to fall within the scope of the present invention.
本发明的实施例提供了一种低温多晶硅薄膜晶体管的制作方法。该方法包括在形成对应于源极和漏极的接触孔后，在接触孔底部形成低温多晶硅，以使得后续形成的源极和漏极通过接触孔以及接触孔底部的低温多晶硅连接有源层，能够解决源极或者漏极与有源层接触不良的技术问题。Embodiments of the present invention provide a method of fabricating a low temperature polysilicon thin film transistor. The method includes forming low temperature polysilicon at a bottom of the contact hole after forming a contact hole corresponding to the source and the drain, so that the subsequently formed source and drain are connected to the active layer through the contact hole and the low temperature polysilicon at the bottom of the contact hole, It can solve the technical problem that the source or the drain is in poor contact with the active layer.
在上述各个步骤中，准分子激光退火工艺中使用的准分子激光退火工艺中使用的准分子激光例如为XeCl激光，其波长为308nm。准分子激光的能量密度为200～300mJ/cm2。准分子激光退火工艺中的相邻两个时刻的光斑之间的重合率为94～98％。但是也可以根据需要形成的低温多晶硅膜层的厚度等要求，选择准分子激光其它的参数值。In each of the above steps, the excimer laser used in the excimer laser annealing process used in the excimer laser annealing process is, for example, a XeCl laser having a wavelength of 308 nm. The excimer laser has an energy density of 200 to 300 mJ/cm 2 . The coincidence ratio between the spots at two adjacent moments in the excimer laser annealing process is 94 to 98%. However, other parameter values of the excimer laser may be selected depending on the thickness of the low-temperature polysilicon film layer to be formed, and the like.
本发明实施例还提供了一种阵列基板的制作方法，该阵列基板的制作方法包括以上所述的低温多晶硅薄膜晶体管的制作方法。该阵列基板的制作方法还包括像素电极等结构的制作，本领域技术人员在不付出创造性劳动的前提下均可获得，本发明实施例对此不进行限定。The embodiment of the invention further provides a method for fabricating an array substrate, and the method for fabricating the array substrate comprises the method for fabricating the low temperature polysilicon thin film transistor described above. The method for fabricating the array substrate further includes the fabrication of a structure such as a pixel electrode, which can be obtained by those skilled in the art without any creative work, which is not limited by the embodiment of the present invention.
以上所述，仅为本发明的示例性实施方式或实施例，但本发明的保护范围并不局限于此。任何熟悉本技术领域的普通技术人员在本发明公开的范围内，可轻易想到各种其他变化或替换，这些变化或替换及其等同方式都应涵盖在本发明的保护范围之内。The above description is only an exemplary embodiment or an embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. It will be apparent to those skilled in the art that various changes and substitutions may be made without departing from the scope of the present invention.
本申请要求于2014年06月10日提交的名称为“低温多晶硅薄膜晶体管的制作方法和阵列基板的制作方法”的中国专利申请No.201410255910.4的优先权，其全文以引用方式合并于本文。
The present application claims priority to Chinese Patent Application No. 20141025591, the entire disclosure of which is incorporated herein by reference.
Claims (10)
- 一种低温多晶硅薄膜晶体管的制作方法，包括：A method for fabricating a low temperature polysilicon thin film transistor, comprising:在衬底基板上形成包括有源层的图形，所述有源层包括低温多晶硅；Forming a pattern including an active layer on the base substrate, the active layer including low temperature polysilicon;在所述有源层上形成栅极绝缘层；Forming a gate insulating layer on the active layer;在所述栅极绝缘层上形成包括栅极的图形；Forming a pattern including a gate on the gate insulating layer;在所述栅极上形成层间绝缘层，通过构图工艺使所述层间绝缘层和所述栅极绝缘层上形成对应于源极和漏极的接触孔；Forming an interlayer insulating layer on the gate, and forming a contact hole corresponding to the source and the drain on the interlayer insulating layer and the gate insulating layer by a patterning process;在所述接触孔底部形成低温多晶硅；以及Forming low temperature polysilicon at the bottom of the contact hole;形成包括所述源极和所述漏极的图形；Forming a pattern including the source and the drain;其中所述源极和所述漏极通过所述接触孔以及所述接触孔底部的低温多晶硅连接所述有源层。Wherein the source and the drain connect the active layer through the contact hole and low temperature polysilicon at the bottom of the contact hole.
- 根据权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中所述在衬底基板上形成包括有源层的图形包括：The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein the forming the pattern including the active layer on the base substrate comprises:在所述衬底基板上形成一层非晶硅；Forming a layer of amorphous silicon on the base substrate;使用准分子激光退火工艺对非晶硅进行处理，使顶部的非晶硅转化为低温多晶硅；以及Amorphous silicon is processed using an excimer laser annealing process to convert the top amorphous silicon to low temperature polysilicon;通过构图工艺形成包括所述有源层的图形，以形成所述有源层，所述有源层包括非晶硅和位于非晶硅上的低温多晶硅。A pattern including the active layer is formed by a patterning process, the active layer including amorphous silicon and low temperature polysilicon on amorphous silicon.
- 根据权利要求1所述的低温多晶硅薄膜晶体管的制作方法，其中所述在衬底基板上形成包括有源层的图形包括：The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein the forming the pattern including the active layer on the base substrate comprises:在所述衬底基板上形成一层非晶硅；Forming a layer of amorphous silicon on the base substrate;使用准分子激光退火工艺对非晶硅进行处理，使非晶硅全部转化为低温多晶硅；以及Amorphous silicon is processed using an excimer laser annealing process to convert all amorphous silicon into low temperature polysilicon;经过构图工艺形成包括所述有源层的图形，以形成所述有源层，所述有源层包括低温多晶硅。A pattern including the active layer is formed through a patterning process to form the active layer, the active layer including low temperature polysilicon.
- 根据权利要求2所述的低温多晶硅薄膜晶体管的制作方法，其中所述在所述接触孔底部形成低温多晶硅包括：The method of fabricating a low temperature polysilicon thin film transistor according to claim 2, wherein said forming low temperature polysilicon at the bottom of said contact hole comprises:使用准分子激光退火工艺对所述接触孔底部的所述有源层进行处理。The active layer at the bottom of the contact hole is processed using an excimer laser annealing process.
- 根据权利要求3所述的低温多晶硅薄膜晶体管的制作方法，其中所述在所述接触孔底部形成低温多晶硅包括： The method of fabricating a low temperature polysilicon thin film transistor according to claim 3, wherein said forming low temperature polysilicon at the bottom of said contact hole comprises:在所述衬底基板上形成非晶硅；Forming amorphous silicon on the base substrate;使用准分子激光退火工艺对非晶硅进行处理，使非晶硅转化为低温多晶硅；以及Amorphous silicon is processed using an excimer laser annealing process to convert amorphous silicon into low temperature polysilicon;通过一次构图工艺，仅保留所述接触孔底部的低温多晶硅。Only one low temperature polysilicon at the bottom of the contact hole is retained by one patterning process.
- 根据权利要求1-5任一项所述的低温多晶硅薄膜晶体管的制作方法，还包括：在衬底基板上形成包括有源层的图形之前，在所述衬底基板上形成缓冲层。The method of fabricating a low temperature polysilicon thin film transistor according to any one of claims 1 to 5, further comprising forming a buffer layer on the base substrate before forming a pattern including the active layer on the base substrate.
- 根据权利要求2-6任一项所述的低温多晶硅薄膜晶体管的制作方法，其中所述准分子激光退火工艺中使用的准分子激光为XeCl激光，其波长为308nm。The method of fabricating a low temperature polysilicon thin film transistor according to any one of claims 2 to 6, wherein the excimer laser used in the excimer laser annealing process is a XeCl laser having a wavelength of 308 nm.
- 根据权利要求2-7任一项所述的低温多晶硅薄膜晶体管的制作方法，其中所述准分子激光退火工艺中使用的准分子激光的能量密度为200～300mJ/cm2。The method of fabricating a low temperature polysilicon thin film transistor according to any one of claims 2 to 7, wherein the excimer laser used in the excimer laser annealing process has an energy density of 200 to 300 mJ/cm 2 .
- 根据权利要求2-8任一项所述的低温多晶硅薄膜晶体管的制作方法，其中所述准分子激光退火工艺中的相邻两个时刻的光斑之间的重合率为94～98％。The method of fabricating a low temperature polysilicon thin film transistor according to any one of claims 2-8, wherein a coincidence ratio between spots at two adjacent moments in the excimer laser annealing process is 94 to 98%.
- 一种阵列基板的制作方法，包括如权利要求1-9任一项所述的低温多晶硅薄膜晶体管的制作方法。 A method of fabricating an array substrate, comprising the method of fabricating a low temperature polysilicon thin film transistor according to any one of claims 1-9.
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