WO2015182361A1 - Amplifying circuit and image sensor - Google Patents

Abstract

[Problem] Provided are an amplifying circuit having a small area and a small gain error due to parasitic capacitance, and an image sensor. [Solution] According to one embodiment of the present invention, an amplifying circuit (2) is provided with first and second current sources (I_CP1, I_CP2), first and second integral capacitors (C₁, C₂), first and second amplifying switches (S_A1, S_A2), first and second reset switches (S_R1, S_R2), and a comparator (21). The first (second) integral capacitor is connected between the first (second) current source and a first (third) voltage source. The first (second) amplifying switch is connected between the first (second)current source and the first (second) integral capacitor. The first (second) reset switch is connected between a first (second) connecting point at which the first (second) integral capacitor and the first (second) amplifying switch are connected to each other, and a second (fourth) voltage source. The comparator (21) opens/closes the first reset switch (S_R1) and the second reset switch (S_R2) corresponding to the results of comparison between an input voltage and a voltage at the first connecting point.

Description

Amplifier circuit and image sensor

Embodiments described herein relate generally to an amplifier circuit and an image sensor.

Conventionally, in an image sensor such as a CMOS image sensor, a signal output from a light receiving unit is amplified by an amplifier, and a digital signal is generated by AD conversion of the amplified signal. As the amplifier, for example, a PGA (Programmable Gain Amplifier) having a variable amplification gain is used. The PGA amplifies the signal with a gain corresponding to the signal intensity of the signal output from the light receiving unit. In a CMOS image sensor, such an amplifier circuit and an AD converter are generally arranged for each column of pixels, and high-speed reading is generally performed by operating them in parallel. For this reason, each amplifier circuit is required to have low power consumption and a small area.

CBSC (Comparator-based Switched Capacitor) amplifier circuit is known as one of amplifier circuits used in image sensors. The CBSC amplifier circuit includes a comparator, a plurality of capacitors, and a switch that controls charge / discharge of the capacitors. When this amplifier circuit is mounted on an LSI, an MIM (Metal-Insulator-Metal) capacitor formed by sandwiching an oxide film between wirings or a MOS capacitor which is a gate insulating film of a MOSFET is used as a capacitor. In general, a MOS capacitor having a large capacitance value per unit area is more advantageous than an MIM capacitor because the area of the capacitor can be reduced.

The above-described CBSC amplifier circuit has a problem that an error occurs in the gain due to the parasitic capacitance included in the amplifier circuit. This is the same regardless of whether an MIM capacitor or a MOS capacitor is used as the capacitor. When a MOS capacitor is used as the capacitor, a large parasitic capacitance is generated between the lower electrode and the silicon substrate, so that a larger gain error can occur than when the MIM capacitor is used.

In the technical field of image sensors, a method of correcting a signal error caused by a gain error of an amplifier circuit by digital processing after AD conversion has been proposed. However, this method requires a digital circuit for correction. Therefore, there is a problem that the circuit area of the image sensor increases.

Provide an amplifier circuit and an image sensor with a small area and a small gain error due to parasitic capacitance.

An amplifier circuit according to an embodiment includes a first current source, a first integration capacitor, a first amplification switch, a first reset switch, a second current source, and a second integration capacitor. , A second amplification switch, a second reset switch, and a comparator.

The first integration capacitor is connected between the first current source and the first voltage source. The first amplification switch is connected between the first current source and the first integration capacitor. The first reset switch is connected between a first connection point where the first integration capacitor and the first amplification switch are connected, and the second voltage source.

The second integration capacitor is connected between the second current source and the third voltage source. The second amplification switch is connected between the second current source and the second integration capacitor. The second reset switch is connected between a second connection point where the second integration capacitor and the second amplification switch are connected, and the fourth voltage source.

The comparator opens and closes the first reset switch and the second reset switch according to the comparison result between the input voltage and the voltage at the first connection point.

1 is a schematic configuration diagram illustrating an image sensor according to a first embodiment. The schematic block diagram which shows the amplifier circuit which concerns on 1st Embodiment. The figure which shows the operation | movement waveform of the amplifier circuit of FIG. The schematic block diagram which shows an example of the conventional CBSC amplifier circuit. The graph which shows the simulation result of a gain error. FIG. 3 is a schematic configuration diagram illustrating another example of the amplifier circuit of FIG. 2. FIG. 3 is a schematic configuration diagram illustrating another example of the amplifier circuit of FIG. 2. FIG. 4 is a diagram illustrating another example of operation waveforms of the amplifier circuit in FIG. 2. The schematic block diagram which shows the amplifier circuit which concerns on 2nd Embodiment. The figure which shows the operation | movement waveform when the delay of a comparator arises. The schematic block diagram which shows an example of the control voltage generator of the amplifier circuit of FIG. The figure which shows the operation | movement waveform of the amplifier circuit of FIG. The schematic block diagram which shows the amplifier circuit which concerns on 3rd Embodiment. FIG. 14 is a diagram illustrating operation waveforms of the amplifier circuit of FIG. 13. The graph which shows the simulation result of a gain error. The schematic block diagram which shows the image sensor which concerns on 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, an image sensor and an amplifier circuit according to the first embodiment will be described with reference to FIGS. FIG. 1 is a schematic configuration diagram illustrating an image sensor according to the present embodiment. The image sensor according to the present embodiment can be applied to a CMOS image sensor or a CCD image sensor. As shown in FIG. 1, the light receiving unit 1, the amplifier circuit 2, the AD converter 3, and the digital circuit 4 are provided. Prepare.

The light receiving unit 1 outputs an electrical signal (voltage or current) corresponding to the irradiated light. The light receiving unit 1 is, for example, a photodiode. In the following, it is assumed that the light receiving unit 1 outputs the voltage _VPIX as an electrical signal.

The amplifier circuit 2 amplifies the voltage V _PIX input from the light receiving unit 1 and outputs a voltage V _SIG . The amplifier circuit 2 may be a PGA with a variable amplification gain A (hereinafter referred to as “gain A”), or the gain A may be fixed. Details of the amplifier circuit 2 will be described later.

The AD converter 3 AD converts the voltage V _SIG input from the amplifier circuit 2 and outputs a digital signal corresponding to the voltage V _SIG . As the AD converter 3, any type of AD converter such as a pipeline type, a flash type, or a delta-sigma type can be used.

The digital circuit 4 executes arbitrary digital processing such as color correction and noise cut based on the digital signal input from the AD converter 3.

Next, the configuration of the amplifier circuit 2 according to the present embodiment will be described with reference to FIG. Amplifier circuit 2 according to the present embodiment is a CBSC amplifier circuit, as shown in FIG. 2, a current source _{I CP1,} a capacitor _{C 1,} and the amplification switch _{S A1,} a reset switch _{S R1,} a current source I _{CP 2} , capacitive element C ₂ , amplification switch S _A2 , reset switch S _R2 , comparator 21, and reset control circuit 22 are provided.

The current source I _CP1 (first current source) is a constant current source having one end connected to the ground and the other end connected to the capacitive element C ₁ via the amplification switch S _A1 . Current source _{I CP1} supplies current _{I CP1} may be a constant or may be variable.

The capacitive element C ₁ (first integration capacitor) is connected between the current source I _CP1 and the voltage source V _CM1 (first voltage source). Capacitance value C ₁ of the capacitor C ₁ may be a fixed value or may be variable. Voltage source _{V CM1} is a constant voltage source for supplying a bias voltage _{V CM} of the input voltage _{V PIX.} In FIG. 2, the voltage source V _CM1 is a power source for the amplifier circuit 2, but a voltage source V _CM1 may be provided separately from the power source. Capacitive element _{C 1} functions as an integration capacitor for integrating the current _{I CP1.}

The amplification switch S _A1 (first amplification switch) is connected between the current source I _CP1 and the capacitive element C _1, and the opening / closing thereof is controlled by the amplification signal φ _AMP output from the comparator 21. When the amplification switch S _A1 is turned on, the current source I _CP1 and the capacitive element C ₁ are connected, and the current I _CP1 is supplied to the capacitive element C ₁ . Hereinafter, a connection point between the capacitive element C ₁ and the amplification switch S _A1 is referred to as a node N ₁ (first connection point), and a voltage at the node N ₁ is referred to as a voltage V _FB . The voltage _VFB is input to one input terminal of the comparator 21 as a reference voltage.

The reset switch S _R1 (first reset switch) is connected between the node N ₁ and the voltage source V _CM2 (second voltage source), and is controlled to open and close by a reset signal φ _RST1 output from the reset control circuit 22. Is done. Voltage source _{V CM2,} a voltage source _{V CM2} is a constant voltage source for supplying a bias voltage _{V CM} of the input voltage _{V PIX.} When the reset switch _{S R1} is turned on, the node _{N 1} and the voltage source _{V CM2} is connected, the voltage _{V FB} at the node _{N 1} is set to the voltage _{V CM.} In FIG. 2, the voltage source V _CM2 is not shown, but the voltage source V _CM2 may be the power source of the amplifier circuit 2 as with the voltage source V _CM1 , or the voltage source V _CM2 is provided separately from the power source. May be.

Current source I _{CP2 (second} current source) is connected at one end to ground, the other end, a constant current source connected to the capacitor C ₂ through the amplifier switches S _A2. Current source _{I CP2} supplies current _{I CP2} may be a fixed value or may be variable.

The capacitive element C ₂ (second integration capacitor) is connected between the current source I _CP2 and the voltage source V _CM3 (third voltage source). Capacitance value C ₂ of the capacitor element C ₂ may be a fixed value or may be variable. The voltage source V _CM3 is a constant voltage source that supplies a bias voltage V _CM of the input voltage V _PIX . In FIG. 2, the voltage source V _CM3 is the power source of the amplifier circuit 2, but the voltage source V _CM3 may be provided separately from the power source. Capacitive element _{C 2} functions as an integration capacitor for integrating the current _{I CP2.}

The amplification switch S _A2 (second amplification switch) is connected between the current source I _CP2 and the capacitive element C _2, and the opening / closing thereof is controlled by the amplification signal φ _AMP output from the comparator 21. When the amplification switch S _A2 is turned on, the current source I _CP2 and the capacitive element C ₂ are connected, and the current I _CP2 is supplied to the capacitive element C ₂ . Hereinafter, a connection point between the capacitive element C ₂ and the amplification switch S _A2 is referred to as a node N ₂ (second connection point), and a voltage at the node N ₂ is referred to as a voltage V _SIG . This voltage V _SIG is output as the output voltage of the amplifier circuit 2.

The reset switch S _R2 (first reset switch) is connected between the node N ₂ and the voltage source V _CM4 (fourth voltage source) and controls opening and closing by a reset signal φ _RST2 output from the reset control circuit 22. Is done. The voltage source V _CM4 is a constant voltage source that supplies a bias voltage V _CM of the input voltage V _PIX . When the reset switch _{S R2} is turned on, and the node _{N 2} and the voltage source _{V CM4} is connected, the voltage _{V SIG} of the node _{N 2} is set to the voltage _{V CM.} In FIG. 2, the voltage source V _CM4 is not shown, but the voltage source V _CM4 may be the power source of the amplifier circuit 2 as with the voltage source V _CM3 , or the voltage source V _CM4 is provided separately from the power source. May be.

The comparator 21 receives the voltage V _FB of the node N ₁ from one input terminal, receives the input voltage V _PIX of the amplifier circuit 2 from the other input terminal, and determines the magnitude of the voltage V _PIX and the voltage V _FB. Compare. The comparator 21 outputs an amplification signal φ _AMP corresponding to the comparison result between the voltage V _PIX and the voltage V _FB and opens and closes the amplification switches S _A1 and S _A2 . The amplified signal _φAMP is a binary signal that is turned on or off. When the amplified signal _φAMP is turned on, the amplification switches S _A1 and S _A2 are turned on, and when the amplified signal _φAMP is turned off, the amplification switch S _A1 is turned on. , S _A2 is turned off. When the voltage V _PIX and the voltage V _FB are different, the amplified signal φ _AMP is turned on, and when the voltage V _PIX and the voltage V _FB coincide with each other, the amplified signal φ _AMP is turned off.

The reset control circuit 22 outputs reset signals φ _RST1 and φ _RST2 to open and close the reset switches S _R1 and S _R2 . The reset signal phi _RST1, phi _RST2 is a binary signal on or off, a reset signal phi _RST1, phi _RST2 and amplification becomes ON switch _{S R1, S R2} is turned on, a reset signal phi _RST1, phi _{When RST2} is turned off, the reset switches S _R1 and S _R2 are turned off. The on / off timing of the reset signals φ _RST1 and φ _RST2 will be described later.

Next, the operation of the amplifier circuit 2 according to the present embodiment will be described with reference to FIG. FIG. 3 is a diagram illustrating operation waveforms of the amplifier circuit according to the present embodiment. Hereinafter, it is assumed that the amplifier circuit 2 amplifies the signal component of V _PIX , that is, the difference between the voltage V _CM and the voltage V _PIX . Voltage _{V CM} and the voltage _{V PIX, V FB,} the difference between the _{V SIG,} respectively referred to as a voltage _{v PIX, v FB, v SIG} . The reset signals φ _RST1 and φ _RST2 are collectively referred to as a reset signal φ _RST .

First, before the amplification operation is started, the amplification signal _φAMP is off and the reset signal _φRST is on. That is, the switches S _A1 and S _A2 are off and the switches S _R1 and S _R2 are on. Therefore, the nodes N ₁ and N ₂ are connected to the voltage sources V _CM2 and V _CM4 , respectively, and the voltages V _FB and V _SIG are set to the voltage V _CM .

When the voltages V _FB and V _SIG are set to the voltage V _CM , the amplification operation is started, the amplification signal φ _AMP is turned on, and the reset signal φ _RST is turned off. That is, the switches S _A1 and S _A2 are turned on and the switches S _R1 and S _R2 are turned off.

Thus, the capacitor C ₁ is connected to a current source I _CP1, one end of the voltage of the capacitor C _1, i.e., the voltage V _FB becomes ramp descending in proportion to time. _Assuming that the time required for the voltage V _FB to decrease from V _CM to V _PIX is T, the voltage v _FB after the time T from the start of the amplification operation is expressed by the following equation.

Similarly, connected to the capacitive element C ₂ and the current source I _CP2, the voltage at one end of the capacitive element C _2, i.e., the voltage V _SIG is a ramp descending in proportion to time. The voltage v _SIG after time T from the start of the amplification operation is expressed by the following equation.

Comparator 21, and the elapsed time T, when the voltage _{V PIX} and the voltage _{V FB} match, to turn off the amplified signal phi _AMP. As a result, the amplification switches S _A1 and S _A2 are turned off, the capacitive elements C ₁ and C ₂ are disconnected from the current sources I _CP1 and I _CP2, and the lowering of the voltages V _FB and V _SIG ends. Therefore, the output voltage v _SIG and the amplification gain A amplified by the amplifier circuit 2 are expressed by the following equations from the above equations (1) and (2).

As shown above equation (4) is, the gain A of the amplifier circuit 2, a capacitor _C 1, _{C 2} of the capacitance value _C 1, _{C 2,} the current source _{I CP1, I CP2} current value _{I CP1,} and I _CP2, determined by. For example, when C ₁ = β × C ₂ and I _CP1 = I _CP2 are set, the gain A is β. Similarly, when C ₁ = C ₂ and I _CP2 = β × I _CP1 , the gain A is β.

Next, the gain A when the capacitive elements C ₁ and C _{2 of the} amplifier circuit 2 have parasitic capacitance will be described. When the capacitance value of the parasitic capacitance of the capacitive element C ₁ is C _p1 and the capacitance value of the parasitic capacitance of the capacitive element C ₂ is C _p2 , the amplification gain Ap of the amplifier circuit 2 having the parasitic capacitance is expressed by the following equation. .

In general, the capacitance value of the parasitic capacitance is proportional to the capacitance value of the capacitive element. Therefore, when C _p1 = α × C 1 and C _p2 = α × C ₂ , the above equation (5) can be modified as follows.

As shown in Expression (6), in the amplifier circuit 2 according to this embodiment, the influence on the gain A due to the parasitic capacitances of the _two capacitive elements C ₁ and C ₂ is canceled, regardless of the presence or absence of the parasitic capacitances. The gain A becomes constant. This is because the capacitive element C ₁ that generates the voltage V _FB and the capacitive element C ₂ that generates the output voltage V _SIG are not connected at the same node.

On the other hand, in the conventional CBSC amplifier circuit, the capacitive element C ₁ that generates the voltage V _FB and the capacitive element C ₂ that generates the output voltage V _SIG are connected at the same node. The parasitic capacitance was synthesized, and the influence of the parasitic capacitance on the gain A could not be canceled. Here, FIG. 4 is a schematic configuration diagram showing an example of a conventional CBSC amplifier circuit. In the amplifier circuit of FIG. 4, the amplification gain A when there is no parasitic capacitance is expressed by the following equation.

That is, the gain A is determined by the capacitance values of the capacitive elements C ₁ and C ₂ . On the other hand, as shown in FIG. 4, the amplification gain Ap when the capacitive elements C ₁ and C ₂ have parasitic capacitances C _p1 and C _p2 is expressed by the following equation.

Thus, in the conventional CBSC amplifier circuit, the amplification gain A changes due to the influence of the synthesized parasitic capacitance, and a gain error as shown in Expression (11) occurs. When C _p1 = α × C 1 and C _p2 = α × C ₂ , the gain error is α.

FIG. 5 is a graph showing a circuit simulation result of gain error between the amplifier circuit 2 according to this embodiment shown in FIG. 2 and the conventional CBSC amplifier circuit shown in FIG. In FIG. 5, the vertical axis represents the gain error (%), and the horizontal axis represents the gain setting value. In this simulation, the amplification gain A is set by the capacitance ratio (I _CP1 = I _CP2 ), and the gain error in each case of C ₁ / C ₂ = 2, 4, 8, 16, 32 is shown. .

As a result of the simulation, as shown in FIG. 5, a gain error of up to 21% occurs in the conventional amplifier circuit, whereas only a gain error of up to 0.7% occurs in the amplifier circuit 2 according to the present embodiment. It was.

As described above, according to the amplifier circuit according to the present embodiment, the influence of parasitic capacitance can be suppressed, and the gain error can be greatly reduced as compared with the conventional amplifier circuit. Thereby, an input signal can be amplified with high accuracy. Further, by using MOS capacitors as the capacitive elements C1 and C2, the circuit area can be reduced. In the conventional amplifier circuit, a gain error has occurred due to the influence of the parasitic capacitance. Therefore, when a MOS capacitor having a large parasitic capacitance is used, there is a risk that the amplification accuracy may be reduced. Thus, a highly accurate amplifier circuit with a small gain error due to the above can be realized.

Further, by configuring the image sensor using such an amplifier circuit 2, the digital circuit 3 for correcting the error of the amplified signal caused by the gain error becomes unnecessary, so that the circuit of the image sensor The area can be reduced. In addition, since the analog signal output from the light receiving unit 1 can be amplified with high accuracy, the sensing accuracy of the image sensor can be improved.

In FIG. 2, the amplifier circuit 2 includes one capacitive element C <b> 1 and one capacitive element C <b> 2 as integral capacitors, but may include an integral capacitor composed of a plurality of capacitive elements as shown in FIG. 6. The amplifying circuit 2 of FIG. 6 includes a plurality of capacitive elements C _1n (n = 1 to N) connected in parallel as a first integration capacitor. Each capacitive element C _1n is connected in series with a gain control switch S _1n (n = 1 to N). The amplifier circuit 2 includes a plurality of capacitive elements C _2m (m = 1 to M) connected in parallel as a second integration capacitor. Each capacitive element C _2m is connected in series with a gain control switch S _2m (m = 1 to M). Moreover, the amplifier circuit 2 is provided with a gain control switch S _1n, the gain control circuit 23 for outputting a gain control signal phi _G for controlling the opening and closing of the S _{1 m.}

The gain control signal φ _G is a binary signal that is turned on or off. When the gain control signal φ _G is turned on, the gain control switches S _1n and S _2m are turned on, and when the gain control signal φ _G is turned off, the gain control signal φ _G is turned on. The control switches S _1n and S _2m are turned off. Gain control signal phi _G, the gain control switch _{S 1n,} is input to the _{S 2m,} it controls the opening and closing.

In the amplifier circuit 2 of FIG. 6, the capacitance value of the integrating capacitor for integrating the currents I _CP1 and I _CP2 can be made variable by controlling the opening and closing of the gain control switches S _1n and S _2m . The capacitance value of the first integration capacitor is the sum of the capacitance values of the capacitive element C _{1n with} the gain control switch S _1n turned on. The capacitance value of the second integration capacitor is the sum of the capacitance values of the capacitive element C _{2m with} the gain control switch S _2m turned on.

As shown in the equation (4), the gain A of the amplifier circuit 2 depends on the capacitance value of the integration capacitor. Therefore, the amplifier circuit 2 in FIG. 6 controls the opening and closing of the gain control switches S _1n and S _2m. Thus, the gain A can be changed to a desired value.

In FIG. 2, the amplifier circuit 2 includes one current source I _CP1 and I _CP2 as current sources. However, as illustrated in FIG. 7, each amplifier circuit 2 may include a plurality of current sources. The amplifier circuit 2 of FIG. 7 includes a plurality of current sources I _CP1n (n = 1 to N) connected in parallel, instead of the current source I _CP1 . Each current source I _CP1n is connected in series with a gain control switch S _1n (n = 1 to N). The amplifier circuit 2 includes a plurality of current sources I _CP2m (m = 1 to M) connected in parallel instead of the current source I _CP1 . Each current source I _CP2m is connected in series with a gain control switch S _2m (m = 1 to M). Moreover, the amplifier circuit 2 is provided similarly to FIG. 6, the gain control switch S _1n, the gain control circuit 23 for outputting a gain control signal phi _G for controlling the opening and closing of the S _{1 m.}

In the amplifier circuit 2 of FIG. 7, the current values I _CP1 and I _CP2 of the current integrated by the integration capacitor can be made variable by controlling the opening and closing of the gain control switches S _1n and S _2m . Current value is integrated by the first integrating capacitor is the sum of the current value of the current source I _CP1n which is gain controlled switch S _1n on. The current value is integrated by the second integrating capacitor is the sum of the current value of the current source I _CP2m which is turned on the gain control switch S _2m.

As shown in the equation (4), the gain A of the amplifier circuit 2 depends on the current value integrated by the integration capacitor. Therefore, in the amplifier circuit 2 of FIG. 7, the gain control switches S _1n and S _2m are opened and closed. By controlling, the gain A can be changed to a desired value.

Further, although the input signal is amplified by performing the amplification operation once in FIG. 3, the input signal may be amplified by repeatedly performing the amplification operation. In this case, as shown in FIG. 8, before the amplification operation is started, the amplification signal _φAMP is off and the reset signals _φRST1 and _φRST2 are on. That is, the switches S _A1 and S _A2 are off and the switches S _R1 and S _R2 are on. Therefore, the nodes N ₁ and N ₂ are connected to the voltage sources V _CM2 and V _CM4 , respectively, and the voltages V _FB and V _SIG are set to the voltage V _CM .

When the voltages V _FB and V _SIG are set to the voltage V _CM , an amplification operation is started, the amplification signal φ _AMP is turned on, and the reset signals φ _RST1 and φ _RST2 are turned off. That is, the switches S _A1 and S _A2 are turned on and the switches S _R1 and S _R2 are turned off. When the voltage V _FB matches the voltage V _PIX , the amplified signal φ _AMP is turned off and the switches S _A1 and S _A2 are turned off. Thereby, the first amplification operation is completed, and the input signal is amplified by A times as described above.

Then, turning on the reset signal phi _RST1, switch _{S R1} is turned on, the node _{N 1} is connected to the voltage source _{V CM2,} a voltage _{V FB} is set to the voltage _{V CM.} Therefore, the next amplification operation can be executed. After repeating this amplification any M times, a reset signal phi _RST2 is turned on, the voltage V _SIG is set to the voltage V _CM, the amplifiable the following input signals. V _SIG and gain Am after the amplification operation is repeated M times are expressed by the following equations.

That is, the gain Am is M times the gain A by one amplification operation. Thus, the gain A of the amplifier circuit 2 can be changed to a desired value by changing the number of times of repeating the amplification operation. The gain A of the amplifier circuit 2 may be set using any one of the above-described capacitance value, current value, and the number of amplification operations, or may be set by combining these.

(Second Embodiment)
Next, an amplifier circuit according to a second embodiment will be described with reference to FIGS. FIG. 9 is a schematic configuration diagram showing the amplifier circuit 2 according to the present embodiment. As shown in FIG. 9, the amplifier circuit 2 according to the present embodiment further includes a control voltage generator 24. Other configurations are the same as those of the first embodiment.

In the description of the first embodiment, it is assumed that the comparator 21 inverts the output (amplified signal) at the same time that the voltage V _FB matches the voltage V _PIX during the amplification operation. However, in the actual comparator 21, there is a delay from when the voltage V _FB matches the voltage V _PIX until the output is inverted. When a delay occurs in the comparator 21, as shown in FIG. 10, the output voltage V _{SIG further} drops by the delay time t _CMP . At this time, the output voltage V _SIG is expressed by the following equation.

M (≧ 1) in Expression (14) is the number of times that the amplification operation is repeated. Hereinafter, the second term of Equation (14) is referred to as an overshoot voltage v _OS . When a delay occurs in the comparator 21, V _SIG decreases by the amount of the overshoot voltage v _OS , and the accuracy of the gain A decreases. In addition, when a current mirror circuit is used as the current source _ICP2 , if V _SIG decreases too much, the operating region of the MOSFET changes from the saturation region to the linear region, and the accuracy of the current mirror decreases. For this reason, problems such as deterioration of the linearity of gain A and gain error occur. Further, since the range of v _SIG is increased by v _OS , it is necessary to design a wide input voltage range of the AD converter 3 connected to the subsequent stage of the amplifier circuit 2. In order to avoid such a problem, it is important to reduce the overshoot voltage v _OS generated by the delay of the comparator 21.

Therefore, in order to reduce the overshoot voltage v _OS , the control voltage generator 24 of this embodiment uses the voltage V _SIG of the node N ₂ set to the voltage V _CM by the voltage source V _CM4 as a delay of the comparator 21. The control voltage v _CTRL corresponding to the time is increased. Thereby, the amplified output voltage v _SIG is expressed by the following equation.

Therefore, by setting the control voltage v _CTRL so that v _CTRL = −v _OS , the overshoot voltage v _OS can be reduced, the accuracy of the gain A can be improved, and the input voltage range of the AD converter 3 can be reduced. It becomes.

Here, FIG. 11 is a schematic configuration diagram illustrating an example of the control voltage generator 24. As shown in FIG. 11, the control voltage generator 24 includes voltage generation switches S _OS1 to S _OS6 and a capacitance switching control circuit 25. In FIG. 11, the reset control circuit 22 is not shown.

The voltage generation switch S _OS1 is in parallel with the voltage generation switch S _OS2 between the voltage source (for example, the light receiving unit 1) that inputs the input voltage V _PIX to the amplifier circuit 2 and the other input terminal of the amplifier circuit 2. Connected. The voltage generation switch S _OS2 is connected between the other input terminal of the comparator 21 and the voltage source _VCM2 .

Voltage generation switch _{S OS3} is connected between the capacitive element _{C 2} and the node _{N 2.} Voltage generation switch _{S OS4} is between the connection point and the voltage source _{V CM3} of the capacitor _{C 2} and the voltage generation switch _{S OS3,} is connected in parallel with the voltage generator switch _{S OS3.}

Voltage generation switch _{S OS5} is connected between the voltage source _{V CM3} and the capacitor _{C 2.} Voltage generation switch _{S OS 6} is provided between the connection point and the node _{N 2} of the capacitor _{C 2} and the voltage generation switch _{S OS5,} is connected in parallel with the voltage generator switch _{S OS5.}

The capacitance switching control circuit 25 outputs a switching signal φ _OS that controls the opening and closing of the voltage generating switches S _OS1 to S _OS6 . The switching signal φ _OS is a binary signal that is turned on or off. When the switching signal φ _OS is turned off, the voltage generation switches S ₁ , S ₃ , S ₅ are turned on, and the voltage generation switches S ₂ , S ₄ are turned on. , S ₆ is turned off. When the switching signal phi _OS is on voltage generation switch _{S 2, S 4, S 6} is turned on, the voltage generating switches _{S 1,} S 3, _{S 5} is turned off.

In this amplifying circuit 2, before the input voltage V _PIX is amplified, the voltage V _CM is input instead of the voltage V _PIX to perform an amplifying operation. That is, the amplifier circuit 2, the capacitance switching control circuit 25 executes the aforementioned amplification operation while turning on the switching signal phi _OS. At this time, the voltage generating switch S ₂ because it is on, the voltage V _CM is input from the two input terminals to the comparator 21. Since the two input voltages match, the comparator 21 turns off the amplification signal _φAMP and turns off the amplification switches S _A1 and S _A2 after the delay time t _CMP . As a result, the voltage V _SIG drops from the voltage V _{CM by} a voltage corresponding to the delay time t _CMP . Further, since the voltage generation switches S ₄ and S ₆ are turned on, the polarity of the capacitive element C ₂ is opposite to the case where the input voltage V _PIX is amplified. The voltage v _SIG after the amplification operation of the voltage V _CM is repeated M times is expressed by the following equation.

That is, the capacitive element _{C 2} is charged by the voltage overshoot _{v OS.} Thereafter, when the capacitor switching control circuit 25 turns off the switching signals phi _OS, voltage generation switch _{S 2, S 4, S 6} is turned on, the polarity of the capacitor _{C 2} is _reversed, and v SIG = _{-v OS} Become. Thereby, as shown in FIG. 12, the voltage V _SIG of the node N ₂ can be set higher than the V _CM by the control voltage v _CTRL (= −v _OS ).

After the voltage V _SIG is set by the control voltage generator 24, when the amplification operation of the input voltage V _PIX is repeated M times, the term v _OS + v _CTRL in the equation (15) is canceled, so that the overshoot voltage v _OS The influence can be suppressed.

Since the actual comparator 21 has an offset voltage, an error may occur in the voltage V _SIG due to the offset voltage. However, when the amplifier circuit 2 is used in a CMOS image sensor, such an error can be suppressed by CDS (correlated double sampling). CDS is a method of amplifying a difference between the output voltage V _{PIX_REF} in a state where the light receiving unit 1 is reset to a reference voltage and the output voltage V _PIX in a state in which the light receiving unit 1 accumulates charges by light irradiation. .

For example, the CDS performs the amplification operation by inputting the voltage V _{PIX_REF} via the switch S _OS2 , then reverses the polarity of the capacitive element C2, and inputs the voltage V _PIX via the switch S _OS1 to perform the amplification operation. It can be realized by doing. In other words, the voltage V _{PIX_REF} may be input instead of the voltage V _CM input via the switch S _OS2 in the present embodiment. Thereby, an error of the output voltage V _SIG due to the offset voltage of the comparator 21 can be suppressed.

(Third embodiment)
Next, an amplifier circuit according to a third embodiment will be described with reference to FIGS. FIG. 13 is a schematic configuration diagram showing the amplifier circuit 2 according to the present embodiment. As shown in FIG. 13, the amplifier circuit 2 further includes a current source switch 26. Other configurations are the same as those of the first embodiment.

When a current mirror circuit is used as the current sources I _CP1 and I _CP2 , an error may occur between the current values I _CP1 and I _CP2 due to variations in the threshold voltage, channel length, channel width, and the like of the MOSFET. As shown in the equation (4), the gain A of the amplifier circuit 2 depends on the current values of the current sources I _CP1 and I _CP2 , so that an error in the current value causes a gain error.

For example, when there is a current error ΔI _CP in the current value (I _CP2 −I _CP1 = ΔI _CP ), the gain A _CP and the gain error of the amplifier circuit 2 can be calculated from Equation (4) as follows.

That is, the ratio ΔI _CP / I _CP1 between the current value and the current error becomes a gain error. Such errors can be reduced by increasing the channel length and channel width of the MOSFET, but there is a problem that the circuit area increases.

Therefore, in order to reduce the gain error due to the variation in the current value, the amplifier circuit 2 according to the present embodiment repeats a plurality of amplification operations to amplify the voltage v _PIX , and the current source switch 26 performs the amplification operation. Each time the current sources I _CP1 and I _CP2 are switched alternately. As shown in FIG. 13, the current source switch 26 includes changeover switches S _CP1 and S _CP2 and a current source switching control circuit 27.

The changeover switch S _CP1 is a switch that switches the connection of the current source I _CP1 between the amplification switch S _A1 and the amplification switch S _A2 . The change-over switch S _CP2 is a switch that switches the connection of the current source I _CP2 between the amplification switch S _A2 and the amplification switch S _A1 .

The current source switching control circuit 17 outputs a switching signal φ _CP that controls switching of the connection by the switches S _CP1 and S _CP2 . The switching signal φ _CP is a binary signal that is on or off. Changeover switch _{S CP1} is switched signal phi _CP is connected to the turned on and the current source _{I CP1} and amplification switches _{S A1,} the switching signal phi _CP is connected to the turned off the current source _{I CP1} and amplification switches _{S A2.} The changeover switch S _CP2 connects the current source I _CP2 and the amplification switch S _A2 when the change signal φ _CP is turned on, and connects the current source I _CP2 and the amplification switch S _A1 when the change signal φCP is turned off.

The current source switching control circuit 17 switches the connection of the current sources I _CP1 and I _CP2 by switching the switching signal φ _CP on and off every time the amplification operation is completed. For example, when the current source switching control circuit 17 turns on the switching signal φ _CP in the odd-numbered amplification operation and turns off the switching signal φ _CP in the even-numbered amplification operation, the gain A _ODD and The gain A _EVEN in the even-numbered amplification operation is expressed by the following equation.

The gain A _TOTAL after repeating the amplification operation a plurality of times is the sum of the gains in each amplification operation, as shown in FIG. Accordingly, it gains _{A TOTAL_EVEN} after the gain _{A TOTAL_ODD} and amplification operation after the amplifying operation was repeated odd repeated an even number of times is expressed by the following equation.

Here, assuming that the current error ΔI _CP is sufficiently smaller than the current values I _CP1 and I _CP2 , the following equation is established.

Therefore, from the equations (21) to (23), A _{TOTAL_ODD} , A _{TOTAL_EVEN} , and gain errors thereof can be approximated as follows.

If the connection of the current source is not switched, a gain error proportional to the first power of ΔI _CP / I _CP1 occurs as shown in the equation (18). For example, when ΔI _CP / I _CP1 = 10%, the gain error is 10%.

On the other hand, when the connection of the current source is switched as in the present embodiment, the gain error proportional to the square of ΔI _CP / I _CP1 is finally obtained as shown in equations (26) and (27). Arise. For example, when ΔI _CP / I _CP1 = 10%, the gain error is about 0.5%. This is because the odd-numbered gain error and the even-numbered gain error are canceled. FIG. 15 shows a simulation result of the gain error of the amplifier circuit 2. In FIG. 15, the horizontal axis represents the ratio of current error, and the vertical axis represents gain error.

As described above, according to the amplifier circuit 2 according to the present embodiment, it is possible to reduce a gain error caused by variation in the current value of the current source and obtain a desired gain. Thereby, the amplification accuracy can be improved. Further, since the gain error can be reduced without increasing the channel length or channel width of the MOSFET, the circuit area can be reduced.

(Fourth embodiment)
Next, an image sensor according to a fourth embodiment will be described with reference to FIG. FIG. 16 is a schematic configuration diagram illustrating an image sensor according to the present embodiment. As shown in FIG. 16, this image sensor is a CMOS image sensor, and includes a pixel array 101, a row selection circuit 102, a readout circuit 103, and a control signal generation circuit 104. As described above, the image sensor may be configured to include the digital circuit 4.

The pixel array 101 includes a plurality of light receiving units 1 arranged in an array. The row selection circuit 102 selects a row of the light receiving unit 1 from which the voltage _VPIX is read. The read circuit 103 converts the voltage _PIX output from each light receiving unit 1 into a digital signal and outputs the digital signal. The readout circuit 103 includes a plurality of amplifier circuits 2 and AD converters 3 provided for each column of the light receiving units 1. The amplifier circuit 2 may be any of the above-described embodiments. The control signal generation circuit 104 generates various control signals used in the amplifier circuit 2 and the AD converter 3 and inputs them to the readout circuit 104. The control signals generated by the control signal generation circuit 104 include, for example, signals φ _RST , φ _G , φ _OS , φ _CP .

In this image sensor, when the pixel array 101 is irradiated with light, the row selection circuit 102 selects a row of the pixel array 101, and the voltage VPIX is output from the light receiving unit 1 of the selected row. The voltage V _PIX is input to the amplifier circuit 2 provided in each column corresponding to the light receiving unit 1. The amplifier circuit 2 outputs a voltage V _SIG obtained by amplifying the voltage V _PIX . The voltage V _SIG is input to an AD converter 3 provided in each column corresponding to the light receiving unit 1 and is digitally converted.

As described above, since the gain A is set with high accuracy, the amplifier circuit 2 does not require a complicated gain correction circuit and has a small circuit area. Therefore, the readout circuit 103 of the image sensor can be reduced in size. Further, the amplification circuit 2 and AD converter 3 provided for each column of the pixel array 101 are operated in parallel, and a signal is read for each row of the pixel array 101, so that the reading speed can be increased.

Further, since the amplification circuit 2 can easily change the gain A while suppressing the gain error, the gain A is reduced in the bright time and increased in the dark time. Thus, the output signal from the pixel array 101 is increased. The gain A can be controlled according to the signal strength. Thereby, the output signal can be amplified with an appropriate gain, and the SN of the signal can be improved.

Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. Further, for example, a configuration in which some components are deleted from all the components shown in each embodiment is also conceivable. Furthermore, you may combine suitably the component described in different embodiment.

1: light receiving unit, 2: amplifier circuit, 3: AD converter, 4: digital circuit, 21: comparator, 22: reset control circuit, 23: gain control circuit, 24: control voltage generator, 25: capacitance switching control Circuit 26: current source switch 27: current source switching control circuit 101: pixel array 102: row selection circuit 103: readout circuit 104: control signal generation circuit

Claims (7)

1. A first current source;
   A first integrating capacitor connected between the first current source and a first voltage source;
   A first amplification switch connected between the first current source and the first integration capacitor;
   A first reset switch connected between a first connection point to which the first integration capacitor and the first amplification switch are connected, and a second voltage source;
   A second current source;
   A second integrating capacitor connected between the second current source and a third voltage source;
   A second amplification switch connected between the second current source and the second integration capacitor;
   A second reset switch connected between a second connection point to which the second integration capacitor and the second amplification switch are connected, and a fourth voltage source;
   A comparator that opens and closes the first reset switch and the second reset switch according to a comparison result between an input voltage and a voltage at the first connection point;
   An amplifier circuit comprising:
2. 2. The amplifier circuit according to claim 1, wherein the comparator turns off the first amplification switch and the second amplification switch when the input voltage matches the voltage at the first connection point.
3. The amplifier circuit according to claim 1, wherein at least one of the first integration capacitor and the second integration capacitor has a variable capacitance.
4. The amplifier circuit according to any one of claims 1 to 3, wherein a current value of at least one of the first current source and the second current source is variable.
5. 5. The voltage generator according to claim 1, further comprising a voltage generator configured to increase a voltage at the second connection point set by the fourth voltage source by a voltage corresponding to a delay time of the comparator. The amplifier circuit according to item.
6. The amplifier circuit according to any one of claims 1 to 5, further comprising a current source switch that alternately switches connection between the first current source and the second current source.
7. A light receiving unit that outputs a signal corresponding to the irradiated light;
   The amplifier circuit according to any one of claims 1 to 6, which amplifies an output signal of the light receiving unit;
   An AD converter for AD converting the signal amplified by the amplifier circuit;
   An image sensor.

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