WO2015149298A1

WO2015149298A1 - Fast timing recovery in energy efficient ethernet devices

Info

Publication number: WO2015149298A1
Application number: PCT/CN2014/074606
Authority: WO
Inventors: Charlie CAI; Qing Shi; James Zhang
Original assignee: Qualcomm Incorporated
Priority date: 2014-04-02
Filing date: 2014-04-02
Publication date: 2015-10-08

Abstract

An Ethernet device is disclosed that may increase the speed of clock recovery operations by concurrently (1) using an adaptive loop filter to adjust a phase and frequency of an error signal to generate a filtered error signal and (2) adding or subtracting a fixed delay to the filtered error signal.

Description

FAST TIMING RECOVERY IN ENERGY EFFICIENT ETHERNET

DEVICES

TECHNICAL FIELD

[0001] The present embodiments relate generally to Ethernet devices, and specifically to increase the speed of timing recovery operations in Ethernet devices.

BACKGROUND OF RELATED ART

[0002] Among the technologies that allow computers and/or other network devices to form a local area network (LAN), Ethernet has become the dominant networking technology and is standardized in the IEEE 802.3 family of standards. The Ethernet standard has evolved over time so that different variants of the Ethernet protocol now exist to support higher bandwidth, improved media access controls, different physical media channels, and/or other functionalities. For example, IEEE 802.3 now has variants covering speeds (or transmission rates) ranging from 10 Mbit/s, 100 Mbit/s, 1 Gbit/s, to 10 Gbit/s and even higher, and has variants that govern physical channels such as coaxial cables, fiber-optics, and unshielded/shielded twisted-pair cables.

[0003] The IEEE 802.3 family of standards also includes the IEEE

802.3az standard, which describes Energy Efficient Ethernet (EEE), a standard designed to reduce power consumption in Ethernet devices. Because many Ethernet devices employ transceivers that may operate at very high speeds (e.g., 1 Gbit/s or 10 Gbit/s), such devices may consume a significant amount of power when transmitting and receiving data. To reduce power consumption, an EEE-compliant devicemay use a low power idle (LPI) signal to place its transceiver (or the transmit portions of the transceiver) into a low power state when there is little or no data being transmitted over an associated data link. The transceiver remains in the low power state for a duration of time commonly referred to as its "quiet period." Once the quiet period ends, the transceiver may wake up and return to the active state. [0004] Timing recovery is an important function of Ethernet systems. Because data is typically transmitted from one device to another device in an asynchronous manner (i.e., without an accompanying clock signal), the receiving (RX) device generates an internal clock signal that is both frequency- aligned and phase-aligned with the received data signal. For example, if data is transmitted by a transmitting (TX) device using a 100 MHz clock signal, the RX device would ideally use a local 100 MHz clock to sample the received data signal. However, the RX device may have to adjust the frequency of the local clock signal to correct for drift in its oscillators and/or transmission paths.

Further, the phase of the local clock signal may be adjusted so that it is aligned with the received data signal such that the RX device samples each data symbol at its peak (e.g., to reduce the effects of intersymbol interference).

[0005] As Ethernet transmission rates increase, the time period in which the Ethernet-compliant transceivers are to transition from the low power state to the active state decreases. For example, while the wake-up period for 100Base- T Ethernet transceivers is 30us, the wake-up period for 10G Base-T Ethernet transceivers is only 4.16us. Thus, as Ethernet transmission rates continue to increase, Ethernet-compliant transceivers are allotted less time to perform clock recovery and clock alignment operations during the wake-up period. As a result, there is a need to increase the speed with which Ethernet transceivers are able to perform clock recovery and clock synchronization operations.

SUMMARY

[0006] This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed

Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] In accordance with the present embodiments, an Ethernet device is disclosed that mayincrease the speed of timing recovery operations in

Ethernet devices. In accordance with the present embodiments, the Ethernet device comprises a clock recovery circuit including an analog-to-digital converter (ADC), a timing error detection circuit, an adaptive loop filter, a voltage-controlled oscillator, a configuration register, and a state machine. The adaptive loop filter may include an input terminal to receive an error signal indicative of an alignment error between a first signal and a second signal; a proportional loop path, including a proportional gain element coupled between the input terminal and a first summing circuit, to generate a phase-adjusted error signal based on a proportional loop parameter provided to the proportional gain element; an integral loop path, including an integral gain element coupled between the input terminal and the first summing circuit, to generate a frequency-adjusted error signal based on an integral loop parameter provided to the integral gain element, wherein the first summing circuit is to sum the phase- adjusted error signal and the frequency-adjusted error signal to generate a filtered error signal; a second summing circuit to generate a phase-adjusted filtered error signal by summing the filtered error signal and a selected phase step signal; and a coarse phase search circuit, coupled to an input of the second summing circuit, to selectively provide either a positive phase step signal or a negative phase step signal as the selected phase step signal to the second summing circuit.

[0008] For some embodiments, the positive phase step signal is to add a fixed delay to the filtered error signal, and the negative phase step signal is to subtract the fixed delay from the filtered error signal. For example, for at least one embodiment, the positive phase step signal is to add a fixed delay to the filtered error signal when phase of the first signal leads the phase of the second signal, and the negative phase step signal is to subtract the fixed delay from the filtered error signal when phase of the first signal leads the phase of the second signal.

[0009] For some embodiments, the coarse phase search circuit includes a multiplexer (MUX) including a first input to receive the positive phase step signal, a second input to receive the negative phase step signal, a control terminal to receive a select signal, and an output to provide the selected phase step signal to the second summing circuit. The select signal may be based on a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link. The coarse phase search circuit may also include a pass gate including a first terminal coupled to the output terminal of the MUX, including a second terminal coupled to the input terminal of the second summing circuit, and including a control terminal to receive an enable signal, wherein the enable signal is based upon a weighted minimum-mean square error (MMSE) signal indicative of channel and

interference estimation of an associated data link.

[0010] An exemplary operation of the adaptive loop filter may be described as follows: generating an error signal based a recovered timing signal from a second Ethernet device; generating a phase-adjusted error signal based on the error signal and a proportional loop parameter; generating a frequency- adjusted error signal based on the error signal and an integral loop parameter; summing the phase-adjusted error signal and the frequency-adjusted error signal to generate a filtered error signal; and combining a fixed phase delay with the filtered error signal to adjust a phase of the filtered error signal. For some embodiments, the combining may comprise: providing a positive phase step signal to a multiplexer (MUX); providing a negative phase step signal to the MUX; selecting either the positive phase step signal or the negative phase step signal based on a select signal; when the positive phase step signal is selected, adding the fixed phase delay from the filtered error signal; and when the negative phase step signal is selected, subtracting the fixed phase delay from the filtered error signal.

[0011] For at least some embodiments, the operation may further comprise: receiving a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link; comparing the weighted MMSE signal with a first threshold; when the weighted MMSE signal is less than the first threshold, allowing the combining; and when the weighted MMSE value is not less than the first threshold, preventing the combining. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present embodiments are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings, where like reference numerals refer to corresponding parts throughout the drawing figures.

[0013] FIG. l is a block diagram of a systemwithin which the present embodiments may be implemented.

[0014] FIG. 2 is a timing diagram depicting state transitions associated with Energy Efficient Ethernet (EEE) devices.

[0015] FIG. 3 is a block diagram of the open system interconnection (OSI) model representative of the network-enabled devices of FIG. 1.

[0016] FIG. 4A is a block diagram of the network-enabled devicesof FIG. 1 in accordance with some embodiments.

[0017] FIG. 4B is a simplified block diagram of an exemplary analog front-end (AFE) circuit in accordance with some embodiments.

[0018] FIG. 5A is a block diagram depicting transceivers of the network- enabled devices of FIG. 1 coupled to each other, in accordance with some embodiments.

[0019] FIG. 5B is a block diagram of the clock recovery circuit of FIG. 5Ain accordance with some embodiments.

[0020] FIG. 6A is block diagram of an adaptive loop filter in accordance with some embodiments.

[0021] FIG. 6B is block diagram of an adaptive loop filter in accordance with other embodiments.

[0022] FIG. 7 is an illustrative flow chart depicting an exemplary wake-up operation in accordance with some embodiments.

[0023] FIG. 8 is an illustrative flow chart depicting an exemplary clock recovery operation a network-enabled device in accordance with some embodiments. [0024] FIG. 9 is an illustrative flow chart depicting an exemplary clock recovery operation a network-enabled device in accordance with other embodiments.

[0025] FIG. 10 is another block diagram of the network-enabled devices of FIG. 1 in accordance with some embodiments.

DETAILED DESCRIPTION

[0026] The present embodiments are described below in the context of an Ethernet device for simplicity only. It is to be understood that the present embodiments may be implemented in any suitable network device that may operate according one or more other communication protocols. In the following description, numerous specific details are set forth such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. The term "coupled" as used herein means connected directly to or connected through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present embodiments. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the present embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the present disclosure. Any of the signals provided over various buses described herein may be time-multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components. The present

embodiments are not to be construed as limited to specific examples described herein but rather to include within their scopes all embodiments defined by the appended claims. [0027] FIG. 1 is a block diagram of an exemplary communication system 100 within which the present embodiments may be implemented.

Communication system 100 is shown to include two network devices 110(a) and 110(b), which are coupled to each other by an established data link 120. For purposes of discussion, network device 110(a) is referred to herein as the master device 110(a), and network device 110(b) is referred to herein as the slave device 110(a). It is to be understood that, for other embodiments, network devices 110(a) and 110(b) may operate as other than a master device and a slave device, respectively.

[0028] Devices 110(a) and 110(b) may be any suitable network-enabled devices including, for example, computers, switches, routers, hubs, gateways, access points, or the like. Also, according to the present embodiments, devices 110(a) and 110(b) may include any electronic device capable of connecting to either a wired or a wireless network including, for example, a mobile phone, a personal digital assistant (PDA), a set-top box, or a game console. Note that devices 110(a) and 110(b) and data link 120 are exemplary components of a network, and the network may further include any number of suitable devices to form a larger network including, for example, a local area network (LAN), a wide area network (WAN), a wireless LAN (WLAN), and/or may be connected to the Internet. Data link 120 may be any suitable physical media including, for example, coaxial cables, fiber-optic cables, and/or unshielded/shielded twisted pairs.

[0029] Devices 110(a)-110(b) may communicate with each other using Ethernet technologies, as described in the IEEE 802.3 family of standards. More specifically, for exemplary embodiments described herein, devices 110(a)- 110(b) are each equipped with Ethernet-compliant transceivers (not shown in FIG. 1 for simplicity) that may be capable of transmitting and receiving data at speeds of 1 Gbit/s or 10Gbit/s, and may be backwards compatible to operate at slower speeds, for example, 100 Mbit/s or 10 Mbit/s. Furthermore, devices 110(a)-110(b) may be capable of reducing the power consumption of their transceivers when not transmitting any data in a manner that is compliant with the IEEE 802.3az standards (EEE). [0030] As mentioned above, as Ethernet transmission rates increase, the time period in which an Ethernet-compliant device's transceivers are to wake-up decreases. Referring to the timing diagram 200 of FIG. 2, EEE-compliant devices typically perform data transmit and data receive operations during the active state. To reduce power consumption, anEEE-compliant device may place its transceiver (or the transmit portions of the transceiver) into a low power state when there is little or no data being transmitted over an associated data link. The transceiver may transition from the active state to a sleep state for a sleep period (denoted as Ts), and may then transition from the sleep state to the quiet state for a quiet period (denoted as Tq). The quiet period corresponds to a low power state during which power consumption of the EEE-compliant device is at a minimum.

[0031] The EEE-compliant devicemay periodically transmit during the quiet periodto allow another EEE-compliant device to refresh its receiver state (e.g. for timing recovery, to update adaptive filter coefficients, and so on). These short periods of activity (not during the active state) are known as refresh periods (denoted as Tr). Once the quiet period ends, the EEE-compliant device's transceiver may wake up and return to the active state. During the wake-up period (denoted as Tw), the receiver portions of the transceiver may perform clock recovery operations (e.g., to ensure that the receiver's clock signal is aligned with the channel conditions and synchronized with other EEE- compliant devices connected to an associated data link).

[0032] Referring also to FIG. 1 , if the slave device 110(b) desires to wake-up from the quiet state, the slave device 110(b)'s receiver components are to complete clock recovery and clock alignment operations within the wake- up period Tw. According to the IEEE802.3az standards, the wake-up period Twfor 100Base-TX systems is 30 us, the wake-up period Tw for 1000Base-T systems 16 us, and the wake-up period Tw for 10G Base-T systems is 4.16us. Therefore, as Ethernet transmission rates increase, corresponding EEE- compliant devices (such as master device 110(a) and slave device 110(b) of FIG. 1) have less time to perform clock recovery and clock alignment operations when transitioning from the quiet state to the active state.Thus, it is desirable to reduce the time associated with performing clock recovery and clock alignment operations in EEE-compliant devices.

[0033] FIG. 3 is a block diagram of the open system interconnection (OSI) model 300 representative of the devices 110(a)-110(b) of FIG. 1. As depicted in FIG. 3, the OSI model 700 is divided into seven logical layers: an application layer (L7); a presentation layer (L6); a session layer (L5); a transport layer (L4); a network layer (L3); a datalink layer (L2); and a physical layer (L1). Although the OSI model 300 may be used to represent devices 110(a)-110(b) for purposes of discussion herein, it is noted that other suitable models may be used to represent Ethernet devices configured in accordance with the present embodiments.

[0034] The higher in hierarchy an OSI layer is, the closer it is to an end user; the lower in hierarchy an OSI layer is, the closer it is to a physical channel. For example, on the top of the OSI model hierarchy is the application layer, which interacts directly with the end user's software application (not shown in FIG. 3 for simplicity). On the contrary, on the bottom of the OSI model hierarchy is the physical layer, which defines the relationship between a network device and a physical communication medium, such as twisted-pairs for Ethernet data transmissions.

[0035] More specifically, the physical layer provides electrical and physical specifications, including details like pin layouts and signal voltages, for interactions between its host (e.g., device 110(a)) and the physical channel (e.g., link 120). The datalink layer provides the functional and/or procedural details, such as addressing and channel access control mechanisms, for data

transmissions between devices 110(a)-110(b). The datalink layer includes two sub-layers, which are the logical link control (LLC) layer on the top (in terms of hierarchy), and the MAC layer on the bottom. For simplicity, the datalink layer is sometimes referred to herein as the MAC layer in the following discussion.

Further, although not shown for simplicity in FIG. 3, an interface exists between the MAC layer and the physical layer to facilitate the exchange of information between the two layers. This interface is commonly referred to as a media independent interface (MM) because the MAC layer is agnostic as to the physical medium used for transmission. As used herein, the terms "media access interface" and "MM" refer to the entire genus of such interfaces, unless otherwise noted. Examples of Mils include Attachment Unit Interface (AUI), MM, Reduced MM, Gigabit MM (GMII), Reduced GMII, Serial GMII (SGMII), Quad SGMII (QSGMII), 10GMII, and Source Synchronous Serial MM (S3MII). The MM allows devices 110(a)-110(b) to interface with different types of physical channels or data links (e.g., Iink120) without replacing their MAC devices.

[0036] FIG. 4Aillustrates an Ethernet device 400 that may be one embodiment of master device 110(a) and/or slave device 110(b) of FIG. 1.

Device 400 includes a PHY device 410, a MAC device 450, an MM 415, and a plurality of ports P1-Pn. PHY device 410 and MAC device 450 are coupled together by MM 415, which may be any suitable MM (e.g., a SGMII). MAC device 450 is responsible for generating (e.g., asserting and de-asserting) the LPI signal, and exchanges data with PHY device 410 via the MM 415. Ports P1-Pn are coupled to communication links 402(1 )-402(n), respectively.

[0037] PHY device 410includes a transceiver 420 and an LPI control circuit 430. Transceiver 420 includes a baseband processor 440 and a plurality of analog front end (AFE) circuits 422(1 )-422(n), each of which may be coupled to a respective one of communication Iinks402(1)-402(n) via a respective one of ports P1-Pn, as depicted in FIG. 4A. For exemplary embodiments described herein, transceiver 420may be compatible with the 10Base-T, 100BASE-T, 1000BASE-T, and/or 10G Base-T standards (or similar standards), and each of communication Iinks402(1)-402(n) may include four twisted pairs of a cable (e.g., a Category 5 cable). Thus, for exemplary embodiments described herein, each of AFE circuits422(1)-422(n) may support four communication channels associated with each of respective communication links 402(1 )-402(n) (although for other embodiments, one or more of AFE circuits422(1)-422(n) may support other numbers of communication channels). For some embodiments, the communication links 402(1 )-402(n) may correspond to data link 120 of FIG. 1.

[0038] The LPI control circuit 430 includes an input to receive an LPI signal from MAC device 450, and includes a set of outputs to generate a plurality of control signals C1-Cn. Each of the control signals C1-Cn is provided to a respective one of AFE circuits 422(1 )-422(n) to selectively power-off and/or power-on a number of components therein (e.g., in response to assertion of the LPI signal).

[0039] Each of the AFE circuits 422(1 )-422(n) may include a plurality of well-known components including, for example, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), filters, mixers, amplifiers, clock recovery circuitry, and so on. More specifically, for exemplary embodiments described herein, each of AFE circuits 422(1 )-422(n) may include four pairs of DACs and ADCs, wherein each pair of DACs and ADCs may be coupled to a corresponding one of the four channels of a respective one of communication links 402(1 )-402(n). For example, FIG. 4B shows an exemplary AFE circuit 422 coupled to an associated communication link 402. AFE circuit 422is shown to include four transceiver chains 1-4. Transceiver chain 1 includes a first ADC (ADC1) and a first DAC (DAC1) coupled to a first channel (CH1) of link 402 via a first switch (SW1). Transceiver chain 2 includes a second ADC (ADC2) and a second DAC (DAC2) coupled to a second channel (CH2) of link 402 via a second switch (SW2). Transceiver chain 3 includes a third ADC (ADC3) and a third DAC (DAC3) coupled to a third channel (CH3) of link 402 via a third switch (SW3). Transceiver chain 4 includes a fourth ADC (ADC4) and a fourth DAC (DAC4) coupled to a fourth channel (CH4) of link 402 via a fourth switch (SW4). Each of ADC1-ADC4 provides signals to baseband processor 440, and each of DAC1-DAC4 receives signals from baseband processor 440. The switches SW1-SW4, which may be implemented within the AFE 422or in the port, may selectively couple each of channels CH1-CH4 to either the ADC (e.g., during receive operations) or the DAC (e.g., during transmit operations) of the corresponding transceiver chain.

[0040] AFE circuit 422 is also shown to receive a plurality of control signals C(1)-C(4), which may be generated by the LPI control circuit 430 of FIG. 4A. The control signals C(1)-C(4), which together may form one of the control signals C1-Cn of FIG. 4A, are provided to respective transceiver chains 1-4. For some embodiments, assertion of a given one of control signalsC(1)-C(4) may power-off the DAC and ADC of the corresponding transceiver chain, and de- assertion of the given one of control signals C(1)-C(4) may power-on the DAC and ADC of the corresponding transceiver chain. [0041] FIG. 5A is a block diagram 500 depicting clock recovery circuitry within the master device 110(a) and the slave device 110(b), in accordance with some embodiments. The master device 110(a) is shown to include a transceiver 510(a) including a transmit amplifier 502(a), a receive amplifier 504(a), and a clock recovery circuit 520(a). The transmit amplifier 502(a) may receive transmit (Tx) data from a baseband processor (not shown for simplicity) of master device 110(a), and may output the Tx data to the slave device 110(b) via the link 202. The receive amplifier 504(a) may receive data from slave device 110(b)via the link 202, and may output the data as receive (Rx) data to the baseband processor (not shown in FIG. 5A for simplicity) of the master device 110(a).

The clock recovery circuit 520(a) may receive a master clock signal (CLK M) from an oscillator (not shown for simplicity) of the master device 110(a), may receive the Rx data from the slave device 110(b), and in response thereto may adjust the phase (and/or frequency) of CLK M. The clock recovery circuit 520(a) may provide CLK Mto the transmit amplifier 502(a) and to the receive amplifier 504(a) of the master device 110(a).

[0042] The slave device 110(b) is shown to include a transceiver 510(b) including a transmit amplifier 502(b), a receive amplifier 504(b), a clock recovery circuit 520(b), and a first-in, first-out (FIFO)buffer 506. The transmit amplifier 502(b) may receive Txdata from FIFO 506, and may output the Tx data to the master device 110(a)via the link 202. The FIFO 506 may receive the Tx data from a baseband processor (not shown for simplicity) of slave device 110(b), and may receive a slave clock signal (CLK S) from an oscillator (not shown in FIG. 5A for simplicity) of the slave device 110(b). The receive amplifier 504(b) may receive data from master device 110(a)via the link 202, and may output the data as Rx data to the baseband processor (not shown for simplicity) of the slave device 110(b). The clock recovery circuit 520(b) may receive data from the master device 110(a)via the link 202, and in response thereto may adjust the phase and/or frequency of CLK S. The clock recovery circuit 520(b) may provide CLK Sto the transmit amplifier 502(b) and to the receive amplifier 504(b) of the slave device 110(b).

[0043] FIG. 5B is a block diagram of the clock recovery circuit 520 in accordance with some embodiments. The clock recovery circuit 520, which may be used as the clock recovery circuit 520(a) of the master device 1 10(a) and/or as the clock recovery circuit 520(b) of the slave device 1 10(b), is shown to include an analog-to-digital converter (ADC) 521 , a timing error detection (TED) circuit 522, an adaptive loop filter523, a voltage-controlled oscillator 524, a configuration register 525, and a state machine 526. For purposes of illustration, the clock recovery circuit 520 of FIG. 5B is discussed below in the context of being used as the clock recovery circuit 520(b) of the slave device 1 10(b), although for at least some embodiments, the clock recovery circuit 520 of FIG. 5B may be used as the clock recovery circuit 520(a) of the master device 1 10(a) (or other suitable Ethernet-compliant devices).

[0044] In operation, the ADC 521 receives an analog data signal from the master device 1 10(a). The analog data signal may contain a training sequence (TS) signal provided by the master device 1 10(a). Using the clock signal CLK vcogenerated by the VCO 524, the ADC 521 may sample the analog data signal, for example.to recover the TS signalprovided by the master device 1 10(a). The recovered TS signal may be provided as a digital signal to the TED circuit 522. The TED circuit 522, which may be any suitable timing error detection circuit, generates an error signal in response to the recovered TS signal provided by the ADC 521. For at least some embodiments, the TED circuit 522 may correspond to a Mueller-Muller timing error detection circuit, wherein the timing error (X) may be calculated as:

XN = TSRN*TDR(N-I) - TSR(N-I)*TDRN

whereTS_R is the recovered training sequence, TD_Ris a hard decision of TS_R (e.g., generated from TSR by a well-known hard decision logic, not shown for simplicity), N represents the current bit of a corresponding training sequence (TSs or TS_R), and N-1 represents the previous bit of the training sequence (e.g., the bit associated with a previous clock cycle).

[0045] The error signal may be filtered by the adaptive loop filter 523, which in turn provides a filtered error signal (e.g., as a control signal) to the VCO 524. The configuration register 525, which may be any suitable memory resource or storage element, includes an input to receive a control (CTRL) signal, and includes outputs coupled to corresponding inputs of the adaptive loop filter 523. More specifically, the configuration register 525 may provide a select (SEL) signal and loop parameters (Kp and Ki) to adaptive loop filter 523. For some embodiments, the values of the SEL signal and the loop parameters Kp/Ki may be adjusted based on the CTRL signal. The loop parameters Kp/Ki may also be referred to as adaptive filter coefficients. The CTRL signal may be generated by state machine 526. For at least some embodiments, the state machine 526 may generate the CTRL signal based on a minimum-mean square error (MMSE) signal indicative of an estimated frequency response of the channels (e.g., channels CH0-CH3 of communications link 402 of FIGS. 4A and 4B).

[0046] The SEL signal and the loop parameters Kp/Ki may be used by the adaptive loop filter 523 to adjust the frequency and/or phase of the filtered error signal, which in turn may be used by the VCO 524 to align CLK vcowith the frequency and/or phase of the received data signal. In operation, the adaptive loop filter 523 may suppress any excess noise in the error signal output by the TED circuit 522, for example, to produce a more useful and precise filtered error signal. For some embodiments, one or more of the loop parameters Kp/Ki may be adjusted to increase the speed of clock recovery operations performed by the clock recovery circuit 520. Further, for some embodiments, the adaptive loop filter 523 may mitigate channel interference using one or more MMSE techniques, as described in more detail below.

[0047] The VCO 524 receives the filtered error signal from the adaptive loop filter 523, and adjusts CLK vco in response thereto. Specifically, the filtered error signal may cause the VCO 524 to align a sampling edge of CLK vcowith the peak (or center) of each symbol of the data signal received by the ADC 521. For example, a voltage level associated with the filtered error signal may cause the VCO 524 to either increase or decrease the oscillation frequency of

CLK vco. More specifically, the VCO 524 may increase the oscillation frequency of CLK vcowhen the voltage level of the filtered error signal is increased, and the VCO 524 may decrease the oscillation frequency of

CLK vcowhen the voltage level of the filtered error signal is decreased.

Accordingly, the clock recovery circuit 520 may operate in a feedback loop until CLK vcois precisely aligned with the symbol peaks of the received data signal. [0048] FIG. 6A shows a block diagram of an adaptive loop filter 600A in accordance with some embodiments. The adaptive loop filter 600A, which is one embodiment of the adaptive loop filter 523 of FIG. 5B, is shown to include a proportional gain element 601 , an integralgain element 602, summing circuits 603-605, a delay element 610, and a coarse phase search circuit 620 including a multiplexer (MUX) 621 and a pass gate 622. The error signal, as received from TED circuit 522 of FIG. 5B, may be divided into two paths: a proportional path 611 and an integral path 612. The proportional path 611 includes the proportional gain element 601 , which multiplies the error signal by the

proportional loop parameter (Kp) to filter phase error, and generates a phase- adjusted error signal. The integral path 612 includes the integral gain element 602, which multiplies the error signal by the integral loop parameter (Ki) and then integrates the Ki-multiplied error signal with a delayed copy of the error signal provided by the delay element 610 to generate a frequency-adjusted error signal. In this manner, the proportional path 611 may be used to correct phase errors between CLK vco and the recovered TS signal, and the integral path 612may be used to correct frequency offsets between CLK vco and the recovered TS signal. The proportional path 611 may becombined with the integral path 612 via summing circuit 604 to generate a filtered error signal, which is provided to a first input of summing circuit 605.

[0049] For some embodiments, the loop parameter K_p associated with proportional gain component 601 and/or the loop parameter Kj associated with the integral gain component 602 may be stored in configuration register 525 of FIG. 5B and/or adjusted (e.g., after a threshold period of time) to improve jitter performance. The threshold period of time may correspond to a fixed duration that allows the timing loop to catch up with an initial frequency offset. More specifically, the loop parameter Kjprovided to the integral gain element 602 may be adjusted to compensate for any frequency offset between the recovered TS signal and CLK vco, and the loop parameter K_pprovided to the proportional gain element 601 may be adjusted to compensate for any phase errors between the recovered TS signal and CLK vco. As discussed above, for at least some embodiments, the values of Kp and/or Ki may be adjusted based on the MMSE signal (or other suitable signal indicative of channel and interference estimates). [0050] The MUX 621 includes input terminals to receive a positive (+) phase step signal and a negative (-) phase step signal, includes a control terminal to receive the SEL signal from the configuration register 525 of FIG. 5B, and includes an output terminal coupled to a second input of summing circuit 605 via pass gate 622. The pass gate 622 includes an input to receive the selected phase step signal from the MUX 621 , an output coupled to the second summing circuit 605, and a control terminal to receive an enable (EN) signal. For some embodiments, the enable signal may be based on the SEL signal. For other embodiments, the enable signal may be based on the MMSE signal (or a weighted MMSE signal generated from a plurality of MMSE signals

corresponding to a plurality of channels of data link 402 of FIGS. 4A and 4B.

[0051] The summing circuit 605 may combine the phase step signal selected by MUX 621 with the filtered error signal to generate a phase-adjusted filtered error signal, which in turn may be provided to the VCO 524 of FIG. 5A.

[0052] In accordance with the present embodiments, thephase step signal provided by MUX 621 may be used to increase the speed with which the adaptive loop filter 600Aaligns the phase of the filtered error signal with the phase of CLK M (as indicated by the recovered TS signal received from the master device 110(a)). More specifically, during phase and frequency alignment operations, the integral path 612 may use non-zero values of Ki to align the frequency of the filtered error signal with the frequency of the recovered TS signal, and the proportional path 611 may use non-zero values of Kp to align the phase of the filtered error signal with the phase of the recovered TS signal. While the values of Kpand/or Ki may be adjusted for the gain elements 601 and 602, respectively, the MUX 621 may selectively provide either the positive (+) phase step signal or the negative (-) phase step signal to the summing circuit 605. The positive (+) phase step signal may quickly decrease the phase of the filtered error signal (e.g., relative to the recovered TS signal) by adding a fixed phase delay to the filtered error signal, and the negative (-) phase step signal may quickly increase the phase of the filtered error signal (e.g., relative to the recovered TS signal) by subtracting a fixed phase delay from the filtered error signal. In this manner, the phase step signal provided by MUX 621 to summing circuit 605 may provide course phase alignment between the filtered error signal and the recovered TS signal, while the proportional gain element 601 may provide fine phase alignment between the filtered error signal and the recovered TS signal.

[0053] FIG. 6B shows a block diagram of an adaptive loop filter 600B in accordance with other embodiments. The adaptive loop filter 600B, which is another embodiment of the adaptive loop filter 523 of FIG. 5B, includes all the elements of the adaptive loop filter 600A of FIG. 6A. However, the structure of the adaptive loop filter 600B of FIG. 6B is modified, as compared to the structure of the adaptive loop filter 600A of FIG. 6A, so that the phase step signal provided by the MUX 621 is first combined with the error signal in summing circuit 605 to generate the filtered error signal. The filtered error signal is then provided to the proportional path 611 and the integral path 612 of adaptive loop filter 600B of FIG. 6B. In the proportional path 611 , proportional gain element 601 multiplies the filtered error signal by the proportional loop parameter Kp to filter phase error. In the integral path 612, integral gain element 602multiplies the filtered error signal by the integral loop parameter Ki and then integrates the Ki-multiplied filtered error signal with a delayed copy of the error signal provided by the delay element 610. The proportional path 611 is combined with the integral path 612 via summing circuit 604 to generate the phase-adjusted filtered error signal.

[0054] As described above with respect to FIG. 6A, the phase step signal provided by MUX 621 may be used to increase the speed with which the adaptive loop filter 600Baligns the phase of the filtered error signal with the phase of CLK M (as indicated by the recovered TS signal received from the master device 110(a)). More specifically, during phase and frequency alignment operations, the MUX 621 may selectively provide either the positive (+) phase step signal or the negative (-) phase step signal to the summing circuit 605. The positive (+) phase step signal may quickly decrease the phase of the filtered error signal (e.g., relative to the recovered TS signal) by adding a fixed phase delay to the error signal, and the negative (-) phase step signal may quickly increase the phase of the filtered error signal (e.g., relative to the recovered TS signal) by subtracting a fixed phase delay from the error signal. In this manner, the phase step signal provided by MUX 621 to summing circuit 605 may provide course phase alignment between the filtered error signal and the recovered TS signal, while the proportional gain element 601 may provide fine phase alignment between the filtered error signal and the recovered TS signal.

[0055] FIG. 7 is an illustrative flow chart 700 depicting an exemplary operation for waking the master device 110(a) and/or the slave device 110(b) of FIG. 1 , in accordance with some embodiments. Referring to both FIGS. 1 and 7, when there is little or no data to be transmitted by the master device 110(a), the transmitter portions of the master device 110(a) and the slave device 110(b) may be placed into the quiet state (702). The devices 110(a) and 110(b) determine whether a wake-up signal is received (704). The wake-up signal may correspond to data received from another network-enabled device and/or may correspond to de-assertion of the LPI signal from the device's MAC device 450 (see also FIG. 4A). If the master device 110(a) initiated the wake-up from the quiet state, as tested as 706, then the master device 110(a) sends a training sequence (TS) signal to the slave device 110(b) (710). The slave device 110(b) may perform clock recovery operations on the received TS signal, and may alsoupdate its adaptive filter coefficients(e.g., loop parametersKp and Ki described above with respect to gain elements 601 and 602, respectively, of FIGS. 6A or FIG. 6B). If the slave device 110(b) is not able to recover timing information (e.g., clock information) from the received TS signal, as tested at 712, then the master device 110(a) may send another TS signal to the slave device 110(b) (710).

[0056] Conversely, if the slave device 110(b) is able to recover timing information from the received TS signal, as tested at 712, then the slave device 110(b)may send a TS signal to the master device 110(a) (714). The master device 110(a) may use the received TS signal to track the timing phase of its local clock and/or to update its adaptive filter coefficients (e.g., coefficients Kp and Ki described above with respect to gain elements 601 and 602, respectively, of FIGS. 6A or FIG. 6B). If the master device 110(a) is not able to recover the timing information from the received TS signal, as tested at 716, then the slave device 110(b) may send another TS signal to the master device 110(a)

(714). Conversely, if the master device 110(a) is able to recover the timing information from the received TS signal, as tested at 716, then the master device 110(a) and the slave device 110(b) may leave the EEE low power state (e.g., because the clock signals of master device 110(a) and the slave device 110(b) are synchronized with each other) (730).

[0057] If the slave device 110(b) initiated the wake-up from the quiet state, as tested as 706, then the slave device 110(b) is to wait for reception of the TS signal from the master device 110(a) (720). Upon receiving the TS signal, the slave device 110(b) determines whether it is able to recover timing

information from the received TS signal (722). If the slave device 110(b) is not able to recover the timing information from the received TS signal, then the slave device 110(b) waits to receive another TS signal from the master device 110(a) (720).

[0058] Conversely, if the slave device 110(b) is able to recover the timing information from the received TS signal, as tested at 722, then the slave device 110(b) may send a TS signal to the master device 110(a) (724). The master device 110(a) may use the received TS signal to track the timing phase of its local clock and/or to update its adaptive filter coefficients (e.g., loop

parametersKp and Ki described above with respect to gain elements 601 and 602, respectively, of FIGS. 6A or FIG. 6B). If the master device 110(a) is not able to recover the timing information from the received TS signal, as tested at 726, then the slave device 110(b) may send another TS signal to the master device 110(a) (724). Conversely, if the master device 110(a) is able to recover the timing information from the received TS signal, as tested at 726, then the master device 110(a) and the slave device 110(b) may leave the EEE low power state (e.g., because the clock signals of master device 110(a) and the slave device 110(b) are synchronized with each other) (730).

[0059] FIG. 8 is an illustrative flow chart 800 depicting an exemplary operation for performing clock recovery operations in accordance with some embodiments. Referring also to FIGS. 1 , 5A, 5B, 6A, and 6B, when there is little or no data to be transmitted, the slave device 110(b) may be placed into the quiet state (802). While the slave device 110(b) is in the quiet state, the slave device's clock recovery circuit 520(b)may no longer tracktiming parameters of the master device 110(a), and therefore the slave device's clock signal CLK S may no longer be synchronized with the master device's clock signal CLK M. As a result, the frequency offset and/or the phase error between CLK S and CLK M may increase during the quiet period. For some applications in which the quiet period is approximately 20ms and the sampling offset is approximately 1 ppm, the sampling point offset may increase to as much as 2.5 points.

[0060] The slave device 110(b) determines whether a wake-up signal is received (804). The wake-up signal may correspond to data received from the master device 110(a) and/or may correspond to de-assertion of the LPI signal from the slave device's MAC device 450 (see also FIG. 4A). If there is no wake- up signal, as tested at 804, the slave device 110(b) remains in the quiet state (802). Conversely, if there is a wake-up signal, as tested at 804, the slave device 110(b) may perform a frequency and phase alignment operation to align the phase and frequency of CLK S with the phase and frequency of CLK M (805). More specifically, referring also to FIGS. 6A and 6B, the integral path 612 may use non-zero values of Ki to align the frequency of the filtered error signal with the recovered TS signal, and the proportional path 611 may use non-zero values of Kp to align the phase of the filtered error signal with the recovered TS signal.

[0061] At the same time as the frequency and phase alignment operation 805, the adaptive loop filter 600A or 600B may perform a coarse phase search operation (806). During the coarse phase search operation, MUX 621 may selectively provide either the positive (+) phase step signal or the negative (-) phase step signal, based on the SEL signal, to the summing circuit 605. The positive (+) phase step signal may quickly decrease the phase of the filtered error signal (e.g., relative to the recovered TS signal) by adding a fixed phase delay to the filtered error signal, and the negative (-) phase step signal may quickly increase the phase of the filtered error signal (e.g., relative to the recovered TS signal) by subtracting a fixed phase delay from the filtered error signal. For example, if the phase of the filtered error signal leads the phase of the recovered TS signal, then the MUX 621 may provide the positive (+) phase step signal to the summing circuit 605. Conversely, if the phase of the filtered error signal lags the phase of the recovered TS signal, then the MUX 621 may provide the negative (-) phase step signal to the summing circuit 605. [0062] For some embodiments, the value of Kp may be maintained at a constant value during the coarse phase search operation, and the value of Ki may be set to zero during the coarse phase search operation. For some embodiments in which adaptive loop filter 600A of FIG. 6A is used, the error signal may not be used during the coarse phase search operation, and the value of Kp may not affect the value of the phase step signal provided by MUX 622. For other embodiments in which adaptive loop filter 600B of FIG. 6B is used, the value of Kp may affect the value of the phase step signal provided by MUX 622.

[0063] During the coarse phase search operation 806, the slave device 110(b) may compare a weighted MMSE value with a first threshold value to determine whether the phase offset between the filtered error signal and the recovered TS signal is within an acceptable range (807). The weighted MMSE value may be determined by averaging (or otherwise weighting or combining) the MMSE values corresponding to the four channels CH0-CH3 of the communications link 402 (see also FIGS. 4A and 4B). For some embodiments, the state machine 526 of FIG. 5B may determine the weighted MMSE value.

[0064] If the weighted MMSE value is less than the first threshold, as tested at 808, then the phase search operation continues at 806. Conversely, if the weighted MMSE value is not less than the first threshold, as tested at 808, then the phase search operation terminates, and the phase step signals are disabled (810). For at least some embodiments, the phase step signals may be disabled by de-coupling the output of MUX 621 from summing circuit 605, for example, using the pass gate 622 (e.g., by driving the EN signal to a state that turns off pass gate 622). Then, the slave device 110(b) compares the largest of the four MMSE values, corresponding to the four channels CH0-CH3 of the communications link 402, with a second thresholdto determine whether the phase error is within an acceptable range (812).

[0065] If the largest of the four MMSE values is less than the second threshold (e.g., which may indicate that the phase search operation successfully reduced the phase error to an acceptable level), as tested at 814, then the slave device 110(b) may exit the quiet state (end). Conversely, if the largest of the four MMSE values is not less than the second threshold value (e.g., which may indicate that the phase search operation did not reduce the phase error to an acceptable level), as tested at 814, then the slave device 110(b) may perform a small phase error adjustment operation (816). In the small phase adjustment operation, the slave device 110(b) may set the integral loop parameter Ki to zero, and may continue to adjust the proportional loop parameter (Kp) to further cause fine phase adjustments to the filtered error signal.

[0066] FIG. 9 is an illustrative flow chart 900 depicting an exemplary operation for performing clock recovery operations in accordance with some embodiments. First, the receiver of slave device 110(b) may generate an error signal based a recovered timing signal from a second Ethernet device, such as the master device 110(a) (902). Then, the adaptive loop filter 600A generatesa phase-adjusted error signal based on the error signal and the proportional loop parameterKp (904). Then, the adaptive loop filter 600A generates a frequency- adjusted error signal based on the error signal and the integral loop parameter Ki (906). Next, the adaptive loop filter 600A sums the phase-adjusted error signal and the frequency-adjusted error signal via summing circuit 605 to generate a filtered error signal (908). Finally, the adaptive loop filter 600A combines the fixed delay with the filtered error signal to adjust a phase of the filtered error signal (910).

[0067] FIG. lOillustrates a network-enabled device 1000that is one embodiment of devices 110(a) and/or 110(b) of FIG. 1. The device 1000 is shown to include a PHY device 1010, a processor 1020, and a memory 1030. The PHY device 1010, which maycorrespond to the PHY device 410 of FIG. 4A, may be used to communicate with one or more other network-enabled devices either directly or via one or more intervening networks. Processor 1020, which is coupled to the PHY device 1010 and the memory 1030, may be any suitable processor capable of executing scripts or instructions stored in the device1000 (e.g., within memory 1030). In one embodiment, the processor 1020 may execute instructions stored in the memory 1030 to determine perform one or more operations corresponding to the flow charts 700, 800, and 900 of FIGS. 7, 8 and 9, respectively.

[0068] Memory 1030 may include a non-transitory computer-readable medium (e.g., one or more nonvolatile memory elements, such as EPROM, EEPROM, Flash memory, a hard drive, and so on) that may store the following software modules:

• an operating state module1032to selectively transition the PHY device 1010 between the quiet state and the active state;

• afrequency alignment module 1034 to align a frequency of the slave device's clock signal CLK S with the master device's clock signal CLK M; and

• aphase alignment modulel 036to align a frequency of the slave device's clock signal CLK S with the master device's clock signal CLK M.

Each software module may include instructions that, when executed by the processor 1020, may cause the device 1000 to perform the corresponding function. Thus, the non-transitory computer-readable storage medium of memory 1030 may include instructions for performing all or a portion of the operations described below above respect to FIGS. 7-9.

[0069] In the foregoing specification, the present embodiments have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. For example, method depicted in the flow charts of FIGS. 7-9 may be performed in other suitable orders and/or one or more methods steps may be omitted.

Claims

CLAIMS What is claimed is:

1. An adaptive loop filter to process a filtered error signal indicative of an alignment error between a first signal and a second signal, the adaptive loop filter comprising:

afirst summing circuit to generate a phase-adjusted filtered error signal by summing the filtered error signal and a selected phase step signal; and

a coarse phase search circuitto selectively provide either a positive phase step signal or a negative phase step signal as the selected phase step signal to the first summing circuit.

2. The adaptive loop filter of claim 1 , wherein the positive phase step signal is to add a fixed delay to the filtered error signal, and the negative phase step signal is to subtract the fixed delay from the filtered error signal.

3. The adaptive loop filter of claim 1 , wherein the positive phase step signal is to add a fixed delay to the filtered error signal when a phase of the first signal leads a phase of the second signal, and the negative phase step signal is to subtract the fixed delay from the filtered error signal when the phase of the first signal leads the phase of the second signal.

4. The adaptive loop filter of claim 1 , wherein the coarse phase search circuit comprises:

a multiplexer (MUX) including a first input to receive the positive phase step signal, a second input to receive the negative phase step signal, a control terminal to receive a select signal, and an output to provide the selected phase step signal to the first summing circuit.

5. The adaptive loop filter of claim 4, wherein the select signal is based on a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link.

6. The adaptive loop filter of claim 4, wherein the coarse phase search circuit further comprises:

a pass gate including a first terminal coupled to the output of the MUX, including a second terminal coupled to an input of the first summing circuit, and including a control terminal to receive an enable signal, wherein the enable signal is based upon a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link.

7. The adaptive loop filter of claim 6, wherein:

when the weighted MMSE signal is less than a first threshold, the pass gate is to provide the selected phase step signal to the first summing circuit; and

when the weighted MMSE signal is not less than the first threshold, the pass gate is to de-couple the selected phase step signal from the first summing circuit.

8. The adaptive loop filter of claim 1 , further comprising:

a proportional loop path, including a proportional gain element coupled between an input terminal of the adaptive loop filter and a second summing circuit, to generate a phase-adjusted error signal based on a proportional loop parameter provided to the proportional gain element; and

an integral loop path, including an integral gain element coupled between the input terminal of the adaptive loop filter and the second summing circuit, to generate a frequency-adjusted error signal based on an integral loop parameter provided to the integral gain element, wherein the second summing circuit is to sum the phase-adjusted error signal and the frequency-adjusted error signal to generate the filtered error signal.

9. An Ethernet-compliant device including a timing recovery circuit comprising an adaptive loop filter, the adaptive loop filtercomprising:

an input terminal to receive an error signalindicative of an alignment error between a first signal and a second signal;

a proportional gain element to generate a phase-adjusted error signal; an integral gain element to generate a frequency-adjusted error signal; afirst summing circuit to generate a filtered error signal by summing the frequency-adjusted error signal and the phase-adjusted error signal;

a coarse phase search circuitto selectively provide either a positive phase step signal or a negative phase step signal as a selected phase step signal in response to a select signal; and

a second summing circuit to generate a phase-adjusted filtered error signal by summing the filtered error signal and the selected phase step signal.

10. The Ethernet-compliant device of claim 9, wherein the positive phase step signal is to add a fixed delay to the filtered error signal, and the negative phase step signal is to subtract the fixed delay from the filtered error signal.

11. The Ethernet-compliant device of claim 9, wherein the coarse phase search circuit comprises:

a multiplexer (MUX) having a first input to receive the positive phase step signal, a second input to receive the negative phase step signal, a control terminal to receive the select signal, and an output to provide the selected phase step signal to the second summing circuit.

12. The Ethernet-compliant device of claim 11 , wherein the select signal is based on a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link.

13. The Ethernet-compliant device of claim 11 , wherein the coarse phase search circuit further comprises:

a pass gate including a first terminal coupled to the output of the MUX, including a second terminal coupled to the second summing circuit, and including a control terminal to receive an enable signal, wherein the enable signal is based upon a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link.

14. The Ethernet-compliant device of claim 13, wherein:

when the weighted MMSE signal is less than a first threshold, the pass gate is to provide the selected phase step signal to the second summing circuit; and

when the weighted MMSE signal is not less than a first threshold, the pass gate is to de-couple the selected phase step signal from the second summing circuit.

15. A method of performing clock recovery operations in a first Ethernet device comprising at least an adaptive loop filter, the method comprising:

receiving a filtered error signal indicative of an alignment error between a first signal and a second signal;and

combininga fixed phase delay with the filtered error signal to adjust a phase of the filtered error signal.

16. The method of claim 15, wherein the fixed delay comprises either a positive phase step signal or a negative phase step signal.

17. The method of claim 15, wherein the combining comprises:

providing a positive phase step signal to a multiplexer (MUX);

providing a negative phase step signal to the MUX;

selecting either the positive phase step signal or the negative phase step signal based on a select signal;

when the positive phase step signal is selected, adding the fixed phase delay to the filtered error signal; and

when the negative phase step signal is selected, subtracting the fixed phase delay from the filtered error signal.

18. The method of claim 17, wherein the select signal is based on a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link.

19. The method of claim 15, further comprising:

receiving a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link; comparing the weighted MMSE signal with a first threshold;

when the weighted MMSE signal is less than the first threshold, allowing the combining;and

when the weighted MMSE signal is not less than the first

threshold, preventing the combining.

20. The method of claim 15, further comprising:

generating an error signal based a recovered timing signal from a second Ethernet device;

generating a phase-adjusted error signal based on the error signal and a proportional loop parameter;

generating a frequency-adjusted error signal based on the error signal and an integral loop parameter; and

summing the phase-adjusted error signal and the frequency-adjusted error signal to generate the filtered error signal.

21. An Ethernet device comprising at least an adaptive loop filter, the Ethernet device comprising:

means for receiving a filtered error signal indicative of an alignment error between a first signal and a second signal; and

means for combining a fixed phase delay with the filtered error signal to adjust a phase of the filtered error signal.

22. The Ethernet device of claim 21 , wherein the fixed delay comprises either a positive phase step signal or a negative phase step signal.

23. The Ethernet device of claim 21 , wherein the means for combining is to:

providea positive phase step signal to a multiplexer (MUX);

providea negative phase step signal to the MUX; selecteither the positive phase step signal or the negative phase step signal based on a select signal;

add the fixed phase delay to the filtered error signal when the positive phase step signal is selected; and

subtract the fixed phase delay from the filtered error signal when the negative phase step signal is selected.

24. The Ethernet device of claim 23, wherein the select signal is based on a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link.

25. The Ethernet device of claim 21 , further comprising:

means for receiving a weighted minimum-mean square error (MMSE) signal indicative of channel and interference estimation of an associated data link;

means for comparing the weighted MMSE signal with a first threshold; means for allowing the combiningwhen the weighted MMSE signal is less than the first threshold; and

means for preventing the combining when the weighted MMSE signal is not less than the first threshold.

26. The Ethernet device of claim 21 , further comprising:

means for generating an error signal based a recovered timing signal from a second Ethernet device;

means for generating a phase-adjusted error signal based on the error signal and a proportional loop parameter;

means for generating a frequency-adjusted error signal based on the error signal and an integral loop parameter; and

means for summing the phase-adjusted error signal and the frequency- adjusted error signal to generate the filtered error signal.