WO2015147844A1 - Hybrid interconnect for low temperature attach - Google Patents
Hybrid interconnect for low temperature attach Download PDFInfo
- Publication number
- WO2015147844A1 WO2015147844A1 PCT/US2014/032084 US2014032084W WO2015147844A1 WO 2015147844 A1 WO2015147844 A1 WO 2015147844A1 US 2014032084 W US2014032084 W US 2014032084W WO 2015147844 A1 WO2015147844 A1 WO 2015147844A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- alloy
- solder
- melting point
- lts
- pad
- Prior art date
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 172
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 92
- 239000000956 alloy Substances 0.000 claims abstract description 92
- 238000000034 method Methods 0.000 claims abstract description 85
- 230000008018 melting Effects 0.000 claims abstract description 75
- 238000002844 melting Methods 0.000 claims abstract description 75
- 230000008569 process Effects 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 61
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 28
- 239000010949 copper Substances 0.000 claims description 27
- 150000001875 compounds Chemical class 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 20
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 15
- 229910000765 intermetallic Inorganic materials 0.000 claims description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 14
- 229910052797 bismuth Inorganic materials 0.000 claims description 14
- 229910052718 tin Inorganic materials 0.000 claims description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 229910052738 indium Inorganic materials 0.000 claims description 9
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 239000011135 tin Substances 0.000 claims description 6
- 239000003755 preservative agent Substances 0.000 claims description 5
- 230000002335 preservative effect Effects 0.000 claims description 5
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000004891 communication Methods 0.000 description 17
- 238000001125 extrusion Methods 0.000 description 8
- 230000004907 flux Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229940070259 deflux Drugs 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 229910001152 Bi alloy Inorganic materials 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- DGLFSNZWRYADFC-UHFFFAOYSA-N chembl2334586 Chemical compound C1CCC2=CN=C(N)N=C2C2=C1NC1=CC=C(C#CC(C)(O)C)C=C12 DGLFSNZWRYADFC-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29113—Bismuth [Bi] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Definitions
- the packages may include a mold compound that is formed on a substrate of the package after disposition of the solder balls.
- the temperature and pressure of the molding process may result in deformation and/or collapse of the solder balls.
- FIG. 2 depicts a more detailed example of an interconnect, in accordance with various embodiments.
- Figure 5 depicts an alternative example process for forming an interconnect on a substrate, in accordance with various embodiments.
- Figure 6 depicts an example process for forming an interconnect on a chip, in accordance with various embodiments.
- Figure 9 schematically illustrates a computing device, in accordance with various embodiments.
- Embodiments of the present disclosure generally relate to the field of low temperature interconnects.
- an interconnect may also be described as a "solder joint.”
- solder joints or solder bumps.
- phrase “A and/or B” means (A), (B), or (A and B).
- phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
- Coupled may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
- directly coupled may mean that two or more elements are in direct contact.
- the phrase "a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the feature layer, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
- direct contact e.g., direct physical and/or electrical contact
- indirect contact e.g., having one or more other features between the first feature and the second feature
- module may refer to, be part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
- ASIC application-specific integrated circuit
- processor shared, dedicated, or group
- memory shared, dedicated, or group
- FIG. 1 may depict one or more layers or elements of a chip, substrate, or interconnect.
- the elements depicted herein are depicted as examples of relative positions of the different elements. The elements are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of elements should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.
- FIG. 1 depicts an example package 100.
- the package 100 includes a substrate 105, which may be an organic laminate or ceramic material.
- the package 100 may include one or more interconnects 110.
- the interconnects 110 may be coupled with pads 115 that are disposed on the substrate 105.
- the pads 115 may be composed of copper, though in other embodiments the pads 115 may be composed of some other electrically or thermally conductive material such as nickel, gold, palladium, platinum, or alloys thereof.
- the pads 115 may have a surface treatment or surface finish generally disposed on an outer surface of the pads 115 and positioned between the pads 115 and the interconnects 110.
- the surface finish may be composed of a material such as nickel, palladium, gold, copper, or an organic solderability preservative.
- the package 100 may further include a mold compound 120 generally disposed around, and laterally adjacent to, the interconnects 110 and/or the pads 115.
- the mold compound 120 may include one or more through-mold vias 125.
- the vias 125 may be formed in the mold compound 120 using one or more methods such as physical, chemical, or optical etching.
- the mold compound 120 may be extruded onto the substrate 105 such that it at least partially covers the interconnects 110, and then the vias 125 may be etched into the mold compound 120.
- the mold compound 120 may be extruded onto the substrate 105 and the interconnects 110 may be protected, for example through use of a covering or other shielding element, such that the mold compound 120 does not cover the interconnects 110.
- Figure 2 depicts an example of an interconnect such as interconnect 110 in greater detail.
- Figure 2 depicts an interconnect 200, which may be similar to one of interconnects 110.
- the interconnect 200 is comprised of a solder ball 205 and a solder paste 210 generally positioned between the solder ball 205 and a pad 215, which may be similar to pad 115 of Figure 1.
- an inter-metallic compound (IMC) 220 may be generally positioned between the solder paste 210 and the pad 215, as will be explained in greater detail below.
- the pad 215 may be disposed on a substrate 225, which may be similar to substrate 105 of Figure 1.
- the solder ball 205 may be constructed of an alloy including tin, silver, and copper (SAC). In other embodiments, the solder ball 205 may be an alloy of tin and antimony, off eutectic tin and copper, a SAC shell ball with a copper core, a SAC shell ball with a polymer core, or some other type of solder ball with a relatively high melting point as described in further detail below. In some embodiments the solder ball 205 may be lead-free. In some embodiments, the melting point of the solder ball 205 may be 217° Celsius. In other embodiments, the melting point of the solder ball 205 may be higher than 217° Celsius, for example 240° Celsius or higher.
- the melting point of the solder ball 205 may be between approximately 180° Celsius and approximately 280° Celsius.
- the melting point of the solder ball 205 or the alloy or material that comprises the solder ball 205 may be referred to as a "relatively high" melting point to distinguish the melting point of the solder ball 205 from a melting point of the solder paste 210 or a low-temperature solder (LTS) alloy as discussed below.
- the solder paste 210 may be an LTS alloy.
- the LTS alloy may be, or include, an alloy of tin and bismuth (SnBi); tin, bismuth, nickel, and copper (SnBiNiCu); tin, bismuth, copper, and antimony (SnBiCuSb); tin, silver, and bismuth (SnAgBi); tin and indium (Snln); tin, indium, and bismuth (SnlnBi); or some other combination of bismuth and/or indium and some other alloy with a relatively low melting point as compared to the melting point of the solder ball 205.
- the solder paste 210 may be lead- free. In some embodiments the solder paste 210 may have a melting point of less than 200° Celsius, for example 175° Celsius, though in other embodiments the solder paste 210 may have a lower melting point or a melting point between approximately 120° Celsius and approximately 180° Celsius. In some embodiments, it may be desirable for the melting point of the solder paste 210 to be about 25° Celsius below that of the solder ball 205.
- a re flow process of the interconnect 200 may be controlled such that the re flow temperature is above the melting point of the solder paste 210, but below that of the solder ball 205.
- the reflow process may include heating the solder paste 210 and/or the solder ball 205 through direct application of an increased temperature and/or pressure such that the solder paste 210 and/or the solder ball 205 liquefies or melts. This liquefaction may result in the solder paste 210 and/or the solder ball 205 bonding with the substrate 225.
- the solder paste 210 may melt and chemically and/or physically bond with the pad 215, while the solder ball 205 may not significantly melt or otherwise deform.
- the interconnect 200 may have a greater z-height, measured as distance from the pad 215, than legacy interconnects.
- the interconnect 200 may have a z-height of between 290 and 310 microns. This z-height may be approximately 32% to 41% higher than the z-height of legacy interconnects.
- Figure 3 depicts a comparison of post-reflow solder ball height correlation with pre-reflow solder ball diameter for one embodiment of a solder ball with a relatively high melting point, such as solder ball 205, and a solder paste with a relatively low melting point, such as solder paste 210.
- the embodiment of Figure 3 assumes an approximately 21 micron solder resist (SR) thickness.
- the SR may be an outermost layer of the substrate such as substrate 225. It can be seen that post-reflow solder ball height, as compared to pre-reflow solder ball diameter, may decrease by approximately 30% to 50% for a 0.3 millimeter to 0.65 millimeter pitch.
- the solder paste 210 may be a combination of an LTS alloy, such as one or more of the LTS alloys described above such as SnBi,
- solder paste 210 may comprise SnBi and SAC. In some embodiments, the solder paste 210 may comprise
- solder paste 210 comprised of approximately equal amounts of an LTS alloy and SAC may be desirable to use in the package 100 of Figure 1.
- the mold compound 120 may be extruded after the interconnects 110 are disposed on the substrate 105.
- the mold compound 120 may be extruded with pressure at a temperature from 165 to 175° Celsius, which may be close to the melting point of a solder paste such as solder paste 210 with a melting point of approximately 175° Celsius. Therefore, extrusion of the mold compound 120 may negatively affect the solder paste 210, for example by causing it to undesirably melt and collapse or otherwise deform.
- a solder paste 210 comprised of an LTS alloy and SAC may reduce the amount of collapse or deformation.
- the LTS alloy and the SAC may be deposited on the substrate 210 in powder form before a reflow process occurs. Then, as the temperature rises above the melting point of the LTS alloy, which may be approximately 175° Celsius as described above, the LTS alloy may melt and wet the SAC powder particles. As described above, the temperature of the interconnect 200 may rise, for example by reflow, mold extrusion, or some other process.
- the overall metallurgical composition of the solder paste 210 post-reflow may no longer be the same, but instead may have a dominating influence on melting temperature due to the relatively higher amount of tin.
- the overall melting temperature of the solder paste 210 may be greater than 175° Celsius due to the combination of the LTS alloy and the SAC.
- the relatively higher melting temperature may therefore prevent or reduce the remelting of the solder paste 210 during the extrusion of the mold compound 120.
- the LTS alloy of the solder paste 210 may melt and wet the solder ball 205.
- the LTS alloy of the solder paste 210 may react with the metallization of the underlying pad 215, and particularly the surface finish of the pad 215, to form the IMC 220.
- the IMC 220 may be comprised of, for example, nickel, copper, tin, bismuth, or alloys thereof.
- the IMC 220 may serve to at least partially anchor the reflowed solder paste 210 and/or the solder ball 205 to the pad 215, thereby increasing the ability of the interconnect 200 to better resist the pressure associated with extrusion of the mold compound 120 at a temperature above the melting point of the LTS alloy.
- the melting temperature of a solder paste 210 that comprises both the LTS alloy and the SAC may be modulated dependent on the ratio of the LTS alloy to the
- the melting point of the solder paste 210 may be further increased above the melting point of the LTS alloy. Additionally, as the concentration of the SAC in the solder paste 210 increases, the extent to which the solder paste 210 may collapse or otherwise deform during the mold extrusion process may decrease, which may result in a greater z-height of the interconnect 200.
- Figure 4 depicts one example process of forming an interconnect such as interconnect 200 on substrate 225. Specifically, Figure 4 depicts an example process for positioning one or more solder balls, such as solder balls 205, on a substrate, such as substrate 225. In some embodiments the process of Figure 4 may be described as a controlled collapse chip connection (C4) bumping process, and the interconnects formed of the solder balls and solder paste may be referred to as first-level interconnects (FLIs). Specifically, a first-level interconnect may be an interconnect that couples a chip to a substrate or board such as a printed circuit board.
- C4 controlled collapse chip connection
- FLIs first-level interconnects
- a substrate 400 with a plurality of pads 405, which may be similar to substrate 105 and pads 115 described above, may be positioned in a mold 410.
- the mold may include a stencil 415 with a plurality of openings 420.
- the mold 410 may be coupled with or otherwise disposed under a dispenser 425 configured to dispense LTS paste 430.
- the LTS paste 430 of Figure 4 may be, in this embodiment, an LTS alloy such as SnBi or some other LTS alloy described above.
- a print process may be performed at 435 such that the LTS paste 440, which may be similar to LTS paste 430, is deposited directly onto the pads 405 of the substrate 400 through the openings 420.
- the stencil 415 may then be removed.
- a ball mount process may be performed at 445.
- the ball mount process may include positioning a second stencil 450 with a plurality of openings 455 over the LTS paste 440, pads 405, and substrate 400.
- One or more solder balls 460 which may be similar to solder ball 205, may be positioned within the openings 455 and directly over the LTS paste 440.
- the solder balls 460 may be comprised of an alloy with a relatively high melting point such as SAC, as discussed above.
- the stencil 450 may be removed and a re flow process may be performed.
- the reflow process may include the application of temperature and/or pressure such that the temperature of the substrate 400, pads 405, LTS paste 440, and solder balls 460 is raised generally above a melting point of the LTS paste 440, but below a melting point of the solder balls 460.
- the reflow process may include extrusion of a mold compound such as mold compound 120 onto the substrate.
- the reflow process may be performed at a temperature higher than the melting point of the solder balls 460. In this embodiment, the reflow process may be performed before the stencil 450 is removed.
- the solder balls 460 and LTS paste 440 may melt during the reflow process and form hybrid LTS/SAC solder balls, that is, solder balls comprised of both an LTS alloy and SAC, on the pads 405 and/or substrate 400.
- a deflux process may be performed. Specifically, any flux that was used in the process of Figure 4 may be removed through electrical, optical, mechanical, or chemical means.
- Figure 5 depicts an alternative example process of positioning one or more solder balls such as solder balls 205 on a substrate such as substrate 225.
- the process of Figure 5 may be described as a "micro bumping" process, and the interconnects formed of the solder balls and solder paste may be referred to as first-level interconnects, as described above.
- a substrate 500 with a plurality of pads 505, which may be similar to substrate 400 and pads 405 described above, may be positioned in a mold 510.
- the mold may include a stencil 515 with a plurality of openings 520.
- the mold 510 may be coupled with or otherwise disposed under a dispenser 525 configured to dispense flux 530.
- the flux 530 may be comprised of, for example rosin, solvent, acid, amine, or a combination thereof.
- a print process may be performed at 535 such that the flux 540, which may be similar to flux 530, is deposited directly onto the pads 505 of the substrate 500 through the openings 520.
- the stencil 515 may then be removed.
- a ball mount process may be performed at 545.
- the ball mount process may include positioning a second stencil 550 with a plurality of openings 555 over the flux 540, pads 505, and substrate 500.
- One or more solder balls 560 which may be similar to solder ball 205, may be positioned within the openings 555 and directly over the flux 540.
- the solder balls may be comprised of a mixture of an alloy with a relatively high melting point, for example SAC, and an alloy with a relatively low melting point, for example an LTS alloy such as SnBi, as discussed above.
- the stencil 550 may be removed and a re flow process may be performed.
- the reflow process may be performed at a temperature that is generally above the melting point of the LTS alloy of the solder balls 560, but below the melting point of the SAC of the solder balls 560.
- the LTS alloy may melt and bond with the pads 505 and/or substrate 500, while the SAC does not melt or otherwise deform.
- the z-height of the interconnect formed of the solder balls 560 and pad 505 may be higher than if a solder ball comprised of only an LTS alloy was used.
- a deflux process may be performed. Specifically, any flux that was used in the process of Figure 5 may be removed through electrical, optical, mechanical, or chemical means.
- Figure 6 depicts an example process to generate an interconnect having a combination of an alloy with a relatively high melting point such as SAC, and an LTS alloy with a relatively low melting point such as SnBi.
- the process of Figure 6 may be used, for example, to generate an interconnect with a SAC/LTS hybrid structure for a chip to chip attach process.
- the chip to chip attach process may be referred to as a local memory interconnect (LMI) process.
- LMI local memory interconnect
- Figure 6 depicts a chip 600, which may include a die 605.
- the die 605 may include a plurality of bumps 610, which may be copper or some other electrically conductive material or alloy.
- a solder 615 alloy with a relatively high melting point, for example SAC may be deposited on the bumps 610.
- the chip 600, and particularly the bumps 610 and solder 615 may be dipped or otherwise submerged into a bath 620 of an alloy with a relatively low melting point, for example a bath 620 of an LTS alloy such as SnBi, at 625.
- the dipping depth of the chip 600 may be controlled such that only the solder 615, or only a portion of the solder 615, is submerged into the bath 620.
- the chip 600 may then be removed from the molten bath 620 at 630.
- the removal of the chip 600 may be at a controlled speed.
- the molten LTS alloy may wet the solder 615, which may result in the formation of a hybrid LTS/SAC alloy due to a strong surface tension and wetting force of the molten LTS alloy in the bath 620.
- the bath 620 may be molten LTS or some other alloy with a relatively low melting point, submersion of the SAC into the bath 620 may not cause the SAC to melt or otherwise deform.
- the chip 600 may therefore have a plurality of bumps or interconnects 635 comprised of a hybrid LTS/SAC alloy.
- Figure 7 depicts an alternative example of a process to generate an interconnect having a combination of an alloy with a relatively high melting point such as SAC, and an LTS alloy with a relatively low melting point such as SnBi.
- the process of Figure 7 may also be used to generate an interconnect with a SAC/LTS hybrid structure for a chip to chip attach process, similarly to the process of Figure 6.
- Figure 7 may include a chip 700 that includes a die 705 with a plurality of bumps 710 with solder 715 disposed on the bumps 710, which may be respectively similar to chip 600, die 605, bumps 610, and solder 615.
- the solder 715 may be comprised of an alloy with a relatively high melting point, for example SAC.
- the LTS 720 may be stamped onto the bumps 710, and specifically the solder 715, using a stamper 722 as shown at 725.
- the stamper 722 applying the LTS 720 may result in bumps or interconnects 735 comprised of a hybrid LTS/SAC alloy as described above with respect to interconnects 635.
- a low temperature reflow process or a low temperature thermocomprossion bonding (TCB) process may be applied to FLIs or LMIs due to the relatively lower melting points for an interconnect comprising a hybrid LTS/SAC alloy. Because of the relatively low temperature reflow or bonding processes, post-chip attach package warpage and TCB process run rate may be improved. Additionally, for LMI processes, silica particle entrapment during an in-situ epoxy TCB process may be improved due to the LTS alloy melting at a relatively lower temperature.
- the LTS alloy may wet the pads of a chip, such as copper pads of a chip, which may repel silica particles off of the pads before the epoxy of the in-situ epoxy TCB process is cured, thereby restricting movement of the silica particles at high temperature.
- Figure 8 depicts a generalized process for forming an interconnect such as interconnect 200 of Figure 2.
- an alloy with a relatively low melting point for example an LTS alloy such as SnBi, may be deposited on a substrate such as substrate 225 at 800.
- the LTS alloy may be deposited on a pad of the substrate such as pad 215.
- an alloy with a relatively high melting point for example SAC
- the alloy may be deposited on the pad of the substrate.
- elements 800 and 805 may be premixed and deposited on the substrate at substantially the same time.
- the alloy may be deposited on the substrate at 805 prior to the deposition of the LTS on the substrate at 800.
- the LTS alloy deposited at 800 and the SAC deposited at 805 may be the solder paste 210 of interconnect 200.
- a solder ball such as solder ball 205 is deposited on the LTS alloy and the SAC at 810.
- a reflow process may occur at 815.
- the reflow process may occur as the result of a mold compound extrusion process.
- the reflow process may occur at a temperature at or above the melting point of the LTS alloy, but below the melting point of the SAC.
- the interconnect formed for example interconnect 200, may have a z-height measured from the substrate that is higher than the z-height of some legacy interconnects.
- FIG. 9 schematically illustrates a computing device 900 in accordance with one implementation of the invention.
- the computing device 900 may house a board such as motherboard 902.
- the motherboard 902 may include a number of components, including but not limited to a processor 904 and at least one
- the processor 904 may be physically and electrically coupled to the motherboard 902.
- the at least one communication chip 906 may also be physically and electrically coupled to the motherboard 902.
- the communication chip 906 may be part of the processor 904.
- the communication chip 906, the processor 904, or one or more of the other components of the computing device 900 may be coupled to one another using an interconnect such as interconnect 200 or another interconnect formed using one or more of the processes described above with respect to Figures 4 through 8.
- computing device 900 may include other components that may or may not be physically and electrically coupled to the motherboard 902. These other components may include, but are not limited to, volatile memory (e.g., dynamic random access memory (DRAM)) 920, non-volatile memory (e.g., read-only memory (ROM)) 924, flash memory 922, a graphics processor 930, a digital signal processor (not shown), a crypto processor (not shown), a chipset 926, an antenna 928, a display (not shown), a touchscreen display 932, a touchscreen controller 946, a battery 936, an audio codec (not shown), a video codec (not shown), a power amplifier 941, a global positioning system (GPS) device 940, a compass 942, an accelerometer (not shown), a gyroscope (not shown), a speaker 950, a camera 952, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and
- volatile memory
- the communication chip 906 may enable wireless communications for the transfer of data to and from the computing device 900.
- wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
- the communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
- IEEE 802.16 compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards.
- the communication chip 906 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E- HSPA), or LTE network.
- GSM Global System for Mobile Communication
- GPRS General Packet Radio Service
- UMTS Universal Mobile Telecommunications System
- High Speed Packet Access HSPA
- E- HSPA Evolved HSPA
- LTE LTE network.
- the communication chip 906 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
- EDGE Enhanced Data for GSM Evolution
- GERAN GSM EDGE Radio Access Network
- UTRAN Universal Terrestrial Radio Access Network
- E-UTRAN Evolved UTRAN
- the communication chip 906 may operate in accordance with
- communication chip 906 may operate in accordance with other wireless protocols in other embodiments.
- Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.
- the processor 904 of the computing device 900 may include a die in a package.
- processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
- the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
- the computing device 900 may be any other electronic device that processes data, for example an all-in-one device such as an all-in-one fax or printing device.
- Example 1 may include an apparatus comprising: a substrate having a pad disposed on the substrate; a solder ball coupled with the pad, the solder ball including an alloy of tin, silver, and copper; and a solder paste generally positioned between the pad and the solder ball, the solder paste including the alloy and a low-temperature solder (LTS) with a melting point that is less than or equal to a melting point of the alloy.
- Example 2 may include the apparatus of example 1 , wherein the pad comprises copper and has a surface finish of nickel, palladium, gold, copper, or an organic solderability
- Example 3 may include the apparatus of example 1 , wherein the alloy is a lead- free alloy.
- Example 4 may include the apparatus of example 1 , wherein the LTS comprises indium or bismuth.
- Example 5 may include the apparatus of example 1 , wherein the solder paste comprises approximately equal amounts of the alloy and the LTS.
- Example 6 may include the apparatus of any of examples 1-5, further comprising: a mold compound coupled with the substrate and generally disposed laterally adjacent to, and generally surrounding, the solder ball and the solder paste.
- Example 7 may include the apparatus of any of examples 1-5, further comprising an inter-metallic compound (IMC) disposed between the solder paste and the substrate.
- IMC inter-metallic compound
- Example 8 may include the apparatus of example 7, wherein the IMC comprises nickel, copper, tin, bismuth, or alloys thereof.
- Example 9 may include the apparatus of any of examples 1-5, wherein the alloy has a melting point between approximately 180° Celsius and approximately 280° Celsius.
- Example 10 may include the apparatus of example 9, wherein the solder paste has a melting point greater than or equal to 175° Celsius.
- Example 11 may include a method comprising: depositing a solder paste on a pad of a substrate, the solder paste including a low-temperature solder (LTS) with a melting point that is less than or equal to 217° Celsius and an alloy of tin, silver, and copper; positioning a solder ball including the alloy on the solder paste such that the solder paste is disposed between the pad and the solder ball; and performing a reflow process at a temperature above the melting point of the LTS and below a melting point of the alloy.
- LTS low-temperature solder
- Example 12 may include the method of example 11, wherein the LTS comprises indium or bismuth.
- Example 15 may include the method of any of examples 11-13, wherein the pad comprises copper.
- Example 19 may include the apparatus of any of examples 16-18, wherein the lead- free alloy has a melting point of 217° Celsius.
- Example 21 may include the apparatus of any of examples 16-18, wherein the pad comprises copper with a surface finish of nickel, palladium, gold, copper, or an organic solderability preservative.
- Example 22 may include one or more non-transitory computer readable media comprising instructions to cause a computing device, upon execution of the instructions by one or more processors of the computing device, to perform the method of any of examples 11-15.
- Various embodiments may include any suitable combination of the above-described embodiments, including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and” may be “and/or”).
- some embodiments may include one or more articles of manufacture (e.g., non-transitory computer- readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments.
- some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1614555.9A GB2540060B (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attach |
US14/430,131 US20160260679A1 (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attach |
PCT/US2014/032084 WO2015147844A1 (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attach |
KR1020167023490A KR20160113686A (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attach |
CN201480076416.XA CN106030783B (en) | 2014-03-27 | 2014-03-27 | Mixing interconnection for low temperature attachment |
DE112014006271.5T DE112014006271B4 (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attachment and method of making same |
JP2016554385A JP2017508293A (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature installation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2014/032084 WO2015147844A1 (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attach |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015147844A1 true WO2015147844A1 (en) | 2015-10-01 |
Family
ID=54196160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2014/032084 WO2015147844A1 (en) | 2014-03-27 | 2014-03-27 | Hybrid interconnect for low temperature attach |
Country Status (7)
Country | Link |
---|---|
US (1) | US20160260679A1 (en) |
JP (1) | JP2017508293A (en) |
KR (1) | KR20160113686A (en) |
CN (1) | CN106030783B (en) |
DE (1) | DE112014006271B4 (en) |
GB (1) | GB2540060B (en) |
WO (1) | WO2015147844A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210157787A (en) | 2020-06-22 | 2021-12-29 | 삼성전자주식회사 | Semiconductor package and method of fabricating the same |
CN117677074A (en) * | 2023-12-29 | 2024-03-08 | 立臻电子科技(昆山)有限公司 | Method for welding multi-layer circuit board |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030030149A1 (en) * | 2000-06-12 | 2003-02-13 | Kazuma Miura | Semiconductor device having solder bumps reliably reflow solderable |
US20030193094A1 (en) * | 2002-04-12 | 2003-10-16 | Nec Electronics Corporation | Semiconductor device and method for fabricating the same |
US20050085013A1 (en) * | 2002-12-04 | 2005-04-21 | Craig Ernsberger | Ball grid array resistor network |
US20060030071A1 (en) * | 2004-08-05 | 2006-02-09 | Fujitsu Limited | Method for processing base |
US20100015796A1 (en) * | 2001-01-15 | 2010-01-21 | Nec Corporation | Semiconductor device, manufacturing method and apparatus for the same |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307565A (en) * | 1998-04-24 | 1999-11-05 | Mitsubishi Electric Corp | Electrode for semiconductor device, its manufacture, and the semiconductor device |
JP2002076605A (en) * | 2000-06-12 | 2002-03-15 | Hitachi Ltd | Semiconductor module and circuit board for connecting semiconductor device |
US6433425B1 (en) * | 2000-09-12 | 2002-08-13 | International Business Machines Corporation | Electronic package interconnect structure comprising lead-free solders |
US6784086B2 (en) * | 2001-02-08 | 2004-08-31 | International Business Machines Corporation | Lead-free solder structure and method for high fatigue life |
JP4008799B2 (en) * | 2002-11-20 | 2007-11-14 | ハリマ化成株式会社 | Lead-free solder paste composition and soldering method |
US6854636B2 (en) * | 2002-12-06 | 2005-02-15 | International Business Machines Corporation | Structure and method for lead free solder electronic package interconnections |
US20040155358A1 (en) * | 2003-02-07 | 2004-08-12 | Toshitsune Iijima | First and second level packaging assemblies and method of assembling package |
JP3905100B2 (en) * | 2004-08-13 | 2007-04-18 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP4939891B2 (en) * | 2006-10-06 | 2012-05-30 | 株式会社日立製作所 | Electronic equipment |
US8378485B2 (en) * | 2009-07-13 | 2013-02-19 | Lsi Corporation | Solder interconnect by addition of copper |
US8232643B2 (en) * | 2010-02-11 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lead free solder interconnections for integrated circuits |
JP5837339B2 (en) * | 2011-06-20 | 2015-12-24 | 新光電気工業株式会社 | Semiconductor device manufacturing method and semiconductor device |
-
2014
- 2014-03-27 WO PCT/US2014/032084 patent/WO2015147844A1/en active Application Filing
- 2014-03-27 CN CN201480076416.XA patent/CN106030783B/en active Active
- 2014-03-27 JP JP2016554385A patent/JP2017508293A/en active Pending
- 2014-03-27 KR KR1020167023490A patent/KR20160113686A/en active Search and Examination
- 2014-03-27 DE DE112014006271.5T patent/DE112014006271B4/en active Active
- 2014-03-27 US US14/430,131 patent/US20160260679A1/en not_active Abandoned
- 2014-03-27 GB GB1614555.9A patent/GB2540060B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030030149A1 (en) * | 2000-06-12 | 2003-02-13 | Kazuma Miura | Semiconductor device having solder bumps reliably reflow solderable |
US20100015796A1 (en) * | 2001-01-15 | 2010-01-21 | Nec Corporation | Semiconductor device, manufacturing method and apparatus for the same |
US20030193094A1 (en) * | 2002-04-12 | 2003-10-16 | Nec Electronics Corporation | Semiconductor device and method for fabricating the same |
US20050085013A1 (en) * | 2002-12-04 | 2005-04-21 | Craig Ernsberger | Ball grid array resistor network |
US20060030071A1 (en) * | 2004-08-05 | 2006-02-09 | Fujitsu Limited | Method for processing base |
Also Published As
Publication number | Publication date |
---|---|
CN106030783A (en) | 2016-10-12 |
GB201614555D0 (en) | 2016-10-12 |
US20160260679A1 (en) | 2016-09-08 |
DE112014006271T5 (en) | 2016-12-01 |
GB2540060B (en) | 2019-02-13 |
GB2540060A (en) | 2017-01-04 |
CN106030783B (en) | 2019-06-18 |
JP2017508293A (en) | 2017-03-23 |
KR20160113686A (en) | 2016-09-30 |
DE112014006271B4 (en) | 2023-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9257405B2 (en) | Multi-solder techniques and configurations for integrated circuit package assembly | |
US10770387B2 (en) | Integrated circuit package substrate | |
US20240030086A1 (en) | Bga stim package architecture for high performance systems | |
US10068863B2 (en) | Formation of solder and copper interconnect structures and associated techniques and configurations | |
US8920934B2 (en) | Hybrid solder and filled paste in microelectronic packaging | |
US9147638B2 (en) | Interconnect structures for embedded bridge | |
US10580758B2 (en) | Scalable package architecture and associated techniques and configurations | |
US9283641B2 (en) | Flux materials for heated solder placement and associated techniques and configurations | |
US9543197B2 (en) | Package with dielectric or anisotropic conductive (ACF) buildup layer | |
US20160260679A1 (en) | Hybrid interconnect for low temperature attach | |
US11804420B2 (en) | Core-shell particles for magnetic packaging | |
US11417592B2 (en) | Methods of utilizing low temperature solder assisted mounting techniques for package structures | |
US20170278818A1 (en) | High temperature solder paste |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 14430131 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14886989 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112014006271 Country of ref document: DE |
|
ENP | Entry into the national phase |
Ref document number: 201614555 Country of ref document: GB Kind code of ref document: A Free format text: PCT FILING DATE = 20140327 Ref document number: 2016554385 Country of ref document: JP Kind code of ref document: A Ref document number: 20167023490 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1614555.9 Country of ref document: GB |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14886989 Country of ref document: EP Kind code of ref document: A1 |